Semiconductor Devices

Abstract

To provide a semiconductor device having a structure capable of suppressing warpage of a wafer while configuring a semiconductor layer constituting a deep layer by an ion implantation layer.SOLUTION: A p-type deep layer 5, a p-type deep layer 30, and a p-type guard ring 21 are formed by an ion implantation. Then, not only the p-type deep layer 5 and the p-type guard ring 21 but also the p-type deep layer 30 is linearly configured. In this way, linearly configuring the p-type deep layer 30 makes a total value TV of occupancy of the p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21 in a chip 40% or lower. This makes it possible to suppress warpage of a wafer while configuring the p-type deep layer 30 by the ion implantation.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, and is particularly suitable for application to a silicon carbide (hereinafter referred to as SiC) semiconductor device. [Background technology]

[0002] Conventionally, semiconductor switching elements such as MOSFETs have been designed with a trench gate structure to achieve low on-resistance. However, to prevent a high electric field from being applied to the gate insulating film, a trench gate structure requires electric field relaxation at the trench bottom. For this reason, for example, in Patent Document 1, deep layers are formed on both sides of the trench gate structure by high-acceleration ion implantation to relax the electric field at the trench bottom. These deep layers prevent the equipotential lines from rising, and by relaxing the electric field at the trench bottom, they prevent a high electric field from being applied to the gate insulating film. In addition, a guard ring is provided in the peripheral region surrounding the cell region, and a deep layer is provided throughout the entire connecting portion located between the cell region and the guard ring. This allows the equipotential lines to extend from the cell region toward the connecting portion and then to the guard ring portion, where they terminate, enabling a high breakdown voltage. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-54087 Summary of the Invention [Problem to be solved by the invention]

[0004] However, when forming a deep layer by high-acceleration ion implantation as in Patent Document 1, wafer warpage occurs during the process depending on the dose and acceleration, causing problems associated with wafer warpage such as transport errors, substrate suction errors, and reduced photoresolution.

[0005] To address this issue, wafer warpage can be alleviated by performing activation annealing or similar processes each time ion implantation is performed, but this process can cause stacking faults in the ion-implanted areas, which not only increases drain leakage but also increases the number of processes, resulting in increased manufacturing costs.

[0006] In addition, counter-dosing measures such as ion implantation on the backside of the wafer can be taken to counter wafer warpage, but this increases the number of processes and can lead to unexpected particle adhesion due to surface adsorption, resulting in pattern collapse and reduced yield.

[0007] Furthermore, a deep layer can be formed by burying a p-type epitaxial layer in the trench, but it is difficult to control the concentration of the deep layer and to flatten the surface.

[0008] In view of the above, an object of the present invention is to provide a semiconductor device having a structure that can suppress wafer warpage while forming a semiconductor layer that constitutes a deep layer using an ion-implanted layer. [Means for solving the problem]

[0009] In order to achieve the above object, the invention described in claim 1 is a semiconductor device having a cell region (RC) in which a semiconductor element (100) is formed within a chip (Ch), a guard ring portion (RG) surrounding the outer periphery of the cell region, and an outer periphery region (RO) including a connecting portion (RJ) located between the guard ring portion and the cell region, and having a substrate (1, 101) of a first or second conductivity type, and a drift layer (2, 50, 60, 102) of the first conductivity type formed on the front side of the substrate having a front surface and a back surface and having a lower impurity concentration than the substrate. The cell region is provided with a vertical semiconductor element having a second conductivity type layer (5, 5a, 51, 103) formed in the drift layer and including a portion formed in a stripe shape with one direction as the longitudinal direction, a first electrode (9, 106) electrically connected to the second conductivity type layer, and a second electrode (11, 107) formed on the back side of the substrate, and allowing a current to flow between the first electrode and the second electrode, and the connecting portion is also provided with a second conductivity type layer (31, 33-35, 71) formed in a line shape in the drift layer. Further, the guard ring portion or the guard ring portion and connecting portion is provided with second conductivity type rings (21, 32, 72, 104, 105) formed in the drift layer and in the shape of a plurality of line frames surrounding the cell region, at least a portion located on the outer periphery of which forms a guard ring (21, 104). The second conductivity type layer and the second conductivity type ring are formed by ion implantation layers, and the proportion of the total area of ​​the chip occupied by the second conductivity type layer and the second conductivity type ring is set to 40% or less.

[0010] In this way, the second-conductivity-type layer and the second-conductivity-type ring are formed by ion implantation, but not only the second-conductivity-type layer in the cell region and the second-conductivity-type ring in the guard ring portion, but also the second-conductivity-type layer in the connecting portion are configured in a linear shape. By configuring the second-conductivity-type layer in the connecting portion in a linear shape, the total occupancy rate of the second-conductivity-type layer and the second-conductivity-type ring in the chip is kept to 40% or less. This makes it possible to suppress wafer warpage while forming the second-conductivity-type layer in the connecting portion, i.e., the semiconductor layer that constitutes the deep layer, by ion implantation.

[0011] Specifically, in the invention described in claim 1, the second conductive type layer provided in the connecting portion includes a linear portion (31) whose longitudinal direction is the same as the longitudinal direction of the second conductive type layer provided in the cell region, the second conductivity type ring is disposed in the guard ring portion and the connecting portion, a mesa portion (RM) is formed in which the cell region and the connecting portion protrude beyond the guard ring portion; The guard rings are spaced apart by larger intervals (DA3, DB3) from the inner periphery toward the outer periphery, The interval between the guard rings is a third interval (DA3, DB3), The relationship is such that the spacing (DA3out, DB3out) of the widest part of the third spacing located on the outermost periphery is greater than the spacing (DA3in, DB3in) of the third spacing located within a predetermined range from the boundary position of the mesa portion.

[0012] By setting the third interval in this manner, the total occupancy rate of the second conductivity type layer and the second conductivity type ring within the chip is set to 40% or less.

[0013] The reference numerals in parentheses for the above-mentioned means indicate an example of the correspondence with the specific means described in the embodiments to be described later. [Brief explanation of the drawings]

[0014] [Figure 1] FIG. 2 is a top view layout diagram of the SiC semiconductor device according to the first embodiment. [Figure 2] FIG. 2 is a cross-sectional view taken along line II-II of FIG. [Figure 3] FIG. 10 is a diagram showing the relationship between the acceleration voltage of ion implantation and wafer warpage. [Figure 4] FIG. 10 is a diagram showing the relationship between the cumulative dose of ion implantation and wafer warpage. [Figure 5A] FIG. 10 is a cross-sectional view showing the rising of equipotential lines. [Figure 5B] FIG. 10 is a diagram showing the relationship between the distance between p-type layers and the breakdown voltage. [Figure 6A] FIG. 10 is a diagram showing the change in the strength of the electric field applied near the bottom of the gate trench when the width of the linear portion in the p-type deep layer is changed in the cell region. [Figure 6B] FIG. 10 is a graph showing the change in the feedback capacitance Crss when the width of the linear portion in the p-type deep layer is changed. [Figure 7] This is a chart showing the results of investigating the area ratios of the cell region, the connecting portion, and the guard ring portion within the chip, and the ratio of the p-type layer therein. [Figure 8A] 3A to 3C are perspective cross-sectional views illustrating manufacturing steps of the SiC semiconductor device shown in FIGS. 1 and 2. [Figure 8B] 8B is a cross-sectional view showing the manufacturing process of the SiC semiconductor device subsequent to FIG. 8A. [Figure 8C] 8C is a cross-sectional view showing the manufacturing process of the SiC semiconductor device subsequent to FIG. 8B. [Figure 8D] 8D is a cross-sectional view showing the manufacturing process of the SiC semiconductor device subsequent to FIG. 8C. [Figure 8E] 8D and 8C are cross-sectional views showing the manufacturing process of the SiC semiconductor device subsequent to FIG. 8D. [Figure 8F] 8B is a cross-sectional view showing the manufacturing process of the SiC semiconductor device subsequent to FIG. 8E. [Figure 8G] 8F is a cross-sectional view showing a manufacturing process of the SiC semiconductor device subsequent to FIG. 8F. [Figure 8H] 8B is a cross-sectional view showing the manufacturing process of the SiC semiconductor device subsequent to FIG. 8G. [Figure 9] FIG. 2 is a top view layout diagram of a SiC semiconductor device according to a modified example of the first embodiment. [Figure 10] FIG. 2 is a top view layout diagram of a SiC semiconductor device according to a modified example of the first embodiment. [Figure 11] FIG. 2 is a top view layout diagram of a SiC semiconductor device according to a modified example of the first embodiment. [Figure 12] FIG. 2 is a top view layout diagram of a SiC semiconductor device according to a modified example of the first embodiment. [Figure 13] FIG. 10 is a perspective cross-sectional view of a SiC semiconductor device according to a second embodiment. [Figure 14A] 14A to 14C are perspective cross-sectional views showing a manufacturing process of the SiC semiconductor device shown in FIG. [Figure 14B] FIG. 14B is a perspective cross-sectional view showing the manufacturing process of the SiC semiconductor device subsequent to FIG. 14A. [Figure 14C] FIG. 14C is a perspective cross-sectional view showing the manufacturing process of the SiC semiconductor device subsequent to FIG. 14B. [Figure 15] FIG. 10 is a top view layout diagram of the SiC semiconductor device according to the third embodiment. [Figure 16] 16 is a cross-sectional view taken along the line XVI-XVI in FIG. 15. DETAILED DESCRIPTION OF THE INVENTION

[0015] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the following embodiments, parts that are identical or equivalent to each other will be denoted by the same reference numerals.

[0016] (First embodiment) A first embodiment will be described below, taking as an example an SiC semiconductor device in which an inversion MOSFET with a trench gate structure is formed as a semiconductor element.

[0017] FIG. 1 shows the top surface layout of a chip CH of a SiC semiconductor device in which a MOSFET 100 with a trench gate structure is formed. The SiC semiconductor device shown in FIG. 1 has a cell region RC in which the MOSFET 100 is formed and an outer periphery region RO surrounding the cell region RC. The outer periphery region RO has a guard ring portion RG and a connecting portion RJ disposed inside the guard ring portion RG, i.e., between the cell region RC and the guard ring portion RG. Note that FIG. 1 is not a cross-sectional view, but is partially hatched to make the drawing easier to see.

[0018] As shown in FIG. 2, the SiC semiconductor device is a n-type semiconductor device made of SiC. + It is formed using a mold substrate 1. + On the main surface of the mold substrate 1, a n-type layer corresponding to a low concentration layer made of SiC is formed. -The p-type layer 2 and the p-type base region 3 are formed by epitaxial growth or the like. + A source region 4 is formed.

[0019] n + The substrate 1 has an n-type impurity concentration of, for example, 1.0×10 19 / cm 3 The surface is the (0001) Si plane, and the off-axis direction is the <11-20> direction. - Mold layer 2 is n + The impurity concentration is lower than that of the n-type substrate 1, for example, the n-type impurity concentration is 5.0×10 15 ~2.0×10 16 / cm 3 In the present embodiment, this n - The mold layer 2 constitutes the drift layer.

[0020] The p-type base region 3 is a region where a channel region is formed, and the p-type impurity concentration is, for example, 2.0×10 17 / cm 3 The surface layer of the p-type base region 3, that is, the n-type base region of each adjacent cell in the MOSFET 100, is about 300 nm thick. + In the area sandwiched between the n-type source regions 4, a p-type contact region 3a and a p-type hole extraction layer 3b are formed, each of which is partially doped with a high concentration of p-type impurities. + The n-type source region 4 - The impurity concentration in the surface layer is higher than that in the second layer 2, and the n-type impurity concentration in the surface layer is, for example, 2.5×10 18 ~1.0×10 19 / cm 3 , and is about 0.5 μm thick.

[0021] In the cell area RC, n + On the surface side of the substrate 1, a p-type base region 3 and an n + The n-type source region 4 remains, and the n-type source region 4 is + The p-type base region 3 including the p-type hole extracting layer 3b remains on the surface side of the substrate 1. In addition, the guard ring portion RG has an n-type hole extracting layer 3b penetrating the p-type base region 3.- A recess 20 is formed so as to reach the mold layer 2. With this structure, a mesa portion RM is formed in which the cell region RC and the connecting portion RJ protrude beyond the guard ring portion RG. Note that the area surrounded by a dashed line in FIG. 1 indicates the mesa portion RM, and the area hatched with dashed lines inside it indicates the connecting portion RJ.

[0022] Also, in the cell region RC, n - A p-type deep layer 5 having a higher p-type impurity concentration than the p-type base region 3 is formed in the surface layer of the n-type layer 2. The p-type deep layer 5 constitutes at least a part of the second conductivity type layer. - It is formed from a predetermined depth position of the mold layer 2 to the surface, and n - It is formed by ion-implanting p-type impurities into the mold layer 2 .

[0023] The p-type deep layer 5 is - A plurality of linear portions 5a are arranged at equal intervals in the n-type layer 2, and as shown in FIG. 1, they have linear portions 5a arranged in stripes that are spaced apart from each other without intersections. In this embodiment, the p-type deep layer 5 also has intersections 5b that extend in a direction that intersects with the linear portions 5a, and the intersections 5b are arranged at both ends of each linear portion 5a, so that the two are connected. In other words, the p-type deep layer 5 forms a rectangular shape that surrounds the periphery of the cell region RC with the outermost of the plurality of linear portions 5a and the intersections 5b, and the remaining linear portions 5a are arranged in stripes inside. The p-type base region 3 and n-type base region 4 described above + The p-type source region 4 is formed on the p-type deep layer 5 .

[0024] In this embodiment, the p-type deep layers 5 are formed to have the same impurity concentration, the same width, and the same depth. For example, the p-type impurity concentration is 1.0×10 17 ~1.0×10 19 / cm 3Each p-type deep layer 5 has a width of 0.4 to 1.0 μm and a depth of approximately 2.0 μm. The distance DA1 between the linear portions 5a of the p-type deep layer 5 is 0.6 to 1.5 μm. The linear portions 31 of the p-type deep layer 30 of the connecting portion RJ, which will be described later, are connected to the intersections 5b of the p-type deep layer 5.

[0025] The direction in which the p-type deep layer 5 extends is arbitrary, but in this embodiment it is the <11-20> direction, which is the same as the off direction.

[0026] The intersections 5b in the p-type deep layers 5 are not essential, and the linear portions 5a in the p-type deep layers 5 do not have to be connected to the p-type deep layers 30 of the connecting portions RJ. Here, the spacing DA1 between the linear portions 5a in the p-type deep layers 5 is made different from the spacing DA2 between the linear portions 31 in the p-type deep layers 30, but the spacing DA1 and the spacing DA2 may be the same, and the linear portions 5a may be connected to the linear portions 31, respectively.

[0027] Also, the p-type base region 3 and the n + through the n-type source region 4 - A plurality of gate trenches 6, each having a width of 0.8 μm and a depth of 1.0 μm, are formed so as to reach the n-type layer 2 and be shallower than the p-type deep layer 5. The p-type base region 3 and the n-type base region 4 are formed so as to contact the side surfaces of each of the plurality of gate trenches 6. + 2 is a cross-sectional view of a p-type deep layer 5. The p-type deep layer 5 has a p-type source region 4 disposed therein. Each gate trench 6 is formed in a linear layout with the width direction extending left to right in the plane of the drawing in FIG. 2, the length direction extending perpendicular to the plane of the drawing, and the depth direction extending up to down in the plane of the drawing. As shown in FIG. 1, the multiple gate trenches 6 are arranged so as to be sandwiched between the linear portions 5a of the p-type deep layer 5, and are arranged in parallel at equal intervals to form a stripe pattern.

[0028] Furthermore, the portion of the p-type base region 3 located on the side of the gate trench 6 is converted into an n-type + Type source region 4 and n -A gate insulating film 7 is formed on the inner wall surface of the gate trench 6, including the channel region, as a channel region connecting the gate insulating film 7 and the gate electrode 8. A gate electrode 8 made of doped polysilicon is formed on the surface of the gate insulating film 7, and the gate trench 6 is filled with the gate insulating film 7 and the gate electrode 8. This forms a trench gate structure with one longitudinal direction. The above-mentioned p-type deep layers 5 are formed on both sides of this trench gate structure, extending in the same direction as the longitudinal direction of the trench gate structure. Note that in Figure 1, the number of trench gate structures and p-type deep layers 5 has been reduced to make the illustration easier to understand, but in reality, many similar structures are arranged.

[0029] Also, n + n for type substrate 1 - The opposite side of the mold layer 2, specifically n + On the surfaces of the p-type source region 4, the p-type base region 3, and the gate electrode 8, a source electrode 9 corresponding to a first electrode and a gate wiring layer (not shown) are formed via an interlayer insulating film 10. The source electrode 9 and the gate wiring layer are made of a plurality of metals, for example, Ni / Al. Among the plurality of metals, at least n-type SiC, specifically n + The portion in contact with the n-type source region 4 is made of a metal that can make ohmic contact with n-type SiC. At least the portion of the plurality of metals that contacts the p-type SiC, specifically the p-type contact region 3a and the p-type hole extraction layer 3b, is made of a metal that can make ohmic contact with p-type SiC. The source electrode 9 and the gate wiring layer are electrically insulated by being separated on the interlayer insulating film 10. The source electrode 9 is connected to the n-type SiC through a contact hole formed in the interlayer insulating film 10. + The gate wiring layer is in electrical contact with the gate electrode 8, and the p-type source region 4 and the p-type contact region 3a.

[0030] Furthermore, n + The back side of the mold substrate 1 is +A drain electrode 11 corresponding to a second electrode electrically connected to the mold substrate 1 is formed. With this structure, an n-channel inversion trench gate MOSFET 100 is formed. A plurality of such MOSFETs 100 are arranged to form a cell region RC.

[0031] On the other hand, in the guard ring portion RG, as described above, the n-type - The recess 20 is formed so as to reach the mold layer 2. Therefore, at a position away from the cell region RC, + The p-type source region 4 and the p-type base region 3 are removed to form an n - The mold layer 2 is exposed. + In the thickness direction of the mold substrate 1, a part of the cell region RC and the connecting portion RJ located inside the recess 20 forms a mesa portion RM that protrudes in an island shape.

[0032] In addition, the n - A plurality of p-type guard rings 21 are provided on the surface of the n-type layer 2 so as to surround the cell region RC and the connecting portion RJ. The p-type guard rings 21 constitute at least a part of the second conductivity type ring. In this embodiment, as shown in FIG. 1, the p-type guard rings 21 are rectangular with rounded corners, but may be formed in other frame shapes such as a circle. The p-type guard rings 21 are - The mold layer 2 is formed from the surface to a predetermined depth, - The p-type guard ring 21 may be formed away from the surface of the n-type layer 2. - It is formed by ion-implanting p-type impurities into the mold layer 2 .

[0033] In this embodiment, the p-type guard rings 21 have a configuration similar to that of the p-type deep layer 5 described above. The p-type guard rings 21 differ from the linearly formed p-type deep layer 5 in that their top surface shape is a line frame surrounding the cell region RC and the connecting portion RJ, but are otherwise similar. That is, the p-type guard rings 21 have the same impurity concentration and width as the p-type deep layer 5. The spacing DA3 between the p-type guard rings 21 may be equal, but in order to alleviate electric field concentration on the cell region RC side and direct equipotential lines toward the periphery, the spacing DA3 between the p-type guard rings 21 is narrower on the cell region RC side and wider toward the periphery. The spacing DA3in between the p-type guard rings 21, located within a predetermined range from the boundary position of the mesa portion RM, is narrower than the spacing DA1 between the linear portions 5a of the p-type deep layer 5 and the spacing DA2 between the linear portions 31 of the p-type deep layer 30 (described later). Furthermore, the widest portion of the interval DA3 located at the outermost periphery, that is, the interval DA3out between the outermost p-type guard ring 21 and the one just inside, is wider than the interval DA1 and the interval DA2.

[0034] Although not shown, if necessary, an EQR structure may be provided on the outer periphery of the p-type guard ring 21, thereby forming a guard ring portion RG that has a peripheral breakdown-resistant structure surrounding the cell region RC.

[0035] Furthermore, the area from the cell region RC to the guard ring portion RG is defined as a connecting portion RJ, and in the connecting portion RJ, n - A p-type deep layer 30 is formed in the surface layer of the base layer 2. The p-type deep layer 30 is in contact with the p-type base region 3 and is fixed to the source potential. In this embodiment, as shown by the dashed hatching in FIG. 1, a connecting portion RJ is formed to surround the cell region RC, and multiple p-type guard rings 21, each having a rectangular shape with rounded corners, are formed to surround the outside of the connecting portion RJ.

[0036] The p-type deep layer 30 has a configuration including a plurality of linear portions 31 arranged in stripes parallel to the p-type deep layer 5 formed in the cell region RC, and one or more frame-shaped portions 32 arranged to surround the p-type deep layer 5 and the linear portions 31. The linear portions 31 of the p-type deep layer 30 constitute a part of the second conductivity type layer, and the frame-shaped portion 32 constitutes a part of the second conductivity type ring.

[0037] The linear portion 31 is formed in the region between the cell region RC and the frame portion 32. - If a p-type layer is not formed in the mold layer 2, there will be places where the equipotential lines rise excessively. Therefore, this structure prevents such places from occurring. In a direction perpendicular to the longitudinal direction of the linear portions 5a of the p-type deep layer 5, multiple linear portions 31 are arranged parallel to the linear portions 5a between the cell region RC and the frame portion 32. In the longitudinal direction of the linear portions 5a, multiple linear portions 31 are also formed between the cell region RC and the frame portion 32, extending in the same direction as the linear portions 5a. The tips of the linear portions 5a are connected to the intersections 5b of the p-type deep layer 5 or the innermost portions of the frame portion 32. In this manner, the linear portions 31 are arranged between the cell region RC and the frame portion 32. The tip of the linear portion 31 may be separated from the intersection portion 5b or the frame portion 32 without being connected to them, but in that case, it is preferable that the distance between them is the same as or smaller than the spacing DA1 of the linear portions 5a in the p-type deep layer 5.

[0038] The frame-shaped portion 32 has a rectangular shape with rounded corners, and surrounds the cell region RC and the linear portion 31. Specifically, the frame-shaped portion 32 is disposed concentrically with the p-type guard ring 21. In this embodiment, a plurality of frame-shaped portions 32 are provided.

[0039] Each p-type deep layer 30 formed by the linear portion 31 and the frame portion 32 is located below the p-type base region 3. - It is formed by implanting ions from the surface of the mold layer 2 to a predetermined depth.

[0040] In this embodiment, the width of the linear portions 31 of the p-type deep layer 30 is 0.4 to 1.0 μm, which is the same as the width of the p-type deep layer 5. The spacing DA2 of the linear portions 31 is 0.6 to 1.5 μm, which may be the same as the spacing DA1 of the linear portions 5a of the p-type deep layer 5, but here it is narrower than the spacing DA1.

[0041] The frame-shaped portions 32 are formed from the inner periphery to the outer periphery of the mesa portion RM and have the same width as the p-type deep layer 5. The intervals DA4 of the frame-shaped portions 32 may all be the same width, or may be different widths. Preferably, the intervals DA4 of the frame-shaped portions 32 are equal to or smaller than the intervals DA1 of the linear portions 5a of the p-type deep layer 5 in the cell region RC. More preferably, the intervals DA4out of the intervals DA4 of the frame-shaped portions 32 located within a predetermined range from the boundary position of the mesa portion RM are narrower than the intervals DA2 of the linear portions 31 in the p-type deep layer 30.

[0042] Here, the spacing DA3in between the p-type guard rings 21 located within a predetermined range from the boundary position of the mesa portion RM and the spacing DA4out between the frame-shaped portions 32 are narrower than the spacing DA2 between the linear portions 31 in the p-type deep layer 30. This is to accommodate mask misalignment when forming the recessed portion 20 for forming the mesa portion RM.

[0043] When mask misalignment occurs, the formation position of the inner circumferential edge of the recess 20 shifts. For example, in the structure shown in FIG. 1 , assume that mask misalignment causes the formation position of the inner circumferential edge of the recess 20 to shift to the right side of the page. In this case, a portion of the frame-shaped portion 32 is formed inside the recess 20, outside the mesa portion RM, on the left side of the page, and a portion of the p-type guard ring 21 is formed inside the mesa portion RM, not inside the recess 20, on the right side of the page. In this structure, since a portion of the frame-shaped portion 32 has a structure similar to that of a guard ring, it is preferable that the width and spacing be the same as that of the inner side of the p-type guard ring 21. Therefore, as in this embodiment, the spacing DA4out of the frame-shaped portion 32 and the spacing DA3in of the p-type guard ring 21 are narrower than the spacing DA1 in portions located within a predetermined range from the boundary position of the mesa portion RM. Preferably, the frame-shaped portion 32 and the p-type guard ring 21 have the same width and spacing. This approach also addresses mask misalignment.

[0044] Although the frame-shaped portion 32 has been described as being distinct from the p-type guard ring 21, it can be said that a plurality of concentric frame-shaped p-type rings are formed by the frame-shaped portion 32 and the p-type guard ring 21. In other words, it can be said that the portion of the p-type ring that is positioned more inward than the recess 20 forms the frame-shaped portion 32, and the portion formed within the recess 20 forms the p-type guard ring 21.

[0045] A p-type base region 3 is also formed in the connecting portion RJ. A p-type hole extraction layer 3b is formed on the p-type base region 3. A source electrode 9 extends up to the p-type hole extraction layer 3b, connecting the p-type base region 3 and the p-type deep layer 30 through the p-type hole extraction layer 3b. The p-type hole extraction layer 3b is formed in the connecting portion RJ so as to surround the cell region RC. Here, the p-type hole extraction layer 3b is formed to completely surround the periphery of the cell region RC. However, it may be divided into multiple layers, spaced equally around the entire periphery. By providing this p-type hole extraction layer 3b, holes generated in the peripheral region can be extracted to the source electrode 9 when avalanche breakdown occurs in the cell region RC, or in the guard ring portion RG or connecting portion RJ. This prevents holes from flowing into the cell region RC, thereby preventing device breakdown.

[0046] In addition, an interlayer insulating film 10 is formed on the surface of the p-type hole extracting layer 3b. Although not shown, a gate pad connected to the gate wiring layer is formed in a location of the interlayer insulating film 10 at the connecting portion RJ that is different from the location where the source electrode 9 is located.

[0047] The SiC semiconductor device according to this embodiment is configured as described above. When the SiC semiconductor device configured as described above turns on the MOSFET 100, a channel region is formed in the surface portion of the p-type base region 3 located on the side surface of the gate trench 6 by controlling the voltage applied to the gate electrode 8. As a result, the n + type source region 4, a channel region and an n - A current is passed between the source electrode 9 and the drain electrode 11 through the mold layer 2 .

[0048] Furthermore, when the MOSFET 100 is turned off, even if a high voltage is applied, the p-type deep layer 5 and the p-type deep layer 30, which are formed to a position deeper than the trench gate structure, suppress the penetration of the electric field into the bottom of the gate trench. This reduces the electric field concentration at the bottom of the gate trench, thereby preventing breakdown of the gate insulating film 7.

[0049] Furthermore, at the connecting portion RJ, the equipotential lines are prevented from rising upward, and are directed toward the guard ring portion RG. At the guard ring portion RG, the equipotential lines are gradually terminated toward the outer periphery by the p-type guard ring 21, and the desired breakdown voltage can be obtained at the guard ring portion RG as well.

[0050] Here, the widths and intervals DA1 to DA4 of each part are set as described above for the p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21. As a result, the proportion of the total area of ​​the chip constituting the SiC semiconductor device that is occupied by the p-type layers deeply implanted by ion implantation, that is, the p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21, is set to 40% or less.

[0051] When forming a p-type layer by ion implantation, warping occurs in the wafer used to form the SiC semiconductor device during the process depending on the dose and acceleration, which can cause problems associated with wafer warping, such as transport errors, substrate suction errors, and reduced photoresolution.

[0052] For this reason, it is required to minimize wafer warpage while achieving the effects of suppressing the penetration of the electric field into the bottom of the gate trench and obtaining the desired breakdown voltage in the guard ring portion RG.

[0053] Specifically, the relationship between the acceleration voltage of ion implantation and wafer warpage is shown in Figure 3. Furthermore, the relationship between the cumulative dose of ion implantation and wafer warpage is shown in Figure 4. The relationship between the acceleration voltage of ion implantation and wafer warpage was investigated using a 350 μm thick substrate, forming a p-type layer with a depth similar to that of the p-type deep layer 5 using Al as a p-type impurity, and performing ion implantation on both the front side and back side of the SiC substrate. The dose in this case was 8×10 14 cm -2 Regarding the relationship between the dose of ion implantation and wafer warpage, a constant acceleration voltage of 150 keV was used, and a p-type layer of approximately the same depth as the p-type deep layer 5 was formed on the surface of the SiC substrate using Al as a p-type impurity, and the difference in height between the outer edge and center of the substrate was measured as the amount of warpage.

[0054] As can be seen from Figure 3, wafer warpage is proportional to the acceleration voltage of ion implantation, with the higher the acceleration voltage, the greater the wafer warpage. Also, as can be seen from Figure 4, wafer warpage is proportional to the dose of ion implantation, with the higher the dose, the greater the wafer warpage.

[0055] For this reason, if the p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21 are to be formed deep at a high acceleration voltage, it is necessary to reduce the dose during ion implantation. To achieve this, it is not preferable to have a structure in which a deep layer is provided over the entire area of ​​the connecting portion as in Patent Document 1, and it is necessary to limit the areas in which the p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21 are formed, as in this embodiment.

[0056] Therefore, in this embodiment, the p-type deep layer 30 formed in the connecting portion RJ is configured with linear straight portions 31 and frame-shaped portions 32, and is not formed over the entire connecting portion RJ. However, if the p-type deep layer 30 is not formed over the entire connecting portion RJ, if the spacing DA2 between the linear portions 31 is large, the equipotential lines may rise, as shown in FIG. 5A, and the breakdown voltage may be reduced. Specifically, when p-type layers are arranged in a stripe pattern and the relationship between the spacing DA2 and the breakdown voltage is examined, the results shown in FIG. 5B are obtained. It is confirmed that the spacing DA2 is preferably 1.5 μm or less to achieve a breakdown voltage of approximately 1800 V. For this reason, the spacing DA2 between the linear portions 31 in the p-type deep layer 30 is set to 1.5 μm or less.

[0057] On the other hand, from the viewpoint of breakdown voltage, it is sufficient if the distance DA2 is 1.5 μm or less, but if the distance DA2 is too narrow, the remaining width of the photomask used in ion implantation of the p-type deep layer 30 becomes narrow, which may result in poor patterning. For this reason, the distance DA2 is set to 0.6 μm or more.

[0058] While the above description has been given of the spacing DA2 between the linear portions 31 in the p-type deep layer 30, the same can be said for the spacing DA1 between the p-type deep layers 5 in the cell region RC, and it is preferable that the spacing DA1 be 0.6 to 1.5 μm. Furthermore, it is also preferable that the spacing DA3in and the spacing DA4out be 0.6 to 1.5 μm, and it is more preferable that they be smaller than the spacing DA1 and the spacing DA2 to accommodate mask misalignment.

[0059] Furthermore, narrowing the intervals DA1 and DA2 improves the breakdown voltage, but increases the proportion of the p-type deep layer 5 and the p-type deep layer 30 formed, resulting in a larger dose during ion implantation. Therefore, while narrowing the intervals DA1 and DA2, it is necessary to ensure that the dose during ion implantation is not too large. Furthermore, not only the intervals DA1 and DA2 but also the widths of the p-type deep layer 5 and the p-type deep layer 30 affect the dose during ion implantation. Since the widths of the p-type deep layer 5 and the p-type deep layer 30 can cause a decrease in breakdown voltage and an increase in feedback capacitance Crss, the widths of the p-type deep layer 5 and the p-type deep layer 30 must be set to a dose during ion implantation that can suppress the feedback capacitance Crss and wafer warpage while maintaining the breakdown voltage.

[0060] FIG. 6A shows the change in the strength of the electric field applied near the bottom of the gate trench 6 when the width of the linear portions 31 in the p-type deep layer 5 is changed in the cell region RC. Similar results were obtained when the width of the linear portions 31 was kept constant and the spacing between the linear portions 31 was increased. While the electric field in the cell region RC is shown here, the same applies to the connecting portion RJ. As shown in this figure, when the width of the p-type deep layer 5 or the p-type deep layer 30 is narrowed, the equipotential lines tend to penetrate into the p-type deep layer 5 or the p-type deep layer 30, as described above. This increases the rise of the equipotential lines between the p-type deep layer 5 or the p-type deep layer 30, resulting in a decrease in breakdown voltage. In particular, in the cell region RC, a high electric field is applied to the bottom of the gate trench 6, which can cause dielectric breakdown of the gate insulating film 7.

[0061] 6B shows the change in the feedback capacitance Crss when the width of the linear portions 31 in the p-type deep layer 30 is changed while the spacing between the linear portions 31 is kept constant. Specifically, the width of the linear portions 31 was changed with actual measurement quantity n=3, and the feedback capacitance Crss was measured when 450 V was applied to the drain side, and the average value was approximated using a curve. Similar results were obtained when the width of the linear portions 31 was kept constant while the spacing between the linear portions 31 was increased.

[0062] Since an increase in the feedback capacitance Crss increases the switching loss, it is necessary to limit the width of the p-type deep layer 30 to a certain extent. - A depletion layer is generated at the PN junction with the p-type layer 2, causing equipotential lines to penetrate into the p-type deep layer 30. Therefore, if the width of the p-type deep layer 30 is too narrow, the feedback capacitance Crss will increase further.

[0063] Considering the switching loss, the feedback capacitance Crss is preferably 60 pF or less, and considering the breakdown voltage, the strength of the electric field applied between the p-type deep layer 5 and the p-type deep layer 30 is preferably 4 MV / cm or less. To satisfy these conditions, in this embodiment, the width of the p-type deep layer 5 and the p-type deep layer 30 is set to 0.4 μm or more.

[0064] Furthermore, the p-type deep layer 5 and the p-type deep layer 30 can satisfy the above conditions by increasing their widths. However, once the widths exceed a certain level, increasing the widths does not significantly improve the effects of suppressing the feedback capacitance Crss or ensuring the breakdown voltage. Conversely, increasing the widths of the p-type deep layer 5 and the p-type deep layer 30 increases the dose of p-type impurities during ion implantation, which affects wafer warpage. For this reason, it is better to limit the widths of the p-type deep layer 5 and the p-type deep layer 30 to a certain extent. Therefore, the widths of the p-type deep layer 5 and the p-type deep layer 30 are set to 1.5 μm or less, preferably 1.0 μm or less, at which point the effects of suppressing the feedback capacitance Crss and ensuring the breakdown voltage almost reach their limit.

[0065] When the width of the p-type deep layer 5 or the p-type deep layer 30 is set to 0.4 to 1.5 μm, it is necessary to set the intervals between the p-type deep layer 5 or the p-type deep layer 30 so that the dose during ion implantation can suppress wafer warpage to a predetermined value or less. For this reason, the intervals DA1 and DA2 are set to 0.6 to 1.5 μm based on the results shown in Fig. 4. As described above, the intervals DA1 and DA2 can be the same, but unlike the interval DA1 in which a trench gate structure is sandwiched, the interval DA2 does not sandwich a trench gate structure, so it is more preferable to make it smaller than the interval DA1.

[0066] While the explanation has been given here regarding the intervals DA1 and DA2, the same can be said about the intervals DA4 and DA4out of the frame portion 32 and the interval DA3in of the p-type guard ring 21 located within a predetermined range from the boundary position of the mesa portion RM. The same can be said about the width of the p-type guard ring 21 as about the p-type deep layer 5 and the p-type deep layer 30. Furthermore, because the equipotential lines are concentrated near the mesa portion RM due to its structure, it is advisable to make the intervals DA4out and DA3in within a predetermined range from the boundary portion of the mesa portion RM smaller than the intervals DA1 and DA2 so as to prevent the equipotential lines from rising up in the mesa portion RM.

[0067] In this manner, the intervals DA1 to DA4 and the widths of the p-type deep layer 5 and the p-type deep layer 30 are defined. FIG. 7 shows the results of examining the area ratios of the cell region RC, the connecting portion RJ, and the guard ring portion RG within a 5 mm square chip on which a SiC semiconductor device is formed, as well as the occupancy rates of the p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21 within that area. As an example, the cell region RC occupies 60%, the connecting portion RJ 30, and the guard ring portion RG 10% of the chip area. As comparative examples, the case where the p-type deep layer 30 is formed over the entire connecting portion RJ and the case where the p-type deep layer 30 is configured with the linear portion 31 and the frame-shaped portion 32 as in this embodiment are examined. The widths of the p-type deep layer 5 and the p-type deep layer 30 are set to 1.0 μm, and the intervals DA1 to DA3 are set to 0.6 μm. The width of the p-type guard ring 21 is set to 1.0 μm, and the interval DA4 is set to 0.6 to 1.5 μm, so that the interval increases with increasing distance from the cell region RC.

[0068] As shown in this figure, in the comparative example in which the p-type deep layer 30 is formed over the entire area of ​​the connecting portion RJ, the proportion of the p-type deep layer 30 in the connecting portion RJ is 100%. Therefore, the proportion of the p-type deep layer 30 in the chip is 30%, the same as the area ratio of the connecting portion RJ in the chip. In the cell region RC, the proportion of the p-type deep layer 5 in the chip is 24%, and in the guard ring region RG, the proportion of the p-type guard ring 21 in the chip is 3%. Therefore, the total proportion of the p-type deep layer 5, p-type deep layer 30, and p-type guard ring 21 in the chip is 57%.

[0069] In contrast, when the p-type deep layer 30 is configured with the linear portion 31 and the frame portion 32 as in this embodiment, the proportion of the p-type deep layer 30 in the connecting portion RJ is 40%. As a result, the proportion of the p-type deep layer 30 in the chip is 12%. Furthermore, in the cell region RC, the proportion of the p-type deep layer 5 in the chip is 24%, and in the guard ring portion RG, the proportion of the p-type guard ring 21 in the chip remains at 3%. As a result, the total occupancy rate TV of the p-type deep layer 5, p-type deep layer 30, and p-type guard ring 21 in the chip is 39%.

[0070] By forming the p-type deep layer 30 in a linear shape like the linear portion 31 and the frame-shaped portion 32, the occupancy rate of the p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21 within the chip can be reduced. Here, the width of the p-type deep layer 5 and the p-type deep layer 30 is 1.0 μm, and the intervals DA1 to DA3 are 0.6 μm. Therefore, compared to when the width is narrower and the intervals DA1 to DA3 are wider, the occupancy rate of the p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21 within the chip is higher. By making the width of the p-type deep layer 30 less than 1.0 μm or increasing the intervals DA1 to DA3 more than 0.6 μm, the total value TV can be further reduced, to at least 40% or less. This reduces the total value TV of the occupancy rate of the p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21 within the chip, i.e., it is possible to reduce the dose during ion implantation, thereby suppressing wafer warpage.

[0071] As described above, in this embodiment, by configuring the p-type deep layer 30 in a linear shape, the total occupancy TV of the p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21 in the chip is set to 40% or less. This makes it possible to suppress wafer warpage while configuring the p-type deep layer 30 by ion implantation.

[0072] In addition, this embodiment can also achieve the following effects.

[0073] (1) As described above, the widths of the p-type deep layers 5 and 30 are set to 0.4 to 1.0 μm, and the spacing DA1 between the p-type deep layers 5, the spacing DA2 between the linear portions 31, and the spacing DA4 between the frame-shaped portions 32 are set to 0.6 to 1.5 μm. This suppresses an increase in the feedback capacitance Crss. Furthermore, this suppresses the rise of equipotential lines between the p-type deep layers 5 and 30 and also suppresses the application of a high electric field to the bottom of the gate trench 6, thereby ensuring the breakdown voltage of the SiC semiconductor device. Furthermore, by setting the widths and spacings DA1, DA2, and DA4 of the p-type deep layers 5 and 30 in this manner, the area occupied by the p-type deep layers 5 and 30 in the chip can be reduced, further reducing the dose during ion implantation. This further reduces wafer warpage.

[0074] In this case, it is preferable to set the intervals DA1 to DA4 to be equal to or greater than the widths of the p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21. By doing so, it is possible to achieve an area ratio of the p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21 in the chip of 40% or less, with the total value TV, without deteriorating functions such as breakdown voltage.

[0075] (2) Furthermore, when the sizes of the gaps are set to be gap DA3out > gap DA1 > gap DA2 > gap DA3in and gap DA4out, a break can be generated in the entire cell region RC. This prevents element destruction even when a high voltage due to a load surge or the like is applied to the SiC semiconductor device.

[0076] (3) Furthermore, in this embodiment, the p-type deep layer 5 in the cell region RC has an intersection 5b, which is connected to the linear portions 5a and the linear portions 31 in the p-type deep layer 30 of the connecting portion RJ. In addition, the innermost portion of the frame portion 32 is connected to the linear portions 31.

[0077] 1, it is possible to reduce the gaps between the p-type deep layers 5 and 30, i.e., the areas where the p-type deep layers 5 and 30 are not disposed, which further suppresses the rise of the equipotential lines and ensures a high breakdown voltage.

[0078] The p-type deep layer 5 and the p-type deep layer 30 are not formed by ion implantation layers, but by n - Another possible method is to form a trench in the surface of the mold layer 2 and then fill the trench with a p-type layer. However, filling a trench with a p-type layer is difficult, and depressions occur in the p-type layer at locations where the linear portions intersect or connect. In contrast, if the p-type deep layer 5 and the p-type deep layer 30 are formed using ion-implanted layers, depressions do not occur in the p-type layer even at locations where the linear portions intersect or connect. This ensures the flatness of the wafer surface.

[0079] Next, a method for manufacturing a SiC semiconductor device according to this embodiment will be described with reference to FIGS. 8A to 8H.

[0080] [Step shown in Figure 8A] First, as the semiconductor substrate, + A n-type substrate 1 is formed on the main surface of the n-type substrate 1. - The mold layer 2 is prepared by epitaxial growth. + On the main surface of the substrate 1, - The semiconductor substrate may be prepared by epitaxially growing the dopant layer 2, or by pre-forming an n + On the main surface of the substrate 1, - A so-called epitaxial substrate on which the mold layer 2 is epitaxially grown may be prepared as the semiconductor substrate.

[0081] [Step shown in Figure 8B] Next, n -A mask (not shown) is placed on the n-type layer 2, and openings are made in the mask in the regions where the p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21 are to be formed. Then, p-type impurities are ion-implanted using the mask. At this time, the range of ion implantation is adjusted so that the p-type impurities are n-type. - The ions are implanted to a predetermined depth from the surface of the mold layer 2. This forms the p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21. Thereafter, the mask is removed.

[0082] Although the p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21 are formed at one time here, they may be formed in multiple parts. In that case, for example, the p-type deep layer 5 and the p-type deep layer 30 may be formed in separate upper and lower parts, with the lower part being wider than the upper part, or the like, so that they have different widths.

[0083] [Step shown in Figure 8C] The p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21 are included in the n - On the top of the p-type layer 2, a p-type base region 3 and an n-type + The source region 4 is then epitaxially grown.

[0084] [Step shown in Figure 8D] n + A mask (not shown) is placed on the p-type source region 4, and then openings are made in the mask in areas where the p-type contact region 3a and the p-type hole extracting layer 3b are to be formed. Then, p-type impurities are ion-implanted using the mask to form the p-type contact region 3a and the p-type hole extracting layer 3b. The mask is then removed.

[0085] Here, n + The p-type source region 4 is epitaxially grown, and the p-type contact region 3a and the p-type hole extraction layer 3b are formed by ion implantation, but this is not limiting. +The p-type source region 4, the p-type contact region 3a, and the p-type hole extraction layer 3b may all be formed by ion implantation into the p-type base region 3. Alternatively, the p-type contact region 3a and the p-type hole extraction layer 3b may be formed by epitaxial growth so that the impurity concentration in the surface layer of the p-type base region 3 is high, and then n-type impurities may be ion implanted into the p-type base region 3 to form the n-type contact region 3a and the p-type hole extraction layer 3b. + A type source region 4 may also be formed.

[0086] [Step shown in Figure 8E] n + After forming a mask (not shown) on the p-type source region 4, the p-type base region 3, etc., the mask is opened in areas where the gate trench 6 and the recess 20 are to be formed. Then, anisotropic etching such as RIE (Reactive Ion Etching) is performed using the mask to form the n - A gate trench 6 and a recess 20 having a depth deeper than the upper surface of the mold layer 2 are simultaneously formed.

[0087] Although the gate trench 6 and the recess 20 are formed simultaneously here, they can also be formed separately. In this case, the gate trench 6 and the recess 20 can be made to different depths, which makes it possible to design each to an optimum depth.

[0088] [Step shown in Figure 8F] After removing the mask, a gate insulating film 7 is formed by depositing, for example, an oxide film. The gate insulating film 7 covers the inner wall surface of the gate trench 6 and the n-type insulating film. + The gate electrode 8 is formed by depositing polysilicon doped with p-type or n-type impurities onto the surface of the source region 4. After depositing polysilicon doped with p-type or n-type impurities, the polysilicon is etched back to leave the polysilicon at least in the gate trench 6. This completes the trench gate structure.

[0089] [Step shown in Figure 8G] An interlayer insulating film 10 made of, for example, an oxide film is formed so as to cover the surfaces of the gate electrodes 8 and the gate insulating film 7. Then, a mask (not shown) is formed on the surface of the interlayer insulating film 10, and the portions of the mask located between the gate electrodes 8, i.e., the portions corresponding to the p-type contact regions 3a and their vicinity, are opened. At the same time, the portions of the mask corresponding to the p-type hole extraction layer 3b are also opened. Thereafter, the interlayer insulating film 10 is patterned using the mask to form the p-type contact regions 3a and the n-type hole extraction layer 3b. + A contact hole exposing the p-type source region 4 and a contact hole exposing the p-type hole extraction layer 3b are formed.

[0090] [Step shown in Figure 8H] An electrode material having a laminated structure of, for example, multiple metals is formed on the surface of the interlayer insulating film 10. Then, the electrode material is patterned to form the source electrode 9 and gate wiring (not shown).

[0091] The subsequent steps are not shown, but + By carrying out processes such as forming a drain electrode 11 on the back surface of the mold substrate 1, the SiC semiconductor device according to this embodiment is completed.

[0092] As described above, the p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21 are formed by ion implantation, but not only the p-type deep layer 5 and the p-type guard ring 21, but also the p-type deep layer 30 is configured in a linear shape. By configuring the p-type deep layer 30 in a linear shape, the total occupancy rate TV of the p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21 in the chip is set to 40% or less. This makes it possible to suppress wafer warpage while configuring the p-type deep layer 30 by ion implantation.

[0093] (Modification of the first embodiment) The layout of the p-type deep layer 5 and the p-type deep layer 30 may be changed from that of the first embodiment.

[0094] For example, as shown in FIG. 9 , the p-type deep layer 5 may be configured with only a stripe-shaped portion composed of linear portions 5a. Alternatively, as shown in FIG. 10 , the portion of the p-type deep layer 30 inside the frame-shaped portion 32 may be configured as a lattice-shaped portion 33 composed of stripes extending in two directions and intersecting at right angles. Specifically, the lattice-shaped portion 33 may be configured with one stripe parallel to the linear portions 5a in the p-type deep layer 5 and the other stripe perpendicular to the linear portions 5a. Alternatively, as shown in FIG. 11 , the portion of the p-type deep layer 30 inside the frame-shaped portion 32 may be configured as a mesh-shaped portion 34 composed of stripes extending in two different directions and intersecting each other and tilted relative to the linear portions 5a. Furthermore, as shown in FIG. 12 , the portion of the p-type deep layer 30 inside the frame-shaped portion 32 may be configured as a dot-shaped portion 35 in which multiple dots are arranged linearly with their longitudinal direction aligned with the linear portions 5a in the p-type deep layer 5. Although the dots shown here are oval dots arranged in a dot line, with their longitudinal direction being the same as the direction in which the dot-shaped portions 35 are linearly arranged, the dots may also be formed in other shapes such as circles or squares. In the structures shown in Figures 10 to 12, the lattice-shaped portion 33, mesh-shaped portion 34, and dot-shaped portion 35 each constitute part of the second conductivity type layer.

[0095] In these cases, it is also preferable to set the spacing DA2 of the p-type deep layer 30 in the connecting portion RJ so that the relationship of spacing DA3out > spacing DA1 > spacing DA2 > spacing DA3in, DA4out holds. In the structures of Figures 10 and 11, the spacing DA2 corresponds to the spacing between the stripes extending in two directions that make up the lattice portion 33 or mesh portion 34. In the structure of Figure 12, the spacing DA2 corresponds to the spacing between adjacent dot lines or the spacing between adjacent dots on the same dot line.

[0096] (Second embodiment) The second embodiment will be described. This embodiment is different from the first embodiment in that the breakdown voltage structure using the p-type layer is changed, and other aspects are the same as the first embodiment, so the differences from the first embodiment will be mainly described.

[0097] 13, in this embodiment, in the cell region RC, a first n-type current spreading layer 50 and a p-type deep layer 51 are provided below the p-type deep layer 5, and a second current spreading layer 60 is provided between the p-type deep layers 5. The p-type deep layer 51 corresponds to the first deep layer and constitutes at least a part of the second conductivity type layer. Furthermore, the p-type deep layer 5 arranged above the p-type deep layer 51 corresponds to the second deep layer.

[0098] Specifically, n - A first current spreading layer 50 and a p-type deep layer 51 are formed on the n-type layer 2. The first current spreading layer 50 has a depth of 0.3 to 1.5 μm. The p-type deep layer 51 is shallower than the first current spreading layer 50, but has a depth of approximately the same 0.3 to 1.4 μm. In other words, the p-type deep layer 51 is formed so that its bottom is located within the first current spreading layer 50, and - The first current spreading layer 50 is formed at a depth such that it is located between the first current spreading layer 50 and the p-type deep layer 2. Here, a part of the first current spreading layer 50 is arranged at the bottom of the p-type deep layer 51, but the first current spreading layer 50 and the p-type deep layer 51 may be at the same depth.

[0099] The first current spreading layer 50 and the p-type deep layer 51 are each extended in one direction to form a stripe shape with multiple lines arranged alternately, and are arranged at equal intervals along the perpendicular direction. In this embodiment, the stripe-shaped portions of the first current spreading layer 50 and the p-type deep layer 51 are extended in a direction intersecting the longitudinal direction of the trench gate structure.

[0100] The spacing between the lines of the striped portion of the first current spreading layer 50 is, for example, 0.6 to 1.5 μm, and the n-type impurity concentration is, for example, 5.0×1016 ~2.0×10 18 / cm 3 The width of each p-type deep layer 51 is set to, for example, 0.4 to 1.0 μm, and the p-type impurity concentration is set to, for example, 3.0×10 17 ~1.0×10 18 / cm 3 The spacing DB1 between the p-type deep layers 51, i.e., the width of each line in the striped portion of the first current spreading layer 50, is different from the spacing DB2 between the linear portions 71 of the p-type deep layers 70 provided in the connecting portion RJ, which will be described later, but they may be the same. Here, the spacing DB1 is set to be equal to or greater than the spacing DB2.

[0101] For the first current spreading layer 50, n - forming a recess in the surface of the n-type layer 2, epitaxially growing the n-type layer, and then flattening the surface; or - The first current spreading layer 50 is formed by ion implantation of n-type impurities into the surface layer of the dopant layer 2. When the first current spreading layer 50 is formed by ion implantation, n - Because n-type impurities are implanted into the doped layer 2, the dose is significantly smaller than when p-type impurities are ion-implanted to form the p-type deep layer 5 or the like. Therefore, wafer warpage is unlikely to occur. Furthermore, the p-type deep layer 51 is formed by ion-implanting p-type impurities. Therefore, the width and dose of the p-type deep layer 51 are set with consideration given to wafer warpage. Furthermore, to prevent the remaining width of the photomask during ion implantation from becoming too narrow, the spacing between the p-type deep layers 51 is set to 0.6 μm or more.

[0102] The second current spreading layer 60 is formed on the first current spreading layer 50 and the p-type deep layer 51 together with the p-type deep layer 5. In the first embodiment, the n-type - In the first embodiment, the n-type impurity layer 2 is replaced by the second current spreading layer 60. The second current spreading layer 60 has an n-type impurity concentration of n - It may be the same as the mold layer 2, but it is preferable to use n -It is preferable that the n-type impurity concentration of the second current spreading layer 60 is higher than that of the n-type layer 2. Here, the n-type impurity concentration of the second current spreading layer 60 is, for example, 1.0×10 16 ~5.0×10 17 / cm 3 The thickness of the second current spreading layer 60 is set to, for example, 0.5 to 2 μm. The p-type deep layer 5 is formed by ion-implanting p-type impurities into the second current spreading layer 60. The p-type deep layer 5 is formed to a depth equal to or greater than the depth of the second current spreading layer 60, and is connected to the p-type deep layer 51.

[0103] In this embodiment, n - In addition to the mold layer 2, the first current spreading layer 50 and the second current spreading layer 60 constitute the drift layer. The second current spreading layer 60 is formed at a position corresponding to the trench gate structure and extends in a direction perpendicular to the first current spreading layer 50, i.e., in the same direction as the longitudinal direction of the trench gate structure.

[0104] In the guard ring part RG, n - The second current spreading layer 60 formed in the cell region RC remains on the surface of the n-type layer 2. In addition, a recess 20 is formed so as to penetrate the p-type base region 3 and reach the second current spreading layer 60. - A p-type guard ring 21 is formed on the surface layer of the mold layer 2. Here, the p-type guard ring 21 is disposed apart from the bottom surface of the recess 20, but it may be formed in contact with the bottom surface of the recess 20.

[0105] The p-type guard rings 21 are formed to surround the cell region RC and the connecting portion RJ, with multiple rings arranged concentrically, forming the layout of the first embodiment. The p-type guard rings 21 have the same width and impurity concentration as the p-type deep layers 51 described above. The spacing DB3 between the p-type guard rings 21 may be equal, but to alleviate electric field concentration on the cell region RC side and direct equipotential lines toward the periphery, the spacing DB3 between the p-type guard rings 21 is narrower on the cell region RC side and wider toward the periphery. The spacing DB3in between the p-type guard rings 21, located within a predetermined range from the boundary position of the mesa portion RM, is narrower than the spacing DB1 between the p-type deep layers 51 in the cell region RC and the spacing DB2 between the linear portions 71 of the p-type deep layers 70 in the connecting portion RJ. Furthermore, the widest portion of the gap DB3, that is, the gap DB3out between the outermost p-type guard ring 21 and the one just inside it, is wider than the gap DB1 and the gap DB2.

[0106] Also, at the connecting part RJ, n - On the surface of the n-type layer 2, a p-type deep layer 5 and a second current spreading layer 60 are formed, and further thereon, a p-type base region 3 is also formed. - A p-type deep layer 70 is formed in the surface layer portion of the p-type layer 2 .

[0107] Although only a cross section is shown in FIG. 13 , the p-type deep layer 70 has a linear portion 71 and a frame-shaped portion 72. The linear portion 71 of the p-type deep layer 70 constitutes a part of the second-conductivity-type layer, and the frame-shaped portion 72 constitutes a part of the second-conductivity-type ring. When the SiC semiconductor device is viewed from above, one or more linear portions 71 are arranged parallel to the p-type deep layer 51. When multiple linear portions 71 are provided, they are laid out so that the spacing DB2 between the linear portions 71 is equal to or smaller than the spacing DB1 between the p-type deep layers 51. When the SiC semiconductor device is viewed from above, the frame-shaped portion 72 is arranged to surround the cell region RC and the linear portion 71 and has a rectangular frame shape with rounded corners. The frame-shaped portion 72 is arranged concentrically with the p-type guard ring 21, and multiple frame-shaped portions 72 are provided in this embodiment.

[0108] The width of the p-type deep layer 70 is the same as that of the p-type deep layer 51. The spacing DB2 between the linear portions 71 may be the same as the spacing DB1 between the linear portions 5a of the p-type deep layer 5, but is set narrower than the spacing DB1 in this example. The spacing DB4 between the frame-shaped portions 72 may all be the same width, or may be different. The spacing DB4 between the frame-shaped portions 72 is preferably equal to or smaller than the spacing DB1 between the p-type deep layers 51 in the cell region RC. In particular, the spacing DB4out between the frame-shaped portions 72, which is a portion of the spacing DB4 located within a predetermined range from the boundary position of the mesa portion RM, is more preferably set narrower than the spacing DB2 between the linear portions 71 in the p-type deep layer 70.

[0109] Furthermore, the spacing DB3in between the p-type guard rings 21 located within a predetermined range from the boundary position of the mesa portion RM and the spacing DB4out between the frame-shaped portions 72 are narrower than the spacing DB2 between the linear portions 71 in the p-type deep layer 70. This makes it possible to deal with mask misalignment when forming the recess 20 for forming the mesa portion RM, as in the first embodiment.

[0110] Here, the p-type deep layer 70 is provided with the linear portions 71 and the frame-shaped portions 72, but it may be configured with only one of them. The number of linear portions 71 and frame-shaped portions 72 can also be set arbitrarily. Furthermore, the inside of the frame-shaped portion 72 may be laid out in a manner similar to the lattice-shaped portion 33, mesh-shaped portion 34, or dot-shaped portion 35 shown in the modified example of the first embodiment.

[0111] The SiC semiconductor device of this embodiment is configured as described above. In the SiC semiconductor device configured in this manner, the p-type layers deeply implanted by ion implantation, i.e., the p-type deep layer 51, the p-type deep layer 70, and the p-type guard ring 21, occupy 40% or less of the total area of ​​the chip constituting the SiC semiconductor device. This makes it possible to reduce the dose during ion implantation and suppress wafer warpage.

[0112] The width of the p-type deep layer 5 is set to 0.4 to 1.0 μm, similarly to the first embodiment. In this way, by limiting the range of implantation into the p-type deep layer 5 disposed above the p-type deep layer 51, wafer warpage can be further suppressed.

[0113] Next, a manufacturing method of the SiC semiconductor device of this embodiment will be described. The manufacturing method of the SiC semiconductor device of this embodiment is generally similar to that of the first embodiment, except for the steps of forming the first current spreading layer 50, the p-type deep layer 51, the p-type deep layer 70, the p-type guard ring 21, the second current spreading layer 60, and the p-type deep layer 5. Therefore, manufacturing steps other than these will be described with reference to the manufacturing steps described in the first embodiment.

[0114] First, similarly to the process shown in FIG. 8A described in the first embodiment, a semiconductor substrate having n + A n-type substrate 1 is formed on the main surface of the n-type substrate 1. - An epitaxially grown mold layer 2 is prepared, and the steps shown in Figures 14A to 14C are then carried out.

[0115] [Step shown in Figure 14A] n - A mask (not shown) having an opening corresponding to the region where the first current spreading layer 50 is to be formed is placed on the mold layer 2, and then n-type impurities are ion-implanted to form the first current spreading layer 50. Note that the first current spreading layer 50 may be formed by selective epitaxial growth instead of ion implantation. For example, - The first current spreading layer 50 may be formed by partially etching the mold layer 2 to form trenches at positions where the first current spreading layer 50 is to be formed, followed by epitaxial growth of an n-type layer and planarization of the layer.

[0116] [Step shown in Figure 14B] Next, the n-type semiconductor layer including the first current spreading layer 50 - A mask (not shown) having openings corresponding to the positions where the p-type deep layer 51, the p-type deep layer 70, and the p-type guard ring 21 are to be formed is placed on the mold layer 2, and then p-type impurities are ion-implanted, thereby forming the p-type deep layer 51, the p-type deep layer 70, and the p-type guard ring 21.

[0117] [Step shown in Figure 14C] Furthermore, the n-type deep layer 51, the p-type deep layer 70, and the p-type guard ring 21 - The second current spreading layer 60 is epitaxially grown on the type layer 2. Then, a mask (not shown) having an opening where the p-type deep layer 5 is to be formed is placed, and then p-type impurities are ion-implanted. This forms the p-type deep layer 5 that penetrates the second current spreading layer 60 and connects to the p-type deep layer 51 and the p-type deep layer 70.

[0118] Although subsequent steps are not shown, the SiC semiconductor device of this embodiment can be manufactured by performing manufacturing steps similar to the steps from FIG. 8D onwards described in the first embodiment.

[0119] In this manner, in this embodiment, the p-type deep layer 51 in the cell region RC, the p-type deep layer 70 in the connecting portion RJ, and the p-type guard ring 21 in the guard ring portion RG are n-type. -The p-type deep layer 51, the p-type deep layer 70, and the p-type guard ring 21 are provided on the surface layer of the mold layer 2, and are formed simultaneously by ion implantation. The p-type layers deeply implanted by ion implantation, that is, the p-type deep layer 51, the p-type deep layer 70, and the p-type guard ring 21, occupy 40% or less of the total area of ​​the chip constituting the SiC semiconductor device. This makes it possible to reduce the dose during ion implantation, and suppress wafer warpage.

[0120] (Third embodiment) A third embodiment will be described. This embodiment is different from the first embodiment in that it includes a junction barrier Schottky diode (hereinafter referred to as JBS) as the power element instead of the vertical MOSFET. Since the rest of the configuration is the same as the first embodiment, only the differences from the first embodiment will be described.

[0121] As shown in Figures 15 and 16, n + On the substrate 101 - The cell region RC has an n-type drift layer 102 formed therein. - A striped p-type deep layer 103 is formed in the drift layer 102, and a p-type guard ring 104 is formed in the guard ring portion RG surrounding the layer 103. A p-type connecting layer 105 is also formed in the connecting portion RJ between the cell region RC and the guard ring portion RG.

[0122] The p-type deep layer 103 constitutes at least a part of the second conductivity type layer, and -A plurality of p-type guard rings 104 are arranged at equal intervals in the second conductivity type drift layer 102, forming a stripe pattern. The p-type guard ring 104 constitutes at least a part of the second conductivity type ring, and is composed of a plurality of rectangular rings with rounded corners arranged concentrically. The p-type connecting layer 105 is composed of a plurality of frame-shaped rings that surround the periphery of the p-type deep layer 103 formed in the cell region. Here, the p-type connecting layer 105 is entirely composed of a frame-shaped portion, but a linear portion may be provided inside the frame-shaped portion. The linear portion of the p-type connecting layer 105 constitutes a part of the second conductivity type layer, and the frame-shaped portion constitutes a part of the second conductivity type ring. The p-type deep layer 103, p-type guard ring 104, and p-type connecting layer 105 are composed of n - The p-type impurity is formed by ion implantation into the p-type drift layer 102.

[0123] In addition, in the cell region RC and the connecting portion RJ, n - A Schottky electrode 106 corresponding to a first electrode is formed in contact with the surfaces of the p-type drift layer 102, the p-type deep layer 103, and the p-type connecting layer 105. That is, in this embodiment, a configuration is provided in which a plurality of p-type rings made of p-type layers in the shape of linear frames surrounding the cell region RC are provided, and the Schottky electrode 106 is arranged to cover a part of the inner periphery of each of the p-type rings. Of these multiple p-type rings, those in contact with the Schottky electrode 106 are called p-type connecting layers 105. In addition, of the multiple p-type layers, those not in contact with the Schottky electrode 106 and located outside it are called n-type connecting layers 105. - The portion disposed at the exposed position of the drift layer 102 is called a p-guard ring 104. The portion where the Schottky electrode 106 is formed becomes a Schottky electrode portion RS consisting of a cell region RC and a connecting portion RJ.

[0124] Furthermore, n + An ohmic electrode 107 corresponding to a second electrode is formed on the back surface of mold substrate 101. In this manner, the SiC semiconductor device of this embodiment is constructed.

[0125] In this configuration, the p-type deep layer 103, p-type guard ring 104, and p-type tie layer 105 each have a width of, for example, 0.4 to 1 μm. They may be formed with the same width or different widths. They also have a depth of, for example, about 2 μm. Their depths may be different, but are set to the same depth here. Furthermore, their intervals DC1 to DC4 are, for example, 0.6 to 1.5 μm. These intervals DC1 to DC4 may be the same, but are set to different depths here. Specifically, the interval DC2 of the p-type tie layer 105 in the tie portion RJ is narrower than the interval DC1 of the p-type deep layer 103 in the cell region RC. In this embodiment, the p-type connecting layer 105 is composed only of a frame-shaped portion. If the distance between the frame-shaped portions of the distance DC2 is defined as distance DC4, the distance DC4out located within a predetermined range from the boundary of the Schottky electrode RS is narrowest. The distances DC3 between the p-type guard rings 104 may be equal, but are narrower on the cell region RC side and wider toward the periphery to alleviate electric field concentration on the cell region RC side and direct equipotential lines toward the periphery. The distance DC3in between the p-type guard rings 104 located within a predetermined range from the boundary of the Schottky electrode RS is narrower than the distance DC1 between the p-type deep layers 103 in the cell region RC and is approximately equal to the distance DC4out. The widest portion of the distance DC3, i.e., the distance DC3out between the outermost p-type guard ring 104 and the p-type guard ring immediately inside it, is wider than the distances DC1 and DC2.

[0126] In this way, even in the SiC semiconductor device having the JBS as a power element, the widths and intervals of the p-type tie layer 105 and the p-type guard ring 104 are the same as those in the first embodiment.

[0127] That is, the spacing DC2 between the p-type connecting layers 105 is basically equal to or smaller than the spacing DC1 between the p-type deep layers 103, and the spacing DC2 is further reduced on the outer edge side of the Schottky electrode portion RS. Furthermore, the spacing DC3 between the p-type guard rings 104 is gradually increased toward the outer periphery. At the outermost periphery, the spacing DC3out between the p-type guard rings 104 is greater than the spacing DC1 between the p-type deep layers 103. This reduces the proportion of the p-type layers deeply implanted by ion implantation, i.e., the p-type deep layers 103, p-type connecting layers 105, and p-type guard rings 104, to 40% or less of the total area of ​​the chip constituting the SiC semiconductor device.

[0128] The SiC semiconductor device having such a structure is formed, for example, as follows. + On the substrate 101 - After epitaxially growing the n-type drift layer 102, - A mask (not shown) is placed on the surface of the n-type drift layer 102. Then, p-type impurities are ion-implanted from above the mask to form the p-type deep layer 103, the p-type guard ring 104, and the p-type connecting layer 105. After that, the n-type deep layer 103, the p-type guard ring 104, and the p-type connecting layer 105 are - After forming a film of an electrode material on the n-type drift layer 102, the film is patterned to form a Schottky electrode 106. + An ohmic electrode 107 is formed on the back surface of the mold substrate 101, thereby completing the SiC semiconductor device of this embodiment.

[0129] In manufacturing such a SiC semiconductor device, the p-type deep layer 103, the p-type guard ring 104, and the p-type tie layer 105 are formed by ion implantation. However, since the p-type deep layer 103, the p-type guard ring 104, and the p-type tie layer 105 are configured as described above, the SiC semiconductor device of this embodiment can also achieve the same effects as those of the first embodiment.

[0130] (Other embodiments) The present invention is not limited to the above-described embodiment, and can be modified as appropriate within the scope of the claims.

[0131] For example, in each of the above embodiments, n - The p-type deep layer 5 and the like are formed by ion implantation of p-type impurities from the surface of the n-type layer 2. + It is also possible to ion-implant p-type impurities from the surface of the p-type source region 4. However, in this case, ion implantation is performed at a higher acceleration voltage, which increases the influence of wafer warpage. Therefore, when the influence of wafer warpage is taken into consideration, it is necessary to limit the allowable range of the dose and width of the p-type deep layer 5, etc. to n. - This may be narrower than when p-type deep layer 5 or the like is formed by ion-implanting p-type impurities from the surface of mold layer 2.

[0132] Furthermore, in the above-described embodiments, the MOSFET 100 and JBS are given as examples of semiconductor elements provided in the cell region RC of the SiC semiconductor device. However, other semiconductor elements may be formed as long as they have a cell region RC and a peripheral region RO and a p-type deep layer is formed in the connecting portion RJ of the peripheral region RO. Examples of such semiconductor elements include an IGBT. Furthermore, in the above-described embodiments, an n-channel type MOSFET 100 in which the first conductivity type is n-type and the second conductivity type is p-type has been described as an example, but a p-channel type MOSFET 100 in which the conductivity types of the respective components are reversed may also be used. Furthermore, the IGBT is not limited to an element having a trench gate structure, and may be a planar type element. Note that the IGBT may be an n-channel type MOSFET in the above-described embodiments. + The only difference is that the conductivity type of the substrate 1 is changed from n-type to p-type, and the other structures and manufacturing methods are the same as those of the above-described embodiments.

[0133] In the first embodiment, the p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21 have the same width, but they may have different widths. In the second embodiment, the p-type deep layer 51, the p-type deep layer 70, and the p-type guard ring 21 have the same width, but they may have different widths. In the third embodiment, the p-type deep layer 103, the p-type guard ring 104, and the p-type connecting layer 105 have the same width, but they may have different widths. Furthermore, in the first to third embodiments, the widths of the p-type guard rings 21 and the p-type guard rings 104 are the same, but the width of the p-type guard rings 21 may be structured so that it increases toward the periphery.

[0134] Furthermore, in each of the above embodiments, the case where SiC is used as the semiconductor material has been described, but the present invention can also be applied to semiconductor devices that use other semiconductor materials such as Si.

[0135] When indicating the crystal orientation, a bar (-) should normally be placed above the desired number. However, due to limitations on expression based on electronic filing, in this specification, a bar will be placed before the desired number. [Explanation of symbols]

[0136] 1n + Mold board 2n - mold layer 3 p-type base region 4n + Type Source Area 5, 30 p-type deep layer 8 gate electrode 9 Source electrode 10 Interlayer insulating film 21 p-type guard ring

Claims

1. A semiconductor device having a cell region (RC) in which a semiconductor element (100) is formed in a chip (Ch), a guard ring portion (RG) surrounding the periphery of the cell region, and an outer periphery region (RO) including a connecting portion (RJ) located between the guard ring portion and the cell region, The semiconductor device includes a first or second conductivity type substrate (1, 101) having a front surface and a back surface, and a first conductivity type drift layer (2, 50, 60, 102) formed on the front surface side of the substrate and having a lower impurity concentration than the substrate, The cell region includes: a second conductivity type layer (5, 5a, 51, 103) formed in the drift layer and including a portion formed in a stripe shape with one direction as a longitudinal direction; a first electrode (9, 106) electrically connected to the second conductivity type layer; a second electrode (11, 107) formed on the back surface side of the substrate; a vertical semiconductor element that allows a current to flow between the first electrode and the second electrode; The connecting portion also has The drift layer is provided with second conductivity type layers (31, 33 to 35, 71) formed in a line shape, The guard ring portion or the guard ring portion and the connecting portion has a second conductivity type ring (21, 32, 72, 104, 105) is provided, the second conductivity type ring (21, 32, 72, 104, 105) being formed in the drift layer and having a plurality of linear frame shapes surrounding the cell region, at least a portion of which located on the outer periphery constitutes a guard ring (21, 104); the second conductivity type layer and the second conductivity type ring are formed by ion implantation layers, and the proportion of the second conductivity type layer and the second conductivity type ring to the total area of ​​the chip is set to 40% or less; the second conductive type layer provided in the connecting portion includes a linear portion (31) whose longitudinal direction is the same as the longitudinal direction of the second conductive type layer provided in the cell region; the second conductivity type ring is disposed in the guard ring portion and the connecting portion, a mesa portion (RM) is formed in which the cell region and the connecting portion protrude beyond the guard ring portion; The guard rings are spaced apart by larger intervals (DA3, DB3) from the inner periphery toward the outer periphery, The interval between the guard rings is a third interval (DA3, DB3), A semiconductor device in which the relationship of the widest part of the third interval located on the outermost periphery (DA3out, DB3out) > the part of the third interval located within a predetermined range from the boundary position of the mesa portion (DA3in, DB3in) is satisfied.

2. The interval between the second conductive type layers arranged in the cell region is defined as a first interval (DA1, DB1), 2. The semiconductor device according to claim 1, wherein the relationship is such that the widest portion of the third interval located at the outermost periphery is greater than the first interval and the third interval is greater than the portion of the third interval located within a predetermined range from the boundary position of the mesa portion.

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