Etching metals during processing of semiconductor structures

Abstract

In one embodiment, a method for processing a semiconductor structure includes forming a patterning layer on a copper layer to be etched. The copper layer is disposed on a substrate. The method includes patterning the copper layer using the patterning layer as an etching mask by performing a cyclic etching process to form recesses in the copper layer. The cyclic etching process includes forming a passivation layer on the exposed surface of the copper layer by exposing the exposed surface of the copper layer to chlorine gas in a first etching step. The passivation layer replaces at least a portion of the surface layer of the copper layer. The cyclic etching process subsequently includes etching the passivation layer using a first plasma including a noble gas in a second etching step. Each cycle of the cyclic etching process extends the recesses in the copper layer.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of U.S. Non-Provisional Patent Application No. 17 / 339,436, filed June 4, 2021, which is incorporated herein by reference in its entirety.

[0002] The present disclosure relates generally to semiconductor manufacturing and, in particular embodiments, to etching metals during processing of semiconductor structures. [Background technology]

[0003] Generally, semiconductor devices such as integrated circuits (ICs) are fabricated by sequentially depositing and patterning layers of dielectric, conductive, and semiconducting materials on a semiconductor substrate using photolithography and etching to form structures that operate as circuit components (e.g., transistors, resistors, and capacitors) and interconnect elements (e.g., conductive lines, contacts, and vias). Examples of metals used to form conductive features in semiconductor devices, such as those in metallization layers, include copper, aluminum, and the like.

[0004] The semiconductor industry is repeatedly shrinking the minimum feature size of semiconductor devices to a few nanometers to increase component packing density. This shrinkage to a few nanometers has exacerbated various challenges associated with semiconductor manufacturing. Manufacturing processes, including plasma and other processes, are expected to deliver precise dimensions (e.g., linewidth, etch depth, and film thickness) in the nanometer range, along with precisely controlled features, such as conformality, anisotropy, selectivity, surface and line edge roughness, and edge profile, often with atomic-scale dimensions, uniformly across wide (e.g., 300 mm) wafers. Summary of the Invention [Means for solving the problem]

[0005] In one embodiment, a method for processing a semiconductor structure includes forming a patterning layer on a copper layer to be etched. The copper layer is disposed on a substrate. The method includes patterning the copper layer using the patterning layer as an etching mask by performing a cyclic etching process to form recesses in the copper layer. The cyclic etching process includes forming a passivation layer on the exposed surface of the copper layer by exposing the exposed surface of the copper layer to chlorine gas in a first etching step. The passivation layer replaces at least a portion of the surface layer of the copper layer. The cyclic etching process subsequently includes etching the passivation layer using a first plasma including a noble gas in a second etching step. Each cycle of the cyclic etching process extends the recesses in the copper layer.

[0006] In one embodiment, a method for processing a semiconductor structure includes receiving a substrate having a copper-containing layer formed thereon. The method includes performing a cyclic etching process to incrementally etch a portion of the copper-containing layer. The copper-containing layer has an exposed target surface that defines the portion of the copper-containing layer to be etched. The cyclic etching process includes exposing the substrate having the copper-containing layer to chlorine gas (Cl) in a chlorine exposure step to convert the portion of the copper-containing layer to a copper chloride (CuCl) structure. The cyclic etching process then includes exposing the substrate having the copper-containing layer to a first plasma in a plasma etching step. The first plasma includes a noble gas and is directed toward the exposed target surface of the copper-containing layer with sufficient energy to remove at least a portion of the CuCl structure from the copper-containing layer.

[0007] In one embodiment, a method for processing a semiconductor structure includes forming a patterning layer on a copper layer to be etched. The copper layer is disposed on a substrate. The method includes patterning the copper layer using the patterning layer as an etching mask by performing a cyclic etching process to incrementally form recesses in the copper layer. The cyclic etching process includes exposing the substrate having the copper layer to chlorine gas (Cl) in a chlorine exposure step to form CuCl structures on one or more exposed surfaces of the copper layer. The cyclic etching process subsequently includes exposing the substrate having the copper layer to an argon-containing plasma directed at a target exposed surface of the copper layer in a plasma etching step with sufficient energy to remove at least a portion of the CuCl structures on one or more exposed surfaces of the copper layer from the copper layer and extend recesses into the copper layer. In a first instance of the chlorine exposure step, the one or more exposed surfaces of the copper layer include a target exposed surface, which is an upper surface of the copper layer at the bottom of the recess. At subsequent instances of the chlorine exposure step, one or more exposed surfaces of the copper layer include the target exposed surface and a sidewall surface of the copper layer within the recess. [Brief explanation of the drawings]

[0008] For a more complete understanding of the present disclosure and its advantages, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

[0009] [Figure 1A] 1A-1C illustrate cross-sectional and plan views of a semiconductor structure during a process for treating the semiconductor structure according to an embodiment of the present disclosure. [Figure 1B] 1A-1C illustrate cross-sectional and plan views of a semiconductor structure during a process for treating the semiconductor structure according to an embodiment of the present disclosure. [Figure 1C] 1A-1C illustrate cross-sectional and plan views of a semiconductor structure during a process for treating the semiconductor structure according to an embodiment of the present disclosure. [Figure 2A]2A-2E show cross-sectional views of a semiconductor structure during a cyclic etching process for treating the semiconductor structure according to an embodiment of the present disclosure. [Figure 2B] 2A-2E show cross-sectional views of a semiconductor structure during a cyclic etching process for treating the semiconductor structure according to an embodiment of the present disclosure. [Figure 2C] 2A-2E show cross-sectional views of a semiconductor structure during a cyclic etching process for treating the semiconductor structure according to an embodiment of the present disclosure. [Figure 2D] 2A-2E show cross-sectional views of a semiconductor structure during a cyclic etching process for treating the semiconductor structure according to an embodiment of the present disclosure. [Figure 2E] 2A-2E show cross-sectional views of a semiconductor structure during a cyclic etching process for treating the semiconductor structure according to an embodiment of the present disclosure. [Figure 3A] 3A-3C show example details of a semiconductor structure during a cyclic etching process of a process for etching metal during processing of the semiconductor structure according to an embodiment of the present disclosure. [Figure 3B] 3A-3C show example details of a semiconductor structure during a cyclic etching process of a process for etching metal during processing of the semiconductor structure according to an embodiment of the present disclosure. [Figure 3C] 3A-3C show example details of a semiconductor structure during a cyclic etching process of a process for etching metal during processing of the semiconductor structure according to an embodiment of the present disclosure. [Figure 4] 1 illustrates an exemplary method for processing a semiconductor structure according to an embodiment of the present disclosure. [Figure 5] 1 illustrates an exemplary method for processing a semiconductor structure according to an embodiment of the present disclosure. [Figure 6] 1 shows a general overview of an exemplary plasma processing system, in accordance with certain embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0010] For many years, and still today, chipmakers have used aluminum to form conductive features such as conductive lines, conductive contacts, and conductive vias in semiconductor devices. As device sizes continue to shrink, the use of aluminum for certain conductive features has become apparent. For example, as the critical dimensions of lines and vias become smaller, the resistance of the metal increases, which can increase the resistance-capacitance (RC) delay of the interconnect. Copper generally exhibits lower resistance than aluminum. In addition, copper can be said to be more durable than aluminum and exhibits higher resistance to electromigration than aluminum. This higher resistance to electromigration can allow a copper conductor of a given size to carry a higher current compared to an aluminum conductor of the same given size. As feature sizes become smaller, the ability of copper conductors to carry a higher current can be advantageous. Joule heating associated with electromigration can further exacerbate electromigration, so a metal with lower resistance can be advantageous.

[0011] Other metals, such as gold and silver, may offer similar benefits to copper, but at a greater cost. Given these advantages, copper has become, and generally remains, the preferred choice for forming conductive features in semiconductor devices, particularly in interconnect layers.

[0012] However, using copper in semiconductor devices, whether for interconnects or otherwise, also presents challenges. For example, copper can be difficult to etch using techniques that may be suitable for semiconductor manufacturing and in a mass production environment.

[0013] Traditionally, copper structures in semiconductor devices are formed using additive processes rather than subtractive processes. For example, copper conductive features may be formed using a damascene or dual damascene process. A damascene process is an additive process that involves etching openings in a layer (e.g., a dielectric layer) in which the copper conductive features will be formed and then filling those openings with copper, often depositing one or more barrier layers and performing one or more intervening and / or subsequent etches (e.g., chemical-mechanical polishing). Damascene processes present challenges at smaller device sizes (including potentially an inability to achieve certain small pitch sizes and poor gap filling of damascene recesses), and many of the processes involved in damascene processes can damage other materials, such as dielectric materials (e.g., low-k materials). Furthermore, damascene processes involve complex etch integration and include forming etch-stop barrier (capping) layers that consume valuable dimensional budgets, thereby becoming even more problematic at smaller node sizes.

[0014] Etching copper using subtractive processes to form copper conductive features presents other challenges.

[0015] For example, one subtractive method for etching copper involves exposing a copper layer to a chlorine plasma, which forms copper chloride salts on the surface of the copper layer being etched. These salts are not volatile and tend to grow. A wet removal is performed to remove the generated salt layer. This wet removal of the salt layer involves exposing the semiconductor substrate to chemicals that lack selectivity, which means that these chemicals can unintentionally etch materials other than copper in an undesirable manner and cause surface damage to the resulting copper structures and other surfaces. Additionally, the salt growth is isotropic and, when mediated by plasma and chlorine radicals, the growth is not self-limiting. Furthermore, such a process is not feasible for mass production.

[0016] As another example of a subtractive method for etching copper, sequential plasma etching of copper also presents problems, with the resulting morphology being a key issue. Plasma processes, in which ions are used to continuously remove copper chlorides that form during exposure of copper to chlorine plasma (e.g., to remove copper chlorides faster than they can accumulate), have poor morphology due to low effective chlorine coverage. Under these conditions, etching by-products may not be volatile and may require significant ion energy. Removing copper chlorides may result in sputtering and mixing of some chemical components. For example, etching copper using sequential reactive ion etching (RIE) processes may use high temperatures to react the copper with the plasma. However, these high temperatures may be harmful to semiconductor features. For example, sequential plasma processes and their associated high temperatures can adversely affect the IC devices being formed (e.g., through dopant diffusion or other undesirable effects), degrade etch masks (e.g., patterned photoresist layers) overlying the copper layer (e.g., affecting the profile of the features being etched), and / or cause stress migration in lower layers. Additionally, some dry etch processes use chlorine, which can contaminate or damage copper. Furthermore, in sequential processes, copper can redeposit, thereby exacerbating surface roughness and etch front profile problems.

[0017] For these and possibly other reasons, the combination of copper and chlorine has been largely viewed as impractical.

[0018] Due at least in part to the lack of a viable subtractive etch process for etching copper and forming copper conductive features, additive damascene processes remain the primary approach for forming copper conductive features, despite the many problems associated with damascene processes. Thus, as conventional dual damascene methods have reached, or may soon reach, the limits of their usefulness at smaller feature sizes, the semiconductor manufacturing industry has shown renewed interest in subtractive copper etch processes.

[0019] In certain embodiments of the present disclosure, a cyclic etching process provides a subtractive process that incrementally etches a copper layer. For example, the cyclic etching process can be used to etch one or more recesses in a copper or other metal layer. As described in more detail below, rather than a single plasma or other etching step, the cyclic etching process of embodiments of the present disclosure can include repeatedly performing two main steps to incrementally form features in a copper (or other metal) layer: a passivation layer formation step (e.g., a chlorine exposure step) that forms a passivation layer on exposed surfaces of the copper layer by exposing the exposed surfaces to chlorine gas in a plasma or thermal process, and an etching step that etches the passivation layer to remove portions of the copper layer (e.g., forming recesses in the copper layer and finally forming features, such as conductive features, in the copper layer). In certain embodiments, the cyclic etching process for etching copper can be used in a mass production setting.

[0020] 1A-1C show cross-sectional and plan views of a semiconductor structure 104 during a process 100 for processing the semiconductor structure 104 in accordance with an embodiment of the present disclosure. In the illustrated example, the process 100 includes stages 102a-102f of processing the semiconductor structure 104. The semiconductor structure 104 is merely one example of a structure that may be processed in accordance with the disclosed techniques, and the present disclosure contemplates processing any suitable semiconductor device. Throughout this disclosure, a "semiconductor structure" may also be referred to as a semiconductor device, a substrate, or a semiconductor wafer (or simply a wafer).

[0021] At step 102a, the semiconductor structure 104 includes a substrate 106, a copper-containing layer 108 formed on the substrate 106, and a patterned layer 110 (the layer to be patterned at step 102a) formed on the copper-containing layer 108 and the substrate 106. Although these particular layers are shown and described, the present disclosure contemplates that the semiconductor structure 104 may include any suitable layers. For example, the semiconductor structure 104 may include one or more intervening layers between the substrate 106 and the copper-containing layer 108 and / or between the copper-containing layer 108 and the patterned layer 110.

[0022] The substrate 106 may be formed using any suitable semiconductor fabrication step or combination of semiconductor fabrication steps. The substrate 106 may include silicon, silicon germanium (SiGe), silicon carbide (SiC), a compound semiconductor (e.g., gallium nitride (GaN), gallium arsenide (GaAs), indium arsenide (InGaAs), indium phosphide (InP), etc.), or a combination of these materials. The present disclosure contemplates that the substrate 106 may comprise any suitable material. The substrate 106 may include a silicon-on-insulator (SOI) structure, a semiconductor wafer (e.g., a silicon wafer), or a die formed from a wafer. In some embodiments, some or all of the substrate 106 may be amorphous, polycrystalline, or single crystalline. The substrate 106 may be doped, undoped, or include both doped and undoped regions.

[0023] Substrate 106 may include any suitable type of substrate. In some embodiments, substrate 106 includes one or more IC elements, such as one or more transistors, one or more diodes, one or more capacitors, one or more resistors, and / or other electronic components. These IC elements may have any suitable design, including any suitable planar or non-planar, and two-dimensional or three-dimensional (e.g., fin field effect transistor (FinFET), gate-all-around (GAA)FET, etc.) designs. In some embodiments, these IC elements may be front-end (FEOL) devices.

[0024] Additionally, substrate 106 may include one or more metallization layers. In some embodiments, whether or not considered a metallization layer (or as including a metallization layer), substrate 106 includes one or more conductive features, such as one or more conductive contacts, one or more conductive vias, one or more conductive lines, and / or one or more other conductive features.

[0025] A copper-containing layer 108 is formed over the substrate 106. In some embodiments, the copper-containing layer 108 is made of pure copper (100% copper), although the present disclosure contemplates that the copper-containing layer 108 may comprise copper with an amount of one or more other materials. In some embodiments, the copper-containing layer 108 comprises 100% copper, or copper and less than about 20 parts per million (ppm) of one or more other materials (e.g., sulfur, chlorine, carbon, nitrogen, silver, aluminum, or another material). The copper-containing layer 108 may comprise a metal or a metal alloy, and for purposes of this description, metal and metal alloy may be used interchangeably.

[0026] The copper-containing layer 108 is a layer that will be patterned into one or more features that may serve as conductive features in a semiconductor device being fabricated through processing of the semiconductor structure 104. The present disclosure contemplates that the features etched into the copper-containing layer 108 may be any suitable features. For example, while the present disclosure primarily describes "recesses," it should be understood that other suitable features, including lines, holes, trenches, vias, and / or other suitable structures (whether or not considered "recesses"), may be formed in the copper-containing layer 108 using embodiments of the present disclosure. In some embodiments, the copper-containing layer 108 is intended to be part of a back-end (BEOL) stack, such as a metallization layer of the BEOL stack.

[0027] The copper-containing layer 108 may be deposited using any technique suitable for depositing materials. Suitable deposition processes used to form the copper-containing layer 108 may include a spin-on coating process, a chemical vapor deposition (CVD) process, a plasma-enhanced chemical vapor deposition (PECVD) process, an atomic layer deposition (ALD) process, a physical vapor deposition (PVD) process, a chemical solution deposition process, or other processes.

[0028] In some embodiments, one or more liner layers may be deposited (e.g., on the surface of the substrate 106) prior to depositing the copper-containing layer 108. The liner layers may also be referred to as barrier layers and may include, for example, titanium nitride (TiN) and / or tantalum nitride (TaN) layers and may have a thickness of about 0.3 to about 3.5 nm. Any suitable number of liner layers of any suitable type of material may be used. In some embodiments, the one or more liner layers may be considered part of the substrate 106 (e.g., as a surface layer of the substrate 106). In some embodiments, the one or more liner layers may reduce or eliminate copper diffusion into another layer (e.g., into other portions of the substrate 106) and / or may act as an etch stop layer during appropriate fabrication steps. One or more of the liner layers may be a capping layer, such as a cobalt (Co)-tungsten (W)-phosphorus (P) (CoWP) capping layer or a Co-W-boron (B) (CoWB) capping layer.

[0029] The semiconductor structure 104 includes a patterned layer 110. As shown in step 102a, the patterned layer 110 is a layer to be patterned because it has yet to be patterned. In some embodiments, the patterned layer 110 is made of a material suitable for use as a hard mask. For example, the patterned layer 110 may include an organic material (such as amorphous carbon or an organosiloxane) or an inorganic material (such as silicon nitride (SiN), silicon oxynitride (SiON), or TiN). In some embodiments, the patterned layer 110 includes multiple layers of materials. The patterned layer 110 may be deposited using any technique suitable for depositing materials. Suitable deposition processes may include a spin-on coating process, a CVD process, a PECVD process, an ALD process, a PVD process, a chemical solution deposition process, or other processes. For example, the patterned layer 110 may be or include an amorphous carbon layer formed by a CVD or ALD process.

[0030] Referring to step 102b, patterning layer 110 is patterned to provide a suitable mask for forming features (e.g., recesses) in the underlying layer (in this example, copper-containing layer 108). The present disclosure contemplates patterning patterning layer 110 in any suitable manner.

[0031] By way of example only, a photoresist layer may be formed over patterning layer 110 (e.g., prior to patterning patterning layer 110), and the photoresist layer may be patterned according to a desired pattern for patterning layer 110 to facilitate formation of respective features in patterning layer 110. The photoresist layer may be patterned in any suitable manner, such as using extreme ultraviolet lithography or any other suitable lithography technique.

[0032] In some embodiments, one or more intervening layers may be formed between the photoresist layer and the patterning layer 110 (prior to patterning the patterning layer 110) for a variety of purposes. Such intervening layers may include, for example, a SiON layer, an organic dielectric layer, a silicon antireflective coating (SiARC) or other antireflective coating, and / or any other suitable intervening layer. While these particular intervening layers are described, the semiconductor structure 104 may be free of such intervening layers or may include different intervening layers (with or without these exemplary intervening layers).

[0033] The patterned layer 110 can be formed by performing an etching process and using the photoresist layer (and any appropriate intervening layers) as an etching mask. Through this technique, the pattern defined by the photoresist layer is transferred to the patterned layer 110. The photoresist layer and any intervening layers may be removed as part of this process, or may be removed subsequently. In some embodiments, the patterned layer 110 serves as an etching mask when forming features from the copper-containing layer 108. In other words, features in the patterned layer 110 may cause corresponding features in the copper-containing layer 108 to remain during a subsequent etching process, as described below. For example, the patterned layer 110 includes recesses 112 that are used to form corresponding recesses 112 in the copper-containing layer 108 in a subsequent stage of the process 100. Additionally, patterned layer 110 may preserve portions of copper-containing layer 108 in a subsequent etching step to facilitate the formation of conductive features (e.g., conductive lines, vias, or contacts) in those preserved portions.

[0034] Referring to the steps in process 100 following step 102b, as shown in FIG. 1B, an embodiment of the present disclosure uses a cyclic etching process 113 to pattern copper-containing layer 108, in this example using patterning layer 110 as an etching mask. In the embodiment shown in FIGS. 1A-1C (and particularly FIG. 1B), cyclic etching process 113 includes two main steps. The first step is a passivation layer formation step, e.g., as shown in step 102c, in which a passivation layer is formed on one or more exposed surfaces of copper-containing layer 108 using chlorine gas. The second step is an etching step, e.g., as shown in step 102d, in which the passivation layer is removed from at least a portion of copper-containing layer 108, thereby removing at least a portion of copper-containing layer 108. Steps 102c and 102d are described in more detail below. In some embodiments, prior to one or more occurrences of step 102c, a surface oxide may be present on the exposed surface of copper-containing layer 108. To substantially or completely remove the surface oxide, a suitable removal process, such as an argon sputtering step, may be performed.

[0035] In stage 102c, in a first etching step of the cyclic etching process 113, a passivation layer 116 is formed on at least a portion of the copper-containing layer 108. In one embodiment, the passivation layer 116 is formed on an exposed surface of the copper-containing layer 108. In a first pass of the cyclic etching process 113, the exposed surface of the copper-containing layer 108 can be the top surface 114 of the copper-containing layer 108 (e.g., at the bottom of a recess in the patterned layer 110 that exposes the copper-containing layer 108), and the passivation layer 116a can be formed on that exposed top surface of the copper-containing layer 108. In subsequent passes of the cyclic etching process 113, additional surfaces of the copper-containing layer 108 are exposed, and the passivation layer 116 can also be formed on those additional exposed surfaces of the copper-containing layer 108 (e.g., shown and described later as passivation layers 116b and 116c). For ease of description, passivation layer 116 may be generally referred to as passivation layer 116, with particularity being given to passivation layers 116a, 116b, and / or 116c, as may be suitable for a given use in some cases. Formation of passivation layer 116 on the sidewall surfaces of copper-containing layer 108 is shown and described below with reference to, for example, Figures 2A-2E.

[0036] The passivation layer 116 may be formed by exposing the semiconductor structure 104 (and surfaces exposed thereby, such as the top surface 114 of the copper-containing layer 108) to a chlorine treatment 115 containing chlorine gas (Cl). The passivation layer 116 may include compounds formed from copper atoms on the exposed surface (e.g., top surface 114) of the copper-containing layer 108 and the Cl to which those copper atoms are exposed. The passivation layer 116 may include Cu atoms formed on one or more exposed surfaces (e.g., top surface 114) of the copper-containing layer 108. y Cl x For example, one or more chlorine particles may combine with one or more copper atoms at or near the surface of the copper-containing layer 108 to form Cu atoms at or near the surface of the copper-containing layer 108. y Cl xA structure (e.g., a partial or soft surface state) may be formed, thereby forming passivation layer 116. Passivation layer 116 thus consumes at least a portion of copper-containing layer 108, such that subsequent etching of passivation layer 116 (e.g., in stage 102d of cyclic etching process 113) removes a portion of copper-containing layer 108. y Cl x For the structure, y and x are integers greater than or equal to 1. In some embodiments, one or more of 1≦y≦6 or 1≦x≦6 is true. As just a few specific examples, Cu is formed y Cl x The structure may include CuCl, CuCl2, CuCl3, CuCl4, Cu2Cl, and / or Cu3Cl. It should be understood that these values ​​for y and x and combinations thereof are given by way of example only.

[0037] Neutral chlorine gas (Cl) may combine with copper in a self-limiting manner. By exposing the exposed surface of the copper-containing layer 108 to chlorine gas, a self-limiting passivation layer 116 of chlorine and copper compounds may be formed on the exposed surface of the copper-containing layer 108. In some embodiments, by exposing the exposed surface of the copper-containing layer 108 to chlorine gas, a monolayer of chlorine and copper compounds may be formed on the exposed surface of the copper-containing layer 108. It should be understood that a monolayer does not necessarily imply that 100 percent coverage of chlorine and copper compounds is achieved.

[0038] The passivation layer 116 may be formed in any suitable manner. The present disclosure contemplates exposing the semiconductor structure 104 (and the surface of the copper-containing layer 108 exposed thereby) to a chlorine treatment 115 (e.g., chlorine gas) in any suitable manner, including, for example, using a thermal process, a plasma process, or any other suitable type of process. That is, the chlorine treatment 115 may be performed as a thermal process, a plasma process, or any other suitable type of process.

[0039] In some embodiments, the chlorine treatment 115 may be performed to convert the semiconductor structure 104 (and the surfaces of the copper-containing layer 108 exposed thereby) to Cu on one or more exposed surfaces of the copper-containing layer 108 (e.g., the top surface 114). y Cl x It is a thermal process that involves exposure to chlorine gas at an appropriate temperature to form the structure.

[0040] In one embodiment, the chlorine treatment 115 includes forming a plasma from chlorine gas and exposing the semiconductor structure 104 (and the surfaces of the copper-containing layer 108 exposed thereby) to the chlorine gas in the generated plasma to deposit Cu on one or more exposed surfaces (e.g., the top surface 114) of the copper-containing layer 108. y Cl x forming a structure.

[0041] The process used to form the passivation layer 116 may be an anisotropic process or an isotropic process, depending on the particular implementation. An anisotropic process, such as an anisotropic plasma process, may result in the passivation layer 116 being formed only on certain exposed surfaces of the copper-containing layer 108, or alternatively, may be formed with different thicknesses on different surfaces of the copper-containing layer 108, if desired. An isotropic process, such as an isotropic plasma process or a thermal process, may result in the formation of a passivation layer 116 having a generally uniform (but not necessarily identical) thickness on potentially all exposed surfaces of the copper-containing layer 108.

[0042] Referring to stage 102d, in a second etching step of the cyclic etching process 113, some or all of the passivation layer 116 is etched to incrementally form / extend recesses 112 in the copper-containing layer 108. In one embodiment, the process for etching the passivation layer 116 is a plasma etch process using a plasma generated from a noble gas, such as argon, which selectively etches the passivation layer 116 relative to copper.

[0043] In some embodiments (e.g., where the goal may be to extend recess 112 down to substrate 106), the etching step of stage 102d is designed to be selective such that it removes a portion of copper-containing layer 108 through recess 112 when recess 112 opens down to substrate 106, without etching (or with minimal etching) the top material of substrate 106. Thus, in such examples, the etching step of cyclic etching process 113 is designed to be self-terminating once recess 112 in copper-containing layer 108 is fully formed, such that the top surface of substrate 106 is exposed at the bottom of recess 112 in some embodiments.

[0044] In one embodiment, the etching step of stage 102d is a plasma etching step performed using plasma 118. In particular embodiments, the plasma 118 used to etch passivation layer 116 comprises argon or another noble gas. Additional details of the exemplary etching process of stage 102d are described below in conjunction with the exemplary passivation layer 116 deposition process of stage 102c.

[0045] The etching step of stage 102d may initially expose, or further expose, additional surfaces of the copper-containing layer 108. For example, the etching step of stage 102d may initially expose, or further expose, the surfaces of the sidewalls 119 of the copper-containing layer 108 of the recesses 112. Once exposed (e.g., after the recesses 112 have been opened in the copper-containing layer 108 and have exposed the surfaces of the sidewalls 119 of the copper-containing layer 108 within the recesses 112), a passivation layer 116 may be formed on such additional surfaces (e.g., the surfaces of the sidewalls 119) during a subsequent performance of stage 102c. In some embodiments, prior to the cyclic etching process 113 and without first forming the passivation layer 116, a partial etch of the copper-containing layer 108 may be performed to begin forming the recesses 112 in the copper-containing layer 108 according to the pattern defined by the patterning layer 110. In other embodiments, such a partial etch is not performed initially.

[0046] The etching process used in the etching step of stage 102d may be an anisotropic etching process, depending on the specific implementation. The anisotropic etching process, such as an anisotropic plasma process, may etch in a specific direction, such as downward, of the recess 112 to extend it further into the copper-containing layer 108 by removing the passivation layer 116a at the top surface 114 of the copper-containing layer 108.

[0047] As indicated by circular arrows 120, the steps of the cyclical etching process 113 (e.g., the passivation layer 116 formation step of stage 102c and the etching step of stage 102d) may be repeated one or more times to incrementally form recesses 112 in the copper-containing layer 108. It should be understood that the present disclosure contemplates performing the cyclical etching process 113 any suitable number of times.

[0048] In some embodiments, each cycle of the cyclical etching process 113 may further extend the recess 112 into the copper-containing layer 108. The appropriate number of cycles to perform the cyclical etching process 113 for a given embodiment depends on a variety of factors, including the exact material of the copper-containing layer 108, the material of the passivation layer 116, the desired dimensions of the recess 112, the allowable amount of time that the cyclical etching process 113 may introduce into the overall process of fabricating the semiconductor structure 104, the materials (e.g., gases) used as part of the cyclical etching process 113, including the materials used to deposit the passivation layer 116 and the materials used to etch the passivation layer 116, and / or other suitable factors.

[0049] In one embodiment, the appropriate number of cycles for performing the cyclical etching process 113 is predetermined (prior to running production manufacturing) by processing a test wafer. The wafer (e.g., semiconductor structure 104) may be sampled at various stages to measure aspects of the wafer, including the dimensions of the features (e.g., recesses 112) being etched and one or more possible pattern defects. For example, samples may be analyzed after one or more stages 102.

[0050] As a more detailed example, a first wafer may be sampled after a first predetermined number of cycles of the cyclic etching process 113, stopping after an instance of the etching step of stage 102d. Measurements of properties such as critical dimensions of the recesses 112 and measurements of possible pattern defects may be compared to desired values ​​for those properties (e.g., technology node parametric). Additionally, a determination may be made whether a surface of the substrate 106 is exposed at the bottom of the recesses 112 (hereinafter referred to as the upper surface 122). A determination may then be made whether to test a new wafer after a second predetermined number of cycles that is less than or greater than the first predetermined number of cycles, depending on the results of the comparison and other factors (e.g., any of the other factors listed above). This process of sampling may be repeated until an appropriate number of cycles is determined for a given implementation.

[0051] Additionally, adjustments to the steps of the cyclic etching process 113 may be determined as part of this testing and analysis. For example, different exposure times of the semiconductor structure 104 to the chlorine treatment 115 and / or plasma 118 may be analyzed to determine the effect on the dimensions of the recess 112, the time of the cyclic etching process 113, and / or other factors.

[0052] Properties such as dimensions of the semiconductor structure 104 may be measured using optical techniques such as scatterometry, scanning electron microscope (SEM), transmission electron microscope (TEM), high-resolution TEM (HR-TEM), scanning probe microscope (SPM), atomic force microscope (AFM), scanning tunneling microscope (STM), or other suitable devices.

[0053] The above-described techniques for determining an appropriate number of cycles for the cyclic etching process 113 are merely examples. This disclosure contemplates any suitable technique for determining an appropriate number of cycles for performing the cyclic etching process 113.

[0054] Referring to the process conditions and related parameters for the passivation layer 116 formation step of Step 102c and the etching step of Step 102d, as described above, in some embodiments, both the passivation layer 116 formation step of Step 102c and the etching step of Step 102d are performed using a plasma process. In some other embodiments, the passivation layer 116 formation step of Step 102c may be performed using a thermal evaporation process (or another suitable type of deposition process), and the etching step of Step 102d may be performed using a plasma process.

[0055] In some embodiments, the steps of the cyclic etch process 113 (e.g., the deposition and etching associated with stages 102c and 102d) may be performed in the same process chamber of a process tool. By way of example, the process tool may be an inductively coupled plasma (ICP) tool, a capacitively coupled plasma (CCP) tool, a helicon wave source (HWS) tool, a helical resonator, a spiral resonator, a microwave or electron beam generated plasma tool, a thermal treatment tool, or any other suitable type or combination of types of tools. Purging of gases in the process chamber may or may not be performed between steps of the cyclic etch process 113, depending on the details of the implementation. For example, purging the process chamber between stages 102c and 102d of the cyclic etch process 113 may reduce the chance that gases used in the passivation layer 116 (stage 102c) will remain in the process chamber during the etching step (stage 102d) and interfere with the etching step. As another example, given the cyclic nature of cyclic etching process 113, purging the process chamber between step 102d and the repetition of step 102c of cyclic etching process 113 may reduce the chance that gases used in the etching step (step 102d) will remain in the process chamber during the passivation layer 116 formation step (step 102c) and interfere with the passivation layer 116 formation step. Alternatively, the present disclosure contemplates not performing a purge during one or both of these times (between steps 102c and 102d, and / or between steps 102d and the repetition of step 102c). For example, in addition to or instead of purging, noble gas plasma activity (e.g., activating Ar or other noble gas radio frequency (RF)) associated with step 102d may be delayed (e.g., by about 1 second or more) after termination of the chlorine gas flow associated with step 102c to reduce or eliminate chlorine gas dissociation that may occur during the etching process associated with step 102d.

[0056] In some embodiments, the steps of the cyclic etch process 113 (e.g., the deposition and etching associated with stages 102c and 102d) may be performed in different process chambers of the same process tool. By way of example, the process tool may be an ICP tool, a CCP tool, an HWS tool, a helical resonator, a spiral resonator, a microwave or electron beam generated plasma tool, a thermal processing tool, or any other suitable type or combination of types of tools. For example, stage 102c may be performed in a first chamber (e.g., a plasma chamber or a thermal processing chamber) of the process tool, and stage 102d may be performed in a separate plasma chamber of the same process tool.

[0057] In some embodiments, the steps of the cyclic etch process 113 (e.g., the passivation and etching associated with stages 102c and 102d, respectively) may be performed in process chambers of different process tools. By way of example, the process tool may be an ICP tool, a CCP tool, an HWS tool, a helical resonator, a spiral resonator, a microwave or electron beam generated plasma tool, a thermal processing tool, or any other suitable type or combination of types of tools. For example, stage 102c may be performed in a chamber (e.g., a plasma chamber or a thermal processing chamber) of a first process tool, and stage 102d may be performed in a plasma chamber of a separate process tool.

[0058] Exemplary process conditions and related parameters that may be considered include process tool parameters (e.g., if applicable depending on the type of process) for each of steps 102c and 102d, gases introduced into the process chamber in each of steps 102c and 102d and their respective amounts, pressures applied in each of steps 102c and 102d, source RF power and bias RF power used in each of steps 102c and 102d, temperatures for each of steps 102c and 102d, and pressures applied in each of steps 102c and 102d. the time for which each of steps 102c and 102d is performed (e.g., number of cycles), whether process parameters are different for any instance of steps 102c and 102d, whether the process chamber is purged between process steps (in embodiments where steps 102c and 102d are performed in the same process chamber), whether anisotropic passivation and / or etching processes are used and associated process conditions, the desired amount of extension of recess 112 into copper-containing layer 108, and / or any other process conditions and associated parameters.

[0059] The selected process conditions and associated parameters may be determined according to a variety of factors, such as some of those factors discussed above in connection with determining an appropriate number of cycles for the cyclical etching process 113. Furthermore, the selected process conditions and associated parameters for steps 102c and 102d may be optimized relative to one another. For example, it may be appropriate to combine the process conditions and associated parameters for passivation (step 102c) and etching (step 102d) to achieve an optimal combination of processes that achieves one or more of the factors discussed above.

[0060] Specific exemplary process conditions for the exemplary cyclic etching process 113 are described below. The passivation layer 116 may be formed in step 102c using a thermal evaporation process or a plasma deposition process, and the etching step may be performed in step 102d using a plasma process. These process conditions are provided for example purposes only. The present disclosure contemplates using any suitable process conditions for performing the cyclic etching process 113 according to the objectives of a particular implementation.

[0061] In one embodiment, the passivation layer 116 formation step (e.g., chlorination 115) of stage 102c is performed as a thermal evaporation process by introducing chlorine gas (Cl) into the process chamber and elevating the temperature of the semiconductor structure 104 to a temperature in the range of about 100°C to about 300°C to cause the Cl to dissociate and react with one or more exposed surfaces of the copper-containing layer to form Cu. y Cl x and forming a structure (passivation layer 116).

[0062] In some embodiments, the passivation layer 116 formation step (e.g., chlorination 115) of Stage 102c is performed as a plasma deposition process and may include introducing chlorine gas (Cl) into a process chamber and generating a plasma containing the chlorine gas (Cl). In some embodiments, the plasma is generated using a relatively high pressure (e.g., greater than about 200 milliTorr (mTorr)). In some embodiments, the plasma is generated using a pressure greater than about 300 mTorr. The high-pressure discharge may reduce the energy of ions directed toward the exposed surface (e.g., upper surface 114) of the copper-containing layer 108. Such ion bombardment may cause alloying at the exposed surface of the copper-containing layer 108, thereby undesirably modifying the surface morphology of the copper-containing layer 108.

[0063] In some embodiments, chlorine is the only gas intentionally introduced to form the plasma. In other embodiments, chlorine gas and one or more other gases may be used to form the plasma. For example, a relatively small amount of a noble gas (e.g., argon) may be added to the plasma chamber (in addition to chlorine gas) to facilitate ignition of the plasma.

[0064] As just one specific example, a plasma deposition process for forming passivation layer 116 may include chlorine gas (Cl) at a flow rate of about 100 standard cubic centimeters per minute (sccm) to about 300 sccm, a pressure of about 50 mTorr to about 300 mTorr, a source power of about 10 W to about 60 W, a bias power of about 10 W to about 50 W, and an elevated temperature of about 100°C.

[0065] In some embodiments, the etching step of stage 102d is performed as a plasma process (e.g., plasma 118) and may include introducing a noble gas (e.g., argon) into the process chamber and generating the plasma 118 using argon gas. Other exemplary noble gases that may be used include helium and xenon, although the use of argon may provide significant cost-effectiveness. In some embodiments, the noble gas (e.g., argon) is the only gas intentionally introduced to form the plasma 118. In other embodiments, chlorine gas and one or more other gases may be used to form the plasma. In some embodiments, the power conditions under which the plasma 118 is generated attempt to strike a balance between adsorption and sputtering. For example, the power may be set high enough to facilitate adsorption of compounds of the passivation layer 116 (e.g., CuCl) and low enough to attempt to maintain ion sputtering at an acceptable and / or minimized level. By way of example only, it may be desirable to keep the ion energy below about 40 eV, and in some embodiments, below about 20 eV. As another example, relatively low pressures (e.g., about 10 mTorr or less) may be used to etch the passivation layer 116, and the ability to complete this etch at such low pressures may reduce the risk of redeposition of etch by-products.

[0066] As just one specific example, a plasma process for etching passivation layer 116 may include a pressure of about 10 mTorr to about 100 mTorr, a source power of about 50 W to about 100 W, a bias power of about 10 W to about 50 W, an Ar flow rate of about 300 sccm, a temperature of about 100° C. or less, and an ion energy of about 10 eV to about 40 eV.

[0067] In a first specific exemplary embodiment in which stage 102c is a thermal process and stage 102d is a plasma process, process conditions and related parameters for the passivation layer 116 formation step (stage 102c) and the etching step (stage 102d) of cyclic etching process 113 may include the following. Exemplary process conditions for stage 102c may include a passivation time of about 5 seconds or less, a Cl flow rate of about 100 sccm to about 300 sccm, and a temperature of about 100°C to about 300°C. Exemplary process conditions for stage 102d may include (e.g., in a CCP tool) an etching time of about 5 seconds or less, a pressure of 100 mTorr, a source power of about 50 W to about 100 W, a bias power of about 10 W to about 50 W, a temperature of about 100°C or less, and an Ar flow rate of about 300 sccm. In one example, cyclic etching process 113 is performed in a different process chamber (of the same or a different process tool).

[0068] In a second specific exemplary embodiment in which stage 102c is a plasma process and stage 102d is a plasma process, process conditions and related parameters for the passivation layer 116 formation step (stage 102c) and the etching step (stage 102d) of cyclic etching process 113 may include the following: Exemplary process conditions for stage 102c may include a passivation time of about 5 seconds or less, a pressure greater than 200 mTorr, a source power of about 10 W to about 60 W, a bias power of about 10 W to about 50 W, a temperature of about 100°C, and a Cl flow rate of about 100 sccm to about 300 sccm. Exemplary process conditions for stage 102d may include (e.g., in a CCP tool) an etching time of about 5 seconds or less, a pressure of 100 mTorr, a source power of about 50 W to about 100 W, a bias power of about 10 W to about 50 W, a temperature of about 100°C or less, and an Ar flow rate of about 300 sccm. In one embodiment, the cyclical etch process 113 is performed in a different process chamber (in the same or a different process tool). In another example, the cyclical etch process 113 is performed in the same process chamber, with purging performed between steps 102 and 102d, and between step 102d and the return to step 102c of another cycle. The time for purging may depend on the pressure used and the process chamber volume.

[0069] 1C , the cyclic etching process 113 is completed, fully forming the recess 112 in the copper-containing layer 108, which in this example includes the upper surface 122 of the substrate 106 exposed at the bottom of the recess 112. In addition, portions of the passivation layer 116 (e.g., passivation layers 116b and 116c) remain on the sidewalls 119 of the copper-containing layer 108 in the recess 112. As mentioned above, the passivation layer 116 (and particularly passivation layers 116b and 116c) may be formed on the surfaces of the sidewalls 119 when the recess 112 opens to the copper-containing layer 108, thereby providing the exposed surface during the subsequent passivation step of step 102c. In some embodiments, the passivation layers 116b and 116c may be partially or entirely removed from the sidewalls 119 using a “cleaning” etch. By way of example only, the cleaning etch may be performed using argon or another suitable material. Such a cleaning etch may be performed using any suitable dry etch process, wet etch process, or combination thereof.

[0070] The remaining portions of copper-containing layer 108 may form structures 123a, 123b, and 123c (generally referred to as structures 123). Structures 123 may be formed to serve as conductive features of the semiconductor device being formed. Such conductive features may be, for example, conductive lines, vias, contacts, etc. This disclosure contemplates that structure 123 may be any suitable type of conductive feature. Furthermore, the type of conductive feature may be different for one or more of structures 123a, 123b, and 123c.

[0071] 1C, the recess 112 may be filled with a suitable fill material 124. In one embodiment, the fill material 124 comprises, for example, a dielectric material to isolate remaining portions of the copper-containing layer 108 from one another. Particular exemplary dielectric materials may include any material suitable for use as a pre-metal dielectric (PMD), an inter-metal dielectric (IMD), an inter-layer dielectric (ILD), or the like. The present disclosure contemplates that the fill material 124 may comprise any suitable dielectric material or combination of dielectric materials. As particular examples, the dielectric material may include SiN, SiON, silicon dioxide (SiO), silicon, carbon, oxygen, and hydrogen (SiCOH), or any other suitable dielectric material or combination of dielectric materials.

[0072] In some embodiments, one or more additional materials may be deposited before depositing the dielectric material. For example, one or more barrier layers, such as a thin alloy layer, may be deposited before filling the remainder of the recess 112 with a dielectric material. Such barrier layers may serve a variety of purposes, including, for example, mediating electromigration at the sidewalls 119 of the copper-containing layer 108 between the copper-containing layer 108 and the dielectric material of the fill material 124 being deposited thereon. Exemplary barrier layers include TaN or TiN. When initially deposited, the barrier layer may cover the semiconductor structure 104, including over the top surface of the semiconductor structure 104. The portion of the barrier layer overlying the top of the semiconductor structure 104 may be removed using any suitable etching technique (e.g., anisotropic etching technique) to leave a portion of the barrier layer on the surface of the sidewalls 119 within the recess 112. Any other suitable material, including a dielectric material, may then be used to fill the remainder of the recess 112.

[0073] The version of semiconductor structure 104 shown in step 102f includes remaining portions of patterning layer 110 (on top of structure 123), which may or may not be removed depending on the particular implementation. In embodiments in which remaining portions of patterning layer 110 are removed, the remaining portions of patterning layer 110 may be removed before or after step 102f.

[0074] In step 102f, the remaining portions of the copper-containing layer may serve as conductive features in the resulting semiconductor device. For example, the remaining portions of the copper-containing layer 108 may serve as conductive contacts, conductive vias, conductive lines, or any other suitable type of conductive feature.

[0075] Although process 100 is shown as including certain steps, the present disclosure contemplates that process 100 may include additional or fewer steps as may be appropriate for a particular implementation. For example, process 100 may include purge steps between steps 102c and 102d, and between steps 102d and the return to 102c.

[0076] Embodiments of the present disclosure may provide one or more technical advantages, and particular embodiments may provide some, none, or all of these advantages.

[0077] In some embodiments, the cyclic nature of the cyclic etching process 113 facilitates etching the copper-containing layer 108 in an incremental manner. The cyclic etching process 113 of some embodiments provides an incremental copper etching process that can be tightly controlled using a layer-by-layer etching technique, resulting in reduced or eliminated morphological changes to the surface of the copper layer being etched. Additionally, the minimal to zero morphological changes to the copper surface provided by some embodiments can reduce or eliminate surface roughness on the copper-containing layer 108 (and the resulting structure 123 made from the copper-containing layer 108) and improved profile of the resulting structure 123 made from the copper-containing layer 108. Furthermore, the passivation layer 116 formation step (e.g., exposing the surface of the copper-containing layer 108 to the chlorine treatment 115) can be self-limiting, and the etching performed using the plasma 118 can have a high selectivity to etching the passivation layer 116, both of which can also reduce or eliminate surface roughness on the copper-containing layer 108 (and the resulting structure 123 made from the copper-containing layer 108) and the improved profile of the resulting structure 123 made from the copper-containing layer 108. That is, the self-limiting nature of the passivation layer 116 and the selectivity of the plasma 118 etching the passivation layer 116 can reduce or eliminate pattern defects in the copper-containing layer 108 while facilitating control of the etch rate of the recesses 112 in the copper-containing layer 108.

[0078] Certain embodiments provide techniques for etching copper that are suitable for use in mass production. For example, certain embodiments provide an incremental and self-limiting process that can be integrated into larger processes for forming semiconductor devices. As another example, compared to other attempts to etch copper in a subtractive manner, certain embodiments reduce or eliminate damage to copper layers and / or other portions of the semiconductor structure being processed.

[0079] In addition to other types of features, certain embodiments provide the ability to etch relatively deep recesses 112 to form high aspect ratio conductive features in which the depth of the recesses 112 is significantly greater than the width of the recesses, possibly significantly greater. Due at least in part to the controllable nature of the etching process, certain embodiments may be usable for advanced packaging and three-dimensional (3D) integration (e.g., fin field effect transistors (FinFETs), gate-all-around (GAA) transistors, 3D NAND devices, etc.).

[0080] 2A-2E illustrate cross-sectional views of semiconductor structure 104 during a cyclic etching process 113 for treating semiconductor structure 104 in accordance with certain embodiments of the present disclosure. In particular, FIGS. 2A-2E illustrate semiconductor structure 104 during five exemplary iterations of cyclic etching process 113 to illustrate layer-by-layer removal of a portion of copper-containing layer 108. These five iterations of steps 102c and 102d are labeled as steps 102c(1) and 102d(1) for iteration 1, steps 102c(2) and 102d(2) for iteration 2, steps 102c(3) and 102d(3) for iteration 3, steps 102c(4) and 102d(4) for iteration 4, and steps 102c(5) and 102d(5) for iteration 5. The specific number of iterations is shown for illustrative purposes only.

[0081] Generally, aspects of steps 102c(1) through 102c(5) correspond to aspects of step 102c described above with respect to Figure 1B and will not be repeated in many details for the sake of brevity. Additionally, generally, aspects of steps 102d(1) through 102d(5) correspond to aspects of step 102d described above with reference to Figure 1B and will not be repeated in many details for the sake of brevity.

[0082] 2A , in step 102c(1), the upper surface 114 of copper-containing layer 108 is exposed to a chlorine treatment 115 at the openings of recesses 112 defined by patterning layer 110 to form passivation layer 116 on those exposed upper surfaces 114. In step 102d(1), the passivation layer 116 formed in step 102c(1) is wholly or partially removed by exposing semiconductor structure 104 to plasma 118. Because passivation layer 116 consumes some portion of copper-containing layer 108, removing passivation layer 116 formed on upper surface 114 of copper-containing layer 108 removes a portion of copper-containing layer 108, extending recess 112 into copper-containing layer 108 and exposing sidewalls 119 of copper-containing layer 108 within recess 112.

[0083] 2B, in step 102c(2), the top surface 114 of the copper-containing layer 108 and the surfaces of the sidewalls 119 of the copper-containing layer 108 are exposed to a chlorine treatment 115 to form a passivation layer 116a on the exposed top surface of the copper-containing layer 108 at the bottom of the recess 112 and passivation layers 116b and 116c on the surfaces of the sidewalls 119 of the copper-containing layer 108. In step 102d(2), the passivation layer 116a is wholly or partially removed by exposing the semiconductor structure 104 to a plasma 118. Because the passivation layer 116a consumes some portion of the copper-containing layer 108, removing the passivation layer 116a formed on the top surface 114 of the copper-containing layer 108 removes a portion of the copper-containing layer 108, extending the recess 112 into the copper-containing layer 108 and thus exposing more of the sidewall 119 of the copper-containing layer 108 within the recess 112. In some embodiments, due to the directional nature of the application of the plasma 118, which is directed toward the top surface 114 of the copper-containing layer 108 (and the passivation layer 116a formed thereon) at the bottom of the recess 112, some or all of the passivation layers 116b and 116c may remain on the surface of the sidewall 119. Note that when the passivation layer 116a is formed on the top surface 114 of the copper-containing layer 108, the passivation layer 116a may also be considered to be the top surface 114 of the copper-containing layer 108.

[0084] 2C, in step 102c(3), the top surface 114 of copper-containing layer 108 and the surfaces of sidewalls 119 of copper-containing layer 108 are exposed to a chlorine treatment 115 to form passivation layer 116a on the exposed top surface 114 of copper-containing layer 108 and passivation layers 116b and 116c on the portions of the surfaces of sidewalls 119 exposed in step 102d(2). In step 102d(3), passivation layer 116a is wholly or partially removed by exposing semiconductor structure 104 to plasma 118. Because the passivation layer 116a consumes some portion of the copper-containing layer 108, removing the passivation layer 116a formed on the top surface of the copper-containing layer 108 (at the bottom of the recess 112) removes a portion of the copper-containing layer 108, extending the recess 112 into the copper-containing layer 108 and exposing more of the sidewall 119. In some embodiments, due to the directional nature of the application of the plasma 118, which is directed toward the top surface 114 of the copper-containing layer 108 (and the passivation layer 116a formed thereon) at the bottom of the recess 112, some or all of the passivation layers 116b and 116c may remain on the surface of the sidewall 119.

[0085] 2D , in step 102c(4), the top surface 114 of copper-containing layer 108 and the surfaces of sidewalls 119 of copper-containing layer 108 are exposed to a chlorine treatment 115 to form passivation layer 116a on the exposed top surface 114 of copper-containing layer 108 and passivation layers 116b and 116c on the portions of the surfaces of sidewalls 119 exposed in step 102d(3). In step 102d(4), passivation layer 116a is wholly or partially removed by exposing semiconductor structure 104 to plasma 118. Because the passivation layer 116a consumes some portion of the copper-containing layer 108, removing the passivation layer 116a formed on the upper surface 114 of the copper-containing layer 108 (at the bottom of the recess 112) removes a portion of the copper-containing layer 108, extending the recess 112 into the copper-containing layer 108 and exposing more of the sidewall 119. In some embodiments, due to the directional nature of the application of the plasma 118, which is directed toward the upper surface 114 of the copper-containing layer 108 (and the passivation layer 116a formed thereon) at the bottom of the recess 112, some or all of the passivation layers 116b and 116c may remain on the surface of the sidewall 119.

[0086] 2E, in step 102c(5), the top surface 114 of copper-containing layer 108 and the surfaces of sidewalls 119 of copper-containing layer 108 are exposed to a chlorine treatment 115 to form passivation layer 116a on the exposed top surface 114 of copper-containing layer 108 and passivation layers 116b and 116c on the portions of the surfaces of sidewalls 119 exposed in step 102d(4). In step 102d(5), passivation layer 116a is wholly or partially removed by exposing semiconductor structure 104 to plasma 118. Because the passivation layer 116a consumes some portion of the copper-containing layer 108, removing the passivation layer 116a formed on the upper surface 114 of the copper-containing layer 108 (at the bottom of the recess 112) removes a portion of the copper-containing layer 108, extending the recess 112 into the copper-containing layer 108 and exposing more of the sidewall 119. In some embodiments, due to the directional nature of the application of the plasma 118, which is directed toward the upper surface 114 of the copper-containing layer 108 (and the passivation layer 116a formed thereon) at the bottom of the recess 112, some or all of the passivation layers 116b and 116c may remain on the surface of the sidewall 119.

[0087] 2a-2E, process 100, and in particular cyclic etching process 113, incrementally etches a target exposed surface (e.g., top surface 114) of copper-containing layer 108, thereby incrementally extending recess 112, in this example, into copper-containing layer 108. The portion of copper-containing layer 108 that is consumed by passivation layer 116a is removed using a directional anisotropic etching process selective to passivation layer 116 to provide a controlled etching process.

[0088] 3A-3C show exemplary details of semiconductor structure 104 during cyclic etching process 113 of process 100 for etching metal during processing of a semiconductor structure, according to certain embodiments of the present disclosure. In particular, FIG. 3A generally corresponds to stage 102c of FIG. 1B when exposure of semiconductor structure 104 to chlorine treatment 115 begins, FIG. 3B (showing both a cross-sectional view and a plan view of semiconductor structure 104) generally corresponds to stage 102c when passivation layer 116 is formed, and FIG. 3C generally corresponds to stage 102d during exposure of semiconductor structure 104 to plasma 118.

[0089] 3A, the copper-containing layer 108 includes copper particles 300, and the chlorination 115 includes chlorine gas particles 302. For purposes of this description, particles may be atoms, molecules, ions, or any other suitable subdivision of the respective layer of which the particles are a part. In one embodiment, the copper particles 300 are copper atoms, and the chlorine gas particles 302 are a compound of two chlorine atoms (Cl), which is neutral chlorine gas.

[0090] As shown in FIG. 3B, at least some of the chlorine gas particles 302 of the chlorine treatment 115 have dissociated from one another (as chlorine particles 304, such as chlorine atoms) and are bonded with copper particles 300 at the surface of the copper-containing layer 108, forming Cu y Cl x Structure 306 (e.g., Cu y Cl x The exposure of the copper particles 300 of the copper-containing layer 108 to chlorine gas (e.g., chlorine gas particles 302) is self-limiting, as the chlorine molecules of the chlorine gas (e.g., Cl) readily dissociate and, after dissociation, bond to the copper atoms (e.g., copper particles 300), thereby forming a passivation layer 116a of Cu. y Cl x Structure 306 (e.g., Cu y Cl x compound).

[0091] The present disclosure provides for the removal of Cu from more than any suitable percentage of the surface of the copper-containing layer 108. y Cl xWhile contemplated for the formation of structure 306, in some embodiments, step 102c (e.g., exposing semiconductor structure 104 to chlorine treatment 115) may result in between about 30 percent and about 70 percent of the exposed surface of copper-containing layer 108 being Cu. y Cl x In some embodiments, step 102c (e.g., exposing semiconductor structure 104 to chlorine treatment 115) results in a coverage of about 50 percent. For example, in some embodiments, the limitation in chlorine adsorption is due to steric hindrance associated with neighboring chlorine particles 304 adhering to copper particles 300 at the surface of copper-containing layer 108. A rougher surface of copper-containing layer 108 has a larger surface area, potentially allowing more chlorine particles 304 to adhere to copper particles 300 at the surface of copper-containing layer 108.

[0092] For example, in some embodiments, the process of chlorine molecules of chlorine gas (e.g., Cl) dissociating and subsequently bonding to copper atoms (e.g., copper particles 300) on the crystalline copper surface may stop after a certain coverage value (e.g., about 50%) on the crystalline copper surface. In some embodiments, at less than 100% coverage of the passivation layer 116, copper atoms not passivated by chlorine near the exposed surface of the copper-containing layer 108 may shift position and attempt to bond to another chlorine atom. This may open a pathway to copper atoms at a subsurface level of the copper-containing layer 108. However, due to the relatively large energy for subsurface adsorption of chlorine atoms (e.g., greater than about 3 V), it may be possible to avoid or at least limit such subsurface adsorption, thereby limiting morphological changes to the exposed surface of the copper-containing layer 108.

[0093] As shown in FIG. 3C, the passivation layer 116 (e.g., passivation layer 116a) of the copper-containing layer 108 is exposed to a plasma 118, which etches the passivation layer 116a. The plasma 118 includes argon particles 308, and exposing the passivation layer 116a of the copper-containing layer 108 to the plasma 118 directs the argon particles 308 in a direction 310 toward the passivation layer 116a of the copper-containing layer 108, which can anisotropically etch the passivation layer 116a. The chlorine particles 304 of the chlorine treatment 115 are bonded to the copper particles 300 (Cu, as shown in FIG. 3B). y Cl x For example, argon particles 308 may be used to remove Cu y Cl x Structure 306 (e.g., Cu y Cl x The particles may be directed at the copper-containing layer 108 (including the passivation layer 116a) with sufficient energy to detach the copper-containing compound (compound) from the surface of the copper-containing layer 108, and in some embodiments, with low enough energy to minimize ion sputtering.

[0094] In some embodiments, a relatively low amount of energy is applied to Cu y Cl x This can liberate structure 306. This ability, coupled with the self-limiting nature of the formation of passivation layer 116a (see, e.g., FIG. 3B), results in near-layer-by-layer removal of one or more target surfaces (e.g., top surface 114) of copper-containing layer 108. In some embodiments, cyclic etching process 113 can be performed at any suitable pressure due to the low ion energy required to remove passivation layer 116; however, cyclic etching process 113 can be performed at low pressures (e.g., about 10 mTorr or less) due to the rapid penetration of copper by chlorine mediated by Cl gas (e.g., in stage 102c during the formation of passivation layer 116). Such low pressures can, in some embodiments, reduce or eliminate the risk of by-product redeposition during the etching process of stage 102d.

[0095] Variations of copper chloride etch by-products may be produced during the etching step (e.g., stage 102d). For example, CuCl, CuCl, and CuCl may be stable etch by-products with ΔE values ​​of approximately −1.33 eV, +0.28 eV, and +2.19 eV, respectively. In some embodiments, only CuCl is generally available through cooperative interactions with physisorbed Cl molecules, thereby limiting the generation of CuCl. In some embodiments, the plasma concentration and power are selected to break approximately 0.86 eV copper surface bonds in the copper-containing layer 108.

[0096] 4 illustrates an exemplary method 400 for processing a semiconductor structure 104 in accordance with an embodiment of the present disclosure. The method begins at step 402. At step 404, a substrate 106 is received. The substrate 106 includes a copper-containing layer 108 formed thereon. In an embodiment, the copper-containing layer 108 is pure copper. At step 406, a patterned layer 110 is formed on the copper-containing layer 108 formed on the substrate 106. For example, the patterned layer 110 may be patterned using a patterning resist layer as an etching mask. In an embodiment, forming the patterned layer 110 includes defining a pattern in the patterned layer 110, which defines an etching pattern for forming features (e.g., recesses 112 and structures 123) in the copper-containing layer 108 using a cyclic etching process 113. For example, the pattern defined by the patterning layer 110 may define recesses 112 for etching corresponding recesses 112 in the copper-containing layer 108 such that the remaining portions of the copper-containing layer 108 after the cyclic etching process 113 define conductive features of a semiconductor device, such as conductive contacts, conductive lines, conductive vias, etc.

[0097] In step 408, the copper-containing layer 108 is patterned by performing a cyclic etching process 113 using the patterning layer 110 as an etching mask. In one embodiment, the cyclic etching process 113 includes forming a passivation layer 116 on one or more exposed surfaces of the copper-containing layer 108 in a first etching step (e.g., a chlorine exposure step) step 408a by exposing one or more exposed surfaces of the copper-containing layer 108 to a chlorine treatment 115 comprising chlorine gas. In one embodiment, the passivation layer 116 is formed by a Cu y Cl x The passivation layer 116 replaces at least a portion of the surface layer of the copper-containing layer 108. In one embodiment, the passivation layer 116 is formed in a self-limiting process and penetrates into the copper-containing layer 108 to a depth of no more than three copper atoms on one or more exposed surfaces.

[0098] In one embodiment, forming a passivation layer 116 on one or more exposed surfaces of the copper-containing layer 108 in Step 408a by exposing one or more exposed surfaces of the copper-containing layer 108 to a chlorine treatment 115 includes performing a thermal evaporation process to dissociate Cl and react with one or more exposed surfaces of the copper-containing layer 108 to form the passivation layer 116 (e.g., Cu y Cl x In one embodiment, forming a passivation layer 116 on one or more exposed surfaces of the copper-containing layer 108 by exposing the one or more exposed surfaces of the copper-containing layer 108 to a chlorine treatment 115 in Step 408a includes a plasma deposition process. For example, the one or more exposed surfaces of the copper-containing layer 108 are chlorinated to form a passivation layer 116 (e.g., Cu y Cl x The silicon dioxide film may be exposed to a chlorine-containing plasma having sufficient energy to form structure 306).

[0099] In some embodiments, the one or more exposed surfaces of the copper-containing layer 108 on which the passivation layer 116 is formed include one or more top surfaces 114 of the copper-containing layer 108, surfaces of the sidewalls 119 of the copper-containing layer 108, or a combination of one or more top surfaces of the copper-containing layer 108 and surfaces of the sidewalls 119 of the copper-containing layer 108.

[0100] In some embodiments, in a first instance of the first etching step (e.g., chlorine exposure step) in Step 408a, the one or more exposed surfaces of the copper-containing layer 108 may include a target exposed surface, which in one example is the top surface 114 of the copper-containing layer 108 at the bottom of the recess 112. In some embodiments, in a subsequent instance of the first etching step (e.g., chlorine exposure step) in Step 408a, the one or more exposed surfaces of the copper-containing layer 108 may include the target exposed surface (e.g., the top surface 114) and a surface of the sidewall 119 of the copper-containing layer 108 within the recess 112.

[0101] In one embodiment, the cyclic etching process 113 includes, in a second etching step (e.g., a plasma etching step) step 408b, etching at least a portion of the passivation layer 116 of the copper-containing layer 108 using a plasma 118. In one embodiment, the plasma 118 includes a noble gas, such as argon. Each etch of the passivation layer 116 removes at least a portion of the copper-containing layer 108 to extend a recess 112 in the copper-containing layer 108.

[0102] In one embodiment, Step 408b includes plasma etching the substrate 106 having the copper-containing layer 108 to remove Cu from one or more exposed surfaces of the copper-containing layer 108. y Cl xThe method includes exposing the copper-containing layer 108 to a plasma 118 (e.g., an argon plasma) directed at a target exposed surface (e.g., upper surface 114) of the copper-containing layer 108 with sufficient energy to remove at least a portion of the structure 306 from the copper-containing layer 108 and extend a recess 112 into the copper-containing layer 108. In some embodiments, the sufficient energy is about 40 eV or less.

[0103] The cyclical nature of the cyclical etching process 113 means that the cyclical etching process 113 can be repeated an appropriate number of times to incrementally form the recesses 112 in the copper-containing layer 108, such that the depth of the recesses 112 increases with each iteration of the cyclical etching process 113. Furthermore, the cyclical nature of the cyclical etching process 113, coupled with the formation of the passivation layer 116, facilitates the reduction or elimination of morphological alterations to the surface of the copper-containing layer 108 during etching of the copper-containing layer 108. For example, the cyclical etching process 113 may be performed a predetermined number of times. As another example, the cyclical etching process 113 may be performed until the top surface 122 of the substrate 106 is exposed at the bottom of the recesses 112 in the copper-containing layer 108.

[0104] In one embodiment, in instances where steps 408a and 408b are performed in the same process chamber, after step 408a of cyclic etching process 113 of method 400 and before step 408b of cyclic etching process 113, the process chamber in which steps 408a and 408b may be performed may be purged to remove any remaining gases or other materials associated with step 408a.

[0105] At step 410, the recess 112 may be filled with a fill material 124. The fill material 124 may include any suitable material or combination of materials. In some embodiments, the fill material includes a dielectric material. The present disclosure contemplates filling the recess with the fill material 124 using any suitable type of process or combination of types of processes. In some embodiments, the method 400 includes removing a portion of the passivation layer 116 (e.g., passivation layers 116b and 116c) formed on the sidewalls 119 of the copper-containing layer 108 within the recess 112 prior to filling the recess 112 with the fill material 124.

[0106] In step 412, the method 400 ends.

[0107] 5 illustrates an exemplary method 500 for processing a semiconductor structure 104 in accordance with an embodiment of the present disclosure. The method begins at step 502. At step 504, a substrate 106 is received. The substrate 106 includes a copper-containing layer 108 formed thereon. In an embodiment, the copper-containing layer 108 is pure copper.

[0108] In step 506, a cyclical etching process 113 is performed to incrementally etch a portion of the copper-containing layer 108. In one embodiment, the copper-containing layer 108 has an exposed target surface that defines the portion of the copper-containing layer that is to be incrementally etched. For example, the exposed target surface may be the top surface 114 of the copper-containing layer 108 at the bottom of the recess 112.

[0109] In one embodiment, the cyclic etching process 113 includes exposing the substrate 106 having the copper-containing layer 108 to chlorine gas (Cl) in a chlorine exposure step 506a to convert a portion of the copper-containing layer 108 to copper chloride (CuCl) at the target exposed surface of the copper-containing layer 108. y Cl x ) structure 306. (Cu y Cl xThe copper in structure 306 may be the surface portion of copper-containing layer 108 at the exposed target surface (and potentially other exposed surfaces of copper-containing layer 108). In some embodiments, the chlorine exposure step of step 506a converts less than 100% of the exposed target surface of copper-containing layer 108 into copper chloride (Cu y Cl x ) structure, and as a specific example, approximately 50% of the exposed target surface of the copper-containing layer 108 is converted to copper chloride (Cu y Cl x ) structure.

[0110] In one embodiment, step 506a comprises injecting Cl into a process chamber of the processing tool according to a thermal evaporation process and increasing the temperature of the process chamber to cause the Cl to dissociate and react with the exposed target surface of the copper-containing layer 108 to form Cu. y Cl x and forming structure 306. In one embodiment, step 506a includes injecting Cl into a process chamber of the processing tool, generating a chlorine-containing plasma (e.g., plasma 118) in the process chamber from the Cl, and dissociating and reacting the Cl with the target exposed surface of copper-containing layer 108 to form Cu. y Cl x exposing the target exposed surface of the copper-containing layer 108 to a chlorine-containing plasma (e.g., plasma 118) having sufficient energy to form the structure 306.

[0111] In one embodiment, the cyclic etching process 113 includes exposing the substrate 106 to a plasma 118 in step 506b of the plasma etching step. In one embodiment, the plasma 118 includes a noble gas, such as argon. In one embodiment, the plasma 118 is used to remove Cu from the exposed target surface of the copper-containing layer 108. y Cl xThe target is directed at an exposed surface (e.g., upper surface 114) of the copper-containing layer 108 with sufficient energy to remove at least a portion of the structure from the copper-containing layer 108, thereby etching a portion of the copper-containing layer 108 at the exposed target surface of the copper-containing layer 108. In some embodiments, the sufficient energy is about 40 eV or less.

[0112] The periodicity of the cyclic etching process 113 means that the cyclic etching process 113 can be repeated a suitable number of times to incrementally etch the copper-containing layer 108 (e.g., to form recesses 112 in the copper-containing layer 108). Furthermore, the periodicity of the cyclic etching process 113, coupled with the formation of copper chloride structures 306 on the target exposed surface of the copper-containing layer 108, facilitates the reduction or elimination of morphological alterations to the target exposed surface of the copper-containing layer 108 during etching of the copper-containing layer 108. For example, the cyclic etching process 113 may be performed a predetermined number of times. As another example, the cyclic etching process 113 may be performed until the top surface 122 of the substrate 106 is exposed at the bottom of the recesses 112 in the copper-containing layer 108.

[0113] In some embodiments, the chlorine exposure step (e.g., step 506a) and the plasma etching step (e.g., step 506b) are performed using different processing tools or in different process chambers of the same processing tool. In some embodiments, in instances where steps 506a and 506b are performed in the same process chamber, after step 506a of cyclical etch process 113 and before step 506b of cyclical etch process 113 of method 500, the process chamber in which steps 506a and 506b may be performed may be purged to remove any remaining gases or other materials associated with step 506a.

[0114] At step 508, the recess 112 may be filled with a fill material 124. The fill material 124 may include any suitable material or combination of materials. In some embodiments, the fill material includes a dielectric material. The present disclosure contemplates filling the recess with the fill material 124 using any suitable type of process or combination of types of processes.

[0115] In step 510, the method 500 ends.

[0116] 6 shows a general overview of an exemplary plasma processing system 600 in accordance with certain embodiments of the present disclosure. Although a particular exemplary plasma processing system 600 is shown and described, the present disclosure contemplates the use of any suitable type of plasma processing system 600. The plasma processing system 600 may be used to perform some or all of the plasma process steps.

[0117] The plasma processing system 600 includes a process chamber 610, a gas delivery system 620, a vacuum pumping system 630, a temperature controller 640, and power supplies 650 and 660. The process chamber 610 includes an electrode 652 and a substrate holder 654.

[0118] 1-5 may be performed using a plasma processing system 600, with the semiconductor structure 104 in position on a substrate holder 654 in a process chamber 610. For example, to the extent that a plasma process is used to form the passivation layer 116 or to etch the copper-containing layer 108, the semiconductor structure 104 may be placed in the process chamber 610 and exposed to a suitable plasma 670, which may be a chlorine treatment 115 implemented as a plasma, or may be plasma 118, as an example, depending on the stage of the process.

[0119] The gas delivery system 620, the vacuum pumping system 630, the temperature controller 640, the power supplies 650 and 660, and the electrode 652 may be programmed or otherwise operated according to desired process conditions for a given processing step. For example, to the extent that a plasma process is used to form the passivation layer 116, these components of the plasma processing system 600 may be set according to the exemplary process conditions and associated parameters described in connection with forming the passivation layer 116. As another example, to the extent that a plasma process is used to etch the recess 112 in the copper-containing layer 108, these components of the plasma processing system 600 may be set according to the exemplary process conditions and associated parameters described in connection with etching the recess 112 in the copper-containing layer 108.

[0120] Although this disclosure may describe or show certain process / method steps as occurring in a particular order, this disclosure contemplates that the process / method steps may occur in any suitable order. Further, this disclosure contemplates that the process / method steps may be repeated one or more times in any suitable order. Although this disclosure may describe or show certain process / method steps as occurring sequentially, this disclosure contemplates that, where appropriate, the process / method steps may occur substantially simultaneously.

[0121] While the present disclosure has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the present disclosure, will be apparent to those skilled in the art upon reference to the description. It is therefore intended that the appended claims cover any and all such modifications or embodiments.

Claims

1. 1. A method of processing a semiconductor structure, comprising: forming a patterning layer on a copper layer to be etched, the copper layer being disposed on a substrate; patterning the copper layer using the patterning layer as an etching mask by performing a cyclic etching process to form recesses in the copper layer, the cyclic etching process comprising: forming a passivation layer on the exposed surface of the copper layer by exposing the exposed surface of the copper layer to chlorine gas in a first etching step, the passivation layer replacing at least a portion of a surface layer of the copper layer; and subsequently etching the passivation layer using a first plasma in a second etching step, the first plasma comprising a noble gas, each cycle of the cyclic etching process extending the recess in the copper layer; patterning, A method comprising:

2. 10. The method of claim 1, wherein in the first etching step, forming the passivation layer on the exposed surface of the copper layer by exposing the exposed surface of the copper layer to chlorine gas comprises a thermal evaporation process.

3. 10. The method of claim 1, wherein in the first etching step, forming the passivation layer on the exposed surface of the copper layer by exposing the exposed surface of the copper layer to chlorine gas comprises a plasma deposition process.

4. 2. The method of claim 1, wherein the exposed surface of the copper layer on which the passivation layer is formed comprises a top surface of the copper layer, a sidewall surface of the copper layer, or a combination of the top surface of the copper layer and the sidewall surface of the copper layer.

5. The method of claim 1 , wherein the passivation layer has a copper chloride (CuCl) structure.

6. 6. The method of claim 5, wherein 30 to 70 percent of the exposed surface of the copper layer is converted to the CuCl structure.

7. The method of claim 1 , wherein the noble gas is argon.

8. The method of claim 1 , further comprising, following completing the cyclic etching process, filling the recess with a fill material comprising a dielectric material.

9. 2. The method of claim 1, wherein during one or more instances of the first etching step, the passivation layer is formed along sidewall surfaces of the copper layer in the recess exposed by the second etching step.

10. 2. The method of claim 1, wherein during the second etching step, the first plasma is directed at a portion of the passivation layer formed on an upper surface of the copper layer located at the bottom of the recess.

11. 1. A method of processing a semiconductor structure, comprising: receiving a substrate, the substrate having a copper-containing layer formed thereon; performing a cyclic etching process to incrementally etch a portion of the copper-containing layer, the copper-containing layer having an exposed target surface that defines the portion of the copper-containing layer to be etched, the cyclic etching process comprising: In the chlorine exposure step, the substrate having the copper-containing layer is exposed to chlorine gas (Cl ２ ) to convert a portion of the copper-containing layer to a copper chloride (CuCl) structure; and subsequently exposing the substrate having the copper-containing layer to a first plasma in a plasma etching step, the first plasma comprising a noble gas and directed at the target exposed surface of the copper-containing layer with sufficient energy to cause at least a portion of the CuCl structures to be removed from the copper-containing layer; etching, A method comprising:

12. 12. The method of claim 11, wherein the chlorine exposure step and the plasma etching step are performed using different processing tools or in different process chambers of the same processing tool.

13. the chlorine exposure step and the plasma etching step are performed in the same process chamber of the same processing tool; 12. The method of claim 11, further comprising performing a purge of the same process chamber between the chlorine exposure step and the plasma etching step during each cycle of the cyclical etching process.

14. The method of claim 11 , comprising repeating the cyclic etching process a number of times sufficient to etch away the portion of the copper-containing layer.

15. The substrate having the copper-containing layer is ２ Being exposed to The Cl was evaporated according to a thermal evaporation process. ２ into a process chamber of a processing tool, and increasing the temperature of the process chamber of the processing tool to ２ and reacting with the exposed target surface of the copper-containing layer to form the CuCl structure; or According to a plasma deposition process, the Cl ２ into a process chamber of a processing tool, and ２ generating a chlorine-containing plasma in the process chamber of the processing tool from the Cl ２ exposing the exposed target surface of the copper-containing layer to the chlorine-containing plasma having sufficient energy to dissociate and react with the exposed target surface of the copper-containing layer to form the CuCl structure; The method of claim 11 , comprising:

16. 1. A method of processing a semiconductor structure, comprising: forming a patterning layer on a copper layer to be etched, the copper layer being disposed on a substrate; patterning the copper layer using the patterning layer as an etch mask by performing a cyclic etching process to incrementally form recesses in the copper layer, the cyclic etching process comprising: In the chlorine exposure step, the substrate having the copper layer is exposed to chlorine gas (Cl ２ ) to form CuCl structures on one or more exposed surfaces of the copper layer; and subsequently, in a plasma etching step, exposing the substrate having the copper layer thereon to an argon-containing plasma directed at a target exposed surface of the copper layer with sufficient energy to remove at least a portion of the CuCl structures at the one or more exposed surfaces of the copper layer from the copper layer and extend the recesses into the copper layer; Including, at a first instance of the chlorine exposure step, the one or more exposed surfaces of the copper layer include the target exposed surface, the target exposed surface being an upper surface of the copper layer at a bottom of the recess; at a subsequent instance of the chlorine exposure step, the one or more exposed surfaces of the copper layer include the target exposed surface and a sidewall surface of the copper layer within the recess. Patterning; and A method comprising:

17. The chlorine exposure step may involve performing a thermal evaporation process to remove the Cl ２ and reacting with the one or more exposed surfaces of the copper layer to form the CuCl structure.

18. The chlorine exposure step comprises: ２ generating a chlorine-containing plasma from the Cl ２ and exposing the one or more exposed surfaces of the copper layer to the chlorine-containing plasma having sufficient energy to cause CuCl to dissociate and react with the one or more exposed surfaces of the copper layer to form the CuCl structure.

19. 17. The method of claim 16, wherein the sufficient energy is 40 eV or less.

20. 17. The method of claim 16, further comprising filling the recess with a fill material comprising a dielectric material after completing the cyclic etching process, the method comprising removing the CuCl structures on the sidewall surfaces of the copper layer in the recess before filling the recess with the fill material.

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