Semiconductor Devices

Abstract

This semiconductor device is provided with: a semiconductor layer; a cell that is provided on the semiconductor layer; an insulating film that covers the cell; a main electrode part that is superposed on the insulating film; a temperature-sensitive diode for sensing temperatures, the diode having a first electrode and a second electrode; and a connection electrode for diode, the connection electrode being used for the purpose of connecting the first electrode to the outside. The main electrode part has: a first bonding region to which a first conductive member is bonded, the first conductive member being used for the purpose of connecting the main electrode part to the outside, and which is electrically connected to the second electrode; and a second bonding region to which a second conductive member is bonded, the second conductive member being used for the purpose of connecting the second electrode to the outside, and which is provided in a region that is different from the first bonding region when viewed from the thickness direction of the semiconductor layer. When viewed from the thickness direction of the semiconductor layer, the cell is provided on both a first semiconductor region in the semiconductor layer, the first semiconductor region overlapping with the first bonding region, and a second semiconductor region in the semiconductor layer, the second semiconductor region overlapping with the second bonding region.

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] For example, switching elements such as IGBTs (Insulated Gate Bipolar Transistors) used in vehicle inverter devices tend to generate heat because they switch between supplying and blocking current at high speeds. For this reason, in order to prevent the temperature of the switching element from exceeding the guaranteed operating range, the switching element may be equipped with a temperature-sensing diode configured to detect the temperature of the switching element (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-103272 Summary of the Invention [Problem to be solved by the invention]

[0004] However, since the temperature-sensitive diode is mounted on the switching element, it is necessary to provide a space in the switching element for drawing out the anode and cathode of the temperature-sensitive diode to the outside of the temperature-sensitive diode, which reduces the area of ​​the cell in the switching element where the transistor is formed. [Means for solving the problem]

[0005] A semiconductor device that solves the above problem includes a semiconductor layer, a cell provided in the semiconductor layer, an insulating film covering the cell, a main electrode portion stacked on the insulating film, a temperature-sensitive diode for detecting temperature and having a first electrode and a second electrode, and a diode connection electrode for connecting the first electrode to an external device, wherein the main electrode portion has a first junction region where a first conductive member for connecting the main electrode portion to an external device is joined and is electrically connected to the second electrode, and a second junction region which is provided in a region different from the first junction region when viewed in the thickness direction of the semiconductor layer and where a second conductive member for connecting the second electrode to an external device is joined, and wherein the cell is provided in both the first semiconductor region of the semiconductor layer that overlaps with the first junction region and the second semiconductor region that overlaps with the second junction region when viewed in the thickness direction of the semiconductor layer. [Effects of the Invention]

[0006] According to the semiconductor device, even if a temperature sensitive diode is mounted, it is possible to suppress a reduction in the area of ​​the region where the cells are formed. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a plan view of a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a plan view of the semiconductor device of FIG. 1 with the protective insulating film removed. [Figure 3] FIG. 3 is a plan view schematically showing the main cell region, the outer periphery region, and the intermediate region of the semiconductor device of FIG. [Figure 4] FIG. 4 is a plan view showing a state in which a conductive member is bonded to the semiconductor device of FIG. [Figure 5] FIG. 5 is a cross-sectional view schematically showing the cross-sectional structure of a part of the main cell region. [Figure 6] FIG. 6 is a cross-sectional view that schematically shows the cross-sectional structure of part of both the main cell region and the intermediate region. [Figure 7] FIG. 7 is a schematic circuit diagram of the semiconductor device of the first embodiment. [Figure 8] FIG. 8 is a schematic plan view of a temperature sensitive diode and a protection diode mounted on a semiconductor device. [Figure 9] FIG. 9 is a schematic plan view showing a state in which wiring is connected to the temperature sensitive diode and the protection diode of FIG. [Figure 10] 10 is a cross-sectional view of the temperature sensitive diode of FIG. 9 taken along line 10-10. [Figure 11] FIG. 11 is a schematic plan view showing the positional relationship between the through wiring and the temperature sensitive diode of the wiring connected to the temperature sensitive diode of FIG. [Figure 12] 12 is a cross-sectional view of the protection diode of FIG. 9 taken along line 12-12. [Figure 13] 13 is a cross-sectional view of the protection diode of FIG. 9 taken along line 13-13. [Figure 14] FIG. 14 is a plan view of a semiconductor device of a comparative example. [Figure 15] 15 is a cross-sectional view of the semiconductor device of FIG. 14 taken along line 15-15. [Figure 16] FIG. 16 is a plan view of the semiconductor device of the second embodiment. [Figure 17] FIG. 17 is a plan view showing a state in which a conductive member is bonded to the semiconductor device of FIG. [Figure 18] FIG. 18 is a schematic plan view of a temperature sensitive diode and a protection diode mounted on a semiconductor device according to the third embodiment. [Figure 19] FIG. 19 is a schematic plan view showing a state in which wiring is connected to the temperature sensing diode and the protection diode of FIG. [Figure 20] 20 is a cross-sectional view of the temperature sensitive diode of FIG. 19 taken along line 20-20. [Figure 21] 21 is a cross-sectional view of the protection diode of FIG. 19 taken along line 21-21. [Figure 22] FIG. 22 is a schematic plan view of a diode cell of a temperature sensitive diode according to a modified example. [Figure 23] FIG. 23 is a schematic plan view of a diode cell of a temperature sensitive diode according to a modified example. [Figure 24] FIG. 24 is a schematic plan view of a diode cell of a temperature sensitive diode according to a modified example. [Figure 25] FIG. 25 is a schematic plan view of a diode cell of a temperature sensitive diode according to a modified example. [Figure 26] FIG. 26 is a schematic plan view of a diode cell of a temperature sensitive diode according to a modified example. [Figure 27] FIG. 27 is a schematic plan view showing a state in which wiring is connected to the temperature sensitive diode and the protection diode of the modified example. [Figure 28] FIG. 28 is a plan view showing a state in which wiring is connected to the temperature sensitive diode of the modified example. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments of a semiconductor device will be described with reference to the drawings. The embodiments shown below are intended to exemplify configurations and methods for embodying the technical ideas, and are not intended to limit the materials, shapes, structures, arrangements, dimensions, etc. of the components described below.

[0009] [First embodiment] A semiconductor device 10 according to a first embodiment will be described with reference to FIGS. 1, the semiconductor device 10 is a trench-gate IGBT (Insulated Gate Bipolar Transistor) including a temperature-sensitive diode 40P for detecting the temperature of the semiconductor device 10. The semiconductor device 10 is used, for example, as a switching element in an in-vehicle inverter device. In this case, a current of, for example, 5 A or more and 1000 A or less flows through the semiconductor device 10.

[0010] The semiconductor device 10 is formed, for example, in the shape of a rectangular plate. The semiconductor device 10 has a main surface 10s, a back surface 10r (see FIG. 5) facing the opposite side of the main surface 10s, and four side surfaces 10a to 10d formed between the main surface 10s and the back surface 10r. The side surfaces 10a to 10d are, for example, surfaces connecting the main surface 10s and the back surface 10r and are perpendicular to both the main surface 10s and the back surface 10r. The main surface 10s is formed, for example, in the shape of a square. In this embodiment, the length of one side of the main surface 10s is approximately 11 mm. In other words, the chip size of the semiconductor device 10 of this embodiment is 11 mm.

[0011] In the following description, the direction in which the device main surface 10s and the device back surface 10r face is referred to as the "z direction." The z direction can also be said to be the height direction of the semiconductor device 10. Two directions perpendicular to the z direction are referred to as the "x direction" and the "y direction." In this embodiment, the device side surfaces 10a and 10b form both end faces of the semiconductor device 10 in the x direction, and the device side surfaces 10c and 10d form both end faces of the semiconductor device 10 in the y direction.

[0012] FIG. 2 shows the electrode configuration of the semiconductor device 10. 2, the semiconductor device 10 includes an emitter electrode 21, an anode electrode 22, a gate electrode 23, and a current sense electrode 24. Here, the emitter electrode 21 corresponds to the "main electrode portion," and the anode electrode 22 corresponds to the "diode connection electrode."

[0013] The semiconductor device 10 also includes gate fingers 26 electrically connected to the gate electrode 23. The gate fingers 26 are intended to quickly supply current supplied to the gate electrode 23 to main cells in portions of the emitter electrode 21 that are distant from the gate electrode 23. As shown in FIGS. 5 and 7, the semiconductor device 10 also includes a collector electrode 27. In this embodiment, the collector electrode 27 is formed over the entire surface of the back surface 10r of the device. For convenience, the gate fingers 26 are omitted from FIGS. 1, 3, and 4.

[0014] When viewed from the z direction, the emitter electrode 21 is formed over most of the device main surface 10s. The anode electrode 22, gate electrode 23, and current sense electrode 24 are each arranged in an electrode arrangement region 10ce near the device side surface 10c at both ends of the device main surface 10s in the y direction. These electrodes 22 to 24 are arranged aligned with each other in the y direction but spaced apart from each other in the x direction.

[0015] The emitter electrode 21 has electrode accommodating portions 21aa and 21ab, a diode placement portion 21b, and a pair of gate finger accommodating portions 21d. The electrode accommodating portions 21aa and 21ab are provided at the end of the emitter electrode 21 in the y direction that is closer to the device side surface 10c. The electrode accommodating portion 21aa is a portion that accommodates the anode electrode 22 and the gate electrode 23 and has a concave shape. The electrode accommodating portion 21ab is a portion that accommodates the current sense electrode 24 and has a concave shape. The electrode accommodating portion 21aa is positioned closer to the device side surface 10a in the x direction than the electrode accommodating portion 21ab.

[0016] The anode electrode 22, the gate electrode 23, and the current sense electrode 24 housed in the electrode housing portions 21aa and 21ab are aligned in the y direction and spaced apart in the x direction. In this embodiment, the anode electrode 22, the gate electrode 23, and the current sense electrode 24 are arranged in this order from the device side surface 10a to the device side surface 10b in the x direction.

[0017] The emitter electrode 21 has a protrusion 21e that protrudes toward the anode electrode 22 in the portion of the concave shape that constitutes the electrode accommodating portion 21aa that is closer to the device side surface 10a, in other words, the portion of the emitter electrode 21 that is adjacent to the anode electrode 22 in the x-direction.

[0018] The portion of the emitter electrode 21 between the electrode accommodating portion 21aa and the electrode accommodating portion 21ab in the x-direction constitutes an emitter sense region 21f that constitutes the emitter sense electrode pad 16 described later. The emitter sense region 21f constitutes a part of the electrode accommodating portion 21aa and a part of the electrode accommodating portion 21ab.

[0019] The diode arrangement portion 21b includes a portion where the temperature-sensitive diode 40P is arranged, and is connected to the electrode accommodating portion 21aa. The portion of the diode arrangement portion 21b where the temperature-sensitive diode 40P is arranged is provided at approximately the center of the emitter electrode 21 in the x and y directions. Therefore, it can be said that the temperature-sensitive diode 40P is arranged at approximately the center of the emitter electrode 21 in the x and y directions. Also, as shown in FIG. 2, it can be said that the temperature-sensitive diode 40P is arranged at approximately the center of the device main surface 10s in the x and y directions.

[0020] The diode arrangement portion 21b is a portion where the emitter electrode 21 is not formed. The portion of the diode arrangement portion 21b where the temperature-sensitive diode 40P is arranged is formed in a rectangular shape when viewed from the z direction. The emitter electrode 21 is formed to surround the temperature-sensitive diode 40P to form the diode arrangement portion 21b. Therefore, it can be said that the emitter electrode 21 has an adjacent region 21P (a region of the emitter electrode 21 surrounded by a two-dot chain line in FIG. 2) adjacent to the temperature-sensitive diode 40P. The adjacent region 21P is a region surrounding the diode arrangement portion 21b. In this embodiment, the adjacent region 21P is formed to surround the entire surface of the temperature-sensitive diode 40P close to the device side faces 10a, 10b, and 10d and a portion close to the device side face 10c. In other words, the adjacent region 21P has a portion adjacent to the entire surface of the temperature-sensitive diode 40P close to the device side faces 10a, 10b, and 10d and a portion close to the device side face 10c.

[0021] The diode arrangement portion 21b extends in the y direction from the portion of the diode arrangement portion 21b where the temperature sensitive diode 40P is arranged to the electrode accommodating portion 21aa, and is connected to the electrode accommodating portion 21aa.

[0022] A pair of gate finger accommodating portions 21d are arranged dispersedly on both sides of the diode arrangement portion 21b in the x direction. One gate finger accommodating portion 21d extends in the y direction from the electrode accommodating portion 21aa, and the other gate finger accommodating portion 21d extends in the y direction from the electrode accommodating portion 21ab. A part of the gate finger 26 is arranged in each gate finger accommodating portion 21d.

[0023] Each gate finger accommodating portion 21d extends in the y direction from the electrode accommodating portions 21aa, 21ab of the emitter electrode 21. The tip of each gate finger accommodating portion 21d is located closer to the electrode accommodating portions 21aa, 21ab than the end of the emitter electrode 21 closer to the device side surface 10d, out of both ends in the y direction.

[0024] The gate finger 26 surrounds the emitter electrode 21 and extends into both the pair of gate finger housing portions 21d and the diode placement portion 21b. The gate finger 26 in the diode placement portion 21b is formed to surround the temperature sensitive diode 40P and the protection diode 40Q. The gate finger 26 has a surface-side wiring and an internal wiring connected to the surface-side wiring. The surface-side wiring includes, for example, a metal material, and the internal wiring includes, for example, polysilicon. The surface-side wiring is formed of, for example, a material containing AlCu (an alloy of aluminum and copper), and is formed at the same position in the z direction as the emitter electrode 21 and each of the electrodes 22 to 24. The internal wiring is arranged closer to the device back surface 10r in the z direction than the surface-side wiring.

[0025] Gate fingers 26A are provided between the diode placement portion 21b and the pair of gate finger housing portions 21d and one of the y-direction ends of the emitter electrode 21 that is closer to the device side surface 10d. The gate fingers 26A have internal wiring connected to the internal wiring of the gate fingers 26. On the other hand, the gate fingers 26A do not have front-side wiring. Therefore, when viewed from the z direction, the gate fingers 26A are arranged closer to the device back surface 10r than the emitter electrode 21 at a position where they overlap with the emitter electrode 21.

[0026] 1, a protective insulating film 17 is provided on the device main surface 10s so as to cover the electrodes 21 to 24. The protective insulating film 17 is an organic protective film that protects the semiconductor device 10, and is made of a material containing, for example, polyimide (PI).

[0027] The protective insulating film 17 is provided with first to sixth openings 17A to 17F that expose the electrodes 21 to 24. The electrodes 21 to 24 exposed by the first to sixth openings 17A to 17F form pads to which conductive members from outside the semiconductor device 10 are bonded. These pads include an emitter electrode pad 11, a cathode electrode pad 12, an anode electrode pad 13, a gate electrode pad 14, a current sense electrode pad 15, and an emitter sense electrode pad 16.

[0028] The first to sixth openings 17A to 17F provided in the protective insulating film 17 are spaced apart from one another when viewed from the z direction. The emitter electrode pad 11 is a portion of the emitter electrode 21 exposed through the first opening 17A and constitutes the emitter of the IGBT. As shown in FIG. 1, the first opening 17A exposes most of the emitter electrode 21. The first opening 17A exposes a portion of the emitter electrode 21 that is closer to the device side surface 10d than the electrode accommodating portions 21aa and 21ab. More specifically, the protective insulating film 17 is provided at a position overlapping the pair of gate finger accommodating portions 21d and at a position overlapping the diode placement portion 21b and the gate finger 26A when viewed from the z direction.

[0029] As shown in FIG. 4, a first conductive member CB is joined to the emitter electrode pad 11 with a conductive bonding material such as solder. The first conductive member CB is, for example, a clip, and is formed by pressing a flat metal plate. Examples of the metal material constituting the first conductive member CB include copper (Cu) and aluminum (Al). Thus, in this embodiment, the emitter electrode pad 11 corresponds to the "first junction region." The first junction region occupies most of the emitter electrode 21 and can be said to be a portion of the emitter electrode 21 closer to the device side surface 10d than the electrode accommodating portions 21aa and 21ab. The emitter electrode pad 11 is provided with a diode placement portion 21b. In other words, the first junction region, which is the emitter electrode pad 11, can be said to include the adjacent region 21P.

[0030] As shown in FIG. 1, the cathode electrode pad 12 is a portion of the emitter electrode 21 exposed through the second opening 17B and constitutes the cathode of the temperature-sensitive diode 40P. As shown in FIG. 2, the second opening 17B opens an end of the emitter electrode 21 that is closer to the device side surface 10a and device side surface 10c. The second opening 17B opens a portion of the protruding portion 21e of the emitter electrode 21. In other words, the second opening 17B opens a portion of the emitter electrode 21 that is adjacent to the anode electrode 22 in the x direction with a gap therebetween. The second opening 17B is located adjacent to the first opening 17A in the y direction with a gap therebetween. In other words, the cathode electrode pad 12 can be said to be located adjacent to the emitter electrode pad 11 in the y direction with a gap therebetween.

[0031] The cathode electrode pad 12 is disposed closer to the side surface 10c of the device than the center in the y direction of the device main surface 10s. The cathode electrode pad 12 is adjacent to the anode electrode 22 in the x direction. The cathode electrode pad 12 and the anode electrode 22 are disposed side by side along the device side surface 10c when viewed from the z direction.

[0032] As shown in FIG. 4, a second conductive member CWA is bonded to the cathode electrode pad 12. The second conductive member CWA is, for example, a bonding wire formed by a wire bonding device. The second conductive member CWA is made of, for example, Al, Cu, or Au (gold). In this manner, in this embodiment, the cathode electrode pad 12 corresponds to the "second junction region." Since the cathode electrode pad 12 is provided in a different region from the emitter electrode pad 11, it can also be said that the second junction region is provided in a different region from the first junction region. In this manner, the emitter electrode 21 has both the first junction region and the second junction region.

[0033] 1, the first opening 17A and the second opening 17B of the protective insulating film 17 are spaced apart from each other, and therefore the protective insulating film 17 exists between the first opening 17A and the second opening 17B. In other words, the protective insulating film 17 has a partition region 17a that separates the first opening 17A and the second opening 17B. In this embodiment, the partition region 17a has a first wall portion that separates the first opening 17A and the second opening 17B in the x direction and a second wall portion that separates the first opening 17A and the second opening 17B in the y direction. Furthermore, the third openings 17C to 17F and the first opening 17A are spaced apart from each other, and therefore the protective insulating film 17 exists between each of the third openings 17C to 17F and the first opening 17A.

[0034] 7 , in the semiconductor device 10 configured as above, when the first conductive member CB is joined to the emitter electrode pad 11 and the second conductive member CWA is joined to the cathode electrode pad 12, the partition region 17a prevents the conductive bonding material, such as solder, between the first conductive member CB and the emitter electrode pad 11 from penetrating into the cathode electrode pad 12. Similarly, the conductive bonding material is prevented from penetrating into the anode electrode pad 13, the gate electrode pad 14, the current sense electrode pad 15, and the emitter sense electrode pad 16.

[0035] 1, the anode electrode pad 13 is a portion of the anode electrode 22 exposed from the third opening 17C, and constitutes the anode of the temperature-sensitive diode 40P. When viewed from the z direction, the third opening 17C is formed in a rectangular shape that is slightly smaller than the anode electrode 22. A third conductive member CWB is joined to the anode electrode pad 13.

[0036] The gate electrode pad 14 is a portion of the gate electrode 23 exposed from the fourth opening 17D, and constitutes the gate of the IGBT. The fourth opening 17D is formed in a rectangular shape that is slightly smaller than the gate electrode 23 when viewed from the z direction. A fourth conductive member CWC is joined to the gate electrode pad 14.

[0037] The current sense electrode pad 15 is a portion of the current sense electrode 24 exposed from the fifth opening 17E, and constitutes a terminal for externally extracting information for detecting a current flowing through the IGBT. When viewed from the z direction, the fifth opening 17E is formed in a rectangular shape that is slightly smaller than the current sense electrode 24. A fifth conductive member CWD is joined to the current sense electrode pad 15.

[0038] The emitter sense electrode pad 16 is a portion of the emitter electrode 21 exposed from the sixth opening 17F. The sixth opening 17F is formed in a rectangular shape that is slightly smaller than the emitter sense region 21f when viewed from the z direction. A sixth conductive member CWE is joined to the emitter sense electrode pad 16.

[0039] The third to sixth conductive members CWB, CWC, CWD, and CWE are each made of the same material as the second conductive member CWA, and are, for example, bonding wires formed by a wire bonding device.

[0040] The gate finger 26 extends from the gate electrode 23 toward the device side surface 10a and the device side surface 10d. A portion of the gate finger 26 extends from the gate electrode 23 toward the gate finger accommodating portion 21d in the y direction, bypassing the gate electrode 23 closer to the device side surface 10c than the anode electrode 22. Another portion of the gate finger 26 extends from the gate electrode 23 toward the device side surface 10b and the device side surface 10d. More specifically, another portion of the gate finger 26 extends from the gate electrode 23 toward the gate finger accommodating portion 21d in the y direction, bypassing the gate electrode 23 closer to the device side surface 10c than the emitter sense region 21f.

[0041] As shown in Figure 3, when viewed from the z direction, the semiconductor device 10 has a main cell region 18 in which main cells 18A (see Figure 6) are formed, a peripheral region 19 surrounding the main cell region 18, and an intermediate region 20 surrounded by the main cell region 18 and the peripheral region 19.

[0042] The main cell region 18 is formed over most of the device principal surface 10s. In this embodiment, the main cell region 18 is formed in a region overlapping with the emitter electrode 21 when viewed from the z direction. In other words, the main cell region 18 is formed in a region overlapping with both the emitter electrode pad 11 and the cathode electrode pad 12 (see FIG. 1). On the other hand, even in a region overlapping with the emitter electrode 21, the main cell region 18 is not formed in a position overlapping with each gate finger 26A (see FIG. 2) in the z direction. In other words, the main cell region 18 is divided into four regions by each gate finger 26A. The four main cell regions 18 are spaced apart from each other in the x direction. Of the four main cell regions 18, the main cell region 18 closest to the device side surface 10a constitutes a region overlapping with both the emitter electrode pad 11 and the cathode electrode pad 12.

[0043] The peripheral region 19 is a region where a termination structure is provided to improve the dielectric strength of the semiconductor device 10. An example of the termination structure includes a guard ring that surrounds the main cell region 18. No main cells 18A (see FIG. 5) are formed in the peripheral region 19.

[0044] When viewed from the z direction, the intermediate region 20 is a region that overlaps with the anode electrode 22, the gate electrode 23, and the current sense electrode 24. The intermediate region 20 is a region outside the main cell region 18, in other words, a region where no main cells 18A are formed.

[0045] FIG. 5 shows an example of the cross-sectional structure of the semiconductor device 10 in the main cell region 18. As shown in FIG. 5, the semiconductor device 10 includes a semiconductor substrate 30. The semiconductor substrate 30 is, for example, an n - The semiconductor substrate 30 is made of a material containing silicon (Si) and has a thickness of, for example, 50 μm or more and 200 μm or less.

[0046] The semiconductor substrate 30 has a substrate front surface 30s and a substrate back surface 30r that face opposite each other in the z direction. In other words, the z direction can also be said to be the thickness direction of the semiconductor substrate 30. Here, in this embodiment, the semiconductor substrate 30 corresponds to the "semiconductor layer." Therefore, the z direction corresponds to the thickness direction of the semiconductor layer. Therefore, "viewed from the z direction" has the same meaning as "viewed from the thickness direction of the semiconductor layer."

[0047] The semiconductor substrate 30 is formed by sequentially stacking p + a n-type collector layer 31, an n-type buffer layer 32, and an n - The semiconductor device 10 has a structure in which a collector layer 31 and a drift layer 33 are stacked. A collector electrode 27 is formed on the substrate back surface 30r. The collector electrode 27 is formed over substantially the entire surface of the substrate back surface 30r. The surface of the collector electrode 27 opposite to the collector layer 31 forms the device back surface 10r of the semiconductor device 10.

[0048] As a p-type dopant for collector layer 31, for example, B (boron), Al (aluminum), etc. are used. The dopant concentration of collector layer 31 is, for example, 1×10 15 cm -3 Over 2×10 19 cm-3 The following is the result.

[0049] For example, N (nitrogen), P (phosphorus), As (arsenic), etc. are used as n-type dopants for buffer layer 32 and drift layer 33. The dopant concentration of buffer layer 32 is, for example, 1×10 15 cm -3 5x10 or more 17 cm -3 The dopant concentration of the drift layer 33 is lower than that of the buffer layer 32, for example, 1×10 13 cm -3 5x10 or more 14 cm -3 The following is the result.

[0050] A p-type base region 34 is formed on the surface of the drift layer 33, i.e., on the substrate surface 30s. The base region 34 is formed over substantially the entire surface of the substrate surface 30s. The dopant concentration of the base region 34 is, for example, 1×10 16 cm -3 More than 1×10 18 cm -3 The depth of the base region 34 from the substrate surface 30s is, for example, not less than 1.0 μm and not more than 3.0 μm.

[0051] A plurality of trenches 35 are arranged side by side on the surface (substrate surface 30s) of the base region 34 in the main cell region 18. The trenches 35 extend, for example, along the y direction and are spaced apart from one another in the x direction. This divides the main cells 18A into stripes. The spacing between adjacent trenches 35 in the x direction (the center-to-center distance between the trenches 35) is, for example, 1.5 μm or more and 7.0 μm or less. The width of each trench 35 (the dimension of the trench 35 in the x direction) is, for example, 0.5 μm or more and 3.0 μm or less. Each trench 35 penetrates the base region 34 in the z direction and extends partway through the drift layer 33. The trenches 35 may be formed in a lattice pattern to divide the matrix-shaped main cells 18A.

[0052] The surface of the base region 34 in the main cell region 18 (substrate surface 30s) has n + The emitter regions 36 are formed in the base region 34. The emitter regions 36 are arranged on both sides of the trench 35 in the x direction. In other words, it can be said that the emitter regions 36 are provided in the base region 34 on both sides of the trench 35 in the arrangement direction of the trenches 35. Therefore, two emitter regions 36 are arranged with a gap between them in the x direction between adjacent trenches 35 in the x direction. The depth of each emitter region 36 is, for example, 0.2 μm or more and 0.6 μm or less. The dopant concentration of each emitter region 36 is higher than that of the base region 34, for example, 1×10 19 cm -3 5x10 or more 20 cm -3 The following is the result.

[0053] The surface of the base region 34 in the main cell region 18 (substrate surface 30s) contains p + A base contact region 37 of a type is formed. The base contact region 37 is provided at a position adjacent to the emitter region 36 in the x direction. In other words, the base contact region 37 is provided in the x direction between two emitter regions 36 provided between the x directions of the trenches 35 adjacent to each other in the x direction. Each base contact region 37 may be formed deeper than the emitter region 36. The depth of each base contact region 37 is, for example, 0.2 μm or more and 1.6 μm or less. The dopant concentration of each base contact region 37 is higher than that of the base region 34, for example, 5×10 18 cm -3 More than 1×10 20 cm -3 The following is the result.

[0054] An insulating film 38 is integrally formed on both the inner surface of each trench 35 and the substrate surface 30s. The insulating film 38 includes, for example, silicon oxide (SiO2). The thickness of the insulating film 38 is, for example, not less than 1100 Å and not more than 1300 Å.

[0055] An electrode material containing, for example, polysilicon is buried in each trench 35 via an insulating film 38. The electrode material buried in each trench 35 is electrically connected to either the gate electrode 23 (gate finger 26) or the emitter electrode 21. That is, the electrode material buried in each trench 35 forms a gate trench 23A and an emitter trench 21A. In this embodiment, the gate trenches 23A and the emitter trenches 21A are alternately provided in the arrangement direction of the multiple trenches 35. In this embodiment, both the gate trenches 23A and the emitter trenches 21A are buried up to the opening end of each trench 35.

[0056] An intermediate insulating film 39 is formed on an insulating film 38 provided on the substrate surface 30s. The intermediate insulating film 39 includes, for example, SiO2. The emitter electrode 21 is formed on the intermediate insulating film 39. In other words, the intermediate insulating film 39 is an interlayer insulating film that fills the gap between the emitter electrode 21 and the gate trench 23A. The intermediate insulating film 39 can also be said to be an interlayer insulating film that fills the gap between the emitter electrode 21 and the emitter trench 21A. The thickness of the intermediate insulating film 39 is 3000 Å or more and 15000 Å or less. In this embodiment, the insulating film 38 and the intermediate insulating film 39 correspond to "insulating films."

[0057] The insulating film 38 and the intermediate insulating film 39 are provided with a plurality of contact holes 39a that penetrate both the insulating film 38 and the intermediate insulating film 39 in the z direction. The contact holes 39a are provided at positions that overlap the base contact regions 37 when viewed from the z direction. The emitter electrode 21 is connected to the base contact regions 37 via the contact holes 39a.

[0058] FIG. 6 shows the cross-sectional structure of the semiconductor device 10 in the main cell region 18, including a part of the emitter electrode pad 11 and the cathode electrode pad 12, and in the intermediate region 20, including the anode electrode 22. As shown in FIG.

[0059] As shown in FIG. 6 , because the cathode electrode pad 12 is composed of the emitter electrode 21, the region RK directly below the cathode electrode pad 12 in the semiconductor substrate 30 can also be defined as the main cell region 18. Furthermore, the region RM directly below the portion of the semiconductor substrate 30 between the first opening 17A and the second opening 17B can also be defined as the main cell region 18. Therefore, as shown in FIG. 6 , main cells 18A are provided in both the region RK and the region RM. That is, when viewed from the z direction, main cells 18A are provided in the region RE overlapping with the emitter electrode pad 11 in the semiconductor substrate 30, the region RK overlapping with the cathode electrode pad 12, and the region RM overlapping with the portion between the first opening 17A and the second opening 17B. Here, the region RE corresponds to the "first semiconductor region," and the region RK corresponds to the "second semiconductor region."

[0060] Furthermore, no emitter region 36 is formed on both sides in the x direction of trench 35A provided in a portion of region RK adjacent to intermediate region 20. In trench 35A, for example, emitter trench 21A is formed.

[0061] On the other hand, the intermediate region 20 is a region outside the main cell region 18, and therefore no main cells 18A are formed in it. A base region 34 is formed directly below the intermediate region 20. The depth of the base region 34 in the intermediate region 20 is deeper than the base region 34 in the main cell region 18. More specifically, the depth of the base region 34 in the intermediate region 20 is deeper than the trench 35A (35).

[0062] The circuit configuration of the semiconductor device 10 described above is shown in FIG. In the semiconductor device 10, the emitter electrode 21 also serves as the cathode electrode, and therefore, as shown in FIG. 7, the cathode of the temperature sensitive diode 40P is electrically connected to the emitter of the IGBT within the semiconductor device 10.

[0063] 7, in this embodiment, the semiconductor device 10 includes a protection diode 40Q connected in anti-parallel to the temperature-sensitive diode 40P. The protection diode 40Q is a diode for protecting the temperature-sensitive diode 40P. The anode of the protection diode 40Q is electrically connected to both the emitter of the IGBT and the cathode of the temperature-sensitive diode 40P within the semiconductor device 10.

[0064] (Configuration of temperature-sensitive diode and protection diode) An example of the detailed configuration of the temperature sensitive diode 40P and the protection diode 40Q will be described with reference to FIGS.

[0065] Fig. 8 schematically shows the planar structure of the temperature-sensing diode 40P and the protection diode 40Q, and Fig. 9 shows the structure of the wiring connected to the temperature-sensing diode 40P and the protection diode 40Q in Fig. 8. Fig. 10 schematically shows the cross-sectional structure of the temperature-sensing diode 40P, and Fig. 12 schematically shows the cross-sectional structure of the protection diode 40Q. Fig. 13 schematically shows the cross-sectional structures of the temperature-sensing diode 40P, the protection diode 40Q, the gate finger 26, etc. Also, Fig. 11 shows an example of the arrangement of the through-wiring connecting the above-mentioned wiring to the temperature-sensing diode 40P.

[0066] 10 and 12, the semiconductor device 10 includes a thin-film diode semiconductor layer 43 in which a temperature-sensitive diode 40P and a protection diode 40Q are provided. The diode semiconductor layer 43 includes, for example, polysilicon. The diode semiconductor layer 43 is formed in a rectangular shape when viewed from the z direction. In this embodiment, the diode semiconductor layer 43 has a square shape when viewed from the z direction.

[0067] The diode semiconductor layer 43 is formed on a surface 38Aa of an insulating film 38A formed on the substrate surface 30s. The insulating film 38A is an insulating film formed integrally with the insulating film 38. That is, the insulating film 38A constitutes a part of the insulating film 38. However, unlike the insulating film 38, the insulating film 38A has a function of insulating the diode semiconductor layer 43 from the semiconductor substrate 30. Therefore, the insulating film 38 and the insulating film 38A may be formed separately.

[0068] As shown in FIG. 8, the temperature sensitive diode 40P includes a plurality of diode cells (four in this embodiment). Here, for convenience, the plurality of diode cells are referred to as a "first diode cell 40A," a "second diode cell 40B," a "third diode cell 40C," and a "fourth diode cell 40D." The first to fourth diode cells 40A to 40D are formed of a diode semiconductor layer 43. Here, in this embodiment, the first to fourth diode cells 40A to 40D are arranged in a line when viewed from the z direction. In this embodiment, the first to fourth diode cells 40A to 40D are arranged in a line in the y direction. More specifically, the first to fourth diode cells 40A to 40D are arranged aligned with each other in the x direction and spaced apart from each other in the y direction. The first to fourth diode cells 40A to 40D are arranged in the order of the first diode cell 40A, the second diode cell 40B, the third diode cell 40C, and the fourth diode cell 40D in the y direction from the device side surface 10d toward the device side surface 10c (see FIG. 2 for both). It can also be said that the first to fourth diode cells 40A to 40D are arranged in the order of the first diode cell 40A, the second diode cell 40B, the third diode cell 40C, and the fourth diode cell 40D in the y direction from the temperature sensitive diode 40P toward each of the electrode pads 12 to 16.

[0069] The first to fourth diode cells 40A to 40D have the same configuration, shape, and size. Therefore, hereinafter, the configuration of the first diode cell 40A will be described in detail, and descriptions of the configurations of the second to fourth diode cells 40B to 40D will be omitted.

[0070] The first diode cell 40A is configured with a first semiconductor region 44P of a first conductivity type and a second semiconductor region 45P of a second conductivity type. The first conductivity type is, for example, p-type, and the second conductivity type is, for example, n-type. In one example, the outer shape of the first diode cell 40A when viewed from the z direction is quadrangular. In this embodiment, the outer shape of the first diode cell 40A when viewed from the z direction is square. Here, in this embodiment, the first semiconductor region 44P corresponds to the "semiconductor region for the first diode," and the second semiconductor region 45P corresponds to the "semiconductor region for the second diode."

[0071] The first semiconductor region 44P is provided at the center of the first diode cell 40A in the x and y directions. In this embodiment, the first semiconductor region 44P has a circular shape when viewed from the z direction. Therefore, the first semiconductor region 44P has a circumferential surface 44Pa.

[0072] The p-type dopant of the first semiconductor region 44P may be, for example, B or Al. The dopant concentration of the first semiconductor region 44P may be, for example, 1×10 18 cm -3 More than 1×10 20 cm -3 The following is the result.

[0073] A first length measurement pattern 46P for measuring the length of the first semiconductor region 44P (for example, the diameter of the first semiconductor region 44P) is formed in the first semiconductor region 44P. The first length measurement pattern 46P is formed at the center of the first semiconductor region 44P. When viewed from the z direction, the shape of the first length measurement pattern 46P is rectangular with the long side direction being in the y direction and the short side direction being in the x direction.

[0074] The first measurement pattern 46P has a pattern in which a plurality of strip-shaped straight lines are arranged in parallel. The dopant concentration in the region in which the first measurement pattern 46P is formed is lower than the dopant concentration in other regions of the first semiconductor region 44P. In this embodiment, the first measurement pattern 46P is provided as a non-doped layer.

[0075] When viewed from the z direction, the second semiconductor region 45P is formed in a ring shape surrounding the first semiconductor region 44P. The second semiconductor region 45P is bonded to the first semiconductor region 44P. The second semiconductor region 45P has an inner circumferential surface 45Pa that is bonded over the entire circumference to the circumferential surface 44Pa of the first semiconductor region 44P.

[0076] The outer shape of the second semiconductor region 45P forms the outer shape of the first diode cell 40A. That is, the outer shape of the second semiconductor region 45P when viewed from the z direction is, for example, a quadrangle, and in this embodiment, a square. It can also be said that the second semiconductor region 45P has an outer side surface 45Pb formed in a quadrangle when viewed from the z direction.

[0077] The n-type dopant of the second semiconductor region 45P may be, for example, N, P, or As. The dopant concentration of the second semiconductor region 45P may be, for example, 1×10 18 cm -3 5x10 or more 20 cm -3 The following is the result.

[0078] A second length measurement pattern 47P is formed in the second semiconductor region 45P to measure the length of the second semiconductor region 45P (for example, the external length of the second semiconductor region 45P in the x direction or the external length of the second semiconductor region 45P in the y direction). The second length measurement pattern 47P is formed at one of the four corners of the second semiconductor region 45P. When viewed from the z direction, the shape of the second length measurement pattern 47P is rectangular with the long side direction being the y direction and the short side direction being the x direction. In this embodiment, the size of the second length measurement pattern 47P is equal to the size of the first length measurement pattern 46P.

[0079] Second measurement pattern 47P has a pattern in which multiple strip-shaped straight lines are arranged in parallel. The dopant concentration in the region in which second measurement pattern 47P is formed is lower than the dopant concentration in other regions of second semiconductor region 45P. In this embodiment, second measurement pattern 47P is provided as a non-doped layer.

[0080] The protection diode 40Q includes a plurality of protection diode cells (four in this embodiment). For convenience, the plurality of protection diode cells are referred to as a "first protection diode cell 40E," a "second protection diode cell 40F," a "third protection diode cell 40G," and a "fourth protection diode cell 40H." The first to fourth protection diode cells 40E to 40H are formed of a diode semiconductor layer 43.

[0081] The first to fourth protection diode cells 40E to 40H are arranged in a line when viewed from the z direction. In this embodiment, the first to fourth protection diode cells 40E to 40H are arranged in a line in the y direction. More specifically, the first to fourth protection diode cells 40E to 40H are arranged aligned with one another in the x direction and spaced apart from one another in the y direction. The first to fourth protection diode cells 40E to 40H are arranged in the following order from the device side surface 10c toward the device side surface 10d in the y direction: the first protection diode cell 40E, the second protection diode cell 40F, the third protection diode cell 40G, and the fourth protection diode cell 40H. It can also be said that the first to fourth protection diode cells 40E to 40H are arranged in the order of the first protection diode cell 40E, the second protection diode cell 40F, the third protection diode cell 40G, and the fourth protection diode cell 40H in the y direction from each of the electrode pads 12 to 16 toward the protection diode 40Q.

[0082] The temperature sensing diode 40P and the protection diode 40Q are aligned in the y direction and spaced apart from each other in the x direction. More specifically, the first diode cell 40A and the fourth protection diode cell 40H are arranged opposite each other in the x direction, the second diode cell 40B and the third protection diode cell 40G are arranged opposite each other in the x direction, the third diode cell 40C and the second protection diode cell 40F are arranged opposite each other in the x direction, and the fourth diode cell 40D and the first protection diode cell 40E are arranged opposite each other in the x direction.

[0083] The protection diode 40Q is disposed closer to the device side surface 10a (see FIG. 2) than the temperature sensing diode 40P. In other words, the temperature sensing diode 40P is disposed closer to the device side surface 10b (see FIG. 2) than the protection diode 40Q.

[0084] The first to fourth protection diode cells 40E to 40H have the same configuration, shape, and size as one another, and also have the same configuration, shape, and size as the first diode cell 40A. Therefore, hereinafter, an outline of the configuration of the first protection diode cell 40E will be described, and a description of the configurations of the second to fourth protection diode cells 40F to 40H will be omitted.

[0085] The first protection diode cell 40E is composed of a first semiconductor region 44Q of a first conductivity type (p-type) and a second semiconductor region 45Q of a second conductivity type (n-type). The first semiconductor region 44Q has a circumferential surface 44Qa, and the second semiconductor region 45Q has an inner circumferential surface 45Qa that is joined to the circumferential surface 44Qa of the first semiconductor region 44Q along the entire periphery. The second semiconductor region 45Q has an outer side surface 45Qb that forms the outer shape of the first protection diode cell 40E. The outer side surface 45Qb is formed in a quadrangular shape when viewed from the z direction. The p-type dopant concentration of the first semiconductor region 44Q is the same as that of the first semiconductor region 44P of the first diode cell 40A, and the n-type dopant concentration of the second semiconductor region 45Q is the same as that of the second semiconductor region 45P of the first diode cell 40A.

[0086] A first length measurement pattern 46Q for measuring the length of the first semiconductor region 44Q (for example, the diameter of the first semiconductor region 44P) is formed in the first semiconductor region 44Q. The first length measurement pattern 46Q is formed in the center of the first semiconductor region 44Q. The outer shape, pattern, and dopant concentration of the first length measurement pattern 46P are the same as those of the first length measurement pattern 46P.

[0087] A second length measurement pattern 47Q is formed in the second semiconductor region 45Q to measure the length of the second semiconductor region 45Q (for example, the outer length of the second semiconductor region 45Q in the x direction or the outer length of the second semiconductor region 45Q in the y direction). The second length measurement pattern 47Q is formed in one of the four corners of the second semiconductor region 45Q. The outer shape, pattern, and dopant concentration of the second length measurement pattern 47Q are the same as those of the second length measurement pattern 47P.

[0088] As shown in FIG. 9, a first wiring lead-out region 21ba and a second wiring lead-out region 21bb are provided at both ends in the y direction of the diode arrangement section 21b that accommodates both the temperature sensing diode 40P and the protection diode 40Q.

[0089] The first wiring lead-out region 21ba is a region formed at one of both ends of the diode arrangement portion 21b in the y direction that is closer to the electrode accommodating portion 21aa. In other words, the first wiring lead-out region 21ba is a region of the diode arrangement portion 21b that is connected to the electrode accommodating portion 21aa. The second wiring lead-out region 21bb is a region formed at one of both ends of the diode arrangement portion 21b in the y direction that is farther from the electrode accommodating portion 21aa. The second wiring lead-out region 21bb is adjacent to the adjacent region 21P in the y direction.

[0090] The temperature sensing diode 40P and the protection diode 40Q are arranged between the first wiring lead-out region 21ba and the second wiring lead-out region 21bb in the y direction. Therefore, it can be said that the fourth diode cell 40D is arranged closer to the first wiring lead-out region 21ba, and the first diode cell 40A is arranged closer to the second wiring lead-out region 21bb. It can also be said that the first protection diode cell 40E is arranged closer to the first wiring lead-out region 21ba, and the fourth protection diode cell 40H is arranged closer to the second wiring lead-out region 21bb.

[0091] In this embodiment, the first wiring lead-out region 21ba is a region of the diode arrangement portion 21b between the temperature sensing diode 40P and the protection diode 40Q and the electrode accommodating portion 21aa in the y direction. The second wiring lead-out region 21bb is a region of the diode arrangement portion 21b between the temperature sensing diode 40P and the protection diode 40Q and the adjacent region 21P in the y direction.

[0092] 10 and 12, the diode semiconductor layer 43 is covered with an intermediate insulating film 39. A temperature-sensing diode wiring 50 electrically connected to the temperature-sensing diode 40P and a protection diode wiring 60 electrically connected to the protection diode 40Q are provided on a surface 39b of the intermediate insulating film 39. Here, the surface 39b of the intermediate insulating film 39 faces the same side as the substrate surface 30s of the semiconductor substrate 30. Here, in this embodiment, the temperature-sensing diode wiring 50 corresponds to "wiring electrically connected to the first diode semiconductor region and the second diode semiconductor region."

[0093] As shown in FIG. 9, the first to fourth diode cells 40A to 40D are connected in series with each other by the temperature sensing diode wiring 50. The temperature sensing diode wiring 50 includes first to fifth wirings 51 to 55. The first to fifth wirings 51 to 55 are aligned with each other in the x direction and spaced apart from each other in the y direction. In other words, the first to fifth wirings 51 to 55 are aligned with each other in the short-side direction of the temperature sensing diode 40P and spaced apart from each other in the longitudinal direction of the temperature sensing diode 40P. The first wiring 51 and the fifth wiring 55 are distributed and arranged at both ends of the temperature sensing diode 40P in the longitudinal direction (y direction). The second to fourth wirings 52 to 54 are arranged between the first wiring 51 and the fifth wiring 55 in the y direction. The second to fourth wirings 52 to 54 are insulated from both the first wiring 51 and the fifth wiring 55, respectively.

[0094] Thus, in this embodiment, the first diode cell 40A corresponds to the “first end cell,” and the fourth diode cell 40D corresponds to the “second end cell.” The first wiring 51 corresponds to the “first end wiring,” and the fifth wiring 55 corresponds to the “second end wiring.”

[0095] The temperature-sensitive diode 40P has a first electrode 41P serving as an anode electrode and a second electrode 42P serving as a cathode electrode. The first electrode 41P and the second electrode 42P are provided separately at both ends of the temperature-sensitive diode 40P in the longitudinal direction (y direction). As shown in FIG. 9, the first electrode 41P is provided at one of both ends of the temperature-sensitive diode 40P that is closer to the second wiring lead-out region 21bb. The second electrode 42P is provided at one of both ends of the temperature-sensitive diode 40P that is closer to the first wiring lead-out region 21ba. In other words, the first electrode 41P is provided at one of both ends of the temperature-sensitive diode 40P that is farther from the electrode pads 12 to 16, and the second electrode 42P is provided at one of both ends of the temperature-sensitive diode 40P that is closer to the electrode pads 12 to 16.

[0096] The first wiring 51 is electrically connected to the first semiconductor region 44P of the first diode cell 40A and is a wiring for supplying a current from outside the temperature-sensitive diode 40P to the first diode cell 40A. The first wiring 51 has a first region connection portion 51A provided at a position overlapping the first semiconductor region 44P of the first diode cell 40A when viewed from the z direction, and a first extension portion 51B extending from the first region connection portion 51A to outside the first semiconductor region 44P of the first diode cell 40A. In this embodiment, the first region connection portion 51A and the first extension portion 51B are integrated. The first extension portion 51B forms the first electrode 41P of the temperature-sensitive diode 40P. Here, in this embodiment, the first region connection portion 51A corresponds to the "first end connection portion," and the first extension portion 51B corresponds to the "first end extension portion."

[0097] The first region connection portion 51A has a circular shape when viewed from the z direction. In this embodiment, the center of the first region connection portion 51A and the center of the first semiconductor region 44P coincide with each other. The diameter of the first region connection portion 51A is slightly smaller than the diameter of the first semiconductor region 44P. The diameter of the first region connection portion 51A can be changed arbitrarily and may be, for example, equal to or larger than the diameter of the first semiconductor region 44P.

[0098] The first extension portion 51B extends from the first region connection portion 51A toward the opposite side to the second wiring 52. Therefore, when viewed from the z direction, the first extension portion 51B is formed so as to overlap with the second semiconductor region 45P of the first diode cell 40A.

[0099] The second wiring 52 is a wiring for connecting the first diode cell 40A and the second diode cell 40B in series. The second wiring 52 electrically connects the second semiconductor region 45P of the first diode cell 40A and the first semiconductor region 44P of the second diode cell 40B. The second wiring 52 is formed so as to straddle the first diode cell 40A and the second diode cell 40B.

[0100] The second wiring 52 includes a first part 56, a second part 57, and a connection part 58. In this embodiment, the first part 56, the second part 57, and the connection part 58 are integrated together.

[0101] When viewed from the z direction, first part 56 is provided at a position overlapping with second semiconductor region 45P of first diode cell 40A, and is electrically connected to second semiconductor region 45P of first diode cell 40A. When viewed from the z direction, first part 56 is shaped like an open ring that surrounds first semiconductor region 44P of first diode cell 40A and has a gap in a portion of the circumferential direction of first semiconductor region 44P of first diode cell 40A. When viewed from the z direction, first part 56 can also be said to be shaped like an open ring that surrounds first region connection portion 51A of first wiring 51 and has a gap so as not to come into contact with first extension portion 51B.

[0102] When viewed from the z direction, the second part 57 is provided at a position overlapping with the first semiconductor region 44P of the second diode cell 40B, and is electrically connected to the first semiconductor region 44P of the second diode cell 40B. When viewed from the z direction, the second part 57 has a circular shape. In this embodiment, the second part 57 has the same shape as the first region connection portion 51A.

[0103] The connecting part 58 connects the first part 56 and the second part 57. The connecting part 58 extends in the y direction. The third wiring 53 is a wiring for connecting the second diode cell 40B and the third diode cell 40C in series. The third wiring 53 electrically connects the second semiconductor region 45P of the second diode cell 40B and the first semiconductor region 44P of the third diode cell 40C. The third wiring 53 is formed so as to straddle the second diode cell 40B and the third diode cell 40C.

[0104] The third wiring 53 has the same shape as the second wiring 52, and therefore a detailed description of its shape will be omitted. A first part 56 of the third wiring 53 is provided at a position overlapping with the second semiconductor region 45P of the second diode cell 40B when viewed from the z direction, and is electrically connected to the second semiconductor region 45P of the second diode cell 40B. A second part 57 of the third wiring 53 is provided at a position overlapping with the first semiconductor region 44P of the third diode cell 40C when viewed from the z direction, and is electrically connected to the first semiconductor region 44P of the third diode cell 40C.

[0105] The fourth wiring 54 is a wiring for connecting the third diode cell 40C and the fourth diode cell 40D in series. The fourth wiring 54 electrically connects the second semiconductor region 45P of the third diode cell 40C and the first semiconductor region 44P of the fourth diode cell 40D. The fourth wiring 54 is formed so as to straddle the third diode cell 40C and the fourth diode cell 40D.

[0106] The fourth wiring 54 has the same shape as the second wiring 52, and therefore a detailed description of its shape will be omitted. A first part 56 of the fourth wiring 54 is provided at a position overlapping with the second semiconductor region 45P of the third diode cell 40C when viewed from the z direction, and is electrically connected to the second semiconductor region 45P of the third diode cell 40C. A second part 57 of the fourth wiring 54 is provided at a position overlapping with the first semiconductor region 44P of the fourth diode cell 40D when viewed from the z direction, and is electrically connected to the first semiconductor region 44P of the fourth diode cell 40D.

[0107] The fifth wiring 55 is electrically connected to the second semiconductor region 45P of the fourth diode cell 40D and is a wiring for supplying the current flowing through the temperature sensing diode 40P to the outside of the temperature sensing diode 40P. The fifth wiring 55 has a fifth region connection portion 55A provided at a position overlapping with the first semiconductor region 44P of the fourth diode cell 40D when viewed from the z direction, and a fifth extension portion 55B extending from the fifth region connection portion 55A to the outside of the first semiconductor region 44P of the fourth diode cell 40D. In this embodiment, the fifth region connection portion 55A and the fifth extension portion 55B are integrated. The fifth extension portion 55B forms the second electrode 42P of the temperature sensing diode 40P. Here, in this embodiment, the fifth region connection portion 55A corresponds to the "second end connection portion," and the fifth extension portion 55B corresponds to the "second end extension portion."

[0108] When viewed from the z direction, the fifth region connection portion 55A is formed in an open ring shape that surrounds the first semiconductor region 44P of the fourth diode cell 40D and has a gap in a portion of the circumferential direction of the first semiconductor region 44P. When viewed from the z direction, the fifth region connection portion 55A can also be said to be formed in an open ring shape that surrounds the second part of the fourth wiring 54 that is electrically connected to the first semiconductor region 44P and has a gap so as to allow contact with the connection part of the fourth wiring 54. In this embodiment, the fifth region connection portion 55A has the same shape as the first part 56 of the second wiring 52.

[0109] The fifth extension portion 55B extends from the fifth region connection portion 55A toward the opposite side to the first wiring 51. In this embodiment, the length of the fifth extension portion 55B is shorter than the length of the first extension portion 51B.

[0110] 10, the semiconductor device 10 includes first to eighth through wirings 81P to 88P as through wirings that penetrate the intermediate insulating film 39. The first to eighth through wirings 81P to 88P are wirings for individually connecting the first to fifth wirings 51 to 55 and the diode cells 40A to 40D. For convenience, FIG. 10 schematically shows the connection structure between the first to fifth wirings 51 to 55 and the diode cells 40A to 40D by the first to eighth through wirings 81P to 88P. Therefore, the arrangement positions and number of the first to eighth through wirings 81P to 88P are not limited to those shown in FIG. 10.

[0111] The first through wiring 81P is a wiring that connects the first semiconductor region 44P of the first diode cell 40A and the first wiring 51. As a result, the first semiconductor region 44P of the first diode cell 40A is electrically connected to the first electrode 41P of the temperature sensitive diode 40P. When viewed from the z direction, the first through wiring 81P is arranged at a position that overlaps both the first semiconductor region 44P of the first diode cell 40A and the first wiring 51.

[0112] The second through wiring 82P is a wiring that connects the second semiconductor region 45P of the first diode cell 40A and the second wiring 52. When viewed from the z direction, the second through wiring 82P is arranged at a position that overlaps both the second semiconductor region 45P of the first diode cell 40A and the second wiring 52.

[0113] The third through wiring 83P is a wiring that connects the first semiconductor region 44P of the second diode cell 40B and the second wiring 52. When viewed from the z direction, the third through wiring 83P is arranged at a position that overlaps both the first semiconductor region 44P of the second diode cell 40B and the second wiring 52.

[0114] In this way, the second semiconductor region 45P of the first diode cell 40A and the first semiconductor region 44P of the second diode cell 40B are connected via the second through wiring 82P, the second wiring 52, and the third through wiring 83P.

[0115] The fourth through wiring 84P is a wiring that connects the second semiconductor region 45P of the second diode cell 40B and the third wiring 53. When viewed from the z direction, the fourth through wiring 84P is arranged at a position that overlaps both the second semiconductor region 45P of the second diode cell 40B and the third wiring 53.

[0116] The fifth through wiring 85P is a wiring that connects the first semiconductor region 44P of the third diode cell 40C and the third wiring 53. When viewed from the z direction, the fifth through wiring 85P is arranged at a position that overlaps with both the first semiconductor region 44P of the third diode cell 40C and the third wiring 53.

[0117] In this way, the second semiconductor region 45P of the second diode cell 40B and the first semiconductor region 44P of the third diode cell 40C are connected via the fourth through wiring 84P, the third wiring 53, and the fifth through wiring 85P.

[0118] The sixth through wiring 86P is a wiring that connects the second semiconductor region 45P of the third diode cell 40C and the fourth wiring 54. When viewed from the z direction, the sixth through wiring 86P is arranged at a position that overlaps with both the second semiconductor region 45P of the third diode cell 40C and the fourth wiring 54.

[0119] The seventh through wiring 87P is a wiring that connects the first semiconductor region 44P of the fourth diode cell 40D and the fourth wiring 54. When viewed from the z direction, the seventh through wiring 87P is disposed at a position that overlaps with both the first semiconductor region 44P of the fourth diode cell 40D and the fourth wiring 54.

[0120] In this way, the second semiconductor region 45P of the third diode cell 40C and the first semiconductor region 44P of the fourth diode cell 40D are connected via the sixth through wire 86P, the fourth wire 54, and the seventh through wire 87P.

[0121] The eighth through wiring 88P is a wiring that connects the second semiconductor region 45P of the fourth diode cell 40D and the fifth wiring 55. As a result, the second semiconductor region 45P of the fourth diode cell 40D is electrically connected to the second electrode 42P of the temperature sensitive diode 40P. When viewed from the z direction, the eighth through wiring 88P is arranged at a position that overlaps both the second semiconductor region 45P of the fourth diode cell 40D and the fifth wiring 55. Note that a plurality of each of the first to eighth through wirings 81P to 88P may be provided.

[0122] 11 shows an example of the arrangement of the first to fourth through wirings 81P to 84P relative to the diode cells 40A, 40B and the first to third wirings 51 to 53. The fifth to eighth through wirings 85P to 88P are arranged in the same manner as the first to fourth through wirings 81P to 84P.

[0123] The first through wiring 81P is arranged at a position overlapping the outer periphery of the first semiconductor region 44P of the first diode cell 40A when viewed from the z direction. That is, the first through wiring 81P is arranged at a position overlapping the outer periphery of the first wiring 51 when viewed from the z direction. Therefore, the first through wiring 81P is arranged at a position different from the first length measurement pattern 46P of the first diode cell 40A. A plurality of first through wirings 81P are provided. Each first through wiring 81P has an annular shape when viewed from the z direction. The plurality of first through wirings 81P are arranged concentrically. In the present embodiment, each first through wiring 81P is arranged concentrically with the first semiconductor region 44P (first wiring 51).

[0124] The second through wiring 82P is arranged at a position where it overlaps with the outer periphery of the first part 56 of the second wiring 52. The second through wiring 82P is arranged at a position different from the second length measurement pattern 47P of the first diode cell 40A. A plurality of second through wirings 82P are provided.

[0125] The third through wiring 83P is arranged at a position overlapping the outer periphery of the first semiconductor region 44P of the second diode cell 40B. In other words, the third through wiring 83P is arranged at a position overlapping the outer periphery of the second part 57 of the second wiring 52. The third through wiring 83P is arranged at a position different from the first length measurement pattern 46P of the second diode cell 40B. A plurality of third through wirings 83P are provided. The shape and number of each third through wiring 83P are the same as those of the first through wirings 81P.

[0126] The fourth through wiring 84P is arranged at a position overlapping the outer periphery of the first part 56 of the third wiring 53. The fourth through wiring 84P is arranged at a position different from the second length measurement pattern 47P of the second diode cell 40B. A plurality of fourth through wirings 84P are provided. The shape of each fourth through wiring 84P and the position of the third wiring 53 relative to the first part 56 are similar to the shape of each second through wiring 82P and the position of the second wiring 52 relative to the first part 56.

[0127] As shown in FIG. 9, the first to fourth protection diode cells 40E to 40H are connected in series to one another by a protection diode wiring 60. The protection diode wiring 60 includes first to fifth wirings 61 to 65. The first to fifth wirings 61 to 65 are aligned with one another in the x direction and spaced apart from one another in the y direction. In other words, the first to fifth wirings 61 to 65 are aligned with one another in the short-side direction of the protection diode 40Q and spaced apart from one another in the longitudinal direction of the protection diode 40Q. The first wiring 61 and the fifth wiring 65 are distributed and arranged at both ends of the protection diode 40Q in the longitudinal direction (y direction). The second to fourth wirings 62 to 64 are arranged between the first wiring 61 and the fifth wiring 65 in the y direction. The second to fourth wirings 62 to 64 are insulated from both the first wiring 61 and the fifth wiring 65.

[0128] The protection diode 40Q has a first electrode 41Q serving as an anode electrode and a second electrode 42Q serving as a cathode electrode. The first electrode 41Q and the second electrode 42Q are provided at both ends of the protection diode 40Q in the longitudinal direction (y direction). As shown in FIG. 9, the first electrode 41Q is provided at one of both ends of the protection diode 40Q that is closer to the first wiring lead-out region 21ba. The second electrode 42Q is provided at one of both ends of the protection diode 40Q that is closer to the second wiring lead-out region 21bb. In other words, the first electrode 41Q is provided at one of both ends of the protection diode 40Q that is closer to the electrode pads 12 to 16 (see FIG. 1), and the second electrode 42Q is provided at one of both ends of the protection diode 40Q that is farther from the electrode pads 12 to 16.

[0129] The first wiring 61 is electrically connected to the second semiconductor region 45Q of the fourth protection diode cell 40H and is a wiring for supplying current from outside the protection diode 40Q to the fourth protection diode cell 40H. The first wiring 61 has a first region connection portion 61A provided at a position overlapping with the second semiconductor region 45Q of the fourth protection diode cell 40H when viewed from the z direction, and a first extension portion 61B extending from the first region connection portion 61A to outside the second semiconductor region 45Q of the fourth protection diode cell 40H. In this embodiment, the first region connection portion 61A and the first extension portion 61B are integrated. The first extension portion 61B forms the second electrode 42Q of the protection diode 40Q. Furthermore, the first wiring 61 is arranged at a position overlapping with the first wiring 51 when viewed from the x direction. When viewed from the z direction, the fifth region connection portion 55A is formed in an open ring shape that surrounds the first semiconductor region 44P of the fourth protection diode cell 40H and has a gap in part of the circumferential direction of the first semiconductor region 44P.

[0130] The first extension portion 61B extends from the first region connection portion 61A toward the opposite side to the second wiring 62. When viewed from the z direction, the first extension portion 61B is formed so as to overlap with the second semiconductor region 45Q of the fourth protection diode cell 40H.

[0131] The second wiring 62 is a wiring for connecting the fourth protection diode cell 40H and the third protection diode cell 40G in series. The second wiring 62 electrically connects the second semiconductor region 45Q of the fourth protection diode cell 40H and the first semiconductor region 44Q of the third protection diode cell 40G. The second wiring 62 is formed so as to straddle the fourth protection diode cell 40H and the third protection diode cell 40G.

[0132] The second wiring 62 includes a first part 66, a second part 67, and a connecting part 68. In this embodiment, the first part 66, the second part 67, and the connecting part 68 are integrated. The shape of the second wiring 62 is the same as the shape of the second wiring 52. The second wiring 62 has a shape rotated 180 degrees with respect to the second wiring 52.

[0133] The first part 66 is provided at a position overlapping with the second semiconductor region 45Q of the third protection diode cell 40G when viewed from the z direction, and is electrically connected to the second semiconductor region 45Q of the third protection diode cell 40G. When viewed from the z direction, the first part 66 has an open ring shape that surrounds the first semiconductor region 44Q of the third protection diode cell 40G and has a gap in part of the circumferential direction of the first semiconductor region 44Q of the third protection diode cell 40G. In this embodiment, the first part 66 has the same shape as the first part 56 of the second wiring 52.

[0134] The second part 67 is provided at a position overlapping with the first semiconductor region 44Q of the fourth protection diode cell 40H when viewed from the z direction, and is electrically connected to the first semiconductor region 44Q of the fourth protection diode cell 40H. When viewed from the z direction, the second part 67 has a circular shape. In this embodiment, the second part 67 has the same shape as the second part 57 of the second wiring 52.

[0135] The connection part 68 connects the first part 66 and the second part 67. The connection part 68 extends in the y direction. In this embodiment, the connection part 68 has the same shape as the connection part 58 of the second wiring 52.

[0136] The third wiring 63 is a wiring for connecting the third protection diode cell 40G and the second protection diode cell 40F in series. The third wiring 63 electrically connects the first semiconductor region 44Q of the third protection diode cell 40G and the second semiconductor region 45Q of the second protection diode cell 40F. The third wiring 63 is formed so as to straddle the third protection diode cell 40G and the second protection diode cell 40F.

[0137] The third wiring 63 has the same shape as the second wiring 62, and therefore a detailed description of its shape will be omitted. A first part 66 of the third wiring 63 is provided at a position overlapping with the second semiconductor region 45Q of the second protection diode cell 40F when viewed from the z direction, and is electrically connected to the second semiconductor region 45Q of the second protection diode cell 40F. A second part 67 of the third wiring 63 is provided at a position overlapping with the first semiconductor region 44Q of the third protection diode cell 40G when viewed from the z direction, and is electrically connected to the first semiconductor region 44Q of the third protection diode cell 40G.

[0138] The fourth wiring 64 is a wiring for connecting the second protection diode cell 40F and the first protection diode cell 40E in series. The fourth wiring 64 electrically connects the first semiconductor region 44Q of the second protection diode cell 40F and the second semiconductor region 45Q of the first protection diode cell 40E. The fourth wiring 64 is formed so as to straddle the second protection diode cell 40F and the first protection diode cell 40E.

[0139] The fourth wiring 64 has the same shape as the second wiring 62, and therefore a detailed description of its shape will be omitted. A first part 66 of the fourth wiring 64 is provided at a position overlapping with the second semiconductor region 45Q of the first protection diode cell 40E when viewed from the z direction, and is electrically connected to the second semiconductor region 45Q of the first protection diode cell 40E. A second part 67 of the fourth wiring 64 is provided at a position overlapping with the first semiconductor region 44Q of the second protection diode cell 40F when viewed from the z direction, and is electrically connected to the first semiconductor region 44Q of the second protection diode cell 40F.

[0140] The fifth wiring 65 is electrically connected to the first semiconductor region 44Q of the first protection diode cell 40E and is a wiring for supplying the current flowing through the protection diode 40Q to the outside of the protection diode 40Q. The fifth wiring 65 has a fifth region connection portion 65A provided at a position overlapping the first semiconductor region 44Q of the first protection diode cell 40E when viewed from the z direction, and a fifth extension portion 65B extending from the fifth region connection portion 65A to the outside of the first semiconductor region 44Q of the first protection diode cell 40E. In this embodiment, the fifth region connection portion 65A and the fifth extension portion 65B are integrated. The fifth extension portion 65B forms the first electrode 41Q of the protection diode 40Q. Furthermore, the fifth wiring 65 is arranged at a position overlapping the fifth wiring 55 when viewed from the x direction.

[0141] The fifth region connection portion 65A has a circular shape when viewed from the z direction. In this embodiment, the center of the fifth region connection portion 65A and the center of the first semiconductor region 44Q of the first protection diode cell 40E coincide with each other. The diameter of the fifth region connection portion 65A is slightly smaller than the diameter of the first semiconductor region 44Q. The diameter of the fifth region connection portion 65A can be changed arbitrarily and may be, for example, equal to or larger than the diameter of the first semiconductor region 44Q.

[0142] The fifth extension portion 65B extends from the fifth region connection portion 65A toward the opposite side to the fourth wiring 64. In this embodiment, the length of the fifth extension portion 65B is shorter than the length of the first extension portion 61B.

[0143] 9 and 12, the semiconductor device 10 includes first to eighth through wirings 81Q to 88Q as through wirings that penetrate the intermediate insulating film 39. The first to eighth through wirings 81Q to 88Q are wirings for individually connecting the first to fifth wirings 61 to 65 and the protection diode cells 40E to 40H. FIG. 12 schematically shows a connection structure between the first to fifth wirings 61 to 65 and the protection diode cells 40E to 40H by the first to eighth through wirings 81Q to 88Q. Therefore, the arrangement positions and number of the first to eighth through wirings 81Q to 88Q are not limited to those shown in FIG.

[0144] The first through wiring 81Q is a wiring that connects the second semiconductor region 45Q of the fourth protection diode cell 40H and the first wiring 61. As a result, the second semiconductor region 45Q of the fourth protection diode cell 40H is electrically connected to the second electrode 42Q of the protection diode 40Q. When viewed from the z direction, the first through wiring 81Q is arranged at a position overlapping both the second semiconductor region 45Q of the fourth protection diode cell 40H and the first wiring 61. Note that a plurality of first through wirings 81Q may be provided. In other words, when viewed from the z direction, the plurality of first through wirings 81Q may be arranged spaced apart from each other at positions overlapping both the second semiconductor region 45Q of the fourth protection diode cell 40H and the first region connection portion 61A of the first wiring 61.

[0145] The second through wiring 82Q is a wiring that connects the first semiconductor region 44Q of the fourth protection diode cell 40H and the second wiring 62. When viewed from the z direction, the second through wiring 82Q is disposed at a position that overlaps both the second semiconductor region 45Q of the fourth protection diode cell 40H and the second wiring 62.

[0146] The third through wiring 83Q is a wiring that connects the second semiconductor region 45Q of the third protection diode cell 40G and the second wiring 62. When viewed from the z direction, the third through wiring 83Q is disposed at a position that overlaps both the second semiconductor region 45Q of the third protection diode cell 40G and the second wiring 62.

[0147] In this way, the first semiconductor region 44Q of the fourth protection diode cell 40H and the second semiconductor region 45Q of the third protection diode cell 40G are connected via the second through wiring 82Q, the second wiring 62, and the third through wiring 83Q.

[0148] The fourth through wiring 84Q is a wiring that connects the first semiconductor region 44Q of the third protection diode cell 40G and the third wiring 63. When viewed from the z direction, the fourth through wiring 84Q is disposed at a position that overlaps both the first semiconductor region 44Q of the third protection diode cell 40G and the third wiring 63.

[0149] The fifth through wiring 85Q is a wiring that connects the second semiconductor region 45Q of the second protection diode cell 40F and the third wiring 63. When viewed from the z direction, the fifth through wiring 85Q is disposed at a position that overlaps with both the second semiconductor region 45Q of the second protection diode cell 40F and the third wiring 63.

[0150] In this way, the first semiconductor region 44Q of the third protection diode cell 40G and the second semiconductor region 45Q of the second protection diode cell 40F are connected via the fourth through wiring 84Q, the third wiring 63, and the fifth through wiring 85Q.

[0151] The sixth through wiring 86Q is a wiring that connects the first semiconductor region 44Q of the second protection diode cell 40F and the fourth wiring 64. When viewed from the z direction, the sixth through wiring 86Q is disposed at a position that overlaps both the first semiconductor region 44Q of the second protection diode cell 40F and the fourth wiring 64.

[0152] The seventh through wiring 87Q is a wiring that connects the second semiconductor region 45Q of the first protection diode cell 40E and the fourth wiring 64. When viewed from the z direction, the seventh through wiring 87Q is disposed at a position that overlaps with both the second semiconductor region 45Q of the first protection diode cell 40E and the fourth wiring 64.

[0153] In this way, the first semiconductor region 44Q of the second protection diode cell 40F and the second semiconductor region 45Q of the first protection diode cell 40E are connected via the sixth through wiring 86Q, the fourth wiring 64, and the seventh through wiring 87Q.

[0154] The eighth through wiring 88Q is a wiring that connects the first semiconductor region 44Q of the first protection diode cell 40E and the fifth wiring 65. As a result, the first semiconductor region 44Q of the first protection diode cell 40E is electrically connected to the first electrode 41Q of the protection diode 40Q. When viewed from the z direction, the eighth through wiring 88Q is arranged at a position that overlaps both the first semiconductor region 44Q of the first protection diode cell 40E and the fifth wiring 65. Note that a plurality of each of the first to eighth through wirings 81Q to 88Q may be provided. In this case, the arrangement of the first to eighth through wirings 81Q to 88Q is similar to the arrangement of the first to fourth through wirings 81P to 84P shown in FIG. 11, for example.

[0155] 9, the semiconductor device 10 has a first connection line 71 and a second connection line 72. The first connection line 71 is a wiring that connects the first electrode 41P of the temperature-sensitive diode 40P and the second electrode 42Q of the protection diode 40Q to the anode electrode 22. The second connection line 72 is a wiring that connects the second electrode 42P of the temperature-sensitive diode 40P and the first electrode 41Q of the protection diode 40Q to the emitter electrode 21. Therefore, the second connection line 72 corresponds to the "second electrode connection wiring."

[0156] The first connection line 71 is connected to both the first wiring 51 and the first wiring 61. More specifically, the first connection line 71 is connected to both the first extension portion 51B of the first wiring 51 and the first extension portion 61B of the first wiring 61. The first connection line 71 passes through the first wiring lead-out region 21ba and is connected to the anode electrode 22. Therefore, the first connection line 71 corresponds to the "first electrode connection line."

[0157] The second connection line 72 is connected to both the fifth wiring 55 and the fifth wiring 65. More specifically, the second connection line 72 is connected to both the fifth extension portion 55B of the fifth wiring 55 and the fifth extension portion 65B of the fifth wiring 65. The second connection line 72 is connected to the emitter electrode 21 through the second wiring lead-out region 21bb.

[0158] 13 schematically illustrates the relative positions of the second diode cell 40B of the temperature sensitive diode 40P, the third protection diode cell 40G of the protection diode 40Q, the second wirings 52, 62, the third wirings 53, 63, the third through wirings 83P, 83Q, the fourth through wirings 84P, 84Q, the two gate fingers 26, the first connection line 71, and the second connection line 72. For this reason, the positions and numbers of the third through wirings 83P, 83Q and the fourth through wirings 84P, 84Q are not limited to those illustrated in FIG.

[0159] 9 and 13, gate fingers 26P and 26Q are provided as two gate fingers 26 within the diode arrangement portion 21b of the emitter electrode 21. When viewed from the z direction, the gate fingers 26P and 26Q are formed to surround both the temperature sensing diode 40P and the protection diode 40Q as a single unit. The tips of the gate fingers 26P and 26Q are provided in the second wiring lead-out region 21bb so as to face each other and be spaced apart in the x direction. A second connection line 72 extends in the y direction between the tips of the gate fingers 26P and 26Q in the x direction and is connected to the emitter electrode 21.

[0160] The gate finger 26P is disposed on the opposite side of the temperature-sensitive diode 40P from the protection diode 40Q. A first connection line 71 is disposed between the gate finger 26P and the temperature-sensitive diode 40P in the x direction. As shown in FIG. 13 , the internal wiring 26Pa of the gate finger 26P and the diode semiconductor layer 43 of the temperature-sensitive diode 40P are both formed on the surface 38a of the insulating film 38. That is, the internal wiring 26Pa and the diode semiconductor layer 43 are disposed at the same position as each other in the z direction. The first connection line 71, the surface-side wiring 26Pb of the gate finger 26P, the second wiring 52, and the third wiring 53 are each formed on the surface 39b of the intermediate insulating film 39. That is, the first connection line 71, the surface-side wiring 26Pb of the gate finger 26P, the second wiring 52, and the third wiring 53 are disposed at the same position as each other in the z direction. Furthermore, the first connection line 71, the front surface side wiring 26Pb of the gate finger 26P, the second wiring 52, and the third wiring 53 are each disposed at a different position in the z direction from the internal wiring 26Pa and the diode semiconductor layer 43. In this embodiment, the first connection line 71, the front surface side wiring 26Pb of the gate finger 26P, the second wiring 52, and the third wiring 53 are each disposed at a position farther from the semiconductor substrate 30 in the z direction than the internal wiring 26Pa and the diode semiconductor layer 43.

[0161] As shown in FIG. 9, the gate finger 26Q is disposed on the opposite side of the protection diode 40Q from the temperature sensitive diode 40P. A second connection line 72 is disposed between the gate finger 26Q and the protection diode 40Q in the x direction. As shown in FIG. 13, both the internal wiring 26Qa of the gate finger 26Q and the diode semiconductor layer 43 of the protection diode 40Q are formed on the surface 38a of the insulating film 38. That is, the internal wiring 26Qa and the diode semiconductor layer 43 are disposed at the same position in the z direction. Furthermore, the second connection line 72, the surface side wiring 26Qb of the gate finger 26Q, the second wiring 62, and the third wiring 63 are disposed at the same position in the z direction. Furthermore, the second connection line 72, the surface side wiring 26Qb of the gate finger 26Q, the second wiring 62, and the third wiring 63 are disposed at different positions in the z direction from the internal wiring 26Qa and the diode semiconductor layer 43. In this embodiment, the second connection line 72, the surface side wiring 26Qb of the gate finger 26Q, the second wiring 62, and the third wiring 63 are each positioned farther from the semiconductor substrate 30 in the z direction than the internal wiring 26Qa and the diode semiconductor layer 43.

[0162] 2, in this embodiment, the adjacent region 21P is formed to surround both the temperature-sensitive diode 40P and the protection diode 40Q. The adjacent region 21P is a region of the emitter electrode 21 (emitter electrode pad 11) that constitutes the diode arrangement portion 21b that surrounds both the temperature-sensitive diode 40P and the protection diode 40Q. Therefore, the adjacent region 21P has a portion adjacent to the second wiring lead-out region 21bb (see FIG. 9) in the y direction.

[0163] 9, the second electrode 42P (cathode) of the temperature-sensitive diode 40P is connected to the adjacent region 21P by the second connection line 72. In other words, the second electrode 42P of the temperature-sensitive diode 40P is electrically connected to the emitter electrode 21. In this way, the emitter electrode 21 also serves as the cathode electrode of the temperature-sensitive diode 40P. In addition, the first electrode 41Q (anode) of the protection diode 40Q is also connected to the adjacent region 21P by the second connection line 72. In other words, the first electrode 41Q of the protection diode 40Q is electrically connected to the emitter electrode 21. In this way, the emitter electrode 21 also serves as the anode electrode of the protection diode 40Q.

[0164] (Operation of the first embodiment) The operation of the semiconductor device 10 of this embodiment will be described. Fig. 14 is a plan view of a semiconductor device 10X of a comparative example, and Fig. 15 is a cross-sectional view of the semiconductor device 10X of Fig. 14 taken along line 15-15. The semiconductor device 10X of the comparative example has a configuration in which the second electrode 42P of the temperature sensitive diode 40P is not electrically connected to the emitter electrode 21.

[0165] 14, in the semiconductor device 10X of the comparative example, the cathode electrode 28X and the emitter electrode 21RX are formed separately. The cathode electrode 28X is arranged at a distance from the emitter electrode 21RX. The cathode electrode 28X is arranged between the emitter electrode 21RX and the anode electrode 22 in the x-direction. Although not shown, the second electrode 42P of the temperature sensitive diode 40P is electrically connected to the cathode electrode 28X.

[0166] 15, in the semiconductor device 10X of the comparative example, the cathode electrode 28X is insulated from the emitter electrode 21RX, and therefore, when viewed from the z direction, the region RX of the semiconductor substrate 30 that overlaps with the cathode electrode 28X cannot make contact with the emitter electrode 21RX. For this reason, a main cell cannot be formed in the region RX.

[0167] On the other hand, in the semiconductor device 10 of this embodiment, the emitter electrode 21 and the second electrode 42P of the temperature-sensitive diode 40P are electrically connected, so the emitter electrode 21 can form the cathode electrode pad 12. Therefore, the emitter electrode 21 can also serve as the cathode electrode 28X of the semiconductor device 10X of the comparative example. That is, in this embodiment, the semiconductor device 10 includes an emitter electrode 21 in which the emitter electrode 21RX and the cathode electrode 28X are integrated. As a result, as shown in FIG. 6, the region RK of the semiconductor substrate 30 that overlaps with the cathode electrode pad 12 can make contact with the emitter electrode 21. Therefore, a main cell 18A can be formed in the region RK.

[0168] In general, in a temperature-sensitive diode, as the junction area between the first p-type semiconductor region and the second n-type semiconductor region increases, the amount of current flowing from the first semiconductor region to the second semiconductor region increases, thereby improving the accuracy of detecting the temperature of the temperature-sensitive diode.

[0169] In a typical diode configuration, for example, a rectangular first semiconductor region and a rectangular second semiconductor region are bonded adjacent to each other when viewed from the z direction, so that the junction surface is linear when viewed from the z direction. Therefore, the length of the junction surface between the first semiconductor region and the second semiconductor region when viewed from the z direction is equal to the length of the side of the diode in the direction perpendicular to the arrangement direction of the first semiconductor region and the second semiconductor region when viewed from the z direction.

[0170] On the other hand, in this embodiment, as shown in FIG. 8 , the temperature-sensitive diode 40P includes a p-type first semiconductor region 44P having a circular circumferential surface 44Pa and an n-type second semiconductor region 45P having an inner circumferential surface 45Pa that is bonded to the circumferential surface 44Pa. In this embodiment, the inner circumferential surface 45Pa is bonded to the circumferential surface 44Pa along the entire circumference. That is, the bonded surface between the first semiconductor region 44P and the second semiconductor region 45P is circular when viewed from the z direction. Therefore, if the outer shape of the first semiconductor region 44P is enlarged, the length of the bonded surface between the first semiconductor region 44P and the second semiconductor region 45P when viewed from the z direction (the length of the circumferential surface 44Pa of the first semiconductor region 44P when viewed from the z direction) becomes longer than the length of one side of the outer surface 45Pb of the second semiconductor region 45P. Therefore, compared to a typical diode, the bonded area between the first semiconductor region 44P and the second semiconductor region 45P can be increased.

[0171] (Effects of the first embodiment) According to the semiconductor device 10 of this embodiment, the following effects can be obtained. (1-1) The semiconductor device 10 includes a semiconductor substrate 30, a main cell 18A provided on the semiconductor substrate 30, an intermediate insulating film 39 covering the main cell 18A, an emitter electrode 21 laminated on the intermediate insulating film 39, a temperature-detecting diode 40P having a first electrode 41P and a second electrode 42P, and an anode electrode 22 for connecting the first electrode 41P to the outside. The emitter electrode 21 has an emitter electrode pad 11 as a first junction region to which a first conductive member CB for connecting the emitter electrode 21 to the outside is bonded and which is electrically bonded to the second electrode 42P, and a cathode electrode pad 12 as a second junction region to which a second conductive member CWA for connecting the second electrode 42P to the outside is bonded. When viewed from the z direction, the main cell 18A is provided in both a region RE (first semiconductor region) overlapping the emitter electrode pad 11 of the semiconductor substrate 30 and a region RK (second semiconductor region) overlapping the cathode electrode pad 12.

[0172] According to this configuration, the area where the main cells 18A are formed can be expanded, and therefore, for the same semiconductor device size, the number of main cells 18A in the semiconductor device 10 can be increased, thereby reducing the on-resistance of the semiconductor device 10. Furthermore, the area where the cathode electrodes 28X are formed can be removed while maintaining the area where the main cells 18A are formed, and therefore the semiconductor device 10 can be downsized while suppressing an increase in the on-resistance of the semiconductor device 10. As a result, the cost of the semiconductor device 10 can be reduced.

[0173] (1-2) The emitter electrode pad 11 includes an adjacent region 21P formed to surround the temperature-sensitive diode 40P. The temperature-sensitive diode 40P is disposed in the diode arrangement portion 21b surrounded by the adjacent region 21P. A second electrode 42P of the temperature-sensitive diode 40P is connected to the adjacent region 21P.

[0174] This configuration allows the wiring connecting the second electrode 42P of the temperature sensitive diode 40P and the adjacent region 21P to be short, thereby reducing the influence of noise caused by this wiring on the temperature sensitive diode 40P.

[0175] (1-3) The cathode electrode pad 12 and the anode electrode pad 13 are arranged side by side along the electrode arrangement region 10ce on the semiconductor substrate 30. According to this configuration, the cathode electrode pads 12 and the anode electrode pads 13 are gathered together, so that when conductive members are bonded to these pads 12 and 13 in order, the bonding operation becomes easier.

[0176] (1-4) The semiconductor device 10 includes a protective insulating film 17 that covers the emitter electrode 21. The protective insulating film 17 has a first opening 17A that exposes the emitter electrode pad 11 and a second opening 17B that exposes the cathode electrode pad 12. The protective insulating film 17 has a partition region 17a that separates the first opening 17A and the second opening 17B.

[0177] According to this configuration, since the protective insulating film 17 (partition region 17a) is present between the first opening 17A and the second opening 17B, for example, when the first conductive member CB is joined to the emitter electrode pad 11 with a conductive bonding material such as solder, the conductive bonding material can be prevented from entering the second opening 17B.

[0178] (1-5) The temperature sensitive diode 40P has a plurality of diode cells 40A to 40D. The plurality of diode cells 40A to 40D are connected in series with each other. This configuration makes it possible to increase the temperature coefficient of the temperature sensitive diode 40P, thereby improving the accuracy of temperature detection by the temperature sensitive diode 40P.

[0179] (1-6) The semiconductor device 10 includes a protection diode 40Q connected in anti-parallel to the temperature-sensitive diode 40P. This configuration can reduce the influence of surges on the temperature-sensitive diode 40P.

[0180] (1-7) The temperature sensitive diode 40P has diode cells 40A to 40D each composed of a first semiconductor region 44P of a first conductivity type formed on the surface 38a of the insulating film 38 and a second semiconductor region 45P of a second conductivity type formed on the surface 38a of the insulating film 38. The second semiconductor region 45P is formed in a ring shape surrounding the first semiconductor region 44P. An inner circumferential surface 45Pa of the second semiconductor region 45P is joined to the first semiconductor region 44P.

[0181] With this configuration, compared to a configuration in which the first semiconductor region and the second semiconductor region are bonded on one surface, the bonded area between the first semiconductor region 44P and the second semiconductor region 45P is increased, which increases the temperature coefficient of the temperature sensing diode 40P and therefore improves the accuracy of temperature detection of the temperature sensing diode 40P.

[0182] (1-8) The first semiconductor region 44P has a circular shape when viewed from the z direction. The second semiconductor region 45P has an inner circumferential surface 45Pa that is joined to the circumferential surface 44Pa of the first semiconductor region 44P over the entire circumference.

[0183] According to this configuration, there are no corners on the junction surface formed by the circumferential surface 44Pa of the first semiconductor region 44P and the inner surface 45Pa of the second semiconductor region 45P, so that the concentration of the current density flowing from the first semiconductor region 44P to the second semiconductor region 45P can be suppressed.

[0184] (1-9) A first length-measurement pattern 46P is provided in the first semiconductor region 44P of the first diode cell 40A, and a second length-measurement pattern 47P is provided in the second semiconductor region 45P. With this configuration, the dimension of the first semiconductor region 44P can be calculated by measuring the first length-measurement pattern 46P, and the dimension of the second semiconductor region 45P can be calculated by measuring the second length-measurement pattern 47P. Therefore, the dimensions of the first semiconductor region 44P and the second semiconductor region 45P can be obtained without directly measuring the dimensions of the first semiconductor region 44P and the second semiconductor region 45P, which are relatively large. Note that the same effect can be obtained for the second to fourth diode cells 40B to 40D and the first to fourth protection diode cells 40E to 40H.

[0185] (1-10) The first through wiring 81P is connected to a position in the first semiconductor region 44P of the first diode cell 40A that is different from the first length measurement pattern 46P. The second through wiring 82P is connected to a position in the second semiconductor region 45P of the first diode cell 40A that is different from the second length measurement pattern 47P.

[0186] According to this configuration, the first through wiring 81P is connected to a position different from the first length measurement pattern 46P, which is a non-doped layer, in the first semiconductor region 44P, so that an increase in resistance between the first through wiring 81P and the first semiconductor region 44P can be suppressed. Also, the second through wiring 82P is connected to a position different from the second length measurement pattern 47P, which is a non-doped layer, in the second semiconductor region 45P, so that an increase in resistance between the second through wiring 82P and the second semiconductor region 45P can be suppressed. Note that the same effect can be obtained for the third to eighth through wirings 83P to 88P and the first to eighth through wirings 81Q to 88Q.

[0187] [Second embodiment] 16 and 17, a semiconductor device 10 of the second embodiment will be described. The semiconductor device 10 of the second embodiment differs from the semiconductor device 10 of the first embodiment in the configuration of the electrode pads. In the following description, configurations that differ from the semiconductor device 10 of the first embodiment will be described in detail, and configurations that are common to the semiconductor device 10 of the first embodiment will be assigned the same reference numerals and descriptions thereof will be omitted.

[0188] 16, the semiconductor device 10 of this embodiment differs from the first embodiment in that an opening 17G is provided instead of the first opening 17A and the second opening 17B (see FIG. 1) of the protective insulating film 17. That is, the opening 17G is an opening in which the partition region 17a (see FIG. 1) of the protective insulating film 17 is omitted and the first opening 17A and the second opening 17B are integrated. The opening 17G can also be said to be an opening that exposes the emitter electrode pad 11, the cathode electrode pad 12, and the region between the emitter electrode pad 11 and the cathode electrode pad 12. In this embodiment, the portion of the emitter electrode 21 exposed by the opening 17G is divided into a first junction region RA and a second junction region RB.

[0189] The first junction region RA is a portion of the emitter electrode 21 closer to the device side surface 10d than the electrodes 22 to 24, and is a region to which a first conductive member CB is bonded for connecting the emitter electrode 21 to the outside. The first junction region RA is formed over most of the emitter electrode 21, in other words, over most of the portion of the emitter electrode 21 exposed by the opening 17G.

[0190] The second bonding region RB is a region including the cathode electrode pad 12 and is a region that forms one of the two ends of the opening 17G in the y direction that is closer to the side surface 10c of the device. Therefore, the second bonding region RB is a region to which the second conductive member CWA for connecting the second electrode 42P of the temperature sensitive diode 40P to the outside is bonded. The second bonding region RB is provided at a position adjacent to the anode electrode 22 in the x direction.

[0191] 17, a first conductive member CB is bonded to the first bonding region RA with a conductive bonding material such as solder, and a second conductive member CWA is bonded to the second bonding region RB with a wire bonding device.

[0192] (Effects of the second embodiment) According to the semiconductor device 10 of this embodiment, in addition to the effects (1-1) to (1-3) and (1-5) to (1-11) of the first embodiment, the following effects can be obtained.

[0193] (2-1) The protective insulating film 17 has an opening 17G that exposes both the first junction region RA and the second junction region RB. With this configuration, the area of ​​the emitter electrode 21 exposed from the protective insulating film 17 is increased, thereby improving heat dissipation.

[0194] [Third embodiment] 18 to 21, a semiconductor device 10 of the third embodiment will be described. The semiconductor device 10 of the present embodiment differs from the semiconductor device 10 of the first embodiment in the configuration of the temperature-sensitive diode 40P. In the following description, configurations that differ from the semiconductor device 10 of the first embodiment will be described in detail, and configurations that are common to the semiconductor device 10 of the first embodiment will be assigned the same reference numerals and descriptions thereof will be omitted.

[0195] Fig. 18 is a plan view schematically showing the configuration of a temperature-sensing diode 40P and a protection diode 40Q according to a third embodiment. Fig. 19 is a plan view schematically showing wiring for the temperature-sensing diode 40P and the protection diode 40Q of Fig. 18. Fig. 20 is a cross-sectional view of the temperature-sensing diode 40P and the wiring taken along line 20-20 in Fig. 19, showing a schematic diagram of the connection between the temperature-sensing diode 40P and the wiring. Fig. 21 is a cross-sectional view of the protection diode 40Q and the wiring taken along line 21-21 in Fig. 19, showing a schematic diagram of the connection between the protection diode 40Q and the wiring.

[0196] As shown in FIG. 18, the semiconductor device 10 includes a diode semiconductor layer 90 formed on a surface 38Aa of an insulating film 38A formed on a substrate surface 30s, similar to the first embodiment.

[0197] The semiconductor device 10 includes a temperature-sensitive diode 100 having a plurality of diode cells, and a protection diode 110 having a plurality of protection diode cells. As in the first embodiment, the protection diode 110 is connected in anti-parallel to the temperature-sensitive diode 100. The temperature-sensitive diode 100 and the protection diode 110 are provided as separate diode semiconductor layers 90.

[0198] The temperature sensitive diodes 100 and the protection diodes 110 are arranged aligned with each other in the y direction and spaced apart from each other in the x direction. In this embodiment, the temperature sensitive diode 100 has first to fourth diode cells 100A to 100D, which are four diode cells connected in series to each other. Each of the diode cells 100A to 100D is formed in one semiconductor layer 90 for diode.

[0199] The first diode cell 100A is composed of a first semiconductor region 101 of a first conductivity type and a second semiconductor region 102 of a second conductivity type. In this embodiment, the first conductivity type is p-type, and the second conductivity type is n-type. The second semiconductor region 102 is formed in a ring shape surrounding the first semiconductor region 101. In this embodiment, the shape of the first semiconductor region 101 is circular when viewed from the z direction. The second semiconductor region 102 is ring-shaped, having an inner circumferential surface 102a that is joined to the circumferential surface 101a of the first semiconductor region 101 along the entire circumference.

[0200] The second diode cell 100B is provided separately from the first diode cell 100A. The second diode cell 100B is composed of a third semiconductor region 103 of the first conductivity type and a fourth semiconductor region 104 of the second conductivity type.

[0201] The third semiconductor region 103 is formed in a ring shape surrounding the second semiconductor region 102. The third semiconductor region 103 is annular, having an inner peripheral surface 103a joined to the outer peripheral surface 102b of the second semiconductor region 102 over the entire circumference. The width of the third semiconductor region 103 (the dimension between the inner peripheral surface 103a and the outer peripheral surface 103b in the radial direction of the third semiconductor region 103) is equal to or smaller than the width of the second semiconductor region 102 (the dimension between the inner peripheral surface 102a and the outer peripheral surface 102b in the radial direction of the second semiconductor region 102). In this embodiment, the width of the third semiconductor region 103 is smaller than the width of the second semiconductor region 102.

[0202] The fourth semiconductor region 104 is formed in a ring shape surrounding the third semiconductor region 103. The fourth semiconductor region 104 is annular in shape and has an inner peripheral surface 104a that is joined to the outer peripheral surface 103b of the third semiconductor region 103 over the entire circumference. The width of the fourth semiconductor region 104 (the dimension between the inner peripheral surface 104a and the outer peripheral surface 104b in the radial direction of the fourth semiconductor region 104) is equal to or greater than the width of the third semiconductor region 103. In this embodiment, the width of the fourth semiconductor region 104 is greater than the width of the third semiconductor region 103 and equal to the width of the second semiconductor region 102.

[0203] The third diode cell 100C is provided separately from both the first diode cell 100A and the second diode cell 100B. The third diode cell 100C is composed of a fifth semiconductor region 105 of the first conductivity type and a sixth semiconductor region 106 of the second conductivity type.

[0204] The fifth semiconductor region 105 is formed in a ring shape surrounding the fourth semiconductor region 104. The fifth semiconductor region 105 is annular in shape and has an inner peripheral surface 105a that is joined to the outer peripheral surface 104b of the fourth semiconductor region 104 over the entire circumference. The width of the fifth semiconductor region 105 (the dimension between the inner peripheral surface 105a and the outer peripheral surface 105b in the radial direction of the fifth semiconductor region 105) is equal to or smaller than the width of the fourth semiconductor region 104. In this embodiment, the width of the fifth semiconductor region 105 is smaller than the width of the fourth semiconductor region 104 and equal to the width of the third semiconductor region 103.

[0205] The sixth semiconductor region 106 is formed in a ring shape surrounding the fifth semiconductor region 105. The sixth semiconductor region 106 is ring-shaped and has an inner peripheral surface 106a that is joined to the outer peripheral surface 105b of the fifth semiconductor region 105 over the entire circumference. The width of the sixth semiconductor region 106 (the dimension between the inner peripheral surface 106a and the outer peripheral surface 106b in the radial direction of the sixth semiconductor region 106) is equal to or greater than the width of the fifth semiconductor region 105. In this embodiment, the width of the sixth semiconductor region 106 is greater than the width of the fifth semiconductor region 105 and equal to the width of the fourth semiconductor region 104.

[0206] The fourth diode cell 100D is provided separately from the first to third diode cells 100A to 100C. The fourth diode cell 100D is composed of a seventh semiconductor region 107 of the first conductivity type and an eighth semiconductor region 108 of the second conductivity type.

[0207] The seventh semiconductor region 107 is formed in a ring shape surrounding the sixth semiconductor region 106. The sixth semiconductor region 106 is ring-shaped and has an inner peripheral surface 107a that is joined to the outer peripheral surface 105b of the fifth semiconductor region 105 along the entire circumference. The width of the seventh semiconductor region 107 (the dimension between the inner peripheral surface 107a and the outer peripheral surface 107b in the radial direction of the seventh semiconductor region 107) is equal to or smaller than the width of the sixth semiconductor region 106. In this embodiment, the width of the seventh semiconductor region 107 is smaller than the width of the sixth semiconductor region 106 and equal to the width of the fifth semiconductor region 105.

[0208] The eighth semiconductor region 108 is formed in a ring shape surrounding the seventh semiconductor region 107. The eighth semiconductor region 108 has an inner peripheral surface 108a that is joined over the entire periphery to the outer peripheral surface 107b of the seventh semiconductor region 107. The outer shape of the eighth semiconductor region 108 when viewed from the z direction is quadrangular.

[0209] 18, when viewed from the z direction, the first to eighth semiconductor regions 101 to 108 are arranged concentrically. In other words, it can be said that the first to fourth diode cells 100A to 100D are arranged concentrically. Furthermore, when viewed from the z direction, the temperature sensitive diode 100 has a configuration in which first conductivity type semiconductor regions and second conductivity type semiconductor regions are arranged alternately in the radial direction of the temperature sensitive diode 100.

[0210] In this embodiment, the protection diode 110 has first to fourth protection diode cells 110A to 110D, which are four protection diode cells connected in series to each other. As shown in Fig. 18, the configuration of the protection diode 110 is the same as the configuration of the temperature sensitive diode 100.

[0211] The first protection diode cell 110A is composed of a first semiconductor region 111 of a first conductivity type and a second semiconductor region 112 of a second conductivity type. The second semiconductor region 112 is formed in a ring shape surrounding the first semiconductor region 111. When viewed from the z direction, the first semiconductor region 111 has a circular shape, and the second semiconductor region 112 has a ring shape having an inner circumferential surface 112a that is joined to a circumferential surface 111a of the first semiconductor region 111 along the entire circumference.

[0212] The second protection diode cell 110B is composed of a third semiconductor region 113 of a first conductivity type and a fourth semiconductor region 114 of a second conductivity type. The third semiconductor region 113 is annular in shape and has an inner circumferential surface 113a joined over the entire periphery to the outer circumferential surface 112b of the second semiconductor region 112. The fourth semiconductor region 114 is annular in shape and has an inner circumferential surface 114a joined over the entire periphery to the outer circumferential surface 113b of the third semiconductor region 113.

[0213] The third protection diode cell 110C is composed of a fifth semiconductor region 115 of a first conductivity type and a sixth semiconductor region 116 of a second conductivity type. The fifth semiconductor region 115 is annular in shape and has an inner circumferential surface 115a joined over the entire periphery to the outer circumferential surface 114b of the fourth semiconductor region 114. The sixth semiconductor region 116 is annular in shape and has an inner circumferential surface 116a joined over the entire periphery to the outer circumferential surface 115b of the fifth semiconductor region 115.

[0214] The fourth protection diode cell 110D is composed of a seventh semiconductor region 117 of a first conductivity type and an eighth semiconductor region 118 of a second conductivity type. The seventh semiconductor region 117 is annular in shape and has an inner circumferential surface 117a joined over the entire periphery to the outer circumferential surface 116b of the sixth semiconductor region 116. The eighth semiconductor region 118 is annular in shape and has an inner circumferential surface 118a joined over the entire periphery to the outer circumferential surface 117b of the seventh semiconductor region 117.

[0215] 20 , both the temperature sensitive diode 100 and the protection diode 110 are covered with an intermediate insulating film 39, as in the first embodiment. On a surface 39b of the intermediate insulating film 39, first to fifth wirings 121 to 125 electrically connected to the temperature sensitive diode 100 and first to fifth wirings 131 to 135 electrically connected to the protection diode 110 are provided. The intermediate insulating film 39 also has first to eighth through wirings 126A to 126H that penetrate the intermediate insulating film 39 in the z direction and are connected to the temperature sensitive diode 100, and first to eighth through wirings 136A to 136H that penetrate the intermediate insulating film 39 in the z direction and are connected to the protection diode 110. That is, the semiconductor device 10 of this embodiment includes an intermediate insulating film 39, first to fifth wirings 121 to 125, 131 to 135 formed on a surface 39b of the intermediate insulating film 39, and first to eighth through wirings 126A to 126H, 136A to 136H that penetrate the intermediate insulating film 39. The wirings 121 to 125 are electrically connected to the temperature sensitive diode 100 via the through wirings 126A to 126H, respectively. Furthermore, the wirings 131 to 135 are electrically connected to the protection diode 110 via the through wirings 136A to 136H, respectively.

[0216] First, the wiring configuration of the temperature sensitive diode 100 will be described. 19, the first to fifth wirings 121 to 125 are arranged at a distance from one another in the y direction. In other words, the first to fifth wirings 121 to 125 are arranged at a distance from one another in the short-side direction of the temperature sensitive diode 100. The second to fourth wirings 122 to 124 are arranged between the first wiring 121 and the fifth wiring 125 in the short-side direction (y direction) of the temperature sensitive diode 100. The second to fourth wirings 122 to 124 are arranged in the order of the second wiring 122, the third wiring 123, and the fourth wiring 124 from the first wiring 121 toward the fifth wiring 125. The first to fifth wirings 121 to 125 are insulated from one another.

[0217] The temperature sensitive diode 100 has a first electrode 100M which serves as an anode electrode and a second electrode 100N which serves as a cathode electrode. The first electrode 100M and the second electrode 100N are provided separately at both ends of the temperature sensitive diode 100 in the y direction. The first electrode 100M is provided at one of both ends of the temperature sensitive diode 100 which is farther from the electrode pads 12 to 16 (see FIG. 1), and the second electrode 100N is provided at one of both ends of the temperature sensitive diode 100 which is closer to the electrode pads 12 to 16.

[0218] The first wiring 121 is electrically connected to the first semiconductor region 101 of the first diode cell 100A, and is a wiring for supplying a current from outside the temperature sensitive diode 100 to the first diode cell 100A. The first wiring 121 has a first region connection portion 121A and a first extension portion 121B. In this embodiment, the first region connection portion 121A and the first extension portion 121B are integrated.

[0219] The first region connection portion 121A is disposed at a position overlapping the first semiconductor region 101 of the first diode cell 100A when viewed from the z direction. The first region connection portion 121A is formed in a shape corresponding to the shape of the first semiconductor region 101 when viewed from the z direction. In this embodiment, the shape of the first semiconductor region 101 when viewed from the z direction is circular, and therefore the shape of the first region connection portion 121A when viewed from the z direction is also circular. In this embodiment, the diameter of the first region connection portion 121A is slightly smaller than the diameter of the first semiconductor region 101. Note that the diameter of the first region connection portion 121A can be changed arbitrarily and may, for example, be equal to or greater than the diameter of the first semiconductor region 101.

[0220] The first extension portion 121B extends from the first region connecting portion 121A toward the outside of the first semiconductor region 101. The first extension portion 121B extends to the outside of the temperature sensitive diode 100. In this embodiment, the first extension portion 121B extends from the first region connecting portion 121A toward the opposite side to the second wiring 122. The first extension portion 121B forms the first electrode 100M of the temperature sensitive diode 100.

[0221] 20, the first region connection portion 121A is connected to the first semiconductor region 101 by a first through wiring 126A. That is, the first through wiring 126A is a wiring that connects the first region connection portion 121A and the first semiconductor region 101. The first through wiring 126A is provided at a position that overlaps both the first region connection portion 121A and the first semiconductor region 101 when viewed from the z direction.

[0222] As shown in FIG. 19 , the second wiring 122 is formed in an open ring shape surrounding the first region connection portion 121A and having a gap so as not to contact the first extension portion 121B when viewed from the z direction. In this embodiment, the second wiring 122 is formed in an arc shape opening toward the first wiring 121 when viewed from the z direction. When viewed from the z direction, the second wiring 122 is provided at a position overlapping both the second semiconductor region 102 of the first diode cell 100A and the third semiconductor region 103 of the second diode cell 100B. When viewed from the z direction, the second wiring 122 can also be said to be arranged so as to straddle the junction surface between the second semiconductor region 102 and the third semiconductor region 103. Here, the junction surface between the second semiconductor region 102 and the third semiconductor region 103 is composed of the outer peripheral surface 102b of the second semiconductor region 102 and the inner peripheral surface 103a of the third semiconductor region 103 shown in FIG. 18 .

[0223] 20, the second wiring 122 is connected to the second semiconductor region 102 of the first diode cell 100A by a second through wiring 126B. That is, the second through wiring 126B is a wiring that connects the second wiring 122 and the second semiconductor region 102. The second through wiring 126B is disposed at a position that overlaps with both the second wiring 122 and the second semiconductor region 102 when viewed from the z direction.

[0224] Furthermore, the second wiring 122 is connected to the third semiconductor region 103 of the second diode cell 100B by a third through wiring 126C. That is, the third through wiring 126C is a wiring that connects the second wiring 122 and the third semiconductor region 103. The third through wiring 126C is disposed at a position that overlaps both the second wiring 122 and the third semiconductor region 103 when viewed from the z direction.

[0225] In this way, the second semiconductor region 102 of the first diode cell 100A and the third semiconductor region 103 of the second diode cell 100B are electrically connected by the second wiring 122, the second through wiring 126B, and the third through wiring 126C. For this reason, the second wiring 122, the second through wiring 126B, and the third through wiring 126C can also be said to be wiring that connects the first diode cell 100A and the second diode cell 100B in series.

[0226] As shown in FIG. 19 , the third wiring 123 is formed in an open ring shape surrounding the second wiring 122 and having a gap in a portion thereof when viewed from the z direction. In this embodiment, the third wiring 123 is formed in an arc shape that opens toward the second wiring 122 when viewed from the z direction. When viewed from the z direction, the third wiring 123 is provided at a position overlapping with the fourth semiconductor region 104 of the second diode cell 100B. In this embodiment, the third wiring 123 is provided at a position overlapping with both the fourth semiconductor region 104 and the fifth semiconductor region 105 of the third diode cell 100C. The third wiring 123 is disposed so as to straddle the junction surface between the fourth semiconductor region 104 and the fifth semiconductor region 105. Here, the junction surface between the fourth semiconductor region 104 and the fifth semiconductor region 105 is composed of the outer peripheral surface 104b of the fourth semiconductor region 104 and the inner peripheral surface 105a of the fifth semiconductor region 105 shown in FIG. 18 .

[0227] 20, the third wiring 123 is connected to the fourth semiconductor region 104 of the second diode cell 100B by a fourth through wiring 126D. That is, the fourth through wiring 126D is a wiring that connects the third wiring 123 and the fourth semiconductor region 104. The fourth through wiring 126D is arranged at a position that overlaps with both the third wiring 123 and the fourth semiconductor region 104 when viewed from the z direction.

[0228] Furthermore, the third wiring 123 is connected to the fifth semiconductor region 105 of the third diode cell 100C by a fifth through wiring 126E. That is, the fifth through wiring 126E is a wiring that connects the third wiring 123 and the fifth semiconductor region 105. The fifth through wiring 126E is disposed at a position that overlaps with both the third wiring 123 and the fifth semiconductor region 105 when viewed from the z direction.

[0229] In this way, the fourth semiconductor region 104 of the second diode cell 100B and the fifth semiconductor region 105 of the third diode cell 100C are electrically connected by the third wiring 123, the fourth through wiring 126D, and the fifth through wiring 126E. Therefore, it can be said that the third wiring 123, the fourth through wiring 126D, and the fifth through wiring 126E are wirings that connect the second diode cell 100B and the third diode cell 100C in series.

[0230] As shown in FIG. 19 , the fourth wiring 124 is formed in an open ring shape surrounding the third wiring 123 and having a gap in a portion thereof when viewed from the z direction. In this embodiment, the fourth wiring 124 is formed in an arc shape that opens toward the third wiring 123 when viewed from the z direction. When viewed from the z direction, the fourth wiring 124 is provided at a position that overlaps both the sixth semiconductor region 106 of the third diode cell 100C and the seventh semiconductor region 107 of the fourth diode cell 100D. When viewed from the z direction, the fourth wiring 124 is disposed so as to straddle the junction surface between the sixth semiconductor region 106 and the seventh semiconductor region 107. Here, the junction surface between the sixth semiconductor region 106 and the seventh semiconductor region 107 is composed of the outer peripheral surface 106b of the sixth semiconductor region 106 and the inner peripheral surface 107a of the seventh semiconductor region 107 shown in FIG. 18 .

[0231] 20, the fourth wiring 124 is connected to the sixth semiconductor region 106 of the third diode cell 100C by a sixth through wiring 126F. That is, the sixth through wiring 126F is a wiring that connects the fourth wiring 124 and the sixth semiconductor region 106. The sixth through wiring 126F is disposed at a position that overlaps with both the fourth wiring 124 and the sixth semiconductor region 106 when viewed from the z direction.

[0232] Furthermore, the fourth wiring 124 is connected to the seventh semiconductor region 107 of the fourth diode cell 100D by a seventh through wiring 126G. That is, the seventh through wiring 126G is a wiring that connects the fourth wiring 124 and the seventh semiconductor region 107. The seventh through wiring 126G is disposed at a position that overlaps both the fourth wiring 124 and the seventh semiconductor region 107 when viewed from the z direction.

[0233] In this way, the sixth semiconductor region 106 of the third diode cell 100C and the seventh semiconductor region 107 of the fourth diode cell 100D are electrically connected by the fourth wiring 124, the sixth through wiring 126F, and the seventh through wiring 126G. For this reason, it can be said that the fourth wiring 124, the sixth through wiring 126F, and the seventh through wiring 126G are wirings that connect the third diode cell 100C and the fourth diode cell 100D in series.

[0234] 19, the fifth wiring 125 is a wiring electrically connected to the eighth semiconductor region 108 of the fourth diode cell 100D. In other words, the fifth wiring 125 is a wiring for electrically connecting the second electrode 100N of the temperature sensitive diode 100 and the eighth semiconductor region 108 of the fourth diode cell 100D.

[0235] When viewed from the z direction, the fifth wiring 125 has a fifth region connection portion 125A and a fifth extension portion 125B. In this embodiment, the fifth region connection portion 125A and the fifth extension portion 125B are integrated.

[0236] The fifth region connecting portion 125A is disposed at a position overlapping with the eighth semiconductor region 108 of the fourth diode cell 100D when viewed from the z direction. When viewed from the z direction, the fifth region connecting portion 125A is formed in a ring shape that surrounds the seventh semiconductor region 107 of the fourth diode cell 100D and has a gap in part.

[0237] The fifth extension portion 125B extends from the fifth region connection portion 125A toward the outside of the seventh semiconductor region 107. The fifth extension portion 125B extends to the outside of the temperature sensitive diode 100. In this embodiment, the fifth extension portion 125B extends from the fifth region connection portion 125A toward the opposite side to the first wiring 121.

[0238] 20, the fifth region connecting portion 125A is connected to the seventh semiconductor region 107 by an eighth through wiring 126H. That is, the eighth through wiring 126H is a wiring that connects the fifth region connecting portion 125A and the seventh semiconductor region 107. The eighth through wiring 126H is disposed at a position that overlaps both the fifth region connecting portion 125A and the seventh semiconductor region 107 when viewed from the z direction.

[0239] A plurality of second to eighth through wirings 126B to 126H may be provided. The plurality of second through wirings 126B are arranged spaced apart from one another. For example, the plurality of second through wirings 126B are arranged spaced apart from one another in the circumferential direction of the second semiconductor region 102. The plurality of third through wirings 126C are arranged spaced apart from one another. For example, the plurality of third through wirings 126C are arranged spaced apart from one another in the circumferential direction of the third semiconductor region 103. The plurality of fourth through wirings 126D are arranged spaced apart from one another. For example, the plurality of fourth through wirings 126D are arranged spaced apart from one another in the circumferential direction of the fourth semiconductor region 104. The plurality of fifth through wirings 126E are arranged spaced apart from one another. For example, the plurality of fifth through wirings 126E are arranged spaced apart from one another in the circumferential direction of the fifth semiconductor region 105. The plurality of sixth through wirings 126F are arranged spaced apart from one another. In one example, the plurality of sixth through wirings 126F are arranged spaced apart from one another in the circumferential direction of the sixth semiconductor region 106. The plurality of seventh through wirings 126G are arranged spaced apart from one another. In one example, the plurality of seventh through wirings 126G are arranged spaced apart from one another in the circumferential direction of the seventh semiconductor region 107. The plurality of eighth through wirings 126H are arranged spaced apart from one another. In one example, the plurality of eighth through wirings 126H are arranged spaced apart from one another in the circumferential direction of the eighth semiconductor region 108.

[0240] Next, the wiring configuration of the protection diode 110 will be described. The protection diode 110 has a first electrode 110M that serves as an anode electrode and a second electrode 110N that serves as a cathode electrode. The first electrode 110M and the second electrode 110N are provided separately at both ends of the protection diode 110 in the y direction. The first electrode 110M is provided at one of both ends of the protection diode 110 that is closer to the electrode pads 12 to 16 (see FIG. 1), and the second electrode 110N is provided at one of both ends of the protection diode 110 that is farther from the electrode pads 12 to 16.

[0241] 19, the configurations of the first to fifth wirings 131 to 135 and the through wirings 136A to 136H are the same as the configurations of the first to fifth wirings 121 to 125 and the through wirings 126A to 126H. Since the protection diode 110 is connected in anti-parallel to the temperature-sensitive diode 100, the arrangement of the first to fifth wirings 131 to 135 relative to the protection diode 110 is rotated 180° with respect to the arrangement of the first to fifth wirings 121 to 125 relative to the temperature-sensitive diode 100. Below, a schematic configuration of the first to fifth wirings 131 to 135 and the through wirings 136A to 136H will be described.

[0242] 21 , the first wiring 131 is provided at a position overlapping with the eighth semiconductor region 118 of the fourth protection diode cell 110D when viewed from the z direction, and is electrically connected to the eighth semiconductor region 118 via the first through wiring 136A. As described above, the first through wiring 136A is a wiring that connects the first wiring 131 and the eighth semiconductor region 118, and is disposed at a position overlapping with both the first wiring 131 and the eighth semiconductor region 118 when viewed from the z direction. The first wiring 131 is provided at a position overlapping with the eighth semiconductor region 118 when viewed from the z direction, and has a first region connection portion 131A to which the first through wiring 136A is connected, and a first extension portion 131B extending from the first region connection portion 131A in a direction opposite to the second wiring 132. The first extension portion 131B constitutes the second electrode 110N of the protection diode 110.

[0243] 19, the second wiring 132 is provided at a position overlapping both the seventh semiconductor region 117 of the fourth protection diode cell 110D and the sixth semiconductor region 116 of the third protection diode cell 110C when viewed from the z direction. As shown in FIG. 21, the second wiring 132 is electrically connected to the seventh semiconductor region 117 via the second through wiring 136B and electrically connected to the sixth semiconductor region 116 via the third through wiring 136C. In this manner, the second through wiring 136B is a wiring that connects the second wiring 132 and the seventh semiconductor region 117, and is arranged at a position overlapping both the second wiring 132 and the seventh semiconductor region 117 when viewed from the z direction. The third through wiring 136C is a wiring that connects the second wiring 132 and the sixth semiconductor region 116, and is arranged at a position overlapping both the second wiring 132 and the sixth semiconductor region 116 when viewed from the z direction. In this way, the first protection diode cell 110A and the second protection diode cell 110B are connected in series by the second wiring 132, the second through wiring 136B, and the third through wiring 136C.

[0244] 19, the third wiring 133 is provided at a position overlapping both the fifth semiconductor region 115 of the third protection diode cell 110C and the fourth semiconductor region 114 of the second protection diode cell 110B when viewed from the z direction. As shown in FIG. 21, the third wiring 133 is electrically connected to the fifth semiconductor region 115 via the fourth through wiring 136D and electrically connected to the fourth semiconductor region 114 via the fifth through wiring 136E. As such, the fourth through wiring 136D is a wiring that connects the third wiring 133 and the fifth semiconductor region 115, and is arranged at a position overlapping both the third wiring 133 and the fifth semiconductor region 115 when viewed from the z direction. The fifth through wiring 136E is a wiring that connects the third wiring 133 and the fourth semiconductor region 114, and is arranged at a position overlapping both the third wiring 133 and the fourth semiconductor region 114 when viewed from the z direction. In this way, the second protection diode cell 110B and the third protection diode cell 110C are connected in series by the third wiring 133, the fourth through wiring 136D, and the fifth through wiring 136E.

[0245] 19, the fourth wiring 134 is provided at a position overlapping both the third semiconductor region 113 of the second protection diode cell 110B and the second semiconductor region 112 of the first protection diode cell 110A when viewed from the z direction. As shown in FIG. 21, the fourth wiring 134 is electrically connected to the third semiconductor region 113 via the sixth through wiring 136F and electrically connected to the second semiconductor region 112 via the seventh through wiring 136G. As described above, the sixth through wiring 136F is a wiring that connects the fourth wiring 134 and the third semiconductor region 113, and is arranged at a position overlapping both the fourth wiring 134 and the third semiconductor region 113 when viewed from the z direction. The seventh through wiring 136G is a wiring that connects the fourth wiring 134 and the second semiconductor region 112, and is arranged at a position overlapping both the fourth wiring 134 and the second semiconductor region 112 when viewed from the z direction. In this way, the first protection diode cell 110A and the second protection diode cell 110B are connected in series by the fourth wiring 134, the sixth through wiring 136F, and the seventh through wiring 136G.

[0246] As shown in FIG. 21 , the fifth wiring 135 is provided at a position overlapping the first semiconductor region 111 of the first protection diode cell 110A when viewed from the z direction, and is electrically connected to the first semiconductor region 111 via the eighth through wiring 136H. As such, the eighth through wiring 136H is a wiring that connects the fifth wiring 135 and the first semiconductor region 111, and is arranged at a position overlapping both the fifth wiring 135 and the first semiconductor region 111 when viewed from the z direction. As shown in FIG. 19 , the fifth wiring 135 is provided at a position overlapping the first semiconductor region 111 when viewed from the z direction, and has a fifth region connection portion 135A to which the eighth through wiring 136H is connected, and a fifth extension portion 135B extending from the fifth region connection portion 135A in a direction opposite to the fourth wiring 134. The fifth extension portion 135B constitutes the first electrode 110M of the protection diode 110. It should be noted that a plurality of each of the second to eighth through wires 136B to 136H may be provided.

[0247] 19, the semiconductor device 10 has a first connection line 141 and a second connection line 142. The first connection line 141 is a wiring that connects the first electrode 100M of the temperature sensitive diode 100 and the second electrode 110N of the protection diode 110 to the anode electrode 22. The second connection line 142 is a wiring that connects the second electrode 100N of the temperature sensitive diode 100 and the first electrode 100M of the protection diode 110 to the emitter electrode 21.

[0248] The first connection line 141 is connected to both the first wiring 121 and the first wiring 131. More specifically, the first connection line 141 is connected to both the first extension portion 121B of the first wiring 121 and the first extension portion 131B of the first wiring 131. Although not shown, the first connection line 141 is connected to the anode electrode 22 through the first wiring lead-out region 21ba, similar to the first connection line 71 of the first embodiment.

[0249] The second connection line 142 is connected to both the fifth wiring 125 and the fifth wiring 135. More specifically, the second connection line 142 is connected to both the fifth extension portion 125B of the fifth wiring 125 and the fifth extension portion 135B of the fifth wiring 135. Although not shown, the second connection line 142 passes through the second wiring lead-out region 21bb and is connected to the adjacent region 21P of the emitter electrode 21.

[0250] (Effects of the third embodiment) According to the semiconductor device 10 of this embodiment, in addition to the effects of the first embodiment, the following effects can be obtained.

[0251] (3-1) The temperature sensitive diode 100 includes a first diode cell 100A and a second diode cell 100B provided separately from the first diode cell 100A. The first diode cell 100A includes a first semiconductor region 101 of a first conductivity type and a second semiconductor region 102 of a second conductivity type, while the second diode cell 100B includes a third semiconductor region 103 of the first conductivity type and a fourth semiconductor region 104 of the second conductivity type. The second semiconductor region 102 is formed in an annular shape surrounding the first semiconductor region 101 and has an inner circumferential surface 102a joined to a circumferential surface 101a of the first semiconductor region 101. The third semiconductor region 103 is formed in an annular shape surrounding the second semiconductor region 102 and has an inner circumferential surface 103a joined to an outer circumferential surface 102b of the second semiconductor region 102. The fourth semiconductor region 104 is formed in a circular ring shape surrounding the third semiconductor region 103 , and has an inner peripheral surface 104 a joined to an outer peripheral surface 103 b of the third semiconductor region 103 .

[0252] This configuration increases the junction area of ​​adjacent semiconductor regions among the first to fourth semiconductor regions 101 to 104, and reduces the space required to arrange the first diode cell 100A and the second diode cell 100B. This increases the accuracy of temperature detection by the temperature sensing diode 100, and also reduces the size of the temperature sensing diode 100.

[0253] (3-2) The first to fourth semiconductor regions 101 to 104 are arranged concentrically. This configuration makes it easier for the density of the current flowing from the first semiconductor region 101 to the fourth semiconductor region 104 to become uniform in the circumferential direction of the first semiconductor region 101.

[0254] [Example of change] The above-described embodiments are merely examples of possible forms of the semiconductor device according to the present disclosure, and are not intended to limit the forms. The semiconductor device according to the present disclosure may take forms different from those exemplified in the above-described embodiments. Examples include forms in which part of the configuration of the above-described embodiments is replaced, modified, or omitted, or forms in which new configurations are added to the above-described embodiments. Furthermore, the following modified examples can be combined with each other as long as there is no technical contradiction. In the following modified examples, parts common to the above-described embodiments are assigned the same reference numerals as the above-described embodiments, and their description will be omitted.

[0255] In the first embodiment, the shape of the first semiconductor region 44P of each of the diode cells 40A to 40D of the temperature sensitive diode 40P can be changed as desired. The shape of the first semiconductor region 44P can be changed, for example, as shown in Figures 22 to 25. Note that the shape of each of the protection diode cells 40E to 40H of the protection diode 40Q can also be changed in the same way.

[0256] As shown in FIG. 22, the shape of the first semiconductor region 44P is quadrangular when viewed from the z direction. That is, the first semiconductor region 44P has a quadrangular outer side surface 44Pc when viewed from the z direction. In this case, the second semiconductor region 45P has an inner side surface 45Pc that is joined to the outer side surface 44Pc of the first semiconductor region 44P along the entire periphery. Similarly to the first embodiment, the second semiconductor region 45P has an outer side surface 45Pb that is formed in a quadrangular shape when viewed from the z direction. In the example shown in FIG. 20, the sides of the outer side surface 44Pc of the first semiconductor region 44P and the sides of the outer side surface 45Pb of the second semiconductor region 45P that correspond to the sides of the outer side surface 44Pc are parallel to each other.

[0257] 23, the shape of the first semiconductor region 44P when viewed from the z direction is quadrangular, and each corner 44Pd is curved. That is, the outer side surface 44Pc of the first semiconductor region 44P has each curved corner 44Pd. In this case, each corner 45Pd of the inner side surface 45Pc of the second semiconductor region 45P is curved to correspond to each corner 44Pd of the first semiconductor region 44P. As a result, the inner side surface 45Pc of the second semiconductor region 45P is bonded to the outer side surface 44Pc of the first semiconductor region 44P around the entire periphery.

[0258] 24, the shape of the first semiconductor region 44P is quadrangular when viewed from the z direction. Furthermore, when viewed from the z direction, each side constituting the outer side surface 44Pc of the first semiconductor region 44P is inclined with respect to each side constituting the outer side surface 45Pb of the second semiconductor region 45P.

[0259] 25, the outer shape of the second semiconductor region 45P is not limited to a square and may be a rectangle. Even in this case, the shape of the first semiconductor region 44P can be changed as desired. For example, as shown in FIG. 25, the shape of the first semiconductor region 44P when viewed from the z direction is an oval.

[0260] In the third embodiment, it is possible to arbitrarily change the shapes of the first to eighth semiconductor regions 101 to 108 of each of the diode cells 100A to 100D of the temperature sensitive diode 100. For example, as shown in Fig. 26, each of the semiconductor regions 101 to 108 may be a rectangle when viewed from the z direction, with each corner of the rectangle being curved.

[0261] 27, the second connection line 72 may pass through the first wiring lead-out region 21ba instead of the second wiring lead-out region 21bb. That is, both the first connection line 71 and the second connection line 72 may pass through the first wiring lead-out region 21ba. In this case, for example, the second electrode 42P of the temperature sensitive diode 40P does not need to be connected to the adjacent region 21P of the emitter electrode 21.

[0262] In the first and second embodiments, the arrangement of the first to fourth diode cells 40A to 40D of the temperature sensitive diode 40P can be changed as desired. For example, the first to fourth diode cells 40A to 40D may be arranged in a line in the x direction. The first to fourth diode cells 40A to 40D may be arranged such that a pair of first and second diode cells 40A, 40B adjacent in the y direction and a pair of third and fourth diode cells 40C, 40D adjacent in the y direction are adjacent in the x direction.

[0263] In the first and second embodiments, the arrangement of the first to fourth protection diode cells 40E to 40H of the protection diode 40Q can be changed as desired. For example, the first to fourth protection diode cells 40E to 40H may be arranged in a line in the x direction. The first to fourth protection diode cells 40E to 40H may be arranged such that a pair of first and second protection diode cells 40E, 40F adjacent in the y direction and a pair of third and fourth protection diode cells 40G, 40H adjacent in the y direction are adjacent in the x direction.

[0264] In each embodiment, the number of diode cells of the temperature sensitive diode 40P, 100 can be changed arbitrarily. The number of diode cells of the temperature sensitive diode 40P, 100 may be two, three, five or more.

[0265] In each embodiment, the number of protection diode cells of the protection diode 40Q, 110 can be changed arbitrarily. The number of protection diode cells of the protection diode 40Q, 110 may be two, three, five or more.

[0266] In each embodiment, the temperature sensitive diode 40P, 100 may have one diode cell. In one example, as shown in Fig. 28, the temperature sensitive diode 40P has a first diode cell 40A. In this case, the semiconductor device 10 includes a first wiring 151 and a second wiring 152 formed on a surface 39b (see Fig. 10) of the intermediate insulating film 39 covering the temperature sensitive diode 40P, and a first through wiring 161 and a second through wiring 162 that penetrate the intermediate insulating film 39.

[0267] The first wiring 151 is a wiring electrically connected to the first semiconductor region 44P of the first diode cell 40A by a first through wiring 161. The first wiring 151 has a first region connection portion 153 provided at a position overlapping the first semiconductor region 44P when viewed from the z direction, and a first extension portion 154 extending from the first region connection portion 153 toward the outside of the first semiconductor region 44P. The first region connection portion 153 is formed to correspond to the shape of the first semiconductor region 44P when viewed from the z direction. In the illustrated example, the shape of the first region connection portion 153 when viewed from the z direction is circular. The first extension portion 154 extends from the first region connection portion 153 to the opposite side to the second wiring 152. The first extension portion 154 constitutes the first electrode 41P of the temperature sensitive diode 40P.

[0268] The first through wiring 161 is a wiring that connects the first wiring 151 and the first semiconductor region 44P. In the illustrated example, the first through wiring 161 is arranged at a position that overlaps both the first region connection portion 153 and the first semiconductor region 44P when viewed from the z direction. The shape of the first through wiring 161 when viewed from the z direction is circular. The first through wiring 161 is arranged on the outer periphery of the first semiconductor region 44P. In the illustrated example, a plurality of (two) first through wirings 161 are provided. The number of first through wirings 161 can be changed arbitrarily and may be one, for example. The first through wiring 161 is arranged at a position different from the first length measurement pattern 46P of the first diode cell 40A.

[0269] The second wiring 152 is electrically connected to the second semiconductor region 45P of the first diode cell 40A by a second through wiring 162. The second wiring 152 is insulated from the first wiring 151. The second wiring 152 has a second region connection portion 155 provided at a position overlapping the second semiconductor region 45P when viewed from the z direction, and a second extension portion 156 extending from the second region connection portion 155 toward the outside of the second semiconductor region 45P. When viewed from the z direction, the second region connection portion 155 is formed in an open ring shape that surrounds a portion of the first region connection portion 153 and has a gap so as not to contact the first extension portion 154. The second extension portion 156 extends from the second region connection portion 155 to the opposite side from the first wiring 151. The second extension portion 156 constitutes the second electrode 42P of the temperature sensitive diode 40P.

[0270] The second through wiring 162 is a wiring that connects the second wiring 152 and the second semiconductor region 45P. In the example shown, the second through wiring 162 is arranged at a position that overlaps both the second region connection portion 155 and the second semiconductor region 45P when viewed from the z direction. Note that a plurality of second through wirings 162 may be provided. The second through wiring 162 is arranged at a position different from the second length measurement pattern 47P of the first diode cell 40A.

[0271] In each embodiment, the scope of the adjacent region 21P is not limited to the region of the emitter electrode 21 surrounded by the two-dot chain line in FIG. 2 and can be changed as desired. The adjacent region 21P may be any region of the emitter electrode 21 adjacent to the temperature-sensitive diode 40P. For example, the adjacent region 21P may be formed from a region of the emitter electrode 21 adjacent to one side of the temperature-sensitive diode 40P in the x direction, or may be formed from a region of the emitter electrode 21 adjacent to one side of the temperature-sensitive diode 40P in the y direction. In other words, the adjacent region 21P may be any region adjacent to a part of the temperature-sensitive diode 40P.

[0272] In each embodiment, the protection diodes 40Q and 110 may be omitted from the semiconductor device 10. In each embodiment, the current sense electrode 24 may be omitted. Also, at least one of the current sense electrode pad 15 and the emitter sense electrode pad 16 may be omitted.

[0273] In each embodiment, the protective insulating film 17 may be omitted. In each embodiment, the semiconductor device 10 may include a cathode electrode provided separately from the emitter electrode 21. The cathode electrode is electrically connected to a second electrode 42P (100N) of the temperature-sensitive diode 40P (100). The cathode electrode is also electrically connected to a first electrode 41Q (110M) of the protection diode 40Q (11).

[0274] In each embodiment, the semiconductor device 10 is embodied as an IGBT, but is not limited to this. The semiconductor device 10 may be a SiCMOSFET (metal-oxide-semiconductor field-effect transistor) or a SiMOSFET.

[0275] The term "on" used in this disclosure includes the meanings of "on" and "above," unless the context clearly indicates otherwise. Therefore, the expression "A is formed on B" is intended to mean that, in this embodiment, A may be in contact with B and disposed directly on B, but as a variant, A may be disposed above B without contacting B. In other words, the term "on" does not exclude a structure in which another member is formed between A and B.

[0276] The z-direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure are not limited to the "up" and "down" of the z-direction described herein being "up" and "down" of the vertical direction. For example, the x-direction may be the vertical direction, or the y-direction may be the vertical direction.

[0277] The statement "at least one of A and B" in this specification should be understood to mean "A only, or B only, or both A and B." [Note] The technical ideas that can be understood from the above-described embodiments and modified examples are described below. Note that the reference numerals of the components of the embodiments corresponding to the components described in each appendix are shown in parentheses. The reference numerals are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.

[0278] (Appendix A1) a semiconductor layer (30); A cell (18A) provided in the semiconductor layer (30); an insulating film (38, 39) covering the cell (18A); a main electrode portion (21) laminated on the insulating film (38, 39); a temperature-sensitive diode (40P) for detecting temperature and having a first electrode (41P) and a second electrode (42P); a diode connection electrode (22) for connecting the first electrode (41P) to an external device, The main electrode portion (21) is a first bonding region (11) to which a first conductive member (CB) for connecting the main electrode portion (21) to an external device is bonded, the first bonding region (11) being electrically connected to the second electrode (42P); a second junction region (12) that is provided in a region different from the first junction region (11) when viewed from the thickness direction (z direction) of the semiconductor layer (30), and to which a second conductive member (CWA) for connecting the second electrode (42P) to an external device is joined; When viewed in the thickness direction (z direction) of the semiconductor layer (30), the cells (18A) are provided in both a first semiconductor region (RE) that overlaps with the first junction region (11) of the semiconductor layer (30) and a second semiconductor region (RK) that overlaps with the second junction region (12). Semiconductor device.

[0279] (Appendix A2) the first junction region (11) includes an adjacent region (21P) adjacent to a part of the temperature sensitive diode (40P) when viewed in the thickness direction (z direction) of the semiconductor layer (30); A second electrode connection wiring (72) is provided to connect the second electrode (42P) and the adjacent region (21P). The semiconductor device according to Appendix A1.

[0280] (Appendix A3) a wiring lead-out region (21ba) adjacent to the temperature sensitive diode (40P) and provided at a position different from the adjacent region (21P); The first electrode connection wiring (71) connected to the first electrode (41P) passes through the wiring lead-out region (21ba) and is connected to the diode connection electrode (22). The semiconductor device according to Appendix A2.

[0281] (Appendix A4) When viewed from the thickness direction (z direction) of the semiconductor layer (30), the cell (18A) is not formed in a region of the semiconductor layer (30) that overlaps with the diode connection electrode (22). The semiconductor device according to any one of Appendices A1 to A3.

[0282] (Appendix A5) When viewed in the thickness direction (z direction) of the semiconductor layer (30), the semiconductor layer (30) is formed in a rectangular shape, When viewed in the thickness direction (z direction) of the semiconductor layer (30), the second junction region (12) and the diode connection electrode (22) are arranged side by side along one side of the semiconductor layer (30). A semiconductor device according to any one of appendices A1 to A4.

[0283] (Appendix A6) When viewed in the thickness direction (z direction) of the semiconductor layer (30), the diode connection electrode (22) is disposed closer to the temperature sensitive diode (40P) than the second junction region (12). The semiconductor device according to Appendix A5.

[0284] (Appendix A7) The semiconductor device (10) includes a protective insulating film (17) that covers the main electrode portion (21), The protective insulating film (17) is a first opening (17A) exposing the first bonding region (11); a second opening (17B) exposing the second bonding region (12); a partition region (17a) disposed so as to separate the first opening (17A) and the second opening (17B); have The semiconductor device according to any one of appendices A1 to A6.

[0285] (Appendix A8) The semiconductor device (10) includes a protective insulating film (17) that covers the main electrode portion (21), The protective insulating film (17) has an opening (17G) that exposes the first bonding region (11) and the second bonding region (12) while they are in communication with each other. The semiconductor device according to any one of appendices A1 to A6.

[0286] (Appendix A9) The cell is a main cell (18A), the temperature-sensitive diode (40P) includes diode cells (40A to 40D) formed on a surface (38a) of the insulating film (38); The diode cells (40A to 40D) are a first conductivity type semiconductor region (44P) for a first diode; a second conductive type semiconductor region (45P) for a second diode formed in an annular shape surrounding the first diode semiconductor region (44P), The semiconductor device according to any one of appendices A1 to A8.

[0287] (Appendix A10) The semiconductor device (10) includes: an intermediate insulating film (39) covering the temperature sensitive diode (40P); and wiring (51-55) formed on a surface (39b) of the intermediate insulating film (39) and electrically connected to the first diode semiconductor region (44P) and the second diode semiconductor region (45P). The semiconductor device according to Appendix A9.

[0288] (Appendix A11) The diode cells (40A to 40D) are provided in plurality, The plurality of diode cells (40A to 40D) are connected in series with each other. The semiconductor device according to appendix A9 or A10.

[0289] (Appendix A12) The plurality of diode cells (40A to 40D) are arranged in a line when viewed from the thickness direction (z direction) of the semiconductor layer (30). The semiconductor device according to Appendix A11.

[0290] (Appendix A13) The semiconductor device (10) includes a protection diode (40Q) connected in antiparallel to the temperature-sensitive diode (40P). The semiconductor device according to any one of appendices A1 to A12.

[0291] (Appendix A14) The semiconductor device (10) is an IGBT, The main electrode portion is an emitter electrode (21), The first electrode (41P) is an anode electrode, The second electrode (42P) is a cathode electrode. The semiconductor device according to any one of appendices A1 to A13.

[0292] (Appendix A15) the semiconductor device (10) is a SiC MOSFET, The main electrode portion (21) is a source electrode, The first electrode (41P) is an anode electrode, The second electrode (42P) is a cathode electrode. The semiconductor device according to any one of appendices A1 to A13.

[0293] (Appendix B1) a semiconductor layer (30); an insulating film (38, 39) formed on a surface (30s) of the semiconductor layer (30); a main cell region (18) having a main cell (18A) provided in the semiconductor layer (30); a temperature-sensitive diode (40P) for detecting temperature, provided in a region separate from the main cell region (18); the temperature-sensitive diode (40P) has diode cells (40A-40D) each including a first semiconductor region (44P) of a first conductivity type formed in a thin film on the surface (38a) of the insulating film (38), and a second semiconductor region (45P) of a second conductivity type formed in a thin film on the surface (38a) of the insulating film (38); the second semiconductor region (45P) is formed in a ring shape surrounding the first semiconductor region (44P), The semiconductor device has an inner surface (45Pa) of the second semiconductor region (45P) in contact with the first semiconductor region (44P).

[0294] (Appendix B2) The first semiconductor region (44P) has a circular shape when viewed in the thickness direction (z direction) of the semiconductor layer (30), The second semiconductor region (45P) is an inner peripheral surface (45Pa) joined to the circumferential surface (44Pa) of the first semiconductor region (44P) over the entire circumference; and an outer surface (45Pb) formed in a quadrangular shape when viewed from the thickness direction (z direction) of the semiconductor layer (30). 10. The semiconductor device according to claim 8, wherein the semiconductor device is a semiconductor device according to claim 9.

[0295] (Appendix B3) The shape of the first semiconductor region (44P) when viewed from the thickness direction (z direction) of the semiconductor layer (30) is quadrangular, The second semiconductor region (45P) is an inner surface (45Pa) entirely bonded to the outer surface (44Pa) of the first semiconductor region (44P); and an outer surface (45Pb) formed in a quadrangular shape when viewed from the thickness direction (z direction) of the semiconductor layer (30). 10. The semiconductor device according to claim 8, wherein the semiconductor device is a semiconductor device according to claim 9.

[0296] (Appendix B4) When viewed from the thickness direction (z direction) of the semiconductor layer (30), each corner (44Pd) of the first semiconductor region (44P) is curved, Corners (45Pd) of an inner side surface (45Pa) of the second semiconductor region (45P) are curved to correspond to the corners (44Pd) of the first semiconductor region (44P) so as to contact the corners (44Pd). 10. The semiconductor device according to claim 9, wherein the semiconductor device is a semiconductor device according to claim 1, wherein the semiconductor device

[0297] (Appendix B5) When viewed from the thickness direction (z direction) of the semiconductor layer (30), each side of the first semiconductor region (44P) is inclined with respect to each side constituting the outer surface (45Pb) of the second semiconductor region (45P). 10. The semiconductor device according to claim 9, wherein the semiconductor device is a semiconductor device according to claim 1, wherein the semiconductor device

[0298] (Appendix B6) The semiconductor device (10) includes: an intermediate insulating film (39) covering the temperature sensitive diode (40P); a first wiring (51) and a second wiring (52) formed on a surface (39b) of the intermediate insulating film (39); a first through wiring (81P) that penetrates the intermediate insulating film (39) and connects the first wiring (51) and the first semiconductor region (44P); a second through-wiring (82P) that penetrates the intermediate insulating film (39) and connects the second wiring (52) and the second semiconductor region (45P); The semiconductor device according to any one of Appendix B1 to B5.

[0299] (Appendix B7) the first wiring (51) has a first region connection portion (51A) provided at a position overlapping the first semiconductor region (44P) when viewed from the thickness direction (z direction) of the semiconductor layer (30), and a first extension portion (51B) extending from the first region connection portion (51A) toward an outside of the first semiconductor region (44P), The second wiring (52) has a second region connection portion (52A) provided at a position overlapping the second semiconductor region (45P) when viewed from the thickness direction (z direction) of the semiconductor layer (30), and a second extension portion (52B) extending from the second region connection portion (52A) toward the outside of the second semiconductor region (45P). The semiconductor device according to Appendix B6.

[0300] (Appendix B8) The second region connection portion (52A) is formed in an open ring shape that surrounds a part of the first region connection portion (51A) and has a gap so as not to come into contact with the first extension portion (51B) when viewed in the thickness direction (z direction) of the semiconductor layer (30). The semiconductor device according to Appendix B7.

[0301] (Appendix B9) The temperature sensitive diode (40P) has a plurality of diode cells (40A to 40D) connected in series with each other and arranged in one direction. The semiconductor device according to any one of Appendix B1 to B5.

[0302] (Appendix B10) the plurality of diode cells (40A to 40D) include a first diode cell (40A) and a second diode cell (40B) adjacent to each other in an arrangement direction of the plurality of diode cells (40A to 40D), The semiconductor device (10) includes: an intermediate insulating film (39) covering the temperature sensitive diode (40P); a first wiring (51) formed on a surface (39b) of the intermediate insulating film (39) and connected to the first semiconductor region (44P) of the first diode cell (40A); a second wiring (52) formed on a surface (39b) of the intermediate insulating film (39) and insulated from the first wiring (51); The second wiring (52) electrically connects the second semiconductor region (45P) of the first diode cell (40A) and the first semiconductor region (44P) of the second diode cell (40B). The semiconductor device according to Appendix B9.

[0303] (Appendix B11) The second wiring (52) is a first part (56) provided at a position overlapping the second semiconductor region (45P) of the first diode cell (40A) when viewed from the thickness direction (z direction) of the semiconductor layer (30), and electrically connected to the second semiconductor region (45P) of the first diode cell (40A); a second part (57) provided at a position overlapping the first semiconductor region (44P) of the second diode cell (40B) when viewed from the thickness direction (z direction) of the semiconductor layer (30), and electrically connected to the first semiconductor region (44P) of the second diode cell (40B); and a connecting part (58) that connects the first part (56) and the second part (57). The semiconductor device according to Appendix B10.

[0304] (Appendix B12) a first wiring lead-out region (21ba) and a second wiring lead-out region (21bb) are provided at both ends in the arrangement direction of the diode arrangement portion (21b) in which the temperature sensitive diodes (40P) are arranged; the plurality of diode cells (40A to 40D) include a first end cell (40A) and a second end cell (40D) provided at both ends in the arrangement direction, the first end cell (40A) is arranged near the second wiring lead-out region (21bb), the second end cell (40B) is disposed closer to the first wiring lead-out region (21ba), The semiconductor device (10) includes: an intermediate insulating film (39) covering the temperature sensitive diode (40P); a first end wiring (51) that is formed on a surface (39b) of the intermediate insulating film (39), the first end wiring (51) having a first end connection portion (51A) that is provided at a position that overlaps with the first semiconductor region (44P) of the first end cell (40A) when viewed from the thickness direction (z direction) of the semiconductor layer (30), and a first end extension portion (51B) that extends from the first end connection portion (51A) to outside the first semiconductor region (44P) of the first end cell (40A) and constitutes a first electrode (41P) of the temperature sensitive diode (40P); a first connection line (71) connected to the first end extension portion (51B) and passing through the first wiring lead-out region (21ba); a second end wiring (55) that is formed on a surface (39b) of the intermediate insulating film (39), the second end wiring (55) having a second end connection portion (55A) provided at a position overlapping with the first semiconductor region (44P) of the second end cell (40D) when viewed from the thickness direction (z direction) of the semiconductor layer (30), and a second end extension portion (55B) that extends from the second end connection portion (55A) to outside the first semiconductor region (44P) of the second end cell (40D) and constitutes a second electrode (42P) of the temperature sensitive diode (40P); a second connection line (72) connected to the second end extension portion (55B) and passing through the second wiring lead-out region (21bb); The semiconductor device according to Appendix B10 or B11.

[0305] (Appendix B13) the diode cell is a first diode cell (40A), the temperature-sensitive diode (40P) has a second diode cell (40B) provided separately from the first diode cell (40A); the second diode cell (40B) is composed of a third semiconductor region (103) of a first conductivity type formed in a thin film on the surface (38a) of the insulating film (38), and a fourth semiconductor region (104) of a second conductivity type formed in a thin film on the surface (38a) of the insulating film (38); the third semiconductor region (103) is formed in a ring shape surrounding the second semiconductor region (102) and has an inner side surface (103a) joined to an outer side surface (102b) of the second semiconductor region (102); The fourth semiconductor region (104) is formed in a ring shape surrounding the third semiconductor region (103) and has an inner side surface (104a) joined to an outer side surface (103b) of the third semiconductor region (103). 10. The semiconductor device according to claim 8, wherein the semiconductor device is a semiconductor device according to claim 9.

[0306] (Appendix B14) The semiconductor device (10) includes: an intermediate insulating film (39) covering the temperature sensitive diode (40P); a first wiring (121) formed on a surface (39b) of the intermediate insulating film (39) and provided at a position overlapping the first semiconductor region (101); a second wiring (122) formed on a surface (39b) of the intermediate insulating film (39) and provided at a position overlapping both the second semiconductor region (102) and the third semiconductor region (103); a third wiring (103) formed on a surface (39b) of the intermediate insulating film (39) and provided at a position overlapping the fourth semiconductor region (104); a first through wiring (126A) that penetrates the intermediate insulating film (39) and connects the first wiring (121) and the first semiconductor region (101); a second through-wiring (126B) that penetrates the intermediate insulating film (39) and connects the second wiring (122) and the second semiconductor region (102); a third through-wiring (126C) that penetrates the intermediate insulating film (39) and connects the second wiring (122) and the third semiconductor region (103); a fourth through-wiring (126D) that penetrates the intermediate insulating film (39) and connects the third wiring (123) and the fourth semiconductor region (104); The semiconductor device according to Appendix B13.

[0307] (Appendix B15) the first wiring (121) has a first region connection portion (121A) and a first extension portion (121B); the first region connection portion (121A) is provided at a position overlapping the first semiconductor region (101) when viewed from the thickness direction (z direction) of the semiconductor layer (30), and is connected to the first through wiring (126A); the first extension portion (121B) extends from the first region connection portion (121A) toward the outside of the first semiconductor region (101); the second wiring (122) is formed in an open ring shape, when viewed from the thickness direction (z direction) of the semiconductor layer (30), so as to surround a part of the first region connection portion (121A) and have a gap so as not to come into contact with the first extension portion (121B); The third wiring (123) is provided at a position spaced apart from the radially outer side of the second wiring (122) when viewed from the thickness direction (z direction) of the semiconductor layer (30), and is formed in an open annular shape with a gap so as not to come into contact with the first extension portion (121B). The semiconductor device according to Appendix B14.

[0308] (Appendix B16) The first semiconductor region (101) has a circular shape when viewed from the thickness direction (z direction) of the semiconductor layer (30), the second semiconductor region (102) is annular and has an inner peripheral surface (102a) joined to the circumferential surface (101a) of the first semiconductor region (101) over the entire circumference; the third semiconductor region (103) is formed in a circular ring shape surrounding the second semiconductor region (102), and has an inner peripheral surface (103a) joined to an outer peripheral surface (102b) of the second semiconductor region (102) along the entire circumference; the fourth semiconductor region (104) is formed in a circular ring shape surrounding the third semiconductor region (103), and has an inner peripheral surface (104a) joined to an outer peripheral surface (103b) of the third semiconductor region (103) along the entire circumference; When viewed from the thickness direction (z direction) of the semiconductor layer (30), the first semiconductor region (101), the second semiconductor region (102), the third semiconductor region (103), and the fourth semiconductor region (104) are provided concentrically. The semiconductor device according to any one of Appendix B13 to B15.

[0309] (Appendix B17) The semiconductor device (10) includes a protection diode (40Q) connected in anti-parallel to the temperature-sensitive diode (40P). The semiconductor device according to any one of Appendix B1 to B16. [Explanation of symbols]

[0310] 10...Semiconductor device 10ce...end 11...Emitter electrode pad (first junction region) 12...Cathode electrode pad (second junction area) 17...Protective insulating film 17A…1st opening 17B…Second opening 17G…Opening 17a...Bulkhead area 18...Main cell area (cell area) 18A...Main cell (cell) 21...Emitter electrode (main electrode) 21P...adjacent area 21b...Diode arrangement section 21ba: First wiring area 21bb...Second wiring lead-out area 22...Anode electrode (connection electrode for diode) 30...Semiconductor substrate (semiconductor layer) 30s...Substrate surface (surface of semiconductor layer) 38...insulating film 38A...insulating film 38Aa…Surface 39...Intermediate insulating film 39b…Surface 40P...Temperature sensitive diode 40A...First diode cell (first end cell) 40B...Second diode cell 40C...Third diode cell 40D...Fourth diode cell (second end cell) 40Q...Protection diode 41P…1st electrode 42P…Second electrode 44P...First semiconductor region 44Pa...circumferential surface 44Pc…Outer surface 44Pd…Corner 45P: Second semiconductor region 45Pa…Inner peripheral surface 45Pb…Outer surface 45Pc…Inner surface 50… 51…1st wiring 51A...First region connection portion (first end connection portion) 51B...First extension part (first end extension part) 52…Second wiring 53...Third wiring 55…5th wiring 55A...Fifth region connection part (second end connection part) 55B...5th extension part (2nd end extension part) 56...First part 57...Second part 58...Connection parts 71...First connection line (first electrode connection wiring) 72...Second connection line (connection wiring for second electrode) 81P...First through wiring 82P...Second through wiring 83P...Third through wiring 84P…4th through wiring 100...Temperature sensitive diode 100A...First diode cell (diode cell) 100B...Second diode cell 100M…1st electrode 100N…Second electrode 101...first semiconductor region 101a...circumferential surface 102...second semiconductor region 102a...Inner peripheral surface 102b…Outer surface 103...Third semiconductor region 103a...Inner peripheral surface 103b…Outer surface 104...Fourth semiconductor region 104a...Inner peripheral surface 104b…Outer surface 110...Protection diode 121…1st wiring 121A...First area connection part 121B…1st extension part 122…Second wiring 123...Third wiring 124…4th wiring 125...5th wiring 125A...5th area connection part 125B…5th extension part 126A…1st through wiring 126B...Second through wiring 126C...Third through wiring 126D…4th through wiring 141...First connecting line 142...Second connecting line 151...1st wiring 152…Second wiring 153...First region connection part 154…1st extension part 155...Second region connection part 156…Second extension part 161...First through wiring 162...Second through wiring CB: First conductive member CWA: Second conductive member RA...1st junction area RB...Second bonding area RE... region (first semiconductor region) RK…area (second semiconductor area)

Claims

1. a semiconductor layer; A cell provided in the semiconductor layer; an insulating film covering the cell; a main electrode portion laminated on the insulating film; a temperature sensing diode for detecting temperature, the temperature sensing diode having a first electrode and a second electrode; a diode connection electrode for connecting the first electrode to an external device; Equipped with The main electrode portion is a first bonding region to which a first conductive member for connecting the main electrode portion to an external device is bonded, the first bonding region being electrically connected to the second electrode; a second junction region provided in a region different from the first junction region when viewed from a thickness direction of the semiconductor layer, to which a second conductive member for connecting the second electrode to an external device is bonded; and When viewed in the thickness direction of the semiconductor layer, the cells are provided in both a first semiconductor region overlapping the first junction region and a second semiconductor region overlapping the second junction region of the semiconductor layer. Semiconductor device.

2. the first junction region includes an adjacent region adjacent to a part of the temperature sensitive diode when viewed in a thickness direction of the semiconductor layer, a second electrode connection wiring that connects the second electrode and the adjacent region; The semiconductor device according to claim 1 .

3. a wiring lead-out region adjacent to the temperature sensitive diode and provided at a position different from the adjacent region; A first electrode connection wiring connected to the first electrode passes through the wiring lead-out region and is connected to the diode connection electrode. The semiconductor device according to claim 2 .

4. When viewed from the thickness direction of the semiconductor layer, the cell is not formed in a region of the semiconductor layer that overlaps with the diode connection electrode. The semiconductor device according to any one of claims 1 to 3.

5. When viewed in a thickness direction of the semiconductor layer, the semiconductor layer is formed in a rectangular shape, When viewed from the thickness direction of the semiconductor layer, the second junction region and the diode connection electrode are arranged side by side along one side of the semiconductor layer. The semiconductor device according to any one of claims 1 to 4.

6. When viewed in the thickness direction of the semiconductor layer, the diode connection electrode is disposed closer to the temperature sensitive diode than the second junction region. The semiconductor device according to claim 5 .

7. the semiconductor device includes a protective insulating film covering the main electrode portion, The protective insulating film is a first opening exposing the first bonding region; a second opening exposing the second bonding region; a partition region disposed to separate the first opening and the second opening; have The semiconductor device according to any one of claims 1 to 6.

8. the semiconductor device includes a protective insulating film covering the main electrode portion, The protective insulating film has openings that expose the first junction region, the second junction region, and a region between the first junction region and the second junction region. The semiconductor device according to any one of claims 1 to 6.

9. the cell is a main cell, the temperature-sensitive diode includes a diode cell formed on the surface of the insulating film, The diode cell comprises: a first diode semiconductor region of a first conductivity type; a second diode semiconductor region of a second conductivity type formed in a ring shape surrounding the first diode semiconductor region; have The semiconductor device according to any one of claims 1 to 8.

10. The semiconductor device includes: an intermediate insulating film covering the temperature sensitive diode; a wiring formed on a surface of the intermediate insulating film and electrically connected to the first diode semiconductor region and the second diode semiconductor region; Equipped with The semiconductor device according to claim 9 .

11. The diode cells are provided in plurality, The plurality of diode cells are connected in series with each other. The semiconductor device according to claim 9 or 10.

12. The plurality of diode cells are arranged in a line when viewed in the thickness direction of the semiconductor layer. The semiconductor device according to claim 11.

13. The semiconductor device includes a protection diode connected in antiparallel to the temperature-sensitive diode. The semiconductor device according to any one of claims 1 to 12.

14. the semiconductor device is an IGBT, the main electrode portion is an emitter electrode, the first electrode is an anode electrode, The second electrode is a cathode electrode. The semiconductor device according to any one of claims 1 to 13.

15. the semiconductor device is a SiC MOSFET, the main electrode portion is a source electrode, the first electrode is an anode electrode, The second electrode is a cathode electrode. The semiconductor device according to any one of claims 1 to 13.

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