Semiconductor Devices

Abstract

This semiconductor device comprises: an n-type drift layer; a p-type base region; a trench extending in the depth direction so as to pass through the base region and reach the drift layer; an insulating film formed on an inner surface of the trench; a gate trench surrounding the insulating film; and a p-type column region provided on the drift layer at a position at the bottom of the trench. The drift layer includes: a first region having a first concentration peak; and a second region that is provided at a position deeper than the trench and corresponding to the column region, and has a second concentration peak lower than the first concentration peak.

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] For example, a trench gate structure capable of achieving a low on-resistance is known for semiconductor devices such as IGBTs (Insulated Gate Bipolar Transistors) (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2018-120990 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in a semiconductor device with a trench gate structure, there is a trade-off between low on-resistance and high breakdown voltage, and therefore there is still room for improvement in achieving both low on-resistance and high breakdown voltage. [Means for solving the problem]

[0005] A semiconductor device that solves the above problem includes a drift layer of a first conductivity type, a body region of a second conductivity type formed on a surface side of the drift layer, a trench extending in a depth direction through the body region to reach the drift layer, an insulating film formed on an inner surface of the trench, a gate electrode surrounded by the insulating film, and a column region of the second conductivity type provided at a bottom of the trench in the drift layer, wherein the drift layer has a first region having a first concentration peak, and a second region that is provided at a position deeper than the trench and corresponding to the column region, and has a second concentration peak lower than the first concentration peak. [Effects of the Invention]

[0006] According to the semiconductor device, it is possible to achieve both a low on-resistance and a high breakdown voltage. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a plan view of an embodiment of a semiconductor device. [Figure 2] FIG. 2 is a cross-sectional view showing an example of the cross-sectional structure of a main cell region of a semiconductor device. [Figure 3] FIG. 3 is an enlarged view of a portion of FIG. [Figure 4] FIG. 4 is a graph showing the relationship between the depth of the drift layer of a semiconductor device and the impurity concentration. [Figure 5] FIG. 5 is an explanatory diagram illustrating the manufacturing steps of one embodiment of a method for manufacturing a semiconductor device. [Figure 6] FIG. 6 is an explanatory diagram illustrating an example of a manufacturing process of a semiconductor device manufacturing method. [Figure 7] FIG. 7 is an explanatory diagram illustrating an example of a manufacturing process of a semiconductor device manufacturing method. [Figure 8] FIG. 8 is an explanatory diagram illustrating an example of a manufacturing process of a semiconductor device manufacturing method. [Figure 9] FIG. 9 is an explanatory diagram illustrating an example of a manufacturing process of a semiconductor device manufacturing method. [Figure 10] FIG. 10 is an explanatory diagram illustrating an example of a manufacturing process of a semiconductor device manufacturing method. [Figure 11] FIG. 11 is an explanatory diagram illustrating an example of a manufacturing process of a semiconductor device manufacturing method. [Figure 12] FIG. 12 is a cross-sectional view showing an example of the cross-sectional structure of the main cell region of the semiconductor device of Experimental Example 1. As shown in FIG. [Figure 13] FIG. 13 is a cross-sectional view showing an example of the cross-sectional structure of the main cell region of the semiconductor device of Experimental Example 2. As shown in FIG. [Figure 14] FIG. 14 is a graph showing the relationship between the depth of the drift layer of a semiconductor device and the electric field strength. [Figure 15]FIG. 15 is a graph showing the relationship between the collector-emitter saturation voltage and loss when the semiconductor device is turned off. [Figure 16] FIG. 16 is a graph showing the relationship between the collector-emitter saturation voltage and loss when the semiconductor device is turned on. [Figure 17] FIG. 17 is a graph showing the relationship between the collector-emitter saturation voltage and the total loss when the semiconductor device is in operation. [Figure 18] FIG. 18 is a graph showing the transition of the collector-emitter voltage, the gate-emitter voltage, and the collector current when the semiconductor device is turned off. [Figure 19] FIG. 19 is a cross-sectional view showing an example of the cross-sectional structure of the main cell region and the diode cell region in a semiconductor device according to a modified example. [Figure 20] FIG. 20 is a cross-sectional view showing an example of the cross-sectional structure of the main cell region and the diode cell region in a semiconductor device according to a modified example. [Figure 21] FIG. 21 is a cross-sectional view showing an example of the cross-sectional structure of the main cell region and the diode cell region in a semiconductor device according to a modified example. [Figure 22] FIG. 22 is a cross-sectional view showing an example of the cross-sectional structure of the main cell region and the diode cell region in a semiconductor device according to a modified example. [Figure 23] FIG. 23 is a cross-sectional view showing an example of the cross-sectional structure of the main cell region and its surrounding region in a semiconductor device according to a modified example. [Figure 24] FIG. 24 is a cross-sectional view showing an example of the cross-sectional structure of the main cell region in the semiconductor device of the modified example. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments of a semiconductor device will be described with reference to the drawings. The embodiments shown below are intended to exemplify configurations and methods for embodying the technical ideas, and are not intended to limit the materials, shapes, structures, arrangements, dimensions, etc. of the components described below.

[0009] (Configuration of semiconductor device) The configuration of one embodiment of a semiconductor device 10 will be described with reference to FIG. 1, a semiconductor device 10 of this embodiment is a trench gate IGBT (Insulated Gate Bipolar Transistor), which is used as a switching element in an in-vehicle inverter device, for example.

[0010] The semiconductor device 10 is formed, for example, in the shape of a rectangular plate. In this embodiment, the device main surface 10s of the semiconductor device 10 is formed, for example, in the shape of a square. In this embodiment, the length of one side of the device main surface 10s is approximately 3.5 mm. In other words, the chip size of the semiconductor device 10 of this embodiment is 3.5 mm square. The semiconductor device 10 has a device back surface 10r (see FIG. 2) facing the opposite side to the device main surface 10s, and four device side surfaces 10a to 10d formed between the device main surface 10s and the device back surface 10r. The device side surfaces 10a to 10d are, for example, surfaces connecting the device main surface 10s and the device back surface 10r, and are perpendicular to both the device main surface 10s and the device back surface 10r.

[0011] The semiconductor device 10 includes an emitter electrode 21, a gate electrode 22, and a collector electrode 27 (see FIG. 3) as external electrodes for connecting the semiconductor device 10 to the outside. The emitter electrode 21 is an electrode that constitutes the emitter of the IGBT and is an electrode through which the main current of the semiconductor device 10 flows. The emitter electrode 21 is formed on the device main surface 10s. A recess 21a is formed in the emitter electrode 21 at a position closer to the device side surface 10c than the center in the y direction and at the center in the x direction. The recess 21a opens toward the device side surface 10c.

[0012] The gate electrode 22 is an electrode that constitutes the gate of the IGBT, and is an electrode to which a drive voltage signal for driving the semiconductor device 10 is supplied from outside the semiconductor device 10. The gate electrode 22 is formed on the device main surface 10s. The gate electrode 22 is formed in the recess 21a of the emitter electrode 21.

[0013] 2 is an electrode that constitutes the collector of the IGBT, and is an electrode through which the main current of the semiconductor device 10 flows. That is, in the semiconductor device 10, the main current flows from the collector electrode 27 to the emitter electrode 21. The collector electrode 27 constitutes the rear surface 10r of the device.

[0014] As indicated by the dashed line in Fig. 1, the semiconductor device 10 includes a main cell region 11 in which multiple main cells 11A (see Fig. 2) are formed, and a peripheral region 12 provided outside the main cell region 11 so as to surround the main cell region 11. In this embodiment, the main cell region 11 is a region that constitutes an IGBT. The peripheral region 12 can also be considered to be a region other than the main cell region 11.

[0015] An emitter electrode 21 is provided in the main cell region 11. The emitter electrode 21 is formed over most of the main cell region 11. When viewed from the z direction, the emitter electrode 21 has a shape that follows the shape of the main cell region 11. No main cell 11A is formed in a position that overlaps with the gate electrode 22 in the z direction. In other words, the main cell region 11 has a recess 11a that is recessed so as to avoid the gate electrode 22.

[0016] The peripheral region 12 is a region where a termination structure that improves the dielectric strength of the semiconductor device 10 is provided. The peripheral region 12 is formed on the peripheral portion of the device main surface 10s when viewed from the z direction. The peripheral region 12 is a region that surrounds the emitter electrode 21.

[0017] The peripheral region 12 is provided with a gate electrode 22, gate fingers 23, an emitter routing portion 24, a field limiting ring (FLR) portion 25, and an equipotential ring 26. The emitter electrode 21, the gate electrode 22, the emitter routing portion 24, the FLR portion 25, and the equipotential ring 26 include a common metal film. This metal film is formed of a material containing AlCu (an alloy of aluminum and copper), for example.

[0018] The gate finger 23 is configured to quickly supply the current supplied to the gate electrode 22 to the main cell 11A in a portion of the emitter electrode 21 that is distant from the gate electrode 22. The gate finger 23 is connected to the gate electrode 22.

[0019] When viewed from the z direction, the gate fingers 23 are provided so as to surround the main cell region 11. When viewed from the z direction, the gate fingers 23 can also be said to be provided so as to surround the emitter electrode 21. The gate fingers 23 have metal wiring provided at the same positions as the emitter electrode 21 and the gate electrode 22 in the z direction.

[0020] Gate finger 23 includes gate fingers 23A and 23B. Gate finger 23A extends from gate electrode 22 toward device side surface 10a and is formed to surround main cell region 11 from device side surface 10c, device side surface 10a, and device side surface 10d. Gate finger 23B extends from gate electrode 22 toward device side surface 10b and is formed to surround main cell region 11 from device side surface 10c, device side surface 10b, and device side surface 10d. The tip of gate finger 23A and the tip of gate finger 23B face each other with a gap in the x direction at a portion closer to device side surface 10d than emitter electrode 21.

[0021] The emitter routing portion 24 is a portion integrated with the emitter electrode 21, and is formed in a ring shape so as to surround the pair of gate fingers 23A and 23B. It can also be said that the emitter routing portion 24 is formed in a ring shape so as to surround the main cell region 11 when viewed from the z direction.

[0022] The FLR section 25 is a termination structure for improving the breakdown voltage of the semiconductor device 10, and is provided outside the emitter electrode 21. The FLR section 25 is formed in a ring shape surrounding the emitter electrode 21 and the gate electrode 22. In this embodiment, the FLR section 25 is formed in a closed ring shape. The FLR section 25 has the function of improving the breakdown voltage of the semiconductor device 10 by alleviating the electric field in the peripheral region 12 and suppressing the influence of external ions.

[0023] The equipotential ring 26 is a termination structure for improving the breakdown voltage of the semiconductor device 10, and is formed in a ring shape to surround the FLR portion 25. In this embodiment, the equipotential ring 26 is formed in a closed ring shape. The equipotential ring 26 has the function of improving the breakdown voltage of the semiconductor device 10.

[0024] (Main cell configuration) Next, we will explain the configuration of the main cell 11A in the main cell region 11. Fig. 2 shows an example of the cross-sectional structure of a part of the main cell region 11 and a part of the peripheral region 12. Note that for convenience, Fig. 2 omits hatching of some of the components of the semiconductor device 10 in the main cell region 11.

[0025] 2, the semiconductor device 10 includes a semiconductor substrate 30. The semiconductor substrate 30 is, for example, an n - The semiconductor substrate 30 is made of a material containing silicon (Si) and has a thickness of, for example, 50 μm or more and 200 μm or less.

[0026] The semiconductor substrate 30 has a substrate front surface 30s and a substrate back surface 30r that face opposite each other in the z direction. In other words, the z direction can also be said to be the thickness direction of the semiconductor substrate 30. The semiconductor substrate 30 is formed by sequentially stacking p + a n-type collector layer 31, an n-type buffer layer 32, and an n - The semiconductor device 10 has a structure in which a collector electrode 27 is formed on a rear surface 30r of the substrate. The collector electrode 27 is formed over substantially the entire surface of the rear surface 30r of the substrate. The surface of the collector electrode 27 opposite to the rear surface 30r of the substrate forms the rear surface 10r of the semiconductor device 10.

[0027] As a p-type dopant for collector layer 31, for example, B (boron), Al (aluminum), etc. are used. The impurity concentration of collector layer 31 is, for example, 1×10 15 cm -3 Over 2×10 19 cm -3 The following is the result.

[0028] For example, N (nitrogen), P (phosphorus), As (arsenic), etc. are used as n-type dopants for buffer layer 32 and drift layer 33. The impurity concentration of buffer layer 32 is, for example, 1×10 15 cm -3 5x10 or more 17 cm -3 The impurity concentration of the drift layer 33 is lower than that of the buffer layer 32, for example, 1×10 13 cm -3 5x10 or more 14 cm -3 The following is the result.

[0029] A p-type base region 34 is formed on the surface of the drift layer 33, i.e., on the substrate surface 30s. The base region 34 is formed over substantially the entire surface of the main cell region 11. The impurity concentration of the base region 34 is, for example, 1×10 16 cm -3 More than 1×10 18 cm -3The depth of the base region 34 from the substrate surface 30s is, for example, 1.0 μm or more and 3.0 μm or less. An interface 39A is formed between the drift layer 33 and the base region 34. Here, in this embodiment, the p-type base region 34 corresponds to the "body region of the second conductivity type."

[0030] Trenches 35 are provided on the surface (substrate surface 30s) of the drift layer 33 in the main cell region 11. In this embodiment, a plurality of trenches 35 are provided and arranged at a distance from each other. The trenches 35 extend, for example, along the y direction and are arranged at a distance from each other in the x direction. This divides the main cells 11A into striped main cells. The interval between adjacent trenches 35 in the x direction (the center-to-center distance between the trenches 35) is, for example, 0.5 μm or more and 1.5 μm or less. The width of each trench 35 (the dimension of the trench 35 in the x direction) is, for example, 0.5 μm or more and 1.5 μm or less. In this embodiment, the interval between adjacent trenches 35 in the x direction is equal to or less than the width of the trench 35. In other words, the distance D between adjacent trenches 35 in the arrangement direction of the trenches 35 is equal to or less than the width dimension Wt of the trench 35. The trenches 35 may be formed in a lattice pattern to separate the main cells 11A arranged in rows and columns.

[0031] Each trench 35 extends in the z direction to penetrate the base region 34 and reach the drift layer 33. That is, each trench 35 penetrates the base region 34 in the z direction and extends partway through the drift layer 33. As a result, the z direction is the depth direction of the trench 35. More specifically, each trench 35 extends in the z direction from the surface (substrate surface 30s) of the drift layer 33. Each trench 35 extends through the base region 34 to reach a region of the drift layer 33 closer to the substrate back surface 30r than the base region 34. In this embodiment, the depth of the trench 35 is approximately 6.0 μm.

[0032] At the position of the bottom 35a of each trench 35 in the drift layer 33, a column region 38 of the second conductivity type (p-type) is provided. That is, the column regions 38 are provided individually for the plurality of trenches 35 corresponding to the plurality of trenches 35. For this reason, a plurality of column regions 38 are provided in a state of being arranged apart from each other. In the present embodiment, each column region 38 is in an electrically floating state.

[0033] The column region 38 is formed so as to cover the entire bottom 35a of the corresponding trench 35. That is, the width dimension Wc of the column region 38 is equal to or greater than the width dimension Wt of the trench 35. The width dimension Wt of the trench 35 is the dimension of the trench 35 in the arrangement direction of the trenches 35, and the width dimension Wc of the column region 38 is the dimension of the column region 38 in the arrangement direction of the trenches 35. The depth of the column region 38 from the bottom 35a of the trench 35 (hereinafter, the depth Hc of the column region 38) is, for example, 1 μm or more and 2 μm or less. In the present embodiment, the depth Hc of the column region 38 is about 1.5 μm. In the present embodiment, the width dimension Wc of the column region 38 is the dimension of the column region 38 in the x direction, and the depth Hc of the column region 38 is the dimension of the column region 38 in the z direction from the bottom 35a of the trench 35. As shown in FIG. 2, the column region 38 is formed such that the depth Hc of the column region 38 is larger than the width dimension Wc thereof (Wc < Hc). The impurity concentration of the column region 38 is lower than the impurity concentration of the base region 34, for example, 1.0×10 15 cm -3 or more and 5.0×10 17 cm -3 or less.

[0034] On the surface of the base region 34 (substrate surface 30s) in the main cell region 11, n +The emitter regions 36 are formed in the base region 34. The emitter regions 36 are arranged on both sides of the trench 35 in the x direction. In other words, the emitter regions 36 can be said to be provided on both sides of the trench 35 in the arrangement direction of the trenches 35 in the base region 34. Therefore, two emitter regions 36 are arranged with a gap between them in the x direction between adjacent trenches 35 in the x direction. The depth of each emitter region 36 is, for example, 0.2 μm or more and 0.6 μm or less. The impurity concentration of each emitter region 36 is higher than that of the base region 34, for example, 1×10 19 cm -3 5x10 or more 20 cm -3 The following is the result.

[0035] The surface of the base region 34 in the main cell region 11 (substrate surface 30s) contains p + A base contact region 37 of the type is formed. The base contact region 37 is provided at a position adjacent to the emitter region 36 in the x direction. In other words, the base contact region 37 is provided in the x direction between two emitter regions 36 provided between the x directions of the trenches 35 adjacent to each other in the x direction. Each base contact region 37 may be formed deeper than the emitter region 36. The depth of each base contact region 37 is, for example, 0.2 μm or more and 0.8 μm or less. The impurity concentration of each base contact region 37 is higher than that of the base region 34, for example, 5×10 18 cm -3 More than 1×10 20 cm -3 The base contact region 37 is formed in the base region 34. Therefore, it can be said that the base region 34 includes the base contact region 37 as a region in the base region 34 with a high impurity concentration.

[0036] An insulating film 41 is integrally formed on both the inner surface of each trench 35 and the substrate surface 30s. Therefore, it can be said that the insulating film 41 is formed on the surface of the drift layer 33. The insulating film 41 includes, for example, silicon oxide (SiO2). The thickness of the insulating film 41 is, for example, not less than 1100 Å and not more than 1300 Å. It can also be said that the insulating film 41 in the main cell region 11 constitutes a gate insulating film. The insulating film 41 formed on the substrate surface 30s has a back surface 41r facing the same side as the substrate back surface 30r. In this embodiment, the back surface 41r of the insulating film 41 is in contact with the substrate surface 30s.

[0037] An electrode material made of, for example, polysilicon is buried in each trench 35 via an insulating film 41. The electrode material buried in each trench 35 is electrically connected to either the gate electrode 22 (gate finger 23) or the emitter electrode 21. That is, the electrode material buried in each trench 35 forms a gate trench 22A and an emitter trench 21A. In this embodiment, the gate trenches 22A and the emitter trenches 21A are alternately provided in the arrangement direction of the plurality of trenches 35. In this embodiment, both the gate trench 22A and the emitter trench 21A are buried up to the opening end of each trench 35. It can also be said that the gate trench 22A constitutes a part of the gate electrode 22 (see FIG. 1).

[0038] An intermediate insulating film 42 is formed on a surface 41s of the insulating film 41 provided on the substrate surface 30s. The intermediate insulating film 42 includes, for example, SiO2. The thickness of the intermediate insulating film 42 is thicker than that of the insulating film 41, and is not less than 3000 Å and not more than 15000 Å.

[0039] The emitter electrode 21 is formed on a surface 42s of the intermediate insulating film 42. The intermediate insulating film 42 is an interlayer insulating film that fills both the space between the emitter electrode 21 and the gate trench 22A and the space between the emitter electrode 21 and the emitter trench 21A.

[0040] A contact hole 43 exposing the base contact region 37 is formed in both the intermediate insulating film 42 and the insulating film 41 in the main cell region 11. In this embodiment, the contact hole 43 is formed for each trench 35 in the main cell region 11. A portion of the emitter electrode 21 is embedded in the contact hole 43 and is in contact with the base contact region 37.

[0041] The emitter electrode 21 has an electrode main body 21c formed on the surface 42s of the intermediate insulating film 42, and a plurality of embedded electrode portions 21b individually embedded in the plurality of contact holes 43. In this embodiment, the electrode main body 21c and each embedded electrode portion 21b are provided separately. The electrode main body 21c is provided on each embedded electrode portion 21b.

[0042] More specifically, a barrier metal layer 21e is formed on a surface 42s of the intermediate insulating film 42 and on the inner surfaces of the intermediate insulating film 42 and insulating film 41 that form the contact hole 43. The barrier metal layer 21e is formed of a laminated structure of, for example, Ti (titanium) and TiN (titanium nitride). Both the embedded electrode portions 21b and the electrode main body portions 21c are formed on the barrier metal layer 21e.

[0043] Next, the relationship between the impurity concentrations of the semiconductor regions in the semiconductor device 10 will be described. FIG. 3 is an enlarged view of a portion of the main cell 11A in the main cell region 11 of FIG. 2. FIG. 4 is a graph showing an example of the distribution of impurity concentrations along a first line L1 and a second line L2, which are dashed lines extending in the z-direction in the main cell 11A of FIG. 3. The first line L1 is located between adjacent trenches 35 in the x-direction. The second line L2 is located within the trench 35. A solid line graph G1 in FIG. 4 is a graph showing the distribution of impurity concentrations along the first line L1, and a dashed-dotted line graph G2 in FIG. 4 is a graph showing the distribution of impurity concentrations along the second line L2. In FIG. 4, the horizontal axis represents the depth from the surface (substrate surface 30s) of the drift layer 33, and the vertical axis represents the impurity concentration. The following description will be made with reference to the components of the semiconductor device 10 of FIG. 3.

[0044] 4, the region from depth H1 to depth H2 corresponds to base region 34, and the region deeper than depth H2 corresponds to a region of drift layer 33 that is closer to substrate back surface 30r than base region 34. Depth H2 corresponds to interface 39A between drift layer 33 and base region 34.

[0045] Furthermore, depth H4, which is deeper than depth H2, corresponds to bottom 35a of trench 35. The region from depth H4 to depth H5 corresponds to column region 38. Depth H5 corresponds to interface 39B between drift layer 33 and column region 38. Interface 39B is the interface between bottom surface 38a of column region 38 and drift layer 33.

[0046] A region of the drift layer 33 adjacent to the base region 34 in the z direction (depth direction in FIG. 4) is defined as a first region 33A, a region of the drift layer 33 including a region formed in the same position as the column region 38 in the z direction is defined as a second region 33B, and a region of the drift layer 33 deeper than the column region 38 in the z direction is defined as a third region 33C. That is, the drift layer 33 has the first region 33A, the second region 33B, and the third region 33C. In this embodiment, the first region 33A, the second region 33B, and the third region 33C are formed to be spaced apart from each other in the z direction.

[0047] The first region 33A is a region deeper than depth H2 and equal to or less than depth H3. The first region 33A can also be said to be a region near an interface 39A between the drift layer 33 and the base region 34. As shown in FIG. 4, the first region 33A has a first concentration peak CP1. More specifically, in the first region 33A, the impurity concentration increases as the depth increases from depth H2, and the impurity concentration reaches the first concentration peak CP1 at depth HA. In this embodiment, the first concentration peak CP1 is, for example, 9×10 16 cm -3 The impurity concentration in the first region 33A is, for example, 1×10 16 cm -3 Higher than 1×10 17 cm -3 Lower than.

[0048] In a region of the first region 33A that is deeper than the depth HA and equal to or less than the depth H3, the impurity concentration decreases to a greater extent as the depth increases from the depth HA. Furthermore, in a region deeper than the depth H3 outside the first region 33A, the impurity concentration also decreases as the depth of the drift layer 33 increases. In this embodiment, in the range from the depth H3 to a depth HC that is deeper than the depth H3 and shallower than the depth H4, the impurity concentration decreases as the depth of the drift layer 33 increases. However, in a region deeper than the depth H3, the degree to which the impurity concentration decreases is smaller than in a region deeper than the depth HA and equal to or less than the depth H3.

[0049] In the region from depth HC to depth H4, the impurity concentration gradually increases as the depth of the drift layer 33 increases. In the region from depth H2 to depth H4, the impurity concentration is lowest at depth HC. In this embodiment, the impurity concentration at depth HC is, for example, 1×10 15 cm -3 Higher than 2×10 15 cm -3In this way, in the region between the first region 33A and the second region 33B in the depth direction (z direction) of the drift layer 33, the impurity concentration gradually decreases as the depth of the drift layer 33 increases, so that the impurity concentration is maintained high overall.

[0050] The second region 33B is a region from a depth H4 to a depth H5. In this embodiment, the second region 33B is formed at the same position as the column region 38 in the z direction (depth direction). The second region 33B can also be said to be a region provided at a position deeper than the bottom 35a of the trench 35 and corresponding to the column region 38. The second region 33B has a portion provided at the same position as the column region 38 in the depth direction as the position corresponding to the column region 38.

[0051] As shown in FIG. 4, the second region 33B has a second concentration peak CP2 that is lower than the first concentration peak CP1. More specifically, in the second region 33B, the impurity concentration increases as the depth increases from depth H4, and reaches the second concentration peak CP2 at depth HB. Here, depth HB is the position at which the second region 33B overlaps with the column region 38 in the z direction (depth direction). That is, the impurity concentration of the second region 33B is highest at the position at which the second region 33B overlaps with the column region 38 in the z direction. In the second region 33B, the impurity concentration decreases from depth HB to depth H5. The second concentration peak CP2 is, for example, 2×10 15 cm -3 The impurity concentration of the second region 33B is, for example, 1×10 14 cm -3 Higher than and 2×10 15 cm -3 The following is the result.

[0052] In a region deeper than depth H5 and shallower than depth H6, the impurity concentration decreases as the depth of drift layer 33 increases. That is, the impurity concentration in this region is higher than the impurity concentration at depth H6.

[0053] The third region 33C is a region equal to or smaller than the depth H6. The depth H6 is a region deeper than the column region 38. This is the region in the drift layer 33 where the impurity concentration is lowest. The third region 33C constitutes the end of the drift layer 33 that is closer to the rear surface 30r of the substrate in the z direction (depth direction in FIG. 4). In the third region 33C, the impurity concentration remains constant even when the depth increases beyond the depth H6. The impurity concentration in the third region 33C is, for example, 1×10 14 cm -3 Therefore, it can be said that the second concentration peak CP2 of the second region 33B is higher than the impurity concentration of the third region 33C. In this way, the impurity concentration of the region between the second region 33B and the third region 33C in the depth direction (z direction) of the drift layer 33 (a region deeper than depth H5 and shallower than depth H6) is higher than the impurity concentration of the third region 33C.

[0054] 4, the maximum value CM1 of the impurity concentration in the column region 38 is higher than the second concentration peak CP2 in the second region 33B. Furthermore, the maximum value CM1 of the impurity concentration in the column region 38 is higher than the first concentration peak CP1 in the first region 33A. On the other hand, the impurity concentration in the column region 38 is lower than the impurity concentration in the base region 34. In other words, the maximum value CM1 of the impurity concentration in the column region 38 is lower than the maximum value CM2 of the impurity concentration in the base region 34.

[0055] Furthermore, in the depth direction (z direction) of the drift layer 33, the impurity concentration of the column region 38 is higher than the impurity concentration of the second region 33B over substantially the entire column region 38. More specifically, the impurity concentration of the column region 38 is higher than the impurity concentration of the second region 33B except near the interface 39B (near the depth H5).

[0056] The range of the first region 33A in the z direction (depth direction) can be changed arbitrarily. In one example, the first region 33A may include a region deeper than depth H3. For example, the first region 33A may be a region from depth H2 to depth HC. Alternatively, for example, the first region 33A may be a region from depth H2 to depth H4.

[0057] The range of the second region 33B in the z direction (depth direction) can be changed arbitrarily. For example, the second region 33B may include a region shallower than depth H4. For example, the second region 33B may be a region from depth HC to depth H5. In this case, the first region 33A is a region from depth H2 to depth H3, or a region from depth H2 to depth HC. Furthermore, for example, the second region 33B may be a region from depth H3 to depth H5. In this case, the first region 33A is a region from depth H2 to depth H3.

[0058] In one example, the second region 33B may include a region deeper than depth H5. In one example, the second region 33B is a region from depth H4 to depth H6. In other words, the second region 33B may be a region from depth H3 to depth H6. In this way, the second region 33B may have a portion that is provided at a position corresponding to the column region 38 and that is shifted from the column region 38 in the depth direction.

[0059] (Method of manufacturing a semiconductor device) A method for manufacturing the semiconductor device 10 of this embodiment will be described with reference to Figures 5 to 11. Note that the following describes a method for manufacturing the main cell region 11. For convenience, the method for manufacturing one semiconductor device 10 will be described with reference to Figures 5 to 11. Here, the method for manufacturing the semiconductor device 10 of this embodiment is not limited to the manufacture of one semiconductor device 10, but may also be the manufacture of multiple semiconductor devices 10.

[0060] The method for manufacturing the semiconductor device 10 of this embodiment includes a step of preparing a semiconductor substrate 830 made of a material containing Si. As shown in FIG. 5, the semiconductor substrate 830 includes an n-type semiconductor layer as a first conductivity type semiconductor layer. - The drift layer 33 is formed over the entire semiconductor substrate 830. The impurity concentration of the drift layer 33 is, for example, 1×10 14 cm -3The semiconductor substrate 830 has a substrate front surface 830s and a substrate back surface (not shown) that face opposite each other in the thickness direction (z direction). Therefore, it can also be said that the substrate front surface 830s is the surface of the drift layer 33.

[0061] 5, the manufacturing method of the semiconductor device 10 of this embodiment includes a step of forming a plurality of trenches 835 in the semiconductor substrate 830. Specifically, first, a trench mask (not shown) is formed on the substrate surface 830s of the semiconductor substrate 830. Next, the trench mask is selectively etched. That is, when viewed from the z direction, regions of the trench mask where the trenches 835 are to be formed are etched. As a result, regions of the substrate surface 830s of the semiconductor substrate 830 where the trenches 835 are to be formed are exposed in the trench mask. Next, regions of the substrate surface 830s of the semiconductor substrate 830 where the trenches 835 are to be formed are etched. As a result, the trenches 835 are formed in the semiconductor substrate 830.

[0062] Next, the manufacturing method of the semiconductor device 10 of this embodiment includes a step of forming a sacrificial oxide film 850 on the surfaces of the plurality of trenches 835 and the semiconductor substrate 830. The sacrificial oxide film 850 is formed by thermally oxidizing the semiconductor substrate 830. The sacrificial oxide film 850 is formed of a material containing, for example, silicon oxide (SiO2).

[0063] As shown in FIG. 6, the method for manufacturing the semiconductor device 10 of this embodiment includes a step of implanting impurities of the first conductivity type (n-type) into the drift layer 33. In this step, impurities are injected into the drift layer 33 from the trench 835 in a direction tilted with respect to the z direction and diffused. In one example, impurities are injected into the drift layer 33 through the trench 835 in a direction tilted by 7° with respect to the z direction and diffused. As a result, a first region 33A, a second region 33B, and a third region 33C are formed in the drift layer 33. The first region 33A is a region having a first concentration peak CP1. The impurity concentration of the first region 33A is, for example, 1×10 15 cm -3 Higher than 1×1017 cm -3 The second region 33B has a second concentration peak CP2 that is lower than the first concentration peak CP1. The impurity concentration of the second region 33B is, for example, 1×10 14 cm -3 Higher than and 2×10 15 cm -3 The third region 33C is closer to the rear surface of the substrate than the trench 835. The impurity concentration of the third region 33C is, for example, 1×10 14 cm -3 This becomes:

[0064] As shown in FIG. 7, the method for manufacturing the semiconductor device 10 of this embodiment includes the steps of forming the base region 34 and the column region 38. In this step, impurities of the second conductivity type (p-type) are implanted into the drift layer 33 along the z direction over the entire main cell region 11. As a result, the p-type impurities are implanted and diffused into the drift layer 33 between the trenches 835 adjacent to each other in the x direction, thereby forming the base region 34. The p-type impurities are implanted and diffused through the trenches 835 into the bottoms 835a of the trenches 835, thereby forming the column region 38. The impurity concentration of the base region 34 is, for example, 1×10 16 cm -3 More than 1×10 18 cm -3 The impurity concentration of the column region 38 is, for example, 1.0×10 15 cm -3 Over 5.0 x 10 17 cm -3 The result is as follows: Then, the sacrificial oxide film 850 is removed.

[0065] As shown in FIG. 8, the method for manufacturing the semiconductor device 10 of this embodiment includes a step of forming an insulating film 841 and a step of forming an electrode. In the step of forming the insulating film 841, first, the semiconductor substrate 830 is thermally oxidized to form an oxide film on the entire surface of the semiconductor substrate 830, including the inner surfaces of each trench 835. As a result, the insulating film 841 is formed on the substrate surface 830s of the semiconductor substrate 830. The insulating film 841 is an insulating film corresponding to the insulating film 41. The insulating film 841 in the main cell region 11 (see FIG. 2) is a gate insulating film, and is also formed on the inner surfaces of each trench 835.

[0066] Subsequently, in the step of forming electrodes, an electrode material PS such as polysilicon is buried in each trench 835 and formed on the substrate surface 830s of the semiconductor substrate 830. This forms the gate trench 22A and the emitter trench 21A.

[0067] Next, the electrode material PS in the main cell region 11 of the substrate surface 830s of the semiconductor substrate 830 is removed by etching. Then, the electrode material PS embedded in each trench 835 is oxidized. As a result, an insulating film 841 is formed on the electrode material PS.

[0068] 9, the method for manufacturing the semiconductor device 10 of this embodiment includes a step of forming the emitter region 36. Specifically, n-type impurities are selectively ion-implanted and diffused into the substrate surface 830s of the semiconductor substrate 830, thereby forming an n + An emitter region 36 of the same type is formed. The impurity concentration of the emitter region 36 is higher than the impurity concentration of the base region 34, for example, 1×10 19 cm -3 5x10 or more 20 cm -3 The following is the result.

[0069] As shown in FIG. 10, the method for manufacturing the semiconductor device 10 of this embodiment includes the steps of forming an intermediate insulating film 842, forming an opening, and forming a base contact region 37.

[0070] The intermediate insulating film 842 is formed over the entire substrate surface 830s of the semiconductor substrate 830 by, for example, chemical vapor deposition (CVD). The intermediate insulating film 842 is formed on a surface 841s of the insulating film 841. The intermediate insulating film 842 is an insulating film corresponding to the intermediate insulating film 42. The intermediate insulating film 842 is laminated on the insulating film 841. In this case, the insulating film covering the substrate surface 830s of the semiconductor substrate 830 is an insulating film with a two-layer structure made up of the insulating film 841 formed on the substrate surface 830s of the semiconductor substrate 830 and the intermediate insulating film 842.

[0071] An opening 843 is formed by etching so as to penetrate each of the intermediate insulating film 842 and the insulating film 841. The opening 843 exposes the base region 34. As a result, the insulating film 41 and the intermediate insulating film 42 are formed.

[0072] Subsequently, p-type dopants are ion-implanted and diffused into the substrate surface 830s of the semiconductor substrate 830 through the openings 843, thereby forming p + The base contact region 37 is formed with an impurity concentration of, for example, 5×10 18 cm -3 More than 1×10 20 cm -3 The following is the result.

[0073] As shown in FIG. 11, the method for manufacturing the semiconductor device 10 of this embodiment includes a step of forming an emitter electrode 21. First, a first metal layer is formed on the surface 42s of the intermediate insulating film 42 and the inner surface of the opening 843 by sputtering using, for example, titanium (Ti). Then, a second metal layer is formed on the first metal layer by sputtering using titanium nitride (TiN). This forms a barrier metal layer 21e. Next, an electrode layer 821 is formed by sputtering using AlCu. The electrode layer 821 is formed over the entire intermediate insulating film 42 when viewed from the z direction. Next, the electrode layer 821 is etched to form the emitter electrode 21.

[0074] Although not shown, the manufacturing method of semiconductor device 10 of this embodiment includes the steps of forming buffer layer 32, collector layer 31, and collector electrode 27. Specifically, buffer layer 32 and collector layer 31 are formed in this order by selectively ion-implanting and diffusing n-type and p-type dopants into the back surface of semiconductor substrate 830. Subsequently, collector electrode 27 is formed on the surface of collector layer 31 opposite to buffer layer 32. Through these steps, semiconductor device 10 is manufactured. Note that FIGS. 5 to 11 show only part of the manufacturing process of semiconductor device 10, and the manufacturing method of semiconductor device 10 may include steps not shown in FIGS. 5 to 11.

[0075] (Action of this embodiment) The operation of this embodiment will be described with reference to FIGS. 3, 4, and 12 to 18. 12 shows a cross-sectional structure of the main cell region 11 of the semiconductor device 10X of Experimental Example 1. FIG. 13 shows a cross-sectional structure of the main cell region 11 of the semiconductor device 10Y of Experimental Example 2. The dashed graph GR in FIG. 4 is a graph showing the distribution of impurity concentrations on the first line L1 of the semiconductor devices 10X and 10Y. The semiconductor device 10 of this embodiment is treated as Experimental Example 3.

[0076] As shown in FIGS. 4, 12, and 13, the semiconductor devices 10X and 10Y are configured such that the column region 38 and the second and third regions 33B and 33C of the drift layer 33 are omitted compared to the semiconductor device 10. The semiconductor device 10Y has a narrower arrangement pitch of the trenches 35 compared to the semiconductor device 10X. The distance DY between adjacent trenches 35 in the x direction in the semiconductor device 10Y is equal to the distance D (see FIG. 3) between adjacent trenches 35 in the x direction in the semiconductor device 10 of this embodiment. That is, the distance DX between adjacent trenches 35 in the x direction in the semiconductor device 10X is greater than the distance D between adjacent trenches 35 in the x direction in the semiconductor device 10 of this embodiment. Because the area of ​​the main cell region 11 viewed from the z direction is unchanged in the semiconductor devices 10, 10X, and 10Y, the number of main cells in the semiconductor device 10X is smaller than the number of main cells in the semiconductor devices 10 and 10Y.

[0077] 4, the first region 33A of the drift layer 33 of the semiconductor devices 10X and 10Y has a first concentration peak CP1 at a depth HA, similar to the semiconductor device 10. In the first region 33A of the semiconductor devices 10X and 10Y, the degree of decrease in the impurity concentration as the depth increases from the first concentration peak CP1 is greater than in the first region 33A of the semiconductor device 10. At a depth HT shallower than the bottom 35a of the trench 35, the impurity concentration is, for example, 1×10 14 cm -3 That is, in the semiconductor devices 10X and 10Y, the impurity concentration at a depth HT shallower than the bottom 35a of the trench 35 is the same as that at a depth H6 in the semiconductor device 10. In the semiconductor devices 10X and 10Y, the impurity concentration in the region of the drift layer 33 at a depth equal to or less than the depth HT is, for example, 1×10 14 cm -3That is, the impurity concentration of the region between the first region 33A and the second region 33B in the semiconductor device 10 is higher than the impurity concentration of the region deeper than the depth HT in the drift layer 33 of the semiconductor devices 10X and 10Y. Also, the impurity concentration of the region between the first region 33A and the second region 33B in the semiconductor device 10 is higher than the impurity concentration of the region corresponding to the region between the first region 33A and the second region 33B in the semiconductor devices 10X and 10Y (the region deeper than the depth H3 and equal to or less than the depth H4 in the semiconductor devices 10X and 10Y). The difference between the impurity concentration of the region between the first region 33A and the second region 33B in the semiconductor device 10 and the impurity concentration of the region deeper than the depth H3 and equal to or less than the depth H4 in the semiconductor devices 10X and 10Y increases from the depth H3 to the depth H4.

[0078] Fig. 14 is a graph showing the relationship between the electric field strength of drift layer 33 and the position in the z direction of drift layer 33 in Experimental Examples 1 to 3. Fig. 14 shows the simulation results when a voltage of 1000 V is applied between the collector and emitter with the collector and emitter short-circuited.

[0079] 14, at a depth H4 corresponding to the bottom 35a of the trench 35, the electric field intensity in Experimental Example 3 is lower than the electric field intensity in Experimental Examples 1 and 2. That is, in Experimental Example 3, the column region 38 is provided at the position of the bottom 35a of the trench 35, so electric field concentration at the bottom 35a of the trench 35 is reduced. On the other hand, in Experimental Examples 1 and 2, the column region 38 is not formed at the position of the bottom 35a of the trench 35, so electric field concentration occurs at the bottom 35a of the trench 35.

[0080] FIG. 15 is a graph showing the relationship between the collector-emitter saturation voltage Vce(sat) and the loss Eoff when the semiconductor devices are turned off in Experimental Examples 1 to 3. In FIG. 15, it can be seen that in Experimental Example 3, the collector-emitter saturation voltage Vce(sat) at the same magnitude of loss Eoff at turn-off is lower than in Experimental Examples 1 and 2. In other words, it can be seen that in Experimental Example 3, the loss Eoff at the collector-emitter voltage Vce at turn-off is lower than in Experimental Examples 1 and 2. As a result, Experimental Example 3 can be designed to reduce both the loss Eoff and the collector-emitter saturation voltage Vce(sat) at turn-off more than Experimental Examples 1 and 2.

[0081] FIG. 16 is a graph showing the relationship between the collector-emitter saturation voltage Vce(sat) and the loss Eon when the semiconductor devices are turned on in Experimental Examples 1 to 3. In FIG. 16, in Experimental Example 3, the loss Eon at the same collector-emitter saturation voltage Vce(sat) is larger than that of Experimental Example 1 and smaller than that of Experimental Example 2. This is thought to be because Experimental Examples 2 and 3 have a larger number of main cells 11A than Experimental Example 1, which increases the Miller capacitance. On the other hand, in Experimental Example 3, the column region 38 is provided at the bottom 35a of the trench 35, which suppresses the increase in Miller capacitance. As a result, Experimental Example 3 has a smaller loss Eon at the same collector-emitter saturation voltage Vce(sat) than Experimental Example 2.

[0082] 17 is a graph showing the relationship between the collector-emitter saturation voltage Vce(sat) and the total loss (hereinafter referred to as loss Etotal) in Experimental Examples 1 to 3. The loss Etotal is the sum of the loss Eoff at turn-on and the loss Eon at turn-off.

[0083] 17, it can be seen that in Experimental Example 3, the collector-emitter saturation voltage Vce(sat) for the same magnitude of loss Etotal is lower than in Experimental Examples 1 and 2. In other words, it can be seen that in Experimental Example 3, the loss Etotal at the collector-emitter voltage Vce is lower than in Experimental Examples 1 and 2. As a result, Experimental Example 3 can be designed to reduce both the loss Etotal and the collector-emitter saturation voltage Vce(sat) more than in Experimental Examples 1 and 2.

[0084] 18 is a graph showing changes in collector current Ic, collector-emitter voltage Vce, and gate-emitter voltage Vge when the semiconductor devices are turned on in Experimental Examples 1 to 3. The dashed line graph shows Experimental Example 1, the dashed line graph shows Experimental Example 2, and the solid line graph shows Experimental Example 3.

[0085] 16, as the number of main cells 11A increases due to miniaturization, the Miller capacitance increases, and the loss Eon at turn-on increases. As a result, as shown in FIG. 18, the current rise rate at turn-on in Experimental Example 2 is slower than that in Experimental Example 1. On the other hand, in Experimental Example 3, the column region 38 is provided at the bottom 35a of the trench 35, which suppresses the increase in Miller capacitance. Therefore, the current rise rate at turn-on in Experimental Example 3 is slower than that in Experimental Example 1 but faster than that in Experimental Example 2.

[0086] (Effects of this embodiment) According to the semiconductor device 10 of this embodiment, the following effects can be obtained. (1) The semiconductor device 10 includes a drift layer 33 of a first conductivity type (n type), a base region 34 of a second conductivity type (p type) formed on the surface side of the drift layer 33, a trench 35 extending in the depth direction (z direction) so as to penetrate the base region 34 and reach the drift layer 33, an insulating film 41 formed on the inner surface of the trench 35, a gate trench 22A surrounded by the insulating film 41, and a column region 38 of the second conductivity type (p type) provided at a bottom 35a of the trench 35 in the drift layer 33. The drift layer 33 includes a first region 33A having a first concentration peak CP1 and a second region 33B provided at a position deeper than the trench 35 and corresponding to the column region 38, the second region 33B having a second concentration peak CP2 lower than the first concentration peak CP1.

[0087] According to this configuration, the column region 38 is provided at the bottom 35a of the trench 35, thereby reducing electric field concentration at the bottom 35a of the trench 35. Therefore, even if the number of main cells 11A increases due to miniaturization, an increase in mirror capacitance can be suppressed. Therefore, it is possible to achieve both a high breakdown voltage and a low on-resistance for the semiconductor device 10.

[0088] However, due to miniaturization, adjacent column regions 38 approach each other in the arrangement direction (x direction) of the trenches 35, which may result in junction between the column regions 38. When adjacent column regions 38 are junctioned, the current flowing from the collector electrode 27 to the emitter electrode 21 must pass through the column regions 38, making it difficult for the current to flow from the collector electrode 27 to the emitter electrode 21.

[0089] On the other hand, in the semiconductor device 10 of this embodiment, a second region 33B having a second concentration peak CP2 is provided in a position corresponding to the column region 38 in the drift layer 33. This makes the impurity concentration of the second region 33B relatively high, and therefore, when the column region 38 is formed, it is possible to suppress the spread of the column region 38 in the arrangement direction (x direction) of the trenches 35. This makes it possible to suppress the junction of adjacent column regions 38 in the arrangement direction of the trenches 35.

[0090] (2) A plurality of column regions 38 are provided corresponding to the plurality of trenches 35 . According to this configuration, the electric field concentration at the bottom 35a of each trench 35 can be reduced, and therefore the semiconductor device 10 can have a high breakdown voltage.

[0091] (3) The second region 33B of the drift layer 33 is provided between the column regions 38 adjacent to each other in the arrangement direction of the trenches 35 (x direction). This configuration makes it possible to prevent the column regions 38 from spreading in the arrangement direction (x direction) of the trenches 35 when the column regions 38 are formed. This makes it possible to prevent the column regions 38 adjacent to each other in the arrangement direction of the trenches 35 from joining together.

[0092] (4) The second region 33B of the drift layer 33 has a portion that is provided at the same position as the column region 38 in the depth direction of the trench 35 (z direction). According to this configuration, when forming the column regions 38, it is possible to further prevent the column regions 38 from spreading in the arrangement direction (x direction) of the trenches 35. This makes it possible to further prevent the column regions 38 adjacent to each other in the arrangement direction of the trenches 35 from joining together.

[0093] (5) The column region 38 is formed to cover the entire bottom 35a of the trench 35. According to this configuration, the electric field concentration at the bottom 35a of the trench 35 can be further reduced.

[0094] (6) The distance D between adjacent trenches 35 in the arrangement direction of the trenches 35 (x direction) is equal to or less than the width dimension Wt of the trenches 35. This configuration allows the number of main cells 11A to be increased for the same chip size. However, in this case, the distance between the trenches 35 tends to be short, and there is a risk that the column regions 38 may join together.

[0095] In this regard, in the present embodiment, as described above, the second region 33B can suppress the expansion of the column regions 38, and therefore, even if the distance between the trenches 35 is shortened as described above, it is possible to suppress the junction between the column regions 38. Therefore, it is possible to achieve integration of the main cells 11A while suppressing the junction between the column regions 38.

[0096] [Example of change] The above-described embodiments are merely examples of possible forms of the semiconductor device according to the present disclosure, and are not intended to limit the forms. The semiconductor device according to the present disclosure may take forms different from those exemplified in the above-described embodiments. Examples include forms in which part of the configuration of each of the above-described embodiments is replaced, modified, or omitted, or forms in which new configurations are added to the above-described embodiments. Furthermore, the following modified examples can be combined with each other as long as there is no technical contradiction. In the following modified examples, parts common to the above-described embodiments are assigned the same reference numerals as in the above-described embodiments, and their description will be omitted.

[0097] In the above embodiment, the semiconductor device 10 may have a main cell region 11 that constitutes an IGBT, and a diode cell region 14 that constitutes a freewheeling diode connected to the IGBT. Four configuration patterns of a semiconductor device 10 having such a diode cell region 14, a so-called RC (Reverse Conducting)-IGBT, will be described using Figures 19 to 22. Note that for the semiconductor device 10 of the modified examples in Figures 20 to 22, differences from the configuration of the semiconductor device 10 of the modified example in Figure 19 will be mainly described.

[0098] 19, a plurality of trenches 35 are provided across both the main cell region 11 and the diode cell region 14. In the illustrated example, in the main cell region 11, emitter trenches 21A and gate trenches 22A are provided alternately in the arrangement direction (x direction) of the trenches 35. In the illustrated example, an emitter trench 21A is provided at an end of the main cell region 11 adjacent to the diode cell region 14. In the diode cell region 14, an emitter trench 21A is provided, but a gate trench 22A is not provided.

[0099] In the illustrated example, a column region 38 is provided at the position of the bottom 35a of the trench 35 in both the main cell region 11 and the diode cell region 14. That is, the column region 38 is provided at the position of the bottom 35a of the trench 35 formed in the main cell region 11, and is also provided at the position of the bottom 35a of the trench 35 formed in the diode cell region 14.

[0100] A base region 34 is provided on the surface of the drift layer 33 in both the main cell region 11 and the diode cell region 14. As in the above embodiment, an emitter region 36 and a base contact region 37 are provided in the main cell region 11. On the other hand, the emitter region 36 and the base contact region 37 are not provided in the diode cell region 14. In other words, the emitter region 36 and the base contact region 37 are selectively provided in the base region 34 of the main cell region 11, not in the base region 34 of the diode cell region 14.

[0101] The collector layer 31 has a first collector region 31A of a first conductivity type (n-type) and a second collector region 31B of a second conductivity type (p-type). The first collector region 31A is provided in the diode cell region 14. The second collector region 31B is provided throughout the main cell region 11. The second collector region 31B is provided in a part of the diode cell region 14. Therefore, the diode cell region 14 has two regions: the first collector region 31A and the second collector region 31B.

[0102] Both the insulating film 41 and the intermediate insulating film 42 are formed so as to cover both the main cell region 11 and the diode cell region 14. The insulating film 41 and the intermediate insulating film 42 are provided with contact holes 43 that penetrate both the insulating film 41 and the intermediate insulating film 42. The contact holes 43 are provided at positions corresponding to the main cell region 11 and the diode cell region 14, respectively.

[0103] The emitter electrode 21 is formed to cover both the main cell region 11 and the diode cell region 14. A barrier metal layer 21e of the emitter electrode 21 is formed on the inner surfaces of the contact holes 43 in both the main cell region 11 and the diode cell region 14 and on the surface 42s of the intermediate insulating film 42. An electrode body 21c and a buried electrode portion 21b of the emitter electrode 21 are formed on this barrier metal layer 21e. The electrode body 21c is formed on the barrier metal layer 21e, which is formed on the surface 42s of the intermediate insulating film 42 that covers both the main cell region 11 and the diode cell region 14. The buried electrode portions 21b are individually buried in the multiple contact holes 43 in both the main cell region 11 and the diode cell region 14.

[0104] The semiconductor device 10 of the modified example shown in FIG. 20 is configured by omitting the intermediate insulating film 42 in the diode cell region 14 and the insulating film 41 in the portion of the substrate surface 30s other than the emitter trench 21A from the semiconductor device 10 shown in FIG. Accordingly, the contact hole 43 is omitted in the diode cell region 14, and therefore the embedded electrode portion 21b is not provided in the portion of the emitter electrode 21 covering the diode cell region 14. In other words, the embedded electrode portion 21b is selectively provided in the emitter electrode 21 corresponding to the main cell region 11, not in the diode cell region 14. The emitter electrode 21 also has a stepped portion 21d. The stepped portion 21d is provided at the end of the diode cell region 14 that forms the boundary with the main cell region 11. In the emitter electrode 21 corresponding to the diode cell region 14, a barrier metal layer 21e is provided on the substrate surface 30s, and an electrode main portion 21c is provided on the barrier metal layer 21e.

[0105] 21 has a configuration in which the column regions 38 provided at the positions of the bottoms 35a of the trenches 35 in the diode cell regions 14 are omitted from the semiconductor device 10 shown in FIG. 19. Accordingly, the first region 33A and the second region 33B are not provided in the drift layer 33 corresponding to the diode cell regions 14. In other words, the first region 33A and the second region 33B are selectively provided in the drift layer 33 corresponding to the main cell regions 11, rather than in the diode cell regions 14.

[0106] The semiconductor device 10 of the modified example shown in Fig. 22 has a configuration in which the intermediate insulating film 42 in the diode cell region 14 and the insulating film 41 in the portion of the substrate surface 30s other than the emitter trench 21A are omitted from the semiconductor device 10 shown in Fig. 21. The configuration of the emitter electrode 21 is the same as the configuration of the emitter electrode 21 in Fig. 20.

[0107] In the above embodiment, the semiconductor device 10 may be provided with a floating region 50 of the second conductivity type (p-type) surrounding the main cell region 11, as shown in FIG. 23 . The floating region 50 is in an electrically floating state. The floating region 50 is provided to be deeper than the trenches 35. The emitter trenches 21A provided at both ends of the main cell region 11 in the arrangement direction of the trenches 35 do not constitute the main cells 11A. The floating region 50 is provided to cover the bottoms 35a of the trenches 35 of these emitter trenches 21A. In the illustrated example, the floating region 50 is formed to cover a portion of the bottoms 35a of the trenches 35 of the emitter trenches 21A. Note that the floating region 50 may be formed to cover the entire bottoms 35a of the trenches 35 of the emitter trenches 21A.

[0108] In the above embodiment, the shape of the column region 38 cut along a plane along the depth direction of the trench 35 and the arrangement direction of the trenches 35, and in this embodiment, the shape of the column region 38 cut along a plane along the z direction and the x direction, can be changed as desired. In one example, as shown in Fig. 24, the column region 38 may have a protruding region 38b that widens in the x direction as it moves away from the bottom 35a of the trench 35 toward the back surface 30r of the substrate in the z direction.

[0109] In the above embodiment, the column region 38 is provided at a position spaced apart from the base region 34 in the z direction, but this is not limited to this. The formation range of the column region 38 can be changed as desired. For example, the column region 38 may be formed so as to be connected to the base region 34. More specifically, the column region 38 includes a first column region provided at the bottom 35a of the trench 35 in the drift layer 33, and a second column region extending from the first column region along the side surface of the trench 35 toward the base region 34. The second column region is a connection region connecting the first column region and the base region 34. The second column region extends, for example, along the depth direction of the trench 35 (the z direction in the above embodiment). Two second column regions formed between adjacent trenches 35 in the arrangement direction of the trenches 35 are spaced apart from each other in the arrangement direction of the trenches 35. In other words, the drift layer 33 is formed between the two second column regions in the arrangement direction of the trenches 35.

[0110] In the above embodiment, the column region 38 is formed to cover the entire bottom 35a of the trench 35, but this is not limiting. In one example, the column region 38 may be formed to cover only a portion of the bottom 35a of the trench 35.

[0111] In the above embodiment, the distance D between adjacent trenches 35 in the arrangement direction of the trenches 35 is equal to or less than the width dimension Wt of the trench 35, but this is not limited to this. The distance D may be greater than the width dimension Wt.

[0112] In the above embodiment, the column regions 38 are formed corresponding to all trenches 35, but this is not limited to this. For example, the column regions 38 may not be provided at the bottoms 35a of trenches 35 that do not constitute main cells 11A in the main cell region 11. Also, for example, the column regions 38 may be selectively provided at the bottoms 35a of multiple trenches 35. In other words, even in trenches 35 that constitute main cells 11A, the column regions 38 may not be provided at the bottoms 35a of the trenches 35.

[0113] In the above embodiment, the gate trenches 22A and the emitter trenches 21A in the main cell region 11 are alternately arranged in the arrangement direction of the trenches 35 (the x direction in the above embodiment), but this is not limited to this. For example, the gate trenches 22A and the emitter trenches 21A may be arranged in the arrangement direction of the trenches 35 as follows: gate trench 22A, emitter trench 21A, emitter trench 21A, emitter trench 21A, and gate trench 22A.

[0114] In the above embodiment, the semiconductor device 10 may be a planar gate IGBT instead of a trench gate IGBT. In the above embodiment, the semiconductor device 10 is embodied as an IGBT, but the present invention is not limited to this. The semiconductor device 10 may be a trench-type SiCMOSFET (metal-oxide-semiconductor field-effect transistor) or a SiMOSFET. In this case, the source electrode of the MOSFET corresponds to the "drive electrode."

[0115] The term "on" used in this disclosure includes the meanings of "on" and "above," unless the context clearly indicates otherwise. Therefore, the expression "A is formed on B" is intended to mean that, in this embodiment, A may be in contact with B and disposed directly on B, but as a variant, A may be disposed above B without contacting B. In other words, the term "on" does not exclude a structure in which another member is formed between A and B.

[0116] The z-direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure are not limited to the "up" and "down" of the z-direction described herein being "up" and "down" of the vertical direction. For example, the x-direction may be the vertical direction, or the y-direction may be the vertical direction.

[0117] [Note] The technical ideas that can be understood from the above-described embodiment and each of the above-described modified examples are described below. Note that the reference numerals of the components of the embodiment corresponding to the components described in each appendix are shown in parentheses. The reference numerals are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.

[0118] (Appendix 1) a drift layer (33) of a first conductivity type; a body region (34) of a second conductivity type formed on the surface (30s) side of the drift layer (33); a trench (35) extending in a depth direction (z direction) so as to penetrate the body region (34) and reach the drift layer (33); an insulating film (41) formed on the inner surface of the trench (35); a gate electrode (21A) surrounded by the insulating film (41); a column region (38) of a second conductivity type provided at a bottom (35a) of the trench (35) in the drift layer (33), The drift layer (33) a first region (33A) having a first concentration peak (CP1); a second region (33B) that is provided at a position deeper than the trench (35) and corresponding to the column region (38), and that has a second concentration peak (CP2) that is lower than the first concentration peak (CP1); A semiconductor device (10).

[0119] (Appendix 2) The trenches (35) are provided in a plurality of locations spaced apart from one another, The column regions (38) are provided in plurality in correspondence with the plurality of trenches (35). 2. The semiconductor device according to claim 1.

[0120] (Appendix 3) the first region (33A) is provided between the trenches (35) adjacent to each other in the arrangement direction (x direction) of the trenches (35), The second region (33B) is provided between the column regions (38) adjacent to each other in the arrangement direction (x direction) of the trenches (35). 3. The semiconductor device according to claim 2.

[0121] (Appendix 4) The first region (33A) is provided in the drift layer (33) near an interface (39A) with the body region (34). 4. The semiconductor device according to claim 3.

[0122] (Appendix 5) The second region (33B) has a portion provided at the same position as the column region (38) in the depth direction (z direction) of the trench (35), as a position corresponding to the column region (38). 5. The semiconductor device according to claim 3 or 4.

[0123] (Appendix 6) The second region (33B) has a portion provided at a position corresponding to the column region (38) and shifted from the column region (38) in the depth direction (z direction) of the trench (35). 6. The semiconductor device according to any one of claims 3 to 5.

[0124] (Appendix 7) The distance (D) between adjacent trenches (35) in the arrangement direction (x direction) of the trenches (35) is equal to or less than the width dimension (Wt) of the trenches (35). 7. The semiconductor device according to any one of claims 2 to 6.

[0125] (Appendix 8) The column region (38) is formed so as to cover the entire bottom (35a) of the trench (35). 8. The semiconductor device according to any one of claims 1 to 7.

[0126] (Appendix 9) The column region (38) is provided at a position spaced apart from the body region (34) in the thickness direction (z direction) of the drift layer (33). 9. The semiconductor device according to any one of appendices 1 to 8.

[0127] (Appendix 10) The column region (38) is in an electrically floating state. 10. The semiconductor device according to claim 9.

[0128] (Appendix 11) The column region (38) is connected to the body region (34). 9. The semiconductor device according to any one of appendices 1 to 8.

[0129] (Appendix 12) The impurity concentration of the column region (38) is lower than the impurity concentration of the body region (34). 12. The semiconductor device according to any one of claims 1 to 11.

[0130] (Appendix 13) The maximum value of the impurity concentration in the column region (38) is higher than the second concentration peak (CP2). 13. The semiconductor device according to any one of claims 1 to 12.

[0131] (Appendix 14) The maximum value of the impurity concentration in the column region (38) is higher than the first concentration peak (CP1). 14. The semiconductor device according to any one of claims 1 to 13.

[0132] (Appendix 15) the drift layer (33) has a third region (33C) provided at a position deeper than the second region (33B), The second concentration peak (CP2) is higher than the impurity concentration of the third region (33C). 15. The semiconductor device according to any one of claims 1 to 14.

[0133] (Appendix 16) The semiconductor device (10) includes: The device has a main cell region (11) that constitutes an IGBT, and a diode cell region (14) that constitutes a free wheel diode connected to the IGBT, The trench (35) is provided in both the main cell region (11) and the diode cell region (14), The column region (38) is provided at the position of the bottom (35a) of the trench (35) formed in the main cell region (11), and is also provided at the position of the bottom (35a) of the trench (35) formed in the diode cell region (14). 16. The semiconductor device according to any one of claims 1 to 15.

[0134] (Appendix 17) The semiconductor device (10) includes: The device has a main cell region (11) that constitutes an IGBT, and a diode cell region (14) that constitutes a free wheel diode connected to the IGBT, The trench (35) is provided in both the main cell region (11) and the diode cell region (14), The column region (38) is selectively provided at the bottom (35a) of the trench (35) formed in the main cell region (11), not at the bottom (35a) of the trench (35) formed in the diode cell region (14). 16. The semiconductor device according to any one of claims 1 to 15. [Explanation of symbols]

[0135] 10...Semiconductor device 11...Main cell area 14...Diode cell area 22...Gate electrode 30s...Substrate surface (drift layer surface) 33...Drift layer 33A…First area 33B…Second area 33C…Third area 34...Base region (body region) 35...Trench 35a...Bottom 38...Column area 41...insulating film 39A...Interface between the drift layer and the base region D: distance between trenches Wt: Trench width

Claims

1. a drift layer of a first conductivity type; a body region of a second conductivity type formed on the surface side of the drift layer; a trench extending in a depth direction so as to penetrate the body region and reach the drift layer; an insulating film formed on the inner surface of the trench; a gate electrode surrounded by the insulating film; a column region of a second conductivity type provided at a bottom of the trench in the drift layer, The drift layer is a first region having a first concentration peak; a second region provided at a position deeper than the trench and corresponding to the column region, the second region having a second concentration peak lower than the first concentration peak; The trenches are provided in a plurality of states spaced apart from each other, a plurality of the column regions are provided corresponding to the plurality of trenches, the first region is provided between the trenches adjacent to each other in an arrangement direction of the trenches, the second region is provided between the column regions adjacent to each other in the arrangement direction of the trenches, the second region has a portion provided at a position corresponding to the column region and shifted from the column region in a depth direction of the trench; Semiconductor device.

2. A drift layer of a first conductivity type; a body region of a second conductivity type formed on the surface side of the drift layer; a trench extending in a depth direction so as to penetrate the body region and reach the drift layer; an insulating film formed on the inner surface of the trench; a gate electrode surrounded by the insulating film; a column region of a second conductivity type provided at a bottom of the trench in the drift layer, The drift layer is a first region having a first concentration peak; a second region provided at a position deeper than the trench and corresponding to the column region, the second region having a second concentration peak lower than the first concentration peak; The trenches are provided in a plurality of states spaced apart from each other, a plurality of the column regions are provided corresponding to the plurality of trenches, a distance between adjacent trenches in an arrangement direction of the trenches is equal to or less than a width dimension of the trenches; Semiconductor device.

3. A drift layer of a first conductivity type; a body region of a second conductivity type formed on the surface side of the drift layer; a trench extending in a depth direction so as to penetrate the body region and reach the drift layer; an insulating film formed on the inner surface of the trench; a gate electrode surrounded by the insulating film; a column region of a second conductivity type provided at a bottom of the trench in the drift layer, The drift layer is a first region having a first concentration peak; a second region provided at a position deeper than the trench and corresponding to the column region, the second region having a second concentration peak lower than the first concentration peak; the column region is provided at a position spaced apart from the body region in a thickness direction of the drift layer, the column region is in an electrically floating state; Semiconductor device.

4. The trenches are provided in a plurality of states spaced apart from each other, A plurality of the column regions are provided corresponding to the plurality of trenches. The semiconductor device according to claim 3 .

5. the first region is provided between the trenches adjacent to each other in an arrangement direction of the trenches, The second region is provided between the column regions adjacent to each other in the arrangement direction of the trenches.

4. The semiconductor device according to claim 2.

6. The first region is provided in the drift layer near the interface with the body region. The semiconductor device according to claim 1 or 5.

7. The second region has a portion that is provided at the same position as the column region in the depth direction of the trench as a position corresponding to the column region.

7. The semiconductor device according to claim 1, 5, or 6.

8. The second region has a portion provided at a position corresponding to the column region and shifted from the column region in the depth direction of the trench.

8. The semiconductor device according to claim 1, or any one of claims 5 to 7.

9. The distance between adjacent trenches in the arrangement direction of the trenches is equal to or less than the width dimension of the trenches.

9. The semiconductor device according to claim 1, or any one of claims 4 to 8.

10. The column region is formed to cover the entire bottom of the trench. The semiconductor device according to any one of claims 1 to 9.

11. The column region is provided at a position spaced apart from the body region in the thickness direction of the drift layer. The semiconductor device according to any one of claims 1, 2, and 4 to 10.

12. The column region is in an electrically floating state. The semiconductor device according to claim 11.

13. The column region is connected to the body region. The semiconductor device according to any one of claims 1 to 10.

14. The impurity concentration of the column region is lower than the impurity concentration of the body region. The semiconductor device according to any one of claims 1 to 13.

15. The maximum value of the impurity concentration in the column region is higher than the second concentration peak. The semiconductor device according to any one of claims 1 to 14.

16. The maximum value of the impurity concentration in the column region is higher than the first concentration peak. The semiconductor device according to any one of claims 1 to 15.

17. the drift layer has a third region provided at a position deeper than the second region, The second concentration peak is higher than the impurity concentration of the third region. The semiconductor device according to any one of claims 1 to 16.

18. The semiconductor device includes: a main cell region constituting an IGBT; and a diode cell region constituting a free wheel diode connected to the IGBT; the trench is provided in both the main cell region and the diode cell region, The column region is provided at the bottom of the trench formed in the main cell region, and is also provided at the bottom of the trench formed in the diode cell region. The semiconductor device according to any one of claims 1 to 17.

19. The semiconductor device includes: a main cell region constituting an IGBT; and a diode cell region constituting a free wheel diode connected to the IGBT; the trench is provided in both the main cell region and the diode cell region, The column region is selectively provided at the bottom of the trench formed in the main cell region, not at the bottom of the trench formed in the diode cell region. The semiconductor device according to any one of claims 1 to 17.

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