Configurable leaded package

Abstract

The semiconductor package includes a base insulative layer (102), a semiconductor die (106) attached to a portion of the base insulative layer, and a first continuous lead (120) electrically connected to the semiconductor die. The first continuous lead includes a first lateral extension (116) on a first surface of the base insulative layer, a second lateral extension (114) on a second surface of the base insulative layer, and a connection portion (118) between the first lateral extension and the second lateral extension. The connection portion passes through the base insulative layer.

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE This disclosure relates generally to semiconductor packages, and more particularly to leaded packages. [Background technology]

[0002] Semiconductor devices are packaged using metal, plastic, or ceramic packages to protect the semiconductor device from shock, corrosion, and moisture, and also provide a means of connection between the semiconductor device inside the package and other electrical components outside the package.

[0003] The package contains the metal connections that electrically connect the semiconductor device to the outside world. These connections, known as leads, can be soldered to a circuit board or other external component. The package molded around the semiconductor die, e.g., a plastic package, additionally provides a mechanical means for holding the leads in place.

[0004] The semiconductor die in the package is attached to the die attach pad of the lead frame and electrically connected to the leads. A given package is limited by its lead frame configuration. An easily configurable lead frame design is desirable. Wire bonding has been the interconnect process of choice. However, wire bonding is reaching its limits due to emerging needs for size, quality, manufacturability, and cost. An alternative approach is needed. Summary of the Invention

[0005] A first aspect provides a semiconductor package. The semiconductor package includes a base insulative layer, a semiconductor die attached to a portion of the base insulative layer, and a first continuous lead electrically connected to the semiconductor die. The first continuous lead includes a first lateral extension on a first surface of the base insulative layer, a second lateral extension on a second surface of the base insulative layer, and a connecting portion between the first lateral extension and the second lateral extension. The connecting portion penetrates the base insulative layer.

[0006] A second aspect provides a semiconductor package. The semiconductor package includes a base insulating layer, leads having a first lateral extension on a first surface of the base insulating layer and a second lateral extension on a second surface of the base insulating layer, and a connection portion between the first lateral extension and the second lateral extension. The connection portion penetrates the base insulating layer. A semiconductor die is attached to a portion of the first lateral extension and electrically connected to the leads.

[0007] A third aspect provides a semiconductor package. The semiconductor package includes a base insulative layer, a semiconductor die attached to a portion of the base insulative layer, and a first lead electrically connected to the semiconductor die. The first lead includes a first lateral extension on a first surface of the base insulative layer, a second lateral extension on a second surface of the base insulative layer, and a connection portion between the first and second lateral extensions. An end of the second lateral extension includes a recess.

[0008] A fourth aspect provides a method for manufacturing a semiconductor package. First and second ends of a conductive pin having a first curvature and a second curvature are inserted through a base insulating material to form a third curvature and a fourth curvature in the conductive pin. A portion of the conductive pin between the first curvature and the second curvature is then removed. A semiconductor die is then attached to the base insulating material.

[0009] A fifth aspect provides a semiconductor package. The semiconductor package includes a conductive pin having a first curvature and a second curvature. The semiconductor package further includes a base insulating material through which the conductive pin extends. The first curvature is on a first side of the base insulating material and the second curvature is on a second, opposite side of the base insulating material. A semiconductor die is electrically connected to the conductive pin.

[0010] Other aspects and examples are provided in the figures and detailed description that follow.

[0011] For a more complete understanding of the present disclosure and its advantages, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: [Brief explanation of the drawings]

[0012] [Figure 1A] 1A-1C illustrate various views of a configurable leaded package, according to various examples. [Figure 1B] 1A-1C illustrate various views of a configurable leaded package, according to various examples. [Figure 1C] 1A-1C illustrate various views of a configurable leaded package, according to various examples. [Figure 1D] 1A-1C illustrate various views of a configurable leaded package, according to various examples. [Figure 1E] 1A-1C illustrate various views of a configurable leaded package, according to various examples. [Figure 1F] 1A-1C illustrate various views of a configurable leaded package, according to various examples. [Figure 1G] 1A-1C illustrate various views of a configurable leaded package, according to various examples. [Figure 1H] 1A-1C illustrate various views of a configurable leaded package, according to various examples. [Figure 1I] 1A-1C illustrate various views of a configurable leaded package, according to various examples. [Figure 1J] 1A-1C illustrate various views of a configurable leaded package, according to various examples. [Figure 1K]1A-1C illustrate various views of a configurable leaded package, according to various examples. [Figure 1L] 1A-1C illustrate various views of a configurable leaded package, according to various examples. [Figure 1M] 1A-1C illustrate various views of a configurable leaded package, according to various examples. [Figure 1N] 1A-1C illustrate various views of a configurable leaded package, according to various examples. [Figure 1O] 1A-1C illustrate various views of a configurable leaded package, according to various examples. [Figure 1P] 1A-1C illustrate various views of a configurable leaded package, according to various examples. [Figure 1Q] 1A-1C illustrate various views of a configurable leaded package, according to various examples. [Figure 1R] 1A-1C illustrate various views of a configurable leaded package, according to various examples. [Figure 1S] 1A-1C illustrate various views of a configurable leaded package, according to various examples. [Figure 1T] 1A-1C illustrate various views of a configurable leaded package, according to various examples. [Figure 1U] 1A-1C illustrate various views of a configurable leaded package, according to various examples. [Figure 1V] 1A-1C illustrate various views of a configurable leaded package, according to various examples. [Figure 1W] 1A-1C illustrate various views of a configurable leaded package, according to various examples.

[0013] [Figure 2A] 1A-1C illustrate various views of a base insulative layer and continuous lead structure in a configurable leaded package, according to various examples. [Figure 2B] 1A-1C illustrate various views of a base insulative layer and continuous lead structure in a configurable leaded package, according to various examples. [Figure 2C]1A-1C illustrate various views of a base insulative layer and continuous lead structure in a configurable leaded package, according to various examples. [Figure 2D] 1A-1C illustrate various views of a base insulative layer and continuous lead structure in a configurable leaded package, according to various examples. [Figure 2E] 1A-1C illustrate various views of a base insulative layer and continuous lead structure in a configurable leaded package, according to various examples. [Figure 2F] 1A-1C illustrate various views of a base insulative layer and continuous lead structure in a configurable leaded package, according to various examples. [Figure 2G] 1A-1C illustrate various views of a base insulative layer and continuous lead structure in a configurable leaded package, according to various examples. [Figure 2H] 1A-1C illustrate various views of a base insulative layer and continuous lead structure in a configurable leaded package, according to various examples.

[0014] [Figure 3A] 1 illustrates a process for creating a continuous lead from a wire, according to various examples. [Figure 3B] 1 illustrates a process for creating a continuous lead from a wire, according to various examples. [Figure 3C] 1 illustrates a process for creating a continuous lead from a wire, according to various examples. [Figure 3D] 1 illustrates a process for creating a continuous lead from a wire, according to various examples.

[0015] [Figure 3E] 1A-1C are various perspective views of stapling forceps, according to various examples. [Figure 3F] 1A-1C are various perspective views of stapling forceps, according to various examples. [Figure 3G] 1A-1C are various perspective views of stapling forceps, according to various examples. [Figure 3H] 1A-1C are various perspective views of stapling forceps, according to various examples.

[0016] [Figure 4A] A base insulating layer with a matrix of conductive pins 304 is shown inserted and formed as a lead frame or panel. [Figure 4B] 1 illustrates a base insulative layer with reinforcing pins, according to various examples.

[0017] [Figure 5A] 1B illustrates a process for making the configurable leaded package of FIG. 1A. [Figure 5B] 1B illustrates a process for making the configurable leaded package of FIG. 1A. [Figure 5C] 1B illustrates a process for making the configurable leaded package of FIG. 1A. [Figure 5D] 1B illustrates a process for making the configurable leaded package of FIG. 1A. [Figure 5E] 1B illustrates a process for making the configurable leaded package of FIG. 1A. [Figure 5F] 1B illustrates a process for making the configurable leaded package of FIG. 1A. [Figure 5G] 1B illustrates a process for making the configurable leaded package of FIG. 1A. [Figure 5H] 1B illustrates a process for making the configurable leaded package of FIG. 1A.

[0018] [Figure 6A] 1 illustrates another view of a block molded strip with several devices, according to an example.

[0019] [Figure 6B] 6B shows an enlarged perspective view of one of the devices of FIG. 6A.

[0020] [Figure 6C] FIG. 6C is a side view of the device of FIG. 6B.

[0021] [Figure 6D]6B shows various views of the device of FIG. 6A after a portion of the continuous lead has been removed. [Figure 6E] 6B shows various views of the device of FIG. 6A after a portion of the continuous lead has been removed. [Figure 6F] 6B shows various views of the device of FIG. 6A after a portion of the continuous lead has been removed.

[0022] [Figure 7A] 1 illustrates the various process steps involved in creating a configurable leaded package with J-type leads for one example. [Figure 7B] 1 illustrates the various process steps involved in creating a configurable leaded package with J-type leads for one example. [Figure 7C] 1 illustrates the various process steps involved in creating a configurable leaded package with J-type leads for one example. [Figure 7D] 1 illustrates the various process steps involved in creating a configurable leaded package with J-type leads for one example. [Figure 7E] 1 illustrates the various process steps involved in creating a configurable leaded package with J-type leads for one example. [Figure 7F] 1 illustrates the various process steps involved in creating a configurable leaded package with J-type leads for one example. [Figure 7G] 1 illustrates the various process steps involved in creating a configurable leaded package with J-type leads for one example.

[0023] [Figure 8A] 1A-1C illustrate various process steps involved in producing wet flanks in a package similar to that of FIG. 1R. [Figure 8B] 1A-1C illustrate various process steps involved in producing wet flanks in a package similar to that of FIG. 1R. [Figure 8C]1A-1C illustrate various process steps involved in producing wet flanks in a package similar to that of FIG. 1R. [Figure 8D] 1A-1C illustrate various process steps involved in producing wet flanks in a package similar to that of FIG. 1R.

[0024] [Figure 9A] 1 shows various examples of configurable leaded packages with clamps. [Figure 9B] 1 shows various examples of configurable leaded packages with clamps. [Figure 9C] 1 shows various examples of configurable leaded packages with clamps. [Figure 9D] 1 shows various examples of configurable leaded packages with clamps.

[0025] [Figure 10A] 1A-1C illustrate various examples of configurable leaded packages in chip-on-lead configurations. [Figure 10B] 1A-1C illustrate various examples of configurable leaded packages in chip-on-lead configurations. [Figure 10C] 1A-1C illustrate various examples of configurable leaded packages in chip-on-lead configurations. [Figure 10D] 1A-1C illustrate various examples of configurable leaded packages in chip-on-lead configurations.

[0026] [Figure 11A] 1A-1C illustrate various examples of configurable leaded packages, including flip-chip configurations. [Figure 11B] 1A-1C illustrate various examples of configurable leaded packages, including flip-chip configurations. [Figure 11C] 1A-1C illustrate various examples of configurable leaded packages, including flip-chip configurations. [Figure 11D] 1A-1C illustrate various examples of configurable leaded packages, including flip-chip configurations.

[0027] [Figure 12A] 1A-1C illustrate various examples of configurable leaded packages with multiple dies. [Figure 12B] 1A-1C illustrate various examples of configurable leaded packages with multiple dies. [Figure 12C] 1A-1C illustrate various examples of configurable leaded packages with multiple dies. [Figure 12D] 1A-1C illustrate various examples of configurable leaded packages with multiple dies.

[0028] [Figure 13A] 1A-1C illustrate various perspective views of a configurable leaded package mounted on a PCB. [Figure 13B] 1A-1C illustrate various perspective views of a configurable leaded package mounted on a PCB. [Figure 13C] 1A-1C illustrate various perspective views of a configurable leaded package mounted on a PCB.

[0029] [Figure 14A] 1A-1C illustrate various views of a printed configurable leaded package, according to various examples. [Figure 14B] 1A-1C illustrate various views of a printed configurable leaded package, according to various examples. [Figure 14C] 1A-1C illustrate various views of a printed configurable leaded package, according to various examples. [Figure 14D] 1A-1C illustrate various views of a printed configurable leaded package, according to various examples. [Figure 14E] 1A-1C illustrate various views of a printed configurable leaded package, according to various examples. [Figure 14F] 1A-1C illustrate various views of a printed configurable leaded package, according to various examples. [Figure 14G] 1A-1C illustrate various views of a printed configurable leaded package, according to various examples. [Figure 14H]1A-1C illustrate various views of a printed configurable leaded package, according to various examples. [Figure 14I] 1A-1C illustrate various views of a printed configurable leaded package, according to various examples. [Figure 14J] 1A-1C illustrate various views of a printed configurable leaded package, according to various examples. [Figure 14K] 1A-1C illustrate various views of a printed configurable leaded package, according to various examples. [Figure 14L] 1A-1C illustrate various views of a printed configurable leaded package, according to various examples. [Figure 14M] 1A-1C illustrate various views of a printed configurable leaded package, according to various examples. [Figure 14N] 1A-1C illustrate various views of a printed configurable leaded package, according to various examples. [Figure 14O] 1A-1C illustrate various views of a printed configurable leaded package, according to various examples.

[0030] [Figure 15A] A cross-section of the printed CLP is shown, along with the dimensions of each component within the package. [Figure 15B] A cross-section of the printed CLP is shown, along with the dimensions of each component within the package.

[0031] [Figure 15C] 1A-1C illustrate various views of a printed configurable leaded package, according to various examples. [Figure 15D] 1A-1C illustrate various views of a printed configurable leaded package, according to various examples. [Figure 15E] 1A-1C illustrate various views of a printed configurable leaded package, according to various examples. [Figure 15F] 1A-1C illustrate various views of a printed configurable leaded package, according to various examples. [Figure 15G]1A-1C illustrate various views of a printed configurable leaded package, according to various examples. [Figure 15H] 1A-1C illustrate various views of a printed configurable leaded package, according to various examples. [Figure 15I] 1A-1C illustrate various views of a printed configurable leaded package, according to various examples. [Figure 15J] 1A-1C illustrate various views of a printed configurable leaded package, according to various examples. [Figure 15K] 1A-1C illustrate various views of a printed configurable leaded package, according to various examples.

[0032] [Figure 15La] 10A-10C illustrate various views of a printed configurable leaded package with clamps according to an example. [Figure 15Lb] 10A-10C illustrate various views of a printed configurable leaded package with clamps according to an example. [Figure 15Lc] 10A-10C illustrate various views of a printed configurable leaded package with clamps according to an example. [Figure 15Ld] 10A-10C illustrate various views of a printed configurable leaded package with clamps according to an example.

[0033] [Figure 15Ma] 1A-1C illustrate various views of a printed configurable leaded package in a chip-on-lead configuration according to an example. [Figure 15Mb] 1A-1C illustrate various views of a printed configurable leaded package in a chip-on-lead configuration according to an example. [Figure 15Mc] 1A-1C illustrate various views of a printed configurable leaded package in a chip-on-lead configuration according to an example. [Figure 15Md] 1A-1C illustrate various views of a printed configurable leaded package in a chip-on-lead configuration according to an example.

[0034] [Figure 15Na] 1A-1C illustrate various views of a printed configurable leaded package with multiple dies according to an example. [Figure 15Nb] 1A-1C illustrate various views of a printed configurable leaded package with multiple dies according to an example. [Figure 15Nc] 1A-1C illustrate various views of a printed configurable leaded package with multiple dies according to an example. [Figure 15Nd] 1A-1C illustrate various views of a printed configurable leaded package with multiple dies according to an example.

[0035] [Figure 16A] 1 illustrates a process for constructing a pin interconnect package, according to various examples. [Figure 16B] 1 illustrates a process for constructing a pin interconnect package, according to various examples. [Figure 16C] 1 illustrates a process for constructing a pin interconnect package, according to various examples. [Figure 16D] 1 illustrates a process for constructing a pin interconnect package, according to various examples.

[0036] [Figure 17A] 1 illustrates various examples of pin interconnect packages, according to various examples. [Figure 17B] 1 illustrates various examples of pin interconnect packages, according to various examples. [Figure 17C] 1 illustrates various examples of pin interconnect packages, according to various examples. [Figure 17D] 1 illustrates various examples of pin interconnect packages, according to various examples. [Figure 17E] 1 illustrates various examples of pin interconnect packages, according to various examples. [Figure 17F] 1 illustrates various examples of pin interconnect packages, according to various examples. [Figure 17G] 1 illustrates various examples of pin interconnect packages, according to various examples.

[0037] [Figure 18A] 1A-1C illustrate various perspective views of a through-hole version of a single in-line pin interconnect package, according to various examples. [Figure 18B] 1A-1C illustrate various perspective views of a through-hole version of a single in-line pin interconnect package, according to various examples. [Figure 18C] 1A-1C illustrate various perspective views of a through-hole version of a single in-line pin interconnect package, according to various examples. [Figure 18D] 1A-1C illustrate various perspective views of a through-hole version of a single in-line pin interconnect package, according to various examples. [Figure 18E] 1A-1C illustrate various perspective views of a through-hole version of a single in-line pin interconnect package, according to various examples. [Figure 18F] 1A-1C illustrate various perspective views of a through-hole version of a single in-line pin interconnect package, according to various examples.

[0038] [Figure 19A] 1A-1C illustrate various perspective views of a molded pin interconnect package, according to various examples. [Figure 19B] 1A-1C illustrate various perspective views of a molded pin interconnect package, according to various examples. [Figure 19C] 1A-1C illustrate various perspective views of a molded pin interconnect package, according to various examples. [Figure 19D] 1A-1C illustrate various perspective views of a molded pin interconnect package, according to various examples.

[0039] [Figure 20] 1 illustrates a system or tool for manufacturing a configurable lead package, according to various examples.

[0040] [Figure 21] 21 shows details of the wire feeder of the system of FIG. 20.

[0041] [Figure 22A] 21 shows details of a forming unit of the system of FIG. 20. [Figure 22B] 21 shows details of a forming unit of the system of FIG. 20.

[0042] [Figure 22C] 21 shows details of the pinning unit of the system of FIG. 20.

[0043] [Figure 23] 1 illustrates a block diagram of a process flow for creating a configurable leaded package, according to various examples. DETAILED DESCRIPTION OF THE INVENTION

[0044] Leaded packages are preferred for industrial and high-reliability applications. Through-hole, gull-wing, and J-lead are common such package configurations. These packages come in configurations such as plastic dual-in-line packages (PDIPs), small-outline integrated circuit (SOIC) packages, quad flat packages (QFPs), thin-shrink small-outline packages (TSSOPs), micro small-outline packages (MSOPs), and small-outline transistor (SOT) packages, each of which is standardized for body size, pin count, pin pitch, lead shape, and leads. Due to their availability and board-level reliability (BLR), these packages are targeted for applications requiring long life and high reliability.

[0045] On the other hand, packages such as quad flat no-lead (QFN) packages, wafer-level chip-scale packages (WCSPs), and ball grid array (BGA) packages are becoming popular in consumer and portable electronics. These newer generation packages offer smaller body sizes and a wide range of flexibility regarding body size, pin count, and pin pitch options. In addition, these packages are easier to manufacture because they use block molding or wafer-level packaging, which significantly lower the cycle time and tooling costs to create new variations. While the marginal revenue tooling costs for new gull-wing packages are well over $500,000 and take months to manufacture, QFN variations are less than $50,000 and can be created in weeks.

[0046] Despite all these benefits, these leadless packages fall short of stringent industrial reliability and usability requirements. While SOIC packages are available in 1.27mm pin pitches and 1.75mm overall thicknesses, TSSOPs are standardized at 0.65mm pin pitches and 1.2mm maximum thicknesses. Both are typically manufactured for discrete pin counts, such as 8, 14, 16, 20, and 24 pins. Once tooled, a significant portion of the equipment and tooling is created for and locked into a specific package, and therefore is not shared between pin / package types. While it is sometimes desirable to optimize leaded packages, such as 1mm and 0.55mm pin pitches, in practice, creating such "odd size" solutions is impossible due to manufacturing complexities, including tooling changes, limitations, and costs. Unfortunately, leadless or BGA packages do not always fit end-use needs.

[0047] To address the limitations of currently available leaded packages, a new package design and manufacturing process is disclosed herein. This new package design offers the manufacturing flexibility of a leadless package with the reliability of a leaded package. Unlike currently available lead frames or package substrates, the lead frame is proposed to be custom constructed in a unique and novel manner. At a high level, the process of creating the new configurable leaded package begins with a blank insulating substrate. Onto this, pins, leads, or continuous leads are inserted / stapled / clamped at desired locations. These pins can be flexibly configured to create the desired footprint. If the blank insulating substrate or blank insulating layer is a flexible base film, it can be kept stretched with a carrier or used in a reel-to-reel configuration. By placing the pins underneath the package, full entitlement of lead frame density is achieved, even with leaded packages. Due to the inherent configurability, multiple package sizes, pin counts, and pin pitches can be easily created. Configurable leaded packages eliminate the need to manage multiple lead frame variations or dedicated package production lines for specific pin / package types.

[0048] On the top side of the pinned blank insulating layer, the die is attached and wire bonded to the leads before forming. The pins on the bottom side can then be singulated if necessary, thus creating J-leads, C-leads, or gull-wing leads from the bottom side of the package. Such a design makes full use of the strip, allowing for varying pin sizes, pitches, and package sizes, along with block molding with no space loss between packages for the pins. Using this process, the largest possible units / strips are achieved, along with leaded package structures.

[0049] In various examples, the base insulative layer or base insulative material (hereinafter used interchangeably) includes an insulating layer having a portion exposed from a semiconductor package that provides mechanical support to a semiconductor die within the semiconductor package. The base insulative layer includes a flexible or semi-rigid layer having a flexibility or tensile strength of 40-50 N / cm. Other material properties and characteristics of the base insulative layer include a 180-degree peel adhesion of approximately 2.4 N / cm and an elongation at break of approximately 37%. Note that the base insulative layer does not include any conductors therein other than the connecting portions of the continuous leads, leads, or conductive pins. Examples of base insulative layers include polyimide material, Kapton tape, fiber cloth, fiberboard, glass cloth, back-ground tape, plastic sheet, or pre-formed blanks.

[0050] In various examples, the uniform structure of a lead, pin, or conductive pin includes a structure that is fabricated as a single unit without any joints therebetween. For example, a lead according to various examples includes no joints between the first and second lateral extensions and the connecting portion. In other words, the lead is formed in a single process and therefore forms a single unit without any evidence of materials formed at different times in the process. In this example, plating or coatings over the base material of the pin or conductive pin that affect corrosion, oxidation, wettability, and bondability and adhesion are not considered materials formed at different times in the process.

[0051] In various examples, a lead, continuous lead, or conductive pin includes a conductive structure formed with a first lateral extension, a second lateral extension parallel to the first lateral extension, and a connection portion between the first and second lateral extensions. The pin includes features and shapes that reflect the curvature of a linear structure (a single unit without any joints between them to form a uniform structure) to form the first and second lateral extensions and the connection portion therebetween. For example, the first and second lateral extensions include a curvature near the connection portion that forms the preferred shape of the lead, continuous lead, or conductive pin.

[0052] In various examples, a portion of the lead, continuous lead, or conductive pin comprises an outer lead of a semiconductor package that is mountable to a printed circuit board. This portion, called the second lateral extension, includes solder wettability and adhesion-promoting properties to allow attachment to solder or other conductive adhesives for attachment to a PCB or insertion into a socket with contacts.

[0053] In various examples, the semiconductor die includes a semiconductor substrate with various conductive layers that form functional circuit elements. A top metal layer of the semiconductor die includes bond pads. It should be noted that the semiconductor die can be replaced in various examples with other electrical components, such as inductors that are electrically connected to leads and are within the scope of this disclosure.

[0054] In various examples, the deposited liquid may be referred to as ink, and the term "ink residue" herein may include hardened ink, which may be of a dielectric, insulating material, conductive material, adhesive, and polymer used in the arrangement.

[0055] In various examples, elements of an arrangement are described as "parallel" to one another when the elements are intended to lie in planes that do not touch when infinitely extended. However, as used herein, the term parallel also includes generally parallel to indicate that two surfaces are generally spaced apart and lie in planes that would not intersect when infinitely extended if the surfaces were fabricated without deviations in direction, and that surfaces may deviate slightly in direction due to manufacturing tolerances, but these surfaces are also parallel. Parallel surfaces extend in adjacent directions and do not touch.

[0056] 1A-1H are cross-sectional views of configurable leaded packages, according to various examples.

[0057] 1A is a cross-sectional view of a configurable leaded package with C-type leads. C-type refers to the shape of the leads resembling the letter C from a cross-sectional view of the semiconductor package. The semiconductor package includes a semiconductor die 106 attached to a base insulative layer 102 via a die attach material 104.

[0058] The semiconductor die 106 includes a plurality of bond pads 108 on its top side. A conductor is attached to each of the bond pads. In this example, the conductor is a bond wire 110. The bond wire 110 may comprise copper, gold, aluminum, silver, or other suitable conductors, with or without plating. Wire bonding uses a combination of downward pressure, ultrasonic energy, and sometimes heat to effect welding or bonding. A ball bond is used to connect one end of the bond wire 110 to the bond pad 108 using thermosonic bonding. The other end of the bond wire 110 is attached to a continuous lead 120. Note that only two continuous leads 120 are shown in FIGS. 1a-1h. As shown in other examples (e.g., FIGS. 2G and 5E), several continuous leads 120 may be present within the package.

[0059] In wire bonding, a wire is placed into and gripped by the bonding head of an automatic wire bonding tool. The bonding head may be of any suitable size and shape and may be formed from any suitable material. The bonding head includes a wire path, also called a "capillary," configured to receive a suitable wire. The wire path may have any suitable profile and may be formed in any suitable manner within the bonding head. After the wire path, a bonding ball is formed using a flash discharge or a small hydrogen flame to melt the tip of the bond wire 110 to form a bonding ball. The bonding head is then positioned over the die using a computer-controlled device, such as a robotic arm, to position the bonding head, and thus the wire and bonding ball, over each of the bond pads. Heat is applied to the bonding ball to soften the ball. After application of heat, the bonding head moves toward the bond pad, thereby pressing the heated bonding ball against the bond pad, at least partially flattening the bonding ball against the bond pad and forming a bond between the bond wire 110 and the bond pad 108. This type of bonding is called "thermocompression" bonding.

[0060] In an alternative example, a pulse of ultrasonic energy may be applied to the ball. This additional energy is sufficient to provide the necessary heat to soften the bonding ball so that it can be pressed against and bonded to the bond pad 108. This type of bonding is referred to as "thermo-sonic" bonding. Although thermo-compression and thermo-sonic bonding methods are discussed above, any other suitable methods for bonding the bond pad 108 and bonding ball may be implemented.

[0061] In thermosonic bonding, one end of bond wire 110 forms a ball bond to bond pad 108 and the other end forms a wedge bond. After ball bonding to bond pad 108, the bonding head moves toward continuous lead 120. As bond wire 110 contacts the surface of continuous lead 120, the bonding head deforms bond wire 110 against continuous lead 120, creating a wedge-shaped bond with a gradual transition into bond wire 110.

[0062] Instead of wire bonds, in one example, ribbon bonds are used to electrically connect between the bond pads 108 and the continuous leads 120. In another example, the conductors include conductive traces that electrically connect between the bond pads 108 and the continuous leads 120. The conductive traces (as shown in FIG. 14D ) include conductive material deposited using any suitable deposition technique, including printing. Various deposition techniques include sputtering, sol-gel techniques, chemical bath deposition, spray pyrolysis techniques, electroplating techniques, electroless deposition, chemical vapor deposition, sputtering techniques, and printing techniques. When printed, the conductive material in the conductive traces is in the form of a hardened ink residue. Printing of conductive traces is described in more detail in a co-pending provisional application entitled “Printed Package and Method of Manufacturing the Same,” filed December 31, 2020, by lead inventor Sreenivasan Kalyani Koduri. A variety of printing techniques have been described and can be used to create conductive traces, such as inkjet printing, screen printing, 2D or 3D printing, spray printing, aerosol jet printing, evaporation printing, microcontact printing, and nanoimprint lithography. [Patent Document 1] Co-pending provisional application filed December 31, 2020 Title of invention: Printed package and method of making the same

[0063] The continuous lead 120 includes two lateral extensions 114 and 116 and a connecting portion 118 connecting the two lateral extensions 114 and 116. The first lateral extension 116 is on and abuts the top surface of the base insulative layer 102, and the second lateral extension 114 is on and abuts the bottom surface of the base insulative layer 102. The connecting portion 118 between the first and second lateral extensions penetrates the base insulative layer 102. In various examples, "penetrating" includes the piercing of the connecting portion 118 through the base insulative layer 102 and is characterized by an action including pushing the continuous lead 120 to penetrate the base insulative layer 102. The continuous lead is then bent near its end to form the desired shape.

[0064] The first and second lateral extensions 116, 114 include a curvature near the connecting portion 118. The curvature reflects the action of creating the first and second lateral extensions 116, 114 and the connecting portion 118 from a linear shape of the continuous lead 120. In various examples in FIGS. 1A-1W, the curvature includes an angle of 20 to 60 degrees from a line perpendicular to a plane along the surface of the base insulative layer 102. FIG. 1A shows an encapsulation material 112 covering the base insulative layer 102, the semiconductor die 106, and a portion of the continuous lead 120. The encapsulation material 112 includes one of a mold compound, such as an epoxy, an insulating film, and a sprayed insulating coating, with suitable chemistries and properties, which can be applied using 3D printing, scribe dispensing, screen printing, spray coating, spin coating, dipping, dam and fill, AB multi-part casting (which uses an epoxy and a hardener), polishing, roller coating, brush coating, casting, potting, and filling. A full leadframe strip, such as that shown in Figure 4A, can be block molded at one time and then cured. Alternatively, most of the leadframe strip can be molded.

[0065] 1B-1D show various cutaway views of the package of FIG. 1A. FIG. 1B shows a cutaway view along line A-A' from a top view showing the shape of first lateral extension 116. FIG. 1B shows the top surface of first lateral extension 116, with bond wire 110 connecting to the surface via ball bond 122. One end of first lateral extension 116 proximal to semiconductor die 106 includes an edge that is approximately perpendicular in a top view. The other end of first lateral extension 116 is approximately perpendicular in a top view, but the cross-sectional thickness of the same portion varies due to the curvature shown in the cross-sectional view of FIG. 1A.

[0066] 1C shows a side cutaway view along line B-B' illustrating the shapes of first lateral extension 116 and second lateral extension 114. In this view, only the edges of first and second lateral extensions 116, 114 are visible. Connection portion 118 is not visible because it penetrates base insulative layer 102. Shown in FIG. 1C is encapsulation material 112 covering base insulative layer 102, semiconductor die 106, and portions of continuous leads 120. Encapsulation material 112 includes one of a mold compound such as epoxy, an insulating film, and a sprayed insulating coating, as well as an encapsulation laminate and a sealing liquid.

[0067] The material of the continuous lead 120 includes, but is not limited to, iron, nickel, cobalt, copper, copper alloy, aluminum, aluminum alloy, or iron-nickel alloy, or an alloy of two or more of these metals. In one example, the continuous lead 120 includes a base material coated with a conductive material that affects the oxidation of the base material. Examples of the base material include copper or cobalt, copper, copper alloy, aluminum, aluminum alloy, or iron-nickel alloy. Examples of the conductive material that affects the oxidation of the base material include a plated layer of nickel, palladium, silver, or an alloy of these metals. For example, the plated layer may include NiPdAu, NiPd, NiPdAgAu, Ag spot, Cu, NiSn, or Sn, and / or plated electroless materials including immersion gold, electroless nickel, electroless palladium, immersion gold, etc. Optionally, the material of the continuous lead 120 may be a CuNi, CuCr, or CuNiMn alloy without post-plating treatment. Additionally, the finish of the plating layer can be roughened to enhance adhesion between the continuous leads 120 and any components attached thereto. Electrolytic deposition or other suitable techniques can be employed to create the plating layer on the base material. In addition to preventing oxidation of the base material, these coatings enhance wettability during the soldering process when a package such as that shown in FIG. 1A is attached to a printed circuit board (PCB).

[0068] 1D shows a cutaway view along line C-C' of view A from a side view, showing the connection portion 118 between the first lateral extension 116 and the second lateral extension 114. The base insulating material 102 and the encapsulating material 112 are visible in this view. A portion of the bond wire 110 can be seen extending from the first lateral extension 116.

[0069] 1E, there is shown a cross-sectional view of a configurable leaded package with inverted C-type leads compared to the C-type leads of FIG. 1A. The edges of the C-type leads in this example face away from the semiconductor die 106. Like components are referenced with like reference numerals as in FIG. 1A and will not be repeated.

[0070] FIG. 1F shows a cutaway view along line D-D' of FIG. 1E from a side view, showing the connection portion 118 between the first lateral extension 116 and the second lateral extension 114. The base insulative material 102 and the encapsulating material 112 are visible in this view. FIG. 1G shows a cutaway view along line E-E' of FIG. 1E from a side view, showing the connection portion 118 between the first lateral extension 116 and the second lateral extension 114. The base insulative material 102 is visible between the first lateral extension 116 and the second lateral extension 114, indicating that the connection portion 118 (not visible in this view) penetrates the base insulative material 102. The encapsulating material 112 and a portion of the bond wire 110 extending from the first lateral extension 116 are visible in this view.

[0071] Referring now to FIG. 1H, a cross-sectional view of a configurable leaded package with J-type leads is shown. The connecting portion 118 and the second lateral extension 114 together form a J shape, hence the name J-type lead. Note that the first lateral extension 116 includes a bend that is proximate to and in contact with the base insulating material 102. The angle of the bend creates a standoff or space between the bottom surface of the base insulating material 102 and the second lateral extension 114. The first lateral extension 116 appears to be in contact with the top surface of the base insulating material 102. When the package is attached to a PCB, the J-leads are more resilient, allowing for greater shock absorption. This reduces thermal mismatch issues between the PCB and the package, which can cause product reliability problems. The mechanical flexibility of the J-lead, which provides protection from thermal expansion issues, is a result of its shape. The second lateral extension 114 also provides more surface area for solder to attach when connected to a PCB. This feature improves the reliability of the electrical connections throughout the package. Other components shown in Figure 1H, such as bond wires 110, semiconductor die 106, etc., are referred to by the same reference numerals as in Figure 1A. The properties, connections, and functions of those components are the same as in Figure 1A and will not be repeated.

[0072] Figure 1I shows a cutaway view along line L-L' of Figure 1H from a side view, showing the base insulating material 102 between the first lateral extension 116 and the second lateral extension 114. The second lateral extension 114 from this view includes the edge or distal end of the J-type lead, as well as a bend in the second lateral extension 114 that creates a standoff space between the base insulating material 102 and the second lateral extension 114. The bond wires 110 and the encapsulation material 112 are visible in this view.

[0073] 1J, there is shown a cross-sectional view of a configurable leaded package with J-type leads that is inverted compared to the J-type leads in FIG. 1H. The edges of the J-type leads in this example face away from the semiconductor die 106.

[0074] FIG. 1K shows a cross-sectional view of a configurable leaded package with J-type leads, with interconnect portions outside the encapsulation material 112. In this example, the second lateral extension 114 contacts the bottom side of the base insulative material 102. The connecting portion 118 contacts the side of the base insulative layer 102, such that the connecting portion 118 protrudes from the side of the package in the cross-sectional view. In this example, the interconnect portion 118 does not penetrate the base insulative layer 102. Instead, the interconnect portion 118, and thus the continuous lead 120, clamps the base insulative layer 102 from three sides. In applications requiring full automated visual inspection (AVI) after assembly or after the package is attached to a PCB (e.g., in automotive industry applications), this package provides wetting flank capability. The wetting flank process was developed to solve the side lead wetting problem of leadless packaging for automotive and commercial component manufacturers. Yield issues from spurious assembly failures, along with poor solder joints, affect the reliability of the package and its operation. One approach to ensuring reliability is to inspect the solder joints between the leads and the PCB. With connecting portions 118 protruding from the sides of the package, this type of protruding C-lead allows for automated visual inspection, which improves the reliability of the package on the PCB.

[0075] 1L shows a cross-sectional view of a configurable leaded package with interconnect portions 118 outside of the encapsulation material 112 and with second lateral extensions 114 comprising J-type leads that create space between the bottom of the base insulative layer 102 and the second lateral extensions 114. Similar to the package of FIG. 1H, this package provides improved shock absorption capabilities when the package is attached to a PCB.

[0076] The configurable leaded packages shown in FIGS. 1A-1L depict the edges of the leads to be straight, or in other words, at 90 degrees relative to the surface of the first or second lateral extensions 116, 114. Edges refer to the distal ends of the first and second lateral extensions 116, 114. Note that any other edge shape or angle is within the scope of this disclosure. For example, the edge surface can be at an angle between 10 and 170 degrees relative to the surface of the first or second lateral extensions 116, 114. Any combination of edge angles is also within the scope of this disclosure, and the edge of the first lateral extension 116 can be different from the edge of the second lateral extension. The edge angle or shape reflects the pinning or cutting mechanism involved in severing individual leads from a roll of wire.

[0077] One such example of different angles or shapes is shown in FIG. 1M, where the edge of the first lateral extension 116 is at an acute angle with respect to a plane along the bottom surface of the first lateral extension 116. However, the edge of the second lateral extension 114 is at a 90-degree angle. In the example shown in FIG. 1N, both edges are at an acute angle with respect to the bottom surfaces of the first and second lateral extensions 116, 114. In the example of FIG. 1O, the edge of the first lateral extension 116 is at an obtuse angle with respect to a plane along the bottom surface of the first lateral extension 116, and the edge of the second lateral extension 114 is at a 90-degree angle with respect to its bottom surface. In the example shown in FIG. 1P, both edges are at an obtuse angle with respect to the bottom surfaces of the first and second lateral extensions 116, 114.

[0078] In the example of FIG. 1Q, each edge of the first and second lateral extensions 116, 114 includes two surfaces. One surface is adjacent to the top surface of each of the first and second lateral extensions 116, 114, and the other surface is adjacent to the bottom surface. Each of the two surfaces connects at approximately a 45-degree angle. The sharp edges created using this example help minimize damage to the base insulative layer 102 as it passes through. A burr created in the base insulative layer 102 can help prevent mold or other material from leaking. The shape of the edges is the result of a pinching action that occurs when separating individual leads from a roll of wire, as will be explained later in this description.

[0079] 1R illustrates another example of a wetted flank in a package that allows for fully automated visual inspection after assembly or after the package is attached to a PCB. The edge of each second lateral extension 114 of continuous lead 120 includes a recess or groove 122. A portion of each second lateral extension 114 above groove 122 (in cross section) is flush with encapsulation material 112. The groove can be formed by either a laser or a saw during the packaging process.

[0080] FIG. 1S shows a cross-sectional view of a configurable leaded package, in which the curvature in each of the first and second lateral extensions 116, 114 is approximately 90 degrees with respect to a plane along the surfaces of the first and second lateral extensions 116, 114. The continuous lead 120 from the cross-sectional view resembles a C-type lead with a sharp edge. In the example shown in the figure, the continuous lead 120 is positioned inward from the edge of the encapsulation material 112. In another example, the continuous lead 120 is positioned so that the surface of the connecting portion 118 (the middle portion of the C-type lead) is exposed from the side of the package. The curvature in each of the first and second lateral extensions 116, 114 is flush with the side surface of the encapsulation material 112, resulting in the connecting portion 118 being exposed.

[0081] Although the foregoing discussion discusses only one semiconductor die, those skilled in the art will understand that one or more semiconductor dies can be packaged within a single package. An example of multiple semiconductor dies 106 is shown in FIG. 1U. In this example, two semiconductor dies 106 are shown. However, any number of semiconductor dies 106 can be attached to the base insulative layer 102. In this example, the semiconductor dies 106 are electrically connected to each other using bond wires 110. Each of the semiconductor dies 106 is also electrically connected to at least one of the continuous leads 120 using bond wires 110. Instead of multiple semiconductor dies 106, any other electrical components or devices, including active and passive devices, can be attached to the base insulative layer 102. In another example, one or more semiconductor dies 106 and passive devices are attached to the base insulative layer 102 and electrically interconnected in addition to being electrically connected to at least one of the continuous leads 120. Passive devices include resistors, capacitors, inductors, or transformers. In another example, one or more semiconductor dies 106 and stacked passive devices are attached to the base insulating layer 102 and electrically interconnected in addition to being electrically connected to at least one of the continuous leads 120.

[0082] In another example, one or more semiconductor dies 106 including printed sensors are attached to the base insulative layer 102 and are electrically interconnected in addition to being electrically connected to at least one of the continuous leads 120. In another example, one or more semiconductor dies 106 and printed sensors are attached to the base insulative layer 102 and are electrically interconnected in addition to being electrically connected to at least one of the continuous leads 120. In another example, one or more semiconductor dies 106 and thermally enhanced components including heat sinks are attached to the base insulative material 102.

[0083] 1V shows a cross-sectional view of a configurable leaded package including multiple semiconductor dies 106 arranged as a multi-chip module (MCM), where the semiconductor dies 106 are connected by stacking one on top of the other. A suitable die attach material is used to attach and stack one die 106 on top of the other. The top semiconductor die 106 is electrically connected to the bottom semiconductor die 106 using bond wires 110. The bottom semiconductor die 106 is electrically connected to at least one of the continuous leads 120 using bond wires 110. In another example, the top semiconductor die is replaced with a passive device that is electrically connected to the bottom semiconductor die 106.

[0084] FIG. 1W shows a cross-sectional view of a configurable leaded package containing multiple semiconductor dies 106 forming a bulk acoustic wave (BAW) package. BAW technology is a key component in advanced filtering solutions for mobile products, as well as improved radar, communication systems, and sensor applications. Sensing performance can be achieved by isolating the sensor die inside the package from mechanical stresses, shock, and / or vibrations that are likely to occur on the package's outer surface. This example includes a stress-absorbing material 124 that structurally isolates the BAW die 126 from external mechanical stresses, such as shock and vibration. The stress-absorbing material 124 serves as a glob top to encapsulate a portion of the top side of the die 106, as well as the top and sides of the BAW die 126 and associated wire bonds that electrically connect the BAW die 126 to the die 106. The stress-absorbing material 124 includes silicon.

[0085] 1A-1W , only one base insulative layer 102 is shown. In other examples, multiple base insulative layers are attached to one another using the connecting portions of the continuous leads 120. In yet other examples, thicker base insulative layers are attached to one another using the connecting portions of the continuous leads 120 to enhance heat dissipation from the package. It should also be noted that the semiconductor packages described above do not involve singulation via dam bars or tie bars, which would extend the life of saw blades used for singulation and save time in the packaging process compared to traditional lead frame strips. It should further be noted that in the above examples, the first lateral extension 116 and the second lateral extension 114 are generally parallel to one another from each cross-sectional view of the package. The first lateral extension 116 and the second lateral extension 114 may deviate slightly (e.g., + / - 20 degrees) due to manufacturing tolerances, and are within the scope of the present disclosure.

[0086] The aforementioned example of a configurable leaded package eliminates prefabricated custom leadframes, which require significant tooling costs (~100k for stamping), long cycle times, inventory costs, and high per-unit manufacturing costs. The low-modulus die attach, eliminating the large metal (leadframe-based) die pad, potentially offers better moisture sensitivity reliability. The pin and package design can be modified with minor changes to the stitching / stapling machine's software program. Additionally, compared to traditional packages, there is no need to lock into a standard body size, pin count, or layout. Instead, it can be optimized to best suit the needs of each individual product. By allowing lead expansion only in the Z-axis, 100% leadframe utilization in the X and Y axes is possible without any lead waste. This allows for more units per strip, less material waste, a smaller physical and environmental footprint, and improved factory productivity. This also results in overall cost reduction. With the continued die shrink driven by Moore's Law, package size can be adjusted on the fly and optimized for each device. The flexibility of creating J, C, S, and through-hole type pin configurations helps address individual end equipment needs. Having pins underneath the package increases PCB utilization, which can allow for higher functional density and lower cost at the PCB and system level. Curved pins can increase mold lock and reduce the risk of pin-level delamination. In short, CLP packages offer the best features of leaded and leadless packages simultaneously.

[0087] 2A-2H show various views of a base insulative layer and the attachment of continuous leads within a configurable leaded package, according to various examples. The construction process for a configurable leaded package begins with a base insulative layer 102, as shown in FIG. 2A. Materials for the base insulative layer 102 include one of polyimide, Kapton tape, fiber cloth, fiberboard, glass cloth, backgrind tape, plastic board, and preformed blanks. Kapton tape is a thin polyimide film produced from the condensation of pyromellitic dianhydride and 4,4-oxydiphenylamine. Kapton's thermal conductivity at temperatures between 0.5 and 5 Kelvin is rather high for these low temperatures: K = 4.638 × 10 T = 0.5678 W·m·K. This, along with its high dielectric qualities and its availability as thin sheets and electrical insulation with low temperature gradients, makes it suitable for use within semiconductor packages. Fiber cloth tape includes woven fibers. Glass cloth or glass cloth tape comprises a rubber-resin adhesive tape coated with a compatible glass cloth backing. Backgrind tape comprises a base material and an adhesive layer that also acts as an insulator when used in semiconductor packaging applications. Preformed blanks comprise a portion of mold compound or epoxy that is formed into a sheet and cured prior to use in semiconductor packaging applications.

[0088] FIG. 2A shows a perspective view of the base insulative layer 102. The base insulative layer 102 is a flexible, semi-flexible, or rigid carrier substrate that functions as a lead frame. One advantage of starting the process with the base insulative layer 102 is that the lead frame and lead layout can be configured based on the needs and dimensions of the required package. The thickness of the base insulative layer is between 0.020 mm and 0.080 mm. In one example, the thickness is 0.050 mm. This thickness can vary by + / - 20% within a single unit of the base insulative layer 102 due to manufacturing tolerances, and such variations are within the scope of this disclosure. FIG. 2A shows only one unit of the base insulative layer 102. In other examples, the base insulative layer 102 includes a large panel with multiple units or multiple units organized into a sheet.

[0089] In another example, as shown in FIG. 2B, the base insulative layer 102 is rolled to different sizes and unrolled flat before the assembly process can begin. The coefficient of thermal expansion (CTE) of the base insulative layer 102 is close to the CTE of the encapsulation material 112 to reduce any stress after encapsulation of the package. The relative expansion or stress divided by the change in temperature is called the coefficient of linear thermal expansion of a material and generally varies with temperature. The CTEs of the two materials in contact are close to each other, so that their relative co-expansion reduces mechanical stress in that region of the package. In one example, the base insulative layer 102 is soft enough to be penetrated but strong enough not to crack or tear under expected forces, allowing continuous leads to be stapled, pinned, or inserted into the base insulative layer 102. FIGS. 2C and 2D show various perspective views of the base insulative layer 102 from the side and top. In another example, the base insulative layer 102 is removable after the package is formed (after molding or encapsulation) and serves as a temporary sacrificial layer during the assembly process.

[0090] FIG. 2E shows a perspective view of the conductive pin 120 after it has been inserted into the base insulative layer 102 and locked in place as a result of the stapling action. The conductive lead 120 is formed from a wire 302 of conductive material as shown in FIG. 3A. The wire 302, and thus the conductive lead 120, includes a circular cross-sectional shape with a diameter of approximately 0.010 to 0.050 mm. The wire 302 is then cut to specific lengths to create individual units, as shown in FIG. 3B. A first bend 306 and a second bend 308 are then created to make each individual unit 304 resemble a stapling pin. Portions of each of the individual units 304 are half-etched using techniques including photoetching, chemical etching, or laser etching. In one example, the wire 302 is half-etched at strategic locations in a repeating pattern so that, as the individual units 304 are created, each individual unit or conductive pin includes the same number of half-etched portions at designated locations. In another example, etching is performed after the individual units 304 are created, as shown in Figure 3D, where the half-etch is at or near the curves 306, 308.

[0091] 2E , the two ends of the conductive pin 304 are inserted through the base insulative layer 102. Two additional bends 202, 204 are then formed in the conductive pin 304 near the ends. After the bends 202, 204 are formed, the bends 306 and 308 are on one side of the base insulative material 102, and the bends 202, 204 are on the opposite side of the base insulative material 102. In other words, after the conductive pin 304 is inserted, the bends 202, 204 create a locking mechanism (stapling) for the conductive pin 304 to attach to the base insulative layer 102. After the conductive pin 304 is attached, either at this stage or after the package is formed (post-molding), the portion 206 between the first and second bends 306, 308 is removed to separate the conductive pin 304 into two separate continuous leads 120. FIG. 2F shows the bottom side of the base insulative layer 102 with the conductive pins 304 inserted and the portion 206 not yet removed. FIG. 2G shows a perspective side view of the blank insulative layer 102 with multiple conductive pins 304 inserted. The area between the two ends of each of the conductive pins 304 is the die attach area where the semiconductor die 106 is attached. FIG. 2H shows the bottom side of the base insulative layer 102 with multiple conductive pins 304 inserted and the portion 206 between the first and second bends 306, 308 not yet removed. FIG. 21 shows a cross-sectional side view of the base insulative layer 102 showing the multiple inserted conductive pins 304, each conductive pin 304 representing the footprint of one configurable leaded package. In the illustrated example, five configurable leaded packages can be formed after the assembly process is completed.

[0092] Instead of forming the conductive pins 304 from wires 302, they can be preformed with multiple conductive pins 304 mechanically connected to one another, and the bends 306, 308 are formed as shown in FIG. 3E. The mechanical connection between the multiple conductive pins 304 is in the form of a bridge or pole 310 connected to each of the pins 304. The pole 310 lies in a plane below the portion 206 between the first and second bends 306, 308. Described differently, the multiple conductive pins 304 in this example resemble stapling tweezers. FIGS. 3E-3H show various perspective views of the stapling tweezers. In one example, creating the conductive pins 304 begins with a copper sheet approximately 125 microns thick. Alternatively, a CuNi alloy sheet can be used. CuNi offers the combination of being highly resistant to corrosion while still being solderable and operational. The edges of the sheet are then tapered to form sharp corners to aid in tearing the base insulative layer 102 and to provide bevels for the interconnect traces. The sheet is then laser cut, and the wires are either electro-discharge machined or chemically etched at specific, preset distances to form the individual wires. Poles 310 are left in the middle to hold the pins together; the poles 310 act as bridges between the pins. The cut specifications include 200-micron-thick lines with 20-micron spacing between the lines. The poles 310 are 20 microns thick. In this example, the poles 310 are left unetched in the middle of the sheet so that they are in the same plane as the pins 304. A bend is then formed in the pins 304 to resemble a stapler pin. The pins are plated after bending with 2-micron-thick nickel, followed by 1-micron-thick palladium.

[0093] FIG. 4A shows the base insulative layer 102 formed as a lead frame or panel with a matrix of inserted conductive pins 304. Specifically, FIG. 4A shows a 16×8 matrix with each individual unit 404 forming one configurable leaded package post assembly process. Depending on requirements, a greater or lesser number of individual units 404 can be formed. In this example, each individual unit 404 includes four conductive pins 304. Again, depending on requirements, a greater or lesser number of conductive pins 304 can be formed in each individual unit 404. A bottom view of the lead frame is shown in FIG. 4A.

[0094] FIG. 4B shows a leadframe 406 comprising a 12×4 matrix of individual units 404. In addition, the leadframe includes stiffening pins 408, 410, and 412 attached to the base insulative layer 102 to improve handling of the base insulative layer 102. The stiffening pins 408 are attached to opposite length sides of the rectangular leadframe 406. The stiffening pins 410 are attached to opposite width sides of the rectangular leadframe 406. In addition, the stiffening pins 410 are attached approximately midway along the length of the rectangular leadframe 406. The stiffening pins 408, 410, and 412 are either the same thickness as the conductive pins 304 or are thicker than the conductive pins 304. In the example shown in FIG. 4B, the stiffening pins 408, 410, and 412 are thicker than the conductive pins 304. In one example, the stiffening pins 410 are made of the same material as the conductive pins 304. In another example, the reinforcing pin 410 is made of any suitable metal capable of acting as a reinforcing material with suitable properties.

[0095] 5A-5H illustrate a process for making a configurable leaded package similar to that of FIG. 1A. FIG. 5A shows a base insulative layer 102 with conductive pins 304 attached and die attach material 104 placed on a central region of the base insulative layer 102. Die attach material 104 is a cured adhesive placed on the base insulative layer prior to attachment of a semiconductor die 106. Die attach material 104 provides mechanical support between the semiconductor die 106 and the base insulative layer 102. Die attach material 104 is essential for the thermal performance of the device, and in some applications, for electrical performance as well. The die attach equipment is configured to handle the incoming wafer and base insulative layer 102 simultaneously. A vision recognition system detects the die attach. While the adhesive material is dispensed in controlled amounts onto the base insulative layer 102, individual semiconductor dies 106 to be removed from the wafer backing / attaching tape are identified.

[0096] In one example, die attach material 104 includes a thermally conductive and electrically insulating material. In another example, die attach material 104 includes lead locks to reduce delamination between components within the package, such as between base insulative layer 102 and die attach material 104, between die attach material 104 and semiconductor die 106, or between die attach material 104 and leads 120.

[0097] The coverage of the material dispensed during the die attach process is critical to package reliability and performance. Voids and variations in thickness are undesirable. Over- or under-coverage of the die attach material tends to reduce device reliability. The adhesive strength of the die attach can be weakened by the presence of voids, especially during temperature cycling excursions, affecting the ability of the die attach material to dissipate heat from the device. The thickness of the die attach material 104 after dispensing is approximately 1-2 mils.

[0098] Die attach techniques include adhesive bonding, eutectic bonding, solder attach, or flip-chip attach. In adhesive bonding, adhesives such as epoxies and polyimides are used to form a bond between the semiconductor die 106 and the base insulative layer 102. In eutectic bonding, a metal alloy is used as an intermediate layer to form the bond. A eutectic bond is formed when a metal alloy in a molten state forms atomic contact between the semiconductor die 106 and the base insulative layer 102. Solder attach uses solder or solder paste to attach the semiconductor die 106 to the base insulative layer 102. In flip-chip attach, the electrical connection between the semiconductor die 106 and the base insulative layer is made directly by flipping the semiconductor die 106 over and making an electrical connection to the continuous leads 120, as shown in FIGS. 11a-11d and 12a-12d. FIG. 5B shows a side cross-sectional view of a device with die attach material 104 attached to the base insulative layer 102.

[0099] Non-penetrating plunge-up needles help separate individual semiconductor dies 106 to be picked up by a collet on a pick-up head of a die attach machine. The semiconductor dies 106 are then aligned in the proper orientation and position on the base insulative layer 102, as shown in Figure 5C. Figure 5D shows a cross-sectional view of a device in which the semiconductor dies 106 are attached to the base insulative layer 102 via the die attach material 104.

[0100] FIG. 5E illustrates a device in which the semiconductor die 106 is electrically connected to the conductive pins 304 using bond wires 110. High-speed wire bond equipment, as described above, is used for wire bonding. The wire bond equipment consists of a handling system for delivering the device of FIG. 5C to a work area. A vision recognition system ensures that the semiconductor die 106 is oriented to match the bonding diagram for the particular device. Wires are bonded one at a time. Two wire bonds are formed for each interconnect: one on the die and one on the conductive pin 304. The first bond involves ball formation using an electrical flame-off (EFO) process. The ball is placed in direct contact within a bond pad opening on the die under bond force and ultrasonic energy within a few milliseconds, forming a ball bond in the bond pad metal. The bond creates a connecting intermetallic layer on the bond pad 108. The bond wire 110 is then lifted to form a loop and then placed in contact with the desired bond area of ​​the conductive pin 304 to form a wedge bond. Bonding temperature, ultrasonic energy, and bond force and time are key process parameters controlled to form a reliable bond and therefore electrical connection. The shape of the bond wire loop for a specific function is controlled by software driving the bond head movement. The mechanical properties and diameter of the wire are wire attributes that affect the bonding process and yield. FIG. 5F shows a side cross-sectional view of the device of FIG. 5D, in which the bond wire 110 electrically connects the semiconductor die 106 to the conductive pin 304. Multiple bond wires 110 can be connected to a single bond pad 108 or a single conductive pin 304 / continuous lead 120, depending on the package design requirements.

[0101] Figure 5G illustrates a molded strip 505 containing five devices such as those shown in Figure 5F. An encapsulant, such as a mold compound, provides mechanical and environmental protection for the device from the external environment. Transfer molding is used to encapsulate most plastic packages. The mold compound is made from an epoxy resin containing inorganic fillers, catalysts, flame retardants, stress modifiers, adhesion promoters, and other additives. Fused silica, the most commonly used filler, provides the desired coefficient of thermal expansion, modulus, and fracture toughness properties. While advanced resin systems have been developed to meet the stringent requirements associated with moisture sensitivity and high-temperature operation, most resin systems are based on epoxy cresol novolac (ECN) chemistry. Filler geometry influences filler loading levels.

[0102] Transfer molding is used to encapsulate leadframe-based packages. This process involves the liquefaction and transfer of pelletized mold compound during the molding process. Liquid encapsulants are used when wire pitch is tight and to fill cavity packages. Liquid encapsulants are made using epoxy resins, fused silica fillers, and other additives. In liquid form, these encapsulant materials have low viscosity and can be filled with high levels of silica to provide desired mechanical properties. The liquid encapsulant is dispensed from a syringe. Depending on the device configuration, a dam resin may be deposited as a first step. The dam resin defines an encapsulation area around the device. The cavity or defined area is filled with encapsulant, covering the device and wires. Finally, a curing process is used. The lower viscosity of the liquid encapsulant significantly reduces the possibility of wire sweep.

[0103] Liquefaction results in a low-viscosity material that flows easily into the mold cavity and completely encapsulates the device. Immediately after the transfer process into the mold cavity, a curing reaction begins, and the viscosity of the mold compound increases until the resin system hardens. To ensure the mold compound is fully cured, an additional cure cycle is performed outside the mold in an oven. Process parameters are optimized to ensure complete filling of the mold cavity and elimination of voids within the mold compound.

[0104] In the mold tool, runners and gates are designed to ensure complete flow of mold compound into the mold cavity without void formation. Depending on the wire pitch, the molding process is further optimized to prevent wire sweep, which can result in electrical shorts inside the package. Controlled process parameters are transfer speed, temperature, and pressure. The final cure cycle (temperature and time) determines the final properties and, therefore, the reliability of the molded package. The dejunking process removes excess mold compound that may have accumulated on the lead frame from the mold. Media deflash bombards the package surface with small glass particles to prepare the lead frame for plating and the mold compound for marking.

[0105] In one example, there is no dead space (unused space between devices in the base insulative layer / lead frame at this stage due to leads protruding from the XY axes of the device), so molding multiple devices in a single cavity of a mold tool can be done without costly tooling modifications. With block molding, high strip utilization (number of units per strip), equipment and tooling reuse (for different package sizes), reduced cycle time, and low cost are achievable because of the absence of continuous leads 120. FIG. 6A shows another view of a block molded strip 505 with several devices. FIG. 6B shows an enlarged perspective view of one of the devices. FIG. 6C shows a side view of the device of FIG. 6B. The portion 206 between the first and second bends 306, 308 is not removed from the device at this stage.

[0106] Instead of epoxy molding compound, in one example, an insulating coating or sheet is used to encapsulate the device. In another example, a spray-based molding technique is used, using a sprayer to spray the insulator onto the device of FIG. 5F. Single or multiple passes of the sprayer to spray various coatings of encapsulating material on top of each other are also within the scope of this disclosure. Note that in the examples illustrated herein so far, the encapsulating material does not cover the bottom side of the blank insulating layer 102. In other words, the blank insulating layer 102 is exposed from the package. In an alternative example, the encapsulating material also covers the bottom side of the blank insulating layer 102. In another example, the blank insulating layer 102 can be removed after molding, exposing the encapsulating material 112 from all sides of the package.

[0107] After molding, the portion 206 between the first and second bends 306, 308 is removed during the trim and form process to separate the conductive pins 304 into separate continuous leads 120. FIG. 5G shows the molded strip 505 after portion 206 has been removed. FIG. 6D shows a bottom perspective view of the molded strip 505 after portion 206 has been removed. The conductive pins 304 include strategically placed half-etched or newly machined slots that are cut using a mechanical saw, laser, water jet, or by chemical etching. At this stage, each individual device 510 is still held together, allowing parallel electrical testing of all individual devices 510 in a single step. Probe testing with a tester capable of testing multiple devices at once allows for parallel testing, improving efficiency and saving test time in the packaging process. If desired, the molded strip 505 can be baked for moisture sensitivity level (MSL) (JEDEC Std-02) before or after electrical testing.

[0108] The individual packages 510 are then singulated from the molding strip 505, as shown in FIG. 5H. The individual devices 510 within the molding strip 505 are cut or singulated to produce the individual devices 510. Such singulation is accomplished via a sawing process. In a mechanical sawing process, a saw blade (or dicing blade) advances along saw blade paths 515 that extend in a defined pattern between the individual devices 510 within the molding strip 505. Singulation separates the individual devices 510 from one another. According to most examples, in the case of configurable leaded packages, there is no metal within the saw blade paths, so the saw blade does not need to pass through any metal of the leads 120. Instead, only the encapsulation material 112 is present within the saw blade paths 515. This improves the efficiency and lifespan of the saw blade compared to leadframe strips, where the leads, and therefore the metal, are present within the saw blade paths. In another example, instead of a saw blade, a laser of appropriate wavelength is used to separate the shaped strips 505 into packages 510 .

[0109] Individual packages 510 are inspected for lead coplanarity and placed into trays or tubes. A lead formation process is essential to achieve the coplanar leads required for the surface mount process. After the package is surface mounted on a PCB, portions of the leads 120 can be extended much closer to the package edge or even outside the package edge (by staggering) to allow for visual inspection of the leads and solder joints. FIG. 6E shows a perspective bottom view of an individual package (after portion 206 has been removed). FIG. 6F shows a side view of the device of FIG. 6E. Each package 510 is marked to place corporate and product identification on the packaged device. Marking allows for product differentiation. Either ink or laser methods are used to mark the packages. Laser marking offers higher throughput and better resolution.

[0110] FIGS. 7A-7G illustrate various process steps involved in creating a configurable leaded package with J-type leads for one example. The die attach, wire bonding, molding, and singulation processes in FIGS. 7A-7G are similar to those in FIGS. 5A-5F and are not repeated for simplicity. The process begins with a blank insulating layer 102 in sheet form. This example shows the blank insulating layer 102 designed to create three individual packages 715, as shown in FIG. 7G. Three conductive pins 304 are then inserted into the blank insulating layer 102 at designated locations, as shown in the cross-sectional side view of FIG. 7B. After insertion into the base insulating layer 102, each conductive pin 304 includes first and second bends 306, 308 and a portion between the bends 306, 308. Each conductive pin also includes two half-etched portions 705 proximate the bends 306, 308. Half-etched portions 705 are on both ends of portion 206, as seen in the cross-sectional side view of FIG. 7B. FIG. 7C shows a cross-sectional side view of the device after semiconductor die 106 has been attached to base insulative layer 102 with die attach material 104 and electrically connected to conductive pins 304 with bond wires 110. A wire bonding process attaches bond wires between semiconductor die 106 and each of the conductive pins. FIG. 7D shows a molded version of the device of FIG. 7D. In FIG. 7E, portion 206 between bends 306, 308 is removed. In FIG. 7F, the device of FIG. 7E is singulated along a saw blade path to separate individual packages 715, one of which is shown in FIG. 7G.

[0111] FIGS. 8A-8D illustrate various process steps involved in creating a wetted flank in a package similar to that of FIG. 1R. The die attach, wire bonding, molding, and singulation processes in FIGS. 8A-8D are similar to those in FIGS. 5A-5F and will not be repeated for simplicity. The process begins with a blank insulating layer 102 in sheet form. This example shows a blank insulating layer 102 designed to create four individual packages 825, as shown in FIG. 8D. Four conductive pins 304 are then inserted into the blank insulating layer 102 at designated locations, as shown in the cross-sectional side view of FIG. 8B. Unlike the conductive pins 304 in FIG. 7B, these conductive pins are smaller in size. Another difference is that each conductive pin 304 forms adjacent leads 120 of two adjacent individual packages. When inserted, each conductive pin 304 includes two first lateral extensions 805 on a first surface of the base insulative layer 102 and two second lateral extensions 810 on a second surface of the base insulative layer 102 opposite the first lateral extensions. A connecting portion connects adjacent first lateral extensions and adjacent second lateral extensions. The connecting portion penetrates the base insulative layer 102. A portion 815 of the conductive pin 304 between the second lateral extensions 810 is half-etched or machined to have approximately half the thickness from the cross-sectional view shown in FIG. 8B . A saw blade passage 820 is located in this portion 815, where the packages 825 are individually separated.

[0112] FIG. 8C shows a cross-sectional side view of the device after the semiconductor die 106 has been attached to the base insulative layer 102 using the die attach material 104, electrically connected to the conductive pins 304 using bond wires 110, and then molded using the encapsulation material 112. A wire bonding process attaches bond wires between the semiconductor die 106 and each of the conductive pins. In FIG. 8D, the molded strip of FIG. 8C has been separated / singulated in a saw blade passage 820 to separate individual packages 825, four of which are shown in FIG. 8D. Note that the thickness of the leads 120 at the end of the second lateral extension is less than the thickness of the leads across the first lateral extension 805, which creates the recess 830. The thickness of the leads 120 at the end of the second lateral extension is less than the thickness of the connection portion and a portion of the second lateral extension 810, which is adjacent the recess 830.

[0113] 9A-12D show various examples of configurable leaded packages in which the leads of the package are created using clamps (905, 1005, 1105, or 1205) instead of conductive pins 304. The advantage of having clamps is that there is no additional step of removing any portions (e.g., portion 206 or portion 815) after the device is molded on the leadframe strip. This reduces the cycle time and improves efficiency of the assembly process. Each of these clamps, or alternatively referred to as conductive leads 905, 1005, 1105, or 1205, forms a straight wire similar to that of wire 302.

[0114] FIG. 9A shows a cross-sectional view of a wire 910 after it has been inserted into the base insulative layer 102 and locked in place as a result of a clamping action. The conductive lead 905 is formed from a straight wire 910 of conductive material, similar to the wire 302 shown in FIG. 3C. The wire 910 after insertion into the base insulative layer 102 is shown by the dotted line in FIG. 9A. The wire 910 is then bent to create first and second lateral extensions 915 and 920. The first lateral extension 915 is on the top surface of the base insulative material 102, and the second lateral extension 920 is on the top surface of the base insulative material 102. The clamping action is similar to the stapling action used in other examples (described in more detail later in this specification) and can be configured to create the bend as well as the lateral extensions 915 and 920. Note that the clamp is securely held to the base insulative layer 102, enabling further assembly processes to form a package. In Figure 9B, semiconductor die 106 is attached to base insulative layer 102 via die attach material 104. Semiconductor die 106 is electrically connected to conductive leads 905 using bond wires 110 in Figure 9C, and then molded with encapsulation material 112 as shown in Figure 9D. Conductive leads 120 in Figures 9A-12D include a circular cross-sectional shape with a diameter of between approximately 0.010 and 0.050 mm, or a rectangular cross-sectional shape with a thickness of approximately 0.125 mm.

[0115] 10A-10D show an example of a chip-on-lead (COL) configurable leaded package. In this example, a semiconductor die 106 is directly attached to leads 1005 using die attach material 104. The die attach material 104 can be electrically conductive or insulating, depending on design requirements, including whether heat and / or current is conducted through the die attach pad or leads 1005 under the semiconductor die 106 for a COL configuration. For a COL configuration, insulating die attach material 104 is necessary to avoid pin shorting. A first lateral extension 1015 of the lead 1005 is longer than a second lateral extension 1020 in the cross-sectional view of the device for attachment to the semiconductor die 106. When attached, the semiconductor die 106 rests on the end of the first lateral extension 1015, as shown in FIG. 10B. The semiconductor die 106 is electrically connected to the conductive leads 905 in FIG. 10C using bond wires 110 and then molded with an encapsulant material 112 as shown in FIG. 10D.

[0116] 11A-11D show an example of a chip-on-lead configurable leaded package. In this example, the semiconductor die 106 is directly attached to the leads 1105 using die attach material 104. Instead of using bond wires to electrically connect the semiconductor die 106 to the leads 1105, the die 106 is flip-chip attached to the leads 1105. In flip-chip attachment, the active side (the side with the bond pads) of the semiconductor die 106 is attached face-down to the top surface of the first lateral extension 1115, as shown in FIG. 11B. A plurality of bumps 1110 extending from the bond pads of the semiconductor die 106 are attached to the top surface of the first lateral extension 1115 using a conductive adhesive such as solder, as shown in FIG. 11C. The device is then molded using an encapsulation material 112, as shown in FIG. 11D. As in the example of FIGS. 10A-10D, first lateral extension 1115 is longer than second lateral extension 1120 in a cross-sectional view of the device for attachment to semiconductor die 106.

[0117] 12A-12D show an example in which two semiconductor dies are attached to a base insulative layer 102, instead of the example of FIGS. 9A-9D. The base insulative layer 102, conductive leads 1205, and encapsulation material are similar in structure and properties to those of FIGS. 9A-9D. After the leads are formed with first and second lateral extensions 1215 and 1220, die attach material 104 is dispensed onto the base insulative material 102. The area coverage and size of the die attach material 104 on the base insulative layer 102 depend on the size of the semiconductor die 106 that needs to be attached, as shown in FIG. 12B. The semiconductor die 106 is electrically connected to the conductive leads 1205 using bond wires 110, as shown in FIG. 12C, and then molded with encapsulation material 112, as shown in FIG. 12D. In this example, each semiconductor die 106 is electrically connected to a first lateral extension 1215 of a conductive lead 1205 using a bond wire 110. In addition, the two semiconductor dies 106 are electrically connected to each other using bond wires 110.

[0118] 13A-13C show various perspective views of a configurable leaded package 1305 attached to a PCB 1310. The configurable leaded package 1305 is attached to the PCB via a conductive adhesive, such as solder 1315. FIG. 13A shows a cross-sectional view of the configurable leaded package with C-type leads 1305 attached to the PCB 1310. FIG. 13B shows a cross-sectional view of the configurable leaded package with J-type leads 1320 attached to the PCB 1310. FIG. 13C shows a top view of the configurable leaded package 1305 attached to the PCB 1310. The PCB 1310 includes contact pads on which portions of the leads rest at the bottom (second lateral extension) of the configurable leaded package 1305 or 1320. Solder paste is applied to the contact pads of the PCB 1310 prior to placing the configurable leaded package. The solder paste placed on the contact pads is reflowed by raising the temperature in a reflow oven to the reflow temperature. The PCB and configurable leaded package 1305 or 1320 are reflowed in an infrared (IR) reflow oven by gradually increasing the temperature from 240°C to the solder reflow temperature of 260°C. In some cases, the reflow temperature can be as high as 350°C. The reflow temperature is then lowered to room temperature while holding the device in place. The lowering of the temperature solidifies the solder joints to attach the package to the contact pads of the PCB. While FIGS. 13A and 13B show examples of only two configurable leaded packages 1305, 1320, it should be noted that any of the packages shown in the figures of this disclosure, such as the packages shown in FIGS. 1A-1S, can be attached to the PCB 1310 using the reflow process described above and are within the scope of this disclosure.

[0119] 14A-14O show various views of a printed configurable leaded package according to various examples. Instead of flip-chip attachment of a semiconductor die using bond wires 110 or using bumps and solder, these figures show printing conductive traces to electrically connect between bond pads on the die 106 to continuous leads 120. Examples of printing described include inkjet, scribe-dispense, aerosol-jet, microprinting, laser transfer, spraying, microdispense, 3D printing, and the like, to print or deposit conductive inks, conductive polymers, metal-filled epoxies, sinterable metal powders, liquid-assisted sintering particles, or solder pastes to form the conductive traces. Printing is described in more detail in a co-pending provisional application, entitled "Printed Package and Method of Manufacturing the Same," filed December 31, 2020, by lead inventor Sreenivasan Kalyani Koduri. Various printing techniques for printing conductive traces in a configurable leaded package are described therein. Additionally, the various layers can be structured by spin coating followed by photolithography.

[0120] 14A shows a semiconductor die 106 attached to a base insulative layer 102 via a die attach material 104, including continuous leads 120 inserted into the base insulative layer 102, using various techniques described in this disclosure according to various examples. In one example in FIG. 14B, a base insulating layer 1405 is printed, deposited, formed, or otherwise applied as a base layer that extends over a portion of the top surfaces of the lateral extensions 116 of the continuous leads 120. The base insulating layer 1405 is deposited in contact with the top surface of the semiconductor die 106, on the sides of the die 106, in contact with the base insulative layer 102, and in contact with the lateral extensions 116, and around the periphery of each of the bond pads 108. The top surfaces of each of the bond pads 108 and the top surfaces of the lateral extensions 116 remain uncovered by the base insulating layer 1405. In other words, the base insulating layer 1405 includes recesses 1410 at these locations to create space for conductive traces to make electrical contact with the bond pads 108 and continuous leads 120. The recesses 1410 comprise closed shapes from a top view of the device, as shown in Figure 14C. Various closed shapes include circles, rectangles, squares, and polygons.

[0121] Optionally, the base insulating layer 1405 can be cured at this point (e.g., at this point or later) with additional layers. Polymers, epoxies, silicones, molds, or other insulators can be used to form the base insulating layer 1405. The base insulating layer 1405 follows the contours of the topology of the continuous leads and lateral extensions 116 of the die 106 while smoothing bends in the Z-axis. The base insulating layer 1405 is applied to create paths and access for subsequent layers of conductive ink or other conductive material that will form the conductive traces. The base insulating layer 1410 can be formed or deposited using one of several techniques, such as screen printing, photolithography and etching, CVD, PVD, vacuum evaporation, inkjet printing, spray coating, microdispensing, aerosol jetting, or electrohydrodynamic (EHD) techniques with suitable insulating properties. If inkjet printing is used, the base insulating layer 1405 can be formed from inkjet-depositable compatible polymers, such as polyimide inks, heat-curable epoxy-based polymer inks, and UV-curable acrylate inks. A polymer with a modulus of less than 2 GPa is used to avoid excessive stress on the assembly. The thickness of the base insulating layer 1410 can be in the range of about 2 μm to 35 μm. In one example, the thickness is about 2 μm to at most 20 μm, and even more specifically, in the range of about 2 μm to about 10 μm. Because inkjet solvent deposited materials have solvent at their initial thickness, after the solvent dissipates, the remaining material forms an insulating layer with a reduced thickness.

[0122] Multiple inkjet depositions can be performed to achieve the desired thickness. Inkjet deposition allows for precise placement of material by using "drop-on-demand" (DOD) technology, in which a reservoir of liquid has a nozzle and small amounts of liquid are extruded from the nozzle in response to an electrical signal. The liquid forms droplets as it falls vertically onto a surface. Any other suitable printing technology can be used to create the base insulating layer 1410, as described in more detail in the co-pending provisional application entitled "Printed Package and Method for Manufacturing Thereof," filed December 31, 2020, by lead inventor Sreenivasan Kalyani Koduri. For any printing technique used, printing can be performed in one pass or multiple passes of the printhead. Figure 14C shows a top view of the device at this stage in the assembly process, showing the base insulating layer 1405, recess 1410, die 106, blank insulating layer 102, and lateral extension 116. The base insulating layer 1405 includes channels formed on the surface to form conductive traces 1415 .

[0123] FIG. 14D shows the printing of conductive traces 1415 within the channels, in the recesses 1410, and on the surface of the base insulating layer 1405. Various shapes of the channels, including semicircular, V-shaped, square, or rectangular, are described in more detail in a co-pending provisional application, entitled "Printed Package and Method for Manufacturing Thereof," filed December 31, 2020, by lead inventor Sreenivasan Kalyani Koduri. The conductive traces and any contacts can be made of low-resistivity materials. Conductive inks, conductive polymers, metal-filled epoxies, sintered metal powders, liquid-assisted sintered particles, solder pastes, and the like can be used to form the traces and contacts. The material can be applied using at least one of many techniques, including inkjet printing, EHD / electrospray printing, spray-coating printing, aerosol jet printing, microdispense printing, laser-induced forward transfer printing, microtransfer printing, scribe-and-dispense (illustrated in FIG. 14Db), screen printing, or 3D printing (illustrated in FIG. 14Da). In one example, the conductive traces 1415 are constructed by photolithography and electroplating similar to that used to form the redistribution layer (RDL) on the bumps of a semiconductor die.

[0124] The conductive material forming the conductive traces is constrained within the channels created by the base insulating layer 1405, preventing accidental shorts or opens. The conductive material conforms to the contours of the base insulating layer and adheres firmly to the base insulating layer 1405. The conductive traces 1415 fill the recesses 1410 on the lateral extensions 116 and the bond pads 108 that electrically connect them. The thickness of the conductive traces 1415 ranges from 5 microns to 30 microns. FIG. 14E shows a top view of the device at this stage in the assembly process, showing the base insulating layer 1405, conductive traces 1415, die 106, blank insulating layer 102, and lateral extensions 116. In one example, the conductive traces 1415 are cured using a thermal, chemical, or rapid curing process. For example, thermal curing can include conduction, convection, infrared, or microwave heating. In another example, the conductive traces 1415 are cured after additional layers are built into the package. The printing techniques described above can print the conductive traces 1415 in one step to form the entire thickness of the conductive traces 1415, or can print multiple layers at different times to finally form the entire thickness.

[0125] One drawback of using wire bonds to electrically connect the semiconductor die 106 to the leads 120 is that the process is limited to a single size and diameter at a time. Wire bonds do not address the need to have wires of various thicknesses for current carrying purposes. For example, certain terminals or bond pads on the die may need to carry higher currents than others, necessitating thicker bond wires to be connected to those bond pads. Printing the conductive traces 1415 provides the flexibility to create conductive traces 1415 with multiple shapes, sizes, materials, and contacts within a single package. Some examples of such conductive traces 1415 are shown in FIG. 14F. The conductive trace 1430 is thinner than the conductive trace 1415. Two bond pads can be interconnected using the conductive trace 1420. A conductive trace 1425, which can interconnect two bond pads and two opposing lateral extensions 116, is formed on and across the semiconductor die 106. The conductive trace 1430 is formed from a different conductive material than the remainder of the conductive trace. Note that while Figure 14F shows only a few examples, any size and shape of the conductive trace 1415 is within the scope of this disclosure.

[0126] The conductive traces 1415 are covered with an overlying insulating layer 1430, which contacts portions of the conductive traces 1415 and the base insulating layer 1405, as shown in FIG. 14G. The overlying insulating layer 1430 is printed, deposited, formed, or otherwise applied over the exposed portions on the base insulating layer 1405 and the exposed portions of the conductive traces 1415 on the base insulating layer 1405, and extends over portions of the top surfaces of the lead lateral extensions 116. The base insulating layer 1405 and the overlying insulating layer 1430 together contact the conductive traces 1415 and completely cover / encapsulate it except where contact is made to the bond pads 108 or the lead lateral extensions 116. The overlying insulating layer 1430 contacts the top surface of the die 106 adjacent the bond pads 108 and follows the contours of the conductive traces 1415 and the base insulating layer 1405. The material of the overlying insulating layer 1430 can be applied using at least one of many techniques, including inkjet printing, EHD / electrospray printing, spray coating printing, spin coating, aerosol jet printing, microdispense printing, laser-induced forward transfer printing, microtransfer printing, scribe dispensing, screen printing, 3D. A top view of the device of Figure 14G is shown in Figure 141.

[0127] The material of the covering insulating layer 1430 can be the same as that of the base insulating layer 1405, or it can be made of a different insulating material. If the base insulating layer 1405 and the covering insulating layer 1430 are made of the same / similar materials, they can form a uniform wrap around the conductive traces 1415. The thickness of the covering insulating layer 1430 is between 5 and 25 microns from the cross-section of the package. Note that at this point, the device topology has no holes. All exposed surfaces are within line of sight, unlike wire bonds with loops. Also, unlike wire bonds, all surfaces are robust, without wire sweep issues or other problems associated with wire bonds.

[0128] In one example, an overlying insulating layer 1435 is applied in one step as a blanket coating across the surfaces of the die 106, the conductive traces 1415, and portions of the lateral extensions 116 of the leads, as shown in Figure 14H. This blanket overlying insulating layer 1435 follows the topology on the base insulating layer 1405 and the contours of the conductive traces 1415 on the base insulating layer 1405 to at least sufficiently ensure that all of these components are wrapped or sealed between the base insulating layer 1405 and the overlying insulating layer 1435.

[0129] As shown in FIG. 14J, a layer of encapsulant material 112 is applied to completely cover the top side of the device. This layer is mostly for mechanical strength and cosmetic appearance. Most reliability and protection is provided by the previous layer, and the electrically critical areas of the device are already protected. The surface of the device is physically pressed down because there are no sensitive wires and loops (zero-hole topology). This allows for multiple encapsulation options. The encapsulant can be applied as a laminate, as shown in FIG. 14N. A sheet of insulating material of the required thickness can be applied over the device to cover the surface of the die 106, the overlying insulating layer 1430, portions of the lateral extensions 116, and portions of the blank insulating layer 102 in the lamination. Other methods of molding include transfer molding or injection molding, as shown in FIG. 14L. Yet another example of molding includes casting, potting, or filling, as shown in FIG. 14M, in which the encapsulant material is poured over designated areas of the device to the required thickness. Methods such as 3D printing, scribe dispensing, screen printing, spray coating, spin coating, dipping, dam and fill, AB multi-part casting (using epoxy and hardener), polishing, roller coating, brush coating, and the like are also within the scope of this disclosure.

[0130] Because the bottom layers (base insulating layer 1405 and overlying insulating layer 1430) provide most of the reliability, the encapsulation material 112 can be optimized for adhesion, trading off moisture permeability and ionic stability. Optionally, the top surface of the device can be planarized with a hot plate while encapsulating. While the overlying insulating layer 1430 completely covers the sensitive areas of the device, the encapsulation material 112 has no contact or interconnections with the die. This significantly reduces reliability and manufacturability requirements. This encapsulation material 112 includes thicknesses ranging from 50 microns to 1 mm.

[0131] In one example, the device does not include encapsulation material 112 because the overlying insulating layer 1430 can provide all of the functions of a mold compound or encapsulation, including protection from moisture. FIG. 14K shows a cross-sectional view of the package after the leads have been separated by removing the portion interconnecting the two leads. FIG. 14O shows an X-ray view of the device after molding with encapsulation material 112. Note that in the examples of FIGS. 14A-14O, only C-type leads are shown as printed configurable leaded packages. The electrical connections between the die 106 and the leads 120 in any other package, such as those shown in FIGS. 1A-1W, can be replaced with printed conductive traces, and such examples are within the scope of this disclosure. The material of the continuous leads is the same as the leads shown in FIGS. 3A-3H. The material and structure of the base insulative layer are the same as the base insulative layer 102 shown in FIGS. 2A, 2B, 2C, and 2D.

[0132] 15A and 15B show cross-sectional views of the printed CLP along with the dimensions of each component within the package. In both of these figures, the cross-sectional thickness of each component is indicated. For example, the thickness of the die 106 is 0.200 mm, the base insulating layer 1405 is 0.010 mm, the conductive traces 1415 are 0.010 mm, the die attach material 104 is 0.025 mm, the base insulating layer 102 is 0.050 mm, the overlying insulating layer 1430 is 0.010 mm, and the leads 120 are 0.0125 mm. The standoffs, or the distance between the leads 120 and the bottom surface of the base insulating layer 102, are 0.125 mm. The laser grooves 1505 for marking symbols on the package are 0.030 mm deep. The total package thickness is 0.785 mm. 15B shows another example of a printed CLP, where the die 106 is 0.200 mm thick, the base insulating layer 1405 is 0.010 mm, the conductive traces 1415 are 0.010 mm, the die attach material 104 is 0.150 mm, the base insulating layer 102 is 0.050 mm, the overlying insulating layer 1430 is 0.010 mm, and the leads 120 are 0.0125 mm. The laser grooves 1505 for marking symbols on the package are 0.030 mm deep. The standoffs are 0.125 mm. The total package thickness is 0.910 mm.

[0133] Figures 15C, 15D, 15E, 15F, 15G, and 15H illustrate various steps in a process for creating a printed CLP with J-type leads, where an overlying insulating layer 1435 is applied as a blanket coating, according to one example. Figures 15I, 15J, and 15K illustrate various steps in a process for creating a printed CLP with C-type leads. Figures 15La, 15Lb, 15Lc, and 15Ld illustrate various steps in a process for creating a printed CLP with J-type leads, according to another example. Figures 15Ma, 15Mb, 15Mc, and 15Md illustrate various steps in a process for creating a printed CLP as a chip-on-lead package, according to one example. Figures 15Na, 15Nb, 15Nc, and 15Nd illustrate various steps in a process for creating a printed CLP with J-type leads and multiple dies 106, according to one example. Various components in Figures 15C-15Nd are similar to previously described components and are identified with similar reference numerals. These components are identical in structure, material properties, and function and will not be repeated here for the sake of brevity. Note that any printed components will contain ink residue after the material has cured. Thus, in various examples, the base insulating layer 1405, the conductive traces 1415, and the covering insulating layers 1430 and 1435 all contain ink residue.

[0134] Typical semiconductor packages use multiple materials that are combined in complex configurations using a series of machines. This complex combination of materials and machines introduces multiple failure mechanisms into the manufacturing process at every step, for example, die attach, wire bonding, etc. Pin interconnect packages eliminate the complexity of such packages and provide a robust solution where die attach, wire bonds, and lead frames are all replaced by set-off pins and insulating carriers. The simplified design and structure make such packages robust and easy to manufacture. The process for constructing a pin interconnect package is shown in FIGS. 16A-16D. The process begins with a blank insulating layer 102, as shown in FIG. 16A. Then, as shown in FIG. 16B, a semiconductor die 106 is placed on the blank insulating layer 102 without attaching the die 106 to the blank insulating layer 102. Because only the placement of the die 106 is required, the die attach material and die attach process are not required.

[0135] In FIG. 16C, continuous leads 1605 are inserted into the base insulative layer 102 and curved on either side of the base insulative layer 102 to create clamps large enough to contact the bond pads of the die 106. The tops of the continuous leads 1605 include portions 1610 that lie below the plane along most of the bottom surface of the tops of the continuous leads 1605. This portion 1610 can be electrically connected to the bond pads of the die 106 when press-fit. The portions of the leads below the base insulative layer 102 serve as external leads for the package and can then be attached to a PCB. The material of the continuous leads is the same as the leads shown in FIGS. 3A-3H. The material and structure of the base insulative layer are the same as the base insulative layer 102 shown in FIGS. 2A, 2B, 2C, and 2D. The device is then molded using a suitable encapsulation material 112, as covered in the various examples.

[0136] The pin interconnect package requires significantly fewer process steps, equipment, materials, and failure modes than other package types. It also eliminates the need for wire bonding or printed conductive traces. Another advantage is that the same continuous lead 1605 provides interconnection to the die side as well as the PCB side. Instead of press-fitting the continuous lead 1605 onto the die, the portion 1610 can be attached to a bond pad on the die 106 using solder, sintered silver, or another conductive adhesive. The portion 1610 can be designed to have a different shape and size than the rest of the continuous lead 1605 to contact the bond pad. For example, the portion 1610 can be tapered at the contact point to contact the bond pad on the die 106.

[0137] Figures 17A-17C show various perspective views of a pin interconnect package. Figure 17A shows a bottom perspective view of the pin interconnect package. Figure 17B shows a top perspective view of the pin interconnect package, where a portion 1610 of continuous lead 1605 contacts die 106. Figure 17D shows a top perspective view of a pin interconnect package including a fan-out feature, where continuous lead 1605 is shaped to radiate from a smaller die 106. This type of fan-out feature is used when the die size needs to be reduced while maintaining a large overall package size. Figures 17E-17G show various views of a pin interconnect package molded with an encapsulant.

[0138] 18A-18F show various perspective views of a through-hole in a single in-line pin interconnect package. In this example, a semiconductor die 106 is placed on a blank insulating layer 102. The size of the blank insulating layer 102 is the same as the size of the die 106 (the size of the bottom surface of the die). Optionally, the blank insulating layer 102 can be placed on the die 106. Because it is only necessary to place the die 106, the need for die attach material and die attach process is eliminated.

[0139] In FIG. 18A, continuous lead 1805 is curved to create a clamp that may be large enough to contact a bond pad of die 106. The top of continuous lead 1805 includes a portion 1810 (clearly visible in FIGS. 18B and 18C) that lies below the plane along most of the bottom surface of the top of continuous lead 1805. This portion 1810 is electrically connectable to a bond pad of die 106 when press-fit into a die attached to base insulative layer 102. In this location, the continuous lead contacts the side surface of die 106 attached to base insulative layer 102, contacts the bottom surface of base insulative layer 102, and protrudes beyond the opposite side surface of die 106 attached to base insulative layer 102. The single in-line pin interconnect package allows for interchangeable die attach materials, bond wires, and leadframe materials. The materials of the continuous lead are the same as those shown in FIGS. 3A-3H. The material and structure of the base insulative layer is the same as the base insulative layer 102 shown in Figures 2A, 2B, 2C, and 2D. The device is then molded with a suitable encapsulant material, as covered in the various examples.

[0140] FIG. 18B shows a side perspective view of the single in-line pin interconnect package. FIG. 18C shows a cross-sectional view of the single in-line pin interconnect package. FIGS. 18D and 18E show side perspective views of the single in-line pin interconnect package. FIG. 18F shows a bottom perspective view of the single in-line pin interconnect package. The single in-line pin interconnect package is optionally molded as shown in FIGS. 19A-19D, which show various perspective views of the molded package. The encapsulation is largely cosmetic and provides mechanical protection to the die. FIGS. 19A and 19B show front and back perspective views, respectively, of the single in-line pin interconnect package. The encapsulation material 112 completely covers the continuous leads 1805, down to the edges of the die and blank insulating layer 102. Molding can be performed by any suitable molding technique to form the encapsulation material 112 as it is covered in various examples. 19C and 19D show perspective views of the front and back, respectively, of a thermally enhanced single in-line pin interconnect package. In this example, the portions of continuous leads 1805 that contact the bottom surface of blank insulating layer 102 are exposed from encapsulation material 112. These exposed portions of continuous leads 1805 are connectable to a heat sink for heat dissipation from the package.

[0141] FIG. 20 illustrates a system or tool for manufacturing configurable leaded packages, according to various examples. A computer can be programmed to move machine components, such as robotic arms within each section of the system, to receive blank insulating layer 102 in sheet or roll form, and wire 302, also in roll form as shown in FIG. 20 . Such a system performs one of a pinching action (to cut wire 302 at designated locations), a bending or forming action (to create continuous leads 304), and a stapling, stitching, or clamping type action (to insert and attach continuous leads 304 to base insulative layer 102). In one example, the system is operated manually or semi-automatically. In another example, the system is fully automatic, including a controller 2005 that is a programmable computer. The controller 2005 can also be connected to a factory database and IT systems to interact with other systems, such as die attach, a wire bonder for forming wire bonds, a printer for printing conductive traces, and a shaping unit. In one example, other systems can be integrated with the system of Figure 20 to perform the entire packaging process in a single tool. In such a case, the system includes additional units as described above. In another example, the system of Figure 20 with its functionality can be added to any other unit used in the assembly process, including a die attach unit, a wire bonder, and a molding unit.

[0142] The system of FIG. 20 can instantly create and attach one pin, a pair of pins, or multiple pins at a time to the base insulating layer 102. A wire feeder 2010 receives a roll of wire 302. Multiple types and qualities of wire can be fed through the wire feeder 201. The wire feeding operation includes wire loading, in which a roll of wire is loaded into the system. In one section of the wire feeder 2010, a robotic arm or other suitable mechanism pulls one end of the wire from the roll and straightens the wire. The wire passes through one section of the wire holder to keep the wire straight. Multiple sharp cutting heads 2105, 2010, as shown in FIG. 21, move from two opposite sides (top and bottom of the wire 302) and are designed to contact the wire 302 at a preset distance. The preset distance is set according to the length of the individual units 304.

[0143] The cutting heads then press together, creating a pinch-cutting action that separates the wire 302 into individual units 304. The cutting heads are T-shaped, with one section of the T containing a sharp cutting feature, in the example shown in FIG. 21 and creating the continuous lead 120 of FIG. 1Q. In other examples, only the cutting feature of the top cutting head 2105 has a sharp tip, and the bottom cutting head 2010 can act as a support to create the lead 120 of FIG. 1M, 1N, 1O, or 1P. The tips of the cutting heads are shaped according to the desired shape of the edges of the individual units 304. The wire 302 can be flat cut, star-pointed, conical-pointed, or wedge / chisel-shaped edge.

[0144] The individual units 304 are then transferred to the forming unit 2015 using a robotic arm or in a tray. The forming unit 2015 creates the first and second curves 306, 308 in the individual units 304, shaping each individual unit 304 to resemble a staple. The forming unit 2015 includes a punch 2205 and an anvil 2210. The punch 2205 is an inverted U-shaped punch. The shape of the punch 2205 can be changed depending on the shape of the curve required, for example, for the continuous lead 1805 or the clamps (905, 1005, 1105, or 1205).

[0145] The forming unit 2015 also includes an anvil at the bottom. The punch 2205 and anvil 2210 are designed as robotic arms that can move up and down along the Y-axis. The anvil 2210 is shaped and sized to fit inside the punch 2205 as it moves up. The individual units 304 are loaded into the forming unit 2015, the anvil comes into contact with the individual units 304, and then the anvil is pushed up to mate with the punch 2205, forming the curves 306, 308 and the desired shape. In other examples, both the punch 2205 and the anvil 2210 are moved relative to and closer to each other, causing the individual units 304 to assume the shape defined by the two together, as shown in FIG. 22B .

[0146] Sheets of base insulative layer are loaded into the carrier loader 2020 either at the same time that the wire 302 is loaded into the wire feeder 2010, or at another point in the process. The carrier loader 2020 receives the sheets of base insulative layer 102 and cuts them to the desired size based on the package size. Each individual sheet of base insulative layer 102 is passed, either individually or as a set, onto the pinning unit 2025. The pinning unit, as shown in FIG. 22C , includes a T-shaped punch 2215. A set of guide plates 2220 is designed to contact the bottom surface of the T-shape of the punch 2215. An anvil 2225 is positioned at the bottom of the tool, which includes a cavity 2230. The sidewalls of the cavity 2230 are aligned with the sidewalls of the guide plate 2220 either when the anvil 2225 is moved up, or when the punch 2215 and guide plate 2220 are moved down together.

[0147] The base insulative layer 102 is fed between a guide plate 2220 and an anvil 2225, as shown in FIG. 22C. With the aid of the guide plate 2220, the pins or individual units 304 are precisely positioned and held in place as shown. When the punch 2215 is pressed down, the individual units 304 are forced down into the defined shape of the anvil cavity 2230. In this manner, each individual unit 304 conforms to its shape defined by the cavity 2230, completing the pinning action to produce the device as shown in FIG. 22D. The shape of the punch 2215, anvil 2225 cavity 2230 can be modified depending on the shape of the curvature required, for example, for the continuous lead 1805 or the clamps (905, 1005, 1105, or 1205).

[0148] FIG. 23 shows a block diagram of a process flow for making a configurable leaded package, according to various examples. In block 2305, a wafer is received from a wafer fab. The wafer includes multiple dies 106. The wafer is then reduced in thickness using a backgrinding process in block 2310. A tape or blank insulating layer 102 is received in block 2320 and, as described in the previous examples, is cut to shape in block 2325 before the leads 120 are inserted. Individual dies are attached to the device at this stage in block 2330, after which electrical connections are made between the dies 106 and the leads 120 using wire bonds, printing conductive traces, or by clamping in block 2335. The device is then encapsulated using a suitable encapsulation material in block 2340. In block 2345, portions of the leads are removed to separate the leads 120. The device is then tested in block 2350, after which the package symbol is laser marked in block 2355. The devices are finally singulated to form individual packages in block 2360. Each individual package is then loaded onto tape and reel in step 2365 and then packed for shipping in block 2370.

[0149] The foregoing description sets forth numerous specific details to convey a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without these specific details. Well-known features have sometimes not been described in detail so as not to obscure the present invention. Other variations and examples are possible in light of the above teachings, and therefore, it is intended that the scope of the present invention be limited not by this detailed description, but only by the claims that follow.

Claims

1. A semiconductor package comprising: a base insulating layer; a semiconductor die attached to a portion of the base insulative layer; a first continuous lead electrically connected to the semiconductor die, the first continuous lead including a first lateral extension on a first surface of the base insulative layer, a second lateral extension on a second surface of the base insulative layer, and a connection portion between the first lateral extension and the second lateral extension, the connection portion passing through the base insulative layer; an encapsulant material covering the base insulative layer, the semiconductor die, and a portion of the first continuous lead; 1. A semiconductor package comprising:

2. 10. The semiconductor package of claim 1, The semiconductor package, wherein the first lateral extension is parallel to the second lateral extension in at least one aspect of the semiconductor package.

3. 10. The semiconductor package of claim 1, The semiconductor package, wherein the second lateral extension is exposed to an environment external to the semiconductor package.

4. 10. The semiconductor package of claim 1, The semiconductor package, wherein the semiconductor die is attached directly to the base insulative layer via a die attach material.

5. 10. The semiconductor package of claim 1, The semiconductor package, wherein the semiconductor die is electrically connected to the first continuous lead via a bond wire.

6. 10. The semiconductor package of claim 1, The semiconductor package, wherein the semiconductor die is electrically connected to the first continuous lead via a conductive trace.

7. 7. The semiconductor package according to claim 6, The semiconductor package, wherein the conductive traces include ink residue of a conductive material.

8. 10. The semiconductor package of claim 1, The second lateral extension functions as an outer lead of the semiconductor package.

9. 10. The semiconductor package of claim 1, The semiconductor package, wherein the first continuous lead includes a uniform structure without any joints between the first lateral extension, the second lateral extension, and the connecting portion.

10. 10. The semiconductor package of claim 1, A semiconductor package, wherein the thicknesses of the first lateral extension portion, the second lateral extension portion, and the connecting portion are the same when viewed in a cross-sectional view of the semiconductor package.

11. 10. The semiconductor package of claim 1, The semiconductor package, wherein the first continuous lead comprises copper.

12. 10. The semiconductor package of claim 1, The semiconductor package, wherein the first continuous lead comprises a copper-based material coated with a conductive material that affects oxidation of the copper.

13. 10. The semiconductor package of claim 1, The semiconductor package, wherein the second lateral extension is mountable to a printed circuit board.

14. 10. The semiconductor package of claim 1, A semiconductor package, wherein the base insulative layer comprises a material with a flexibility of between 40 and 50 N / cm.

15. 10. The semiconductor package of claim 1, The semiconductor package, wherein the base insulative layer comprises one of Kapton tape, fiber cloth, fiberboard, glass cloth, backgrind tape, plastic board, and a preformed blank.

16. 10. The semiconductor package of claim 1, A semiconductor package, wherein a portion of each of the first lateral extension and the second lateral extension adjacent to the connecting portion includes a curvature when viewed from a cross-sectional view of the semiconductor package.

17. 10. The semiconductor package of claim 1, The semiconductor package wherein the base insulative layer comprises an insulating material as a whole.

18. 10. The semiconductor package of claim 1, The semiconductor package, wherein the second lateral extension does not extend from a cross-sectional view of the semiconductor package along a surface of the encapsulant material past a periphery of the semiconductor package.

19. 10. The semiconductor package of claim 1, A semiconductor package, wherein a portion of the second lateral extension does not extend beyond a periphery of the semiconductor package along a surface of the encapsulant from a cross-sectional view of the semiconductor package.

20. 10. The semiconductor package of claim 1, The semiconductor package, wherein the encapsulating material comprises one of a mold compound, an insulating film, and a sprayed insulating coating.

21. 10. The semiconductor package of claim 1, further comprising a second continuous lead opposite the first continuous lead; a first end of the second lateral extension of the first continuous lead and a second end of the second lateral extension of the second continuous lead facing each other on at least one side of the semiconductor package.

22. A semiconductor package comprising: a base insulating layer; a lead including a first lateral extension on a first surface of the base insulative layer, a second lateral extension on a second surface of the base insulative layer, and a connection portion between the first lateral extension and the second lateral extension, the connection portion passing through the base insulative layer; a semiconductor die attached to a portion of the first lateral extension, the semiconductor die being electrically connected to the leads; an encapsulating material covering the base insulative layer, the semiconductor die, and a portion of the leads; 1. A semiconductor package comprising:

23. 23. The semiconductor package of claim 22, The semiconductor package, wherein the semiconductor die is attached to a portion of the first lateral extension via a die attach material.

24. 23. The semiconductor package of claim 22, The semiconductor package, wherein the semiconductor die is electrically connected to the leads via bond wires.

25. 23. The semiconductor package of claim 22, The semiconductor package, wherein the semiconductor die is electrically connected to the leads via bumps.

26. 23. The semiconductor package of claim 22, The semiconductor package wherein the base insulative layer comprises an insulating material as a whole.

27. 23. The semiconductor package of claim 22, The semiconductor package, wherein the leads comprise copper.

28. 23. The semiconductor package of claim 22, A semiconductor package, wherein the leads comprise a copper-based material coated with a conductive material that affects the oxidation of the copper.

29. 23. The semiconductor package of claim 22, The semiconductor package, wherein the first lateral extension is parallel to the second lateral extension in at least one aspect of the semiconductor package.

30. 23. The semiconductor package of claim 22, The semiconductor package, wherein the second lateral extension is exposed from the semiconductor package.

31. 23. The semiconductor package of claim 22, The semiconductor package, wherein the semiconductor die is attached to the base insulative layer via a die attach material.

32. 23. The semiconductor package of claim 22, The semiconductor package, wherein the semiconductor die is electrically connected to the leads via bond wires.

33. 23. The semiconductor package of claim 22, a semiconductor package, wherein the semiconductor die is electrically connected to the leads via conductive traces;

34. 34. The semiconductor package of claim 33, The semiconductor package, wherein the conductive traces include ink residue of a conductive material.

35. 23. The semiconductor package of claim 22, The semiconductor package, wherein the second lateral extension is mountable to a printed circuit board.

36. 23. The semiconductor package of claim 22, The second lateral extension functions as an outer lead of the semiconductor package.

37. 23. The semiconductor package of claim 22, The semiconductor package, wherein the leads include a uniform structure without any joints between the first lateral extension, the second lateral extension, and the connecting portion.

38. A semiconductor package comprising: a base insulating layer; a semiconductor die attached to a portion of the base insulative layer; a first lead electrically connected to the semiconductor die, the first lead including a first lateral extension on a first surface of the base insulative layer, a second lateral extension on a second surface of the base insulative layer, and a connection portion between the first lateral extension and the second lateral extension, one end of the second lateral extension including a recess; an encapsulating material covering the base insulative layer, the semiconductor die, and a portion of the first lead; 1. A semiconductor package comprising:

39. 39. The semiconductor package of claim 38, The semiconductor package, wherein the connecting portion penetrates the base insulating layer.

40. 39. The semiconductor package of claim 38, A semiconductor package, wherein the thickness of the first lead at one end of the second lateral extension is smaller than the thickness of the first lead across the first lateral extension, the connection portion, and a portion of the second lateral extension.

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