Integrated circuit package with pre-wetted contact sidewall surfaces - Patent Application 20070122997

Abstract

To provide an integrated circuit package having a pre-wetted contact side wall surface.SOLUTION: In an integrated circuit (IC) package (100) having a sealed package (106) including an integrated circuit die (341) attached to a lead frame (104), a set of contacts (102, 103) are formed on a package (100), each of the contacts has an exposed side wall surface and an exposed lower side surface of the contact (813, 823), and a protective layer (814, 824) of a material with solder wettability covers each contact side wall surface.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] This application relates generally to integrated circuit packages, and more particularly to packages with pre-wetted contact sidewall surfaces. [Background technology]

[0002] Flat no-lead packages, such as quad flat no-lead (QFN) and dual flat no-lead (DFN), physically and electrically connect integrated circuits to printed circuit boards. Flat no-lead, also known as micro lead frame (MLF) and small outline no-lead (SON), is a surface-mount technology that is one of several packaging technologies that connect an integrated circuit (IC) to the surface of a printed circuit board (PCB) without through-holes. Flat no-lead is a near-chip-scale, plastic-encapsulated package made with a flat copper leadframe substrate. Peripheral lands on the bottom of the package provide electrical connection to the PCB. Flat no-lead packages include an exposed thermal pad to improve heat transfer from the IC to the PCB.

[0003] To ensure vehicles meet modern demands for safety and reliability, the automotive industry requires original equipment manufacturers (OEMs) to perform 100% automatic visual inspection (AVI) on circuit board assemblies. However, quad flat no-lead (QFN) packages do not have solderable pins / terminals that are easily observable for AVI to determine whether the package has been properly soldered onto the printed circuit board (PCB). The package edges have exposed copper for the terminals, which are prone to oxidation, making sidewall solder wetting difficult. Summary of the Invention

[0004] The integrated circuit (IC) package includes an encapsulated package including an integrated circuit die attached to a lead frame, wherein the lead frame defines a set of contacts, each having an exposed contact sidewall surface and an exposed contact underside surface, and wherein a protective layer of solderable material covers each contact sidewall surface.

[0005] In a method for performing automated visual inspection (AVI), an integrated circuit (IC) package is soldered to a pad on a substrate. The IC package has contacts, each of which has a bottom surface and a sidewall surface. The solder profile for each of the contacts on the IC package can be visually inspected. For each of the contacts on the IC package, if the solder profile forms a fillet that substantially covers the contact sidewall, the joint can be passed; otherwise, if the solder profile does not form a fillet that substantially covers the contact sidewall, the joint can be rejected. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is an illustration of a QFN IC package with pre-tinned contact sidewalls.

[0007] [Figure 2] 1 is a cross-sectional side view of a PCB with a QFN package attached, illustrating the problems associated with soldering the QFN package.

[0008] [Figure 3] 2 is a top view of a leadframe strip that can be used to form the QFN of FIG. 1.

[0009] [Figure 4] FIG. 4 is a more detailed view of a portion of the lead frame strip of FIG. 3.

[0010] [Figure 5A]2 illustrates a sequence of steps that may be used to pre-tin the contact sidewall surfaces of the QFN of FIG. 1; [Figure 5B] 2 illustrates a sequence of steps that may be used to pre-tin the contact sidewall surfaces of the QFN of FIG. 1; [Figure 5C] 2 illustrates a sequence of steps that may be used to pre-tin the contact sidewall surfaces of the QFN of FIG. 1; [Figure 5D] 2 illustrates a sequence of steps that may be used to pre-tin the contact sidewall surfaces of the QFN of FIG. 1; [Figure 5E] 2 illustrates a sequence of steps that may be used to pre-tin the contact sidewall surfaces of the QFN of FIG. 1; [Figure 5F] 2 illustrates a sequence of steps that may be used to pre-tin the contact sidewall surfaces of the QFN of FIG. 1; [Figure 5G] 2 illustrates a sequence of steps that may be used to pre-tin the contact sidewall surfaces of the QFN of FIG. 1;

[0011] [Figure 6] 2 illustrates the use of an inkjet printer during the fabrication of the QFN of FIG. 1; [Figure 7] 2 illustrates the use of an inkjet printer during the fabrication of the QFN of FIG. 1;

[0012] [Figure 8] 2 illustrates a side view of the QFN of FIG. 1 soldered onto a PCB.

[0013] [Figure 9] 1 is a flowchart illustrating packaging of a QFN IC. DETAILED DESCRIPTION OF THE INVENTION

[0014] In the drawings, for the sake of consistency, identical elements are designated with like reference numerals.

[0015] Achieving 100% AVI on conventional QFN packages can be difficult because contact sidewall solder coverage can vary between 50 and 90%. OEMs can incur additional costs due to yield issues caused by false assembly failures, as well as true failures with poor solder joints that highlight the assembly process. AVI can be supplemented with X-ray imaging, but using X-ray equipment to inspect for good, reliable solder joints adds additional cost. Also, X-ray equipment may not be available for some AVI systems.

[0016] One embodiment may include a QFN package with contact sidewalls that are pre-tinned during package manufacturing to allow for reliable sidewall solder coverage that can be verified by AVI.

[0017] FIG. 1 is an illustration of a QFN IC package 100 with pre-tinned contact sidewalls. The bottom side of the QFN package 100 is shown. Flat no-lead packages, such as quad flat no-lead (QFN) and dual flat no-lead (DFN), physically and electrically connect an integrated circuit to a printed circuit board. Flat no-lead, also known as micro lead frame (MLF) and small outline no-lead (SON), is a surface mount technology that connects an IC to the surface of a PCB without through holes. Flat no-lead is a near-chip-scale plastic-encapsulated package made with a flat copper leadframe substrate. Peripheral lands on the bottom of the package provide electrical connection to the PCB. Flat no-lead packages include an exposed thermal pad to improve heat transfer from the integrated circuit (to the PCB). Heat transfer can be further enhanced by metal vias in the thermal pad. QFN packages are similar to quad flat packages and ball grid arrays.

[0018] QFN package 100 includes a set of contacts, such as contacts 102 and 103, arranged around the periphery of the package on the bottom side. Each of the contacts has an exposed surface on the bottom side of QFN package 100 and an exposed sidewall. Thermal pad 104 has an exposed surface on the bottom side of QFN 100. An integrated circuit die (not shown) is attached to the other side of thermal pad 104. The entire assembly is encapsulated in a molding compound 106, such as various types of epoxy compounds. While a QFN is shown in FIG. 1, other embodiments may use other types of integrated circuit packages that may include one or more contacts that may have sidewall contact surfaces.

[0019] 2 is a cross-sectional side view of a PCB 210 with mounted QFN packages 211, 221, illustrating the problems associated with soldering QFN packages. The cross-sectional view illustrates a portion of QFN 210, including contact 212, and a portion of QFN 221, including contact 222. As noted above, each contact in a QFN package has an exposed contact underside surface 213, 223 and an exposed contact sidewall surface 214, 224.

[0020] During assembly of PCB 210, QFNs may be attached to PCB 210 using solder, as shown at 215 and 225. After assembly of PCB 210, an AVI process may be performed using a camera, as shown at 230. Camera 230 may be mounted on a robotic arm, allowing camera 230 to move over the surface of PCB 210 and visually inspect every solder joint. Alternatively, camera 230 may be fixed, and PCB 210 may be mounted on a robotic table that can move PCB 210 so that camera 230 can visually inspect every solder joint on PCB 210.

[0021] A good solder joint can be assumed to have been formed between contact 212 and PCB pad 216 if the solder joint, such as solder joint 215, forms a smooth solder fillet that extends from copper pad 216 to contact sidewall surface 214 and substantially covers the entire contact sidewall surface. As used herein, the term "substantially covers" means that the solder fillet covers a majority of the contact sidewall surface, such as 90-95%. Thus, when camera 230 is within view of solder joint 215, as shown at 221, the AVI system can infer that a good solder joint has been formed based on the size and configuration of the solder fillet.

[0022] Contamination on contact sidewall surface 224, such as oxides formed on the copper surface, can inhibit solder wetting. In this case, contact sidewall surface 224 may remain exposed after the soldering operation. In many cases, a good joint is formed between contact 222 and PCB pad 226 as long as bottom surface 223 of contact 222 is not contaminated. However, in some cases, such as when contamination is present on bottom surface 223, when contamination is present on PCB pad 226, or when insufficient solder is applied, a good solder joint may not be formed. Therefore, if a solder joint, such as solder joint 225, does not wick up contact sidewall surface 224, it is difficult to tell by visual inspection that a good solder joint has been formed between contact 222 and PCB pad 226, as shown at 232. Therefore, if the solder profile does not include a fillet covering a substantial portion of the contact sidewall, the joint may be rejected.

[0023] FIG. 3 is a top view of a leadframe strip 340 that can be used to form the QFN 100 of FIG. 1. The leadframe strip 340 can include one or more arrays of individual leadframes. The leadframe strip 340 is typically fabricated from a copper sheet that is etched or stamped to form a pattern of thermal pads and contacts. The leadframe strip 340 can be plated with tin or other metal, which can prevent oxidation of the copper and provide an underside contact surface that is easy to solder. An IC die can be attached to each of the individual leadframes, as shown at 341 and 342.

[0024] FIG. 4 is a more detailed view of a portion of leadframe strip 340. Each individual leadframe includes a thermal pad, such as thermal pads 404 and 405. Each individual leadframe also includes a set of contacts, such as contacts 402 and 403, surrounding the thermal pad. A metal sacrificial strip connects all of the contacts together and provides mechanical support until the sawing process removes it. An IC chip, such as IC chips 341 and 342, is attached to each thermal pad. Wire bonding can then be performed to connect the bond pads on each IC to the respective contacts on the leadframe. The entire leadframe strip 340 can then be covered with a layer of molding compound to encapsulate the IC. The leadframe strip 340 can then be singulated into individual packaged ICs by cutting along cut lines 448 and 449.

[0025] Prior to cutting along lines 448, 449, the contacts of adjacent leadframes are connected together. For example, contacts 402 and 403 are a single unit prior to cutting along cut line 449. Sawing leadframe strip 340 produces contact sidewalls for each QFN package, but the resulting contact sidewalls are bare copper surfaces. These exposed copper contact sidewalls are subject to oxidation, which can prevent solder wetting, as discussed with respect to FIG. 2. Processes that can be used to pre-tin the contact sidewall surfaces will now be described in more detail.

[0026] 5A-5G illustrate a sequence of steps that may be used, for example, to pre-tin the contact sidewall surfaces of QFN 100 of FIG. 1. FIGS. 5A-5G are cross-sectional views of a portion of leadframe strip 340, as illustrated in FIG. 4. FIG. 5A illustrates leadframe strip 340 after an encapsulation process. IC dies 341, 342 are attached to respective thermal pads 404, 405 using a known or later-developed die attach process. Contact element 401 is cut to form individual contacts 402, 403 in a later step, illustrated in FIG. 5B. Bond wire 551 connects a bond pad on IC die 404 to the portion of contact element 401 that will become contact 402. Similarly, bond wire 552 connects a bond pad on IC die 405 to the portion of contact element 401 that will become contact 403. A molding compound 506 is applied to the leadframe strips 340 using any known or later developed process.

[0027] 5B illustrates a sawing process using a saw 562 to form a partially sawed trench 563 that separates contact element 401 into individual contacts 402, 403. The sawing process forms similar partially sawed trenches along each cut line 448, 449 (as illustrated in FIG. 4) throughout lead frame 340. As described above, sawing each contact element (such as contact element 401) into individual contacts (such as contacts 402, 403) creates bare copper contact sidewall surfaces. Sacrificial metal may also be removed by partial sawing.

[0028] The partially sawed trench 563 is deep enough to completely separate the contacts 402, 403 and remove the sacrificial strip of metal between each contact, but shallow enough to leave the encapsulated leadframe strip 340 in one piece.

[0029] 5C illustrates the process of depositing pre-tinned material 565 from a dispenser 564 into the partially sawed trench 563. The term "pre-tinned material" refers to any type of material that can be used to form a protective layer over the exposed contact sidewall surfaces to prevent oxidation or other contaminants from forming on the exposed contact sidewall surfaces. The protective layer of pre-tinned material provides a wettable surface for the solder when the package is soldered to a PCB.

[0030] The pre-tinned material 565 may be a solder paste that may include flux, in which case the dispenser 564 may be, for example, a MY600 solder jet printer, which may also be used to dispense solder paste dots onto a PCB.

[0031] In another example, the pre-tin plating material 565 can be an ink containing silver (Ag) nanoparticles. Silver nanoparticles are typically nanoparticles of silver ranging in size from 1 nm to 100 nm. While often described as "silver," some contain a higher percentage of silver oxide due to a higher ratio of surface to bulk silver atoms. A commonly used shape is spherical silver nanoparticles, although diamond, octagonal, or other shapes may also be used.

[0032] In this case, the dispenser 564 can be a single-nozzle or multi-nozzle inkjet dispenser. In some embodiments, the inkjet dispenser 564 can have, for example, 500-1000 inkjet nozzles. A reducing gas, such as formic acid, can be used to clean the exposed copper contact sidewall surfaces before and / or during the deposition of the nano-Ag ink.

[0033] 5D and 5E illustrate a baking process in which the deposited pre-tinned material 565 is heated to reflow and wick up the contact sidewall surfaces of the contacts 402, 403, wetting the contact sidewalls, thereby forming pre-tinned layers 566, 567 that cover the entire contact sidewall surface of each contact 402, 403 with a protective layer of solder-wettable material.

[0034] The baking temperature is selected to be high enough to reflow the pre-tinned material, but not so high as to damage the encapsulation material 506. If the pre-tinned material 565 is a solder paste, a temperature in the range of about 200-280° C. may be used. If the pre-tinned material 565 is nano-Ag, for example, a temperature in the range of about 150-250° C. may be used.

[0035] Although only two contacts 402, 403 are shown, all of the contacts on the leadframe strip 340 are similarly treated.

[0036] 5F illustrates a filling process in which the partially sawed trenches 563 may be filled with a filling material 568. The filling material 568 may be, for example, an epoxy compound similar to the mold compound 506. The filling material 568 may be applied, for example, using a known or later-developed printing process. Filling the partially sawed trenches 563 may result in a final QFN package having smooth sides, for example.

[0037] FIG. 5G illustrates the sawing process of singulating the encapsulated leadframe strip 340 into individual QFN packages by sawing completely through the cut lines 448, 449 with a saw 571 (as shown in FIG. 4).

[0038] 5B, the partially sawed trench 563 has a width 574 wide enough to remove the sacrificial metal strip between each of the contacts that provided mechanical support prior to encapsulation. The saw 571 is selected to create a kerf having a width 573 narrower than the width 574 of the partially sawed trench 563, so that at least a portion of the pre-tinned layers 566, 567 remain on the contact sidewall surfaces of the contacts 402, 403, forming a protective layer after each package is singulated.

[0039] 6 is an enlarged view of a portion of the bottom surface of leadframe 340. In this example, the contacts are approximately 240 μm wide and the contact spacing is approximately 260 μm. The width 574 of the partially sawed trench 563 is approximately 200 μm.

[0040] FIG. 7 illustrates the use of a multi-head inkjet printer during fabrication of the QFN of FIG. 1. As described above, the pre-tin plating material 565 can be an ink containing silver (Ag) nanoparticles. In this case, the dispenser 564 can be a single- or multi-nozzle inkjet dispenser. In some embodiments, the inkjet dispenser 564 can have, for example, 500-1000 inkjet nozzles. A reducing gas, such as formic acid, can be used to clean exposed copper contact sidewall surfaces before and / or during deposition of the nano-Ag ink.

[0041] FIG. 8 illustrates a cross-sectional side view of the QFN 100 of FIG. 1 soldered onto a PCB 810. The QFN includes a leadframe having a thermal pad 104 and a set of contacts, represented by contacts 102 and 103, surrounding the thermal pad 104. Each of the contacts has an exposed surface on the bottom side of the QFN package 100 and an exposed sidewall. For example, contact 102 has an exposed lower surface 813 on the bottom side of the QFN package 100 and an exposed contact sidewall 814. Similarly, contact 103 has an exposed lower surface 823 on the bottom side of the QFN package 100 and an exposed contact sidewall 824. Each contact sidewall surface is pre-tinned using a process described in more detail with respect to FIGS. 5A-5G. An IC die 341 is attached to the thermal pad 104 using a known or later-developed die attach material 854.

[0042] Contact 102 is connected to pad 816 on PCB 810 by solder 815. Similarly, contact 103 is connected to pad 826 on PCB 810 by solder 825. Thermal pad 104 may be connected to pad 831 by solder 830. PCB 810 mechanically supports and electrically connects electronic components using conductive tracks, pads, and other features etched from copper sheets laminated onto a non-conductive substrate. Components (e.g., capacitors, resistors, or active devices) are typically soldered onto the PCB. Advanced PCBs may include components embedded in the substrate.

[0043] The PCB 810 can be single-sided (one copper layer), double-sided (two copper layers), or multi-layer (outer and inner layers). Conductors on different layers can be connected with vias. While glass epoxy is the primary insulating substrate, various embodiments can use various types of known or later-developed PCBs.

[0044] As described in more detail above, pre-tinning the contact sidewall surfaces of QFN 100, such as contact sidewall surfaces 814, 824, allows each contact solder joint to wick up the contact sidewall surface and form a fillet, as shown by solder joints 815, 825. AVI can then reliably determine whether a proper solder joint has been formed.

[0045] 9 is a flowchart illustrating the fabrication of a QFN IC. A semiconductor wafer may be fabricated to form a set of integrated circuits, which may be singulated into individual dies using known or later developed processing techniques, as shown in box 900.

[0046] The set of dies may then be attached to a single leadframe strip, as indicated by box 902, and wire bonded to contacts on the leadframe strip using any known or later developed die attach process.

[0047] The entire leadframe strip may then be encapsulated with a molding compound, as indicated at box 904, using any known or later developed encapsulating material.

[0048] As shown in box 906, the encapsulated leadframe strip is partially sawn to form partially sawn trenches between each individual leadframe, as described in more detail with respect to Figures 4 and 5B. Each partially sawn trench is deep enough to completely separate the contacts between adjacent individual leadframes and remove the sacrificial strip of metal between each contact, but shallow enough so that the encapsulated leadframe strip remains in one piece.

[0049] A pre-tin plating material may be dispensed from a dispenser into the partially sawed trenches, as shown in box 908. The pre-tin plating material may be a solder paste, which may include flux, an ink containing silver (Ag) nanoparticles, etc. A reducing gas, such as formic acid, may be used to clean the exposed copper contact sidewall surfaces before and / or during deposition of the nano-Ag ink.

[0050] As shown in box 910, a baking process may be performed in which the deposited pre-tin plated material is heated, reflows, and wicks up and wets the contact sidewall surfaces of the contacts, thereby forming a pre-tin plated layer covering the entire contact sidewall surface of each contact.

[0051] A backside fill process may be performed, as indicated by box 912, in which the partially sawed trenches may be filled with a fill material. The fill material may be, for example, an epoxy compound similar to the molding compound used in step 904. The fill material may be applied, for example, using a known or later-developed printing process. Filling the partially sawed trenches may result in a final QFN package having smooth sides, for example.

[0052] As shown in box 914, a sawing process may be performed to singulate the encapsulated leadframe strip into individual QFN packages by sawing completely between each individual leadframe using a known or later-developed sawing process. The partially sawed trenches formed in step 906 have a width wide enough to remove the sacrificial metal strip between each of the contacts that provided mechanical support prior to encapsulation. The final sawing process is selected to produce a kerf having a width narrower than the width of the partially sawed trenches, such that at least a portion of the pre-tinned layer remains on the contact sidewall surfaces of the contacts.

[0053] Previous solutions to the problem of contact sidewall oxidation involved a partial cut that did not completely separate adjacent contacts, followed by an electroplating operation. Complete separation of the contacts was not possible due to the electrical conductivity required for each contact to be electroplated. Thus, after singulation, a portion of the contact sidewall surface was bare copper that had been oxidized. Embodiments overcome the problems resulting from oxidation of only a portion of the contact sidewall surface.

[0054] Other Examples Although nano-Ag ink is described herein as the pre-tinned material, other types of conductive inks may be used, such as tin nanoparticles, gold nanoparticles, etc.

[0055] Although one exemplary embodiment based on a QFN package is described herein, other embodiments may use other leadless configurations such as a dual flat no-lead package (DFN), a single flat no-lead package, a top exposed pad leadless package, a thin leadless package, and an ultra thin leadless package.

[0056] Although sawing is described herein to singulate the completed leadframe strips, alternative embodiments may use other techniques for singulation, such as laser cutting, water jet cutting, etc.

[0057] Although copper leadframe strips are described herein, other embodiments may use leadframes constructed from other conductive metallic or non-metallic materials that are subject to oxidation.

[0058] Although tin plating of the leadframe surface is described herein to protect the exposed contact underside surfaces, alternative embodiments may treat the surface of the leadframe strip with another material that prevents oxidation of the leadframe surface and is solder wettable.

[0059] Although a glass epoxy printed circuit board is described herein which may have several interconnect layers, other embodiments may use a different substrate such as multi-layer ceramic.

[0060] In this description, the term "couple" and its derivatives refer to an indirect, direct, optical, and / or wireless electrical connection. Thus, if a first device couples to a second device, the connection may be through a direct electrical connection, through an indirect electrical connection via other devices and connections, through an optical electrical connection, and / or through a wireless electrical connection.

[0061] Although method steps may be presented and described herein sequentially, one or more of the steps shown and described may be omitted, repeated, performed simultaneously, and / or performed in a different order than shown and / or described herein. Thus, embodiments are not limited to the particular order of steps shown and / or described herein.

[0062] Modifications may be made to the exemplary embodiments described, and other embodiments are possible, within the scope of the claims of the invention.

Claims

1. 1. An integrated circuit (IC) package comprising: an encapsulated package including an integrated circuit die attached to a lead frame; a set of contacts each having a contact sidewall surface and a contact underside surface; a protective layer of pre-tinned material covering each contact sidewall surface, the protective layer of pre-tinned material having a surface flush with the sidewall surface of the encapsulated package; An IC package comprising:

2. 2. The IC package of claim 1, The protective layer of the pre-tinned material comprises silver nanoparticles.

3. 2. The IC package of claim 1, The protective layer of pre-tinned material is solder.

4. 2. The IC package of claim 1, The IC package wherein the lead frame is copper.

5. 2. The IC package of claim 1, An IC package in which the underside surface of each contact is covered with tin plating.

6. 1. An integrated circuit package comprising: an encapsulated package including an integrated circuit die attached to a lead frame; a set of contacts each having a contact sidewall surface and a contact underside surface, the contact sidewall surfaces being covered by a layer of pre-tinned material; Including, The layer of pre-tinned material has a surface that is flush with a sidewall surface of the encapsulated package.

7. 7. The integrated circuit package of claim 6, an integrated circuit package, wherein the integrated circuit die includes electrical contacts electrically connected to respective ones of the set of contacts;

8. 8. An integrated circuit package according to claim 6 or 7, The integrated circuit package, wherein the layer of pre-tinned material comprises silver nanoparticles.

9. 8. An integrated circuit package according to claim 6 or 7, The integrated circuit package wherein the layer of pre-tinned material is solder.

10. 8. An integrated circuit package according to claim 6 or 7, The integrated circuit package, wherein the layer of pre-tinned material is deposited using an inkjet printer.

11. 8. An integrated circuit package according to claim 6 or 7, An integrated circuit package wherein the lead frame is copper.

12. 8. An integrated circuit package according to claim 6 or 7, An integrated circuit package in which the underside surface of each contact is covered with tin plating.

13. 1. An integrated circuit (IC) package comprising: an encapsulated package including an integrated circuit die attached to a lead frame; a set of contacts each having a contact sidewall surface and a contact lower surface; a protective layer covering each contact sidewall surface, the protective layer having a surface flush with the sidewall surface of the encapsulated package, the protective layer including flux; An IC package comprising:

14. 14. The IC package of claim 13, The IC package, wherein the protective layer further comprises silver nanoparticles.

15. 14. The IC package of claim 13, The IC package, wherein the protective layer is solder.

16. 14. The IC package of claim 13, The IC package wherein the lead frame is copper.

17. 14. The IC package of claim 13, An IC package in which the underside surface of each contact is covered with tin plating.

18. 1. An integrated circuit package comprising: an encapsulated package including an integrated circuit die attached to a lead frame; a set of contacts each having a contact sidewall surface and a contact underside surface, the contact sidewall surfaces being covered with a layer of pre-tinned material including a flux; Including, The layer of pre-tinned material has a surface that is flush with a sidewall surface of the encapsulated package.

19. 20. The integrated circuit package of claim 18, an integrated circuit package, wherein the integrated circuit die includes electrical contacts electrically connected to respective ones of the set of contacts;

20. 20. An integrated circuit package according to claim 18 or 19, comprising: The integrated circuit package, wherein the layer of pre-tinned material further comprises silver nanoparticles.

21. 20. An integrated circuit package according to claim 18 or 19, comprising: The integrated circuit package wherein the layer of pre-tinned material is solder.

22. 20. An integrated circuit package according to claim 18 or 19, comprising: An integrated circuit package wherein the lead frame is copper.

23. 20. An integrated circuit package according to claim 18 or 19, comprising: The integrated circuit package wherein the lower surfaces of the contacts are covered with a tin plating.

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