Semiconductor device with lateral superjunction field-effect transistor

Abstract

A semiconductor device comprising: a substrate (1) of a first conductivity type serving as a base of the semiconductor device; a high-voltage junction field-effect transistor (JFET) on the substrate (1), the JFET including a plurality of parallel conductive layers (p; n); a first conductive layer (n1) of a second conductivity type of parallel conductive layers (p; n) extending on the substrate (1, 2); and a plurality of layers for forming a parallel conductive layer having a channel formed by a plurality of doped epitaxial layers (n2 - n6) of the second conductivity type having a plurality of gate layers (p1 - p5) of the first conductivity type on both sides thereof are disposed above the first conductive layer (n1) of the second conductivity type, and the lowermost layer (p1) of the first conductivity type is arranged in the form of continuous dots (5) having different lengths and distances (6) between them. Representative drawing: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device comprising a lateral superjunction field effect transistor, JFET, which can be realized by stacking multiple n-type and p-type layers alternately on top of each other and connecting them in parallel. [Background technology]

[0002] Such devices have already been described in many patent documents, for example, U.S. Pat. No. 11,031,480 (US11,031,480 B2), U.S. Patent Application Publication No. 2019 / 01986091 (US2019 / 0198609A1), U.S. Patent Application Publication No. 2017 / 0222043 (US2017 / 0222043A1), and U.S. Patent Application Publication No. 2011 / 0127606 (US2011 / 0127606A1).

[0003] The alternating n- and p-layer stacks, if charge-matched, can completely deplete each other and create a uniform electric field within the material with near-optimal use of the material in terms of breakdown voltage. The alternating n- and p-layer stacks must be terminated at the bottom, rotating the electric field by 90 degrees because the substrate is grounded and has a constant potential along the entire drift region. This locally increases the electric field, and this increase in field induces a lower electrical breakdown than the breakdown within the stack. Several different approaches to shaping the electric field have been proposed.

[0004] US Patent Application Publication No. 2011 / 0127606 proposes an n-buffer layer (160) located below the bottom channel, between the source and drain, or partially between the source and drain (160-1). Another proposal is to place a floating n+ region (661) in the substrate below the drain to shield it from high electric fields.

[0005] US Patent Application Publication No. 2017 / 0222043 also proposes diffused p-regions (253) and / or diffused n-regions (252) under the source and drain, respectively, to shape the electric field and reduce the maximum electric field.

[0006] US Patent Application Publication No. 2019 / 01986091 proposes a region (202) whose thickness increases linearly or non-linearly from source to drain, also intended to shape the electric field.

[0007] The stack of n and p layers has already been shown in some of the above-cited documents. Typically, the bottom channel abruptly terminates at the drain, with the substrate below the channel acting as both the bottom gate and the substrate that must support the breakdown voltage of the device. Within the channel, the electric field is entirely lateral, but because the backside is grounded, it must rotate vertically below the drain. This means that the field must rotate 90 degrees below the bottom channel in the substrate. Without further ado, the electric field profile from source to drain forms a U-shape with the highest field near the drain. This U-shape means that the electric field is not uniformly distributed, resulting in a lower breakdown voltage than would otherwise be possible.

[0008] The object of the present invention is to alleviate the above drawbacks and to obtain a higher breakdown voltage. Summary of the Invention

[0009] This object is achieved by a device according to the invention, in which the bottom layer of a first conductivity type is arranged in the form of dots having different lengths and distances between deep poly trenches of a second conductivity type at the bottom of the JFET. Further improvements can be obtained through the devices defined in the dependent claims. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a diagram showing a first embodiment of the present invention. [Figure 2] FIG. 2 shows a second embodiment of a further development of the invention. DETAILED DESCRIPTION OF THE INVENTION

[0011] The present invention will now be described with reference to some non-limiting embodiments of semiconductor devices, focusing on the JFET portion as shown in the accompanying drawings, in which Figure 1 shows a first embodiment of the invention and Figure 2 shows a second embodiment of a further development of the invention.

[0012] FIG. 1 illustrates the present invention, starting with a heavily doped substrate 1 of a first conductivity type connected to a grounded back contact. A thick, lightly doped layer 2 of the first conductivity type is epitaxially grown on the substrate. The thickness of the epitaxial layer must be large enough to support the breakdown voltage of the device. A layer n1 of a second conductivity type is epitaxially grown on the lightly doped layer 2 of the first conductivity type. An implantation mask is placed on the epitaxial layer n1, and an ion implantation is performed to form a masked layer p1 of the first conductivity type. By splitting the layer and varying the length and distance of the resulting p-region in the masked layer p1 of the first conductivity type, the effective amount of charge of the first conductivity type is reduced toward the drain side D of the structure. This reduces the electric field near the drain, resulting in a more uniform electric field and a higher breakdown voltage. On top of the structure, an epitaxial layer n2 of the second conductivity type is now placed, and a first gate of the first conductivity type is buried or epitaxially grown on the channel n2. These two layers are then repeated upwards, as shown in several prior publications, e.g., the patent documents cited above.

[0013] Deep trenches are etched from the surface and then filled with highly doped silicon. Shown in the figure are two filled trenches 3 of a second conductivity type connecting channels n2-n6 of the second conductivity type. A filled trench 4 of a first conductivity type is used to connect layers p1-p5 of the first conductivity type. Gates p2-p5 are connected to ground in the third dimension, for example, by forming an interruption in the source trench as shown in U.S. Pat. No. 11,031,480, or by forming a filled trench pillar of the first conductivity type as shown in U.S. Patent Application Publication No. 2019 / 0198609 and U.S. Patent Application Publication No. 2017 / 022043.

[0014] A semiconductor device according to the invention can be combined with a further insulating region X disposed on the substrate to the left of the components shown in the figure, containing logic and analog control functions isolated on either side by deep polycrystalline trenches 4 of the first conductivity type. Such a semiconductor device is disclosed, for example, in U.S. Pat. No. 11,031,480.

[0015] Preferably, successive dots 5 of different lengths have a length that decreases in the direction towards the drain side D of the structure, and the distance 6 between the dots 5 increases in the direction towards the drain side D of the structure.

[0016] The whole structure is mirrored around a line of symmetry L which allows for a high voltage on the drain trench.

[0017] Figure 2 shows a modified device in which gate layers p2-p5 are fabricated by ion implantation through a photoresist mask, creating interruptions 7 in the first conductivity type layers p2-p5. The doping of the interruptions is the same as that of the adjacent second conductivity type channel regions n2-n5. The interruptions 7 are evenly distributed along the drift region. The interruptions 7 within the layers divide the region into several shorter regions 8 of the first conductivity type. The leftmost of the shorter regions is connected to ground as described above, while the others are floating. For small drain voltages, the floating regions of the first conductivity type deplete a smaller channel region than a long p-gate connected to ground along the entire drift region. This increases the current through the device for low drain voltages. For higher voltages, current flows through the shorter regions, connecting them together.

[0018] For this to happen, the length of the interruptions 7 must not be too large. For example, the distance 7 between the regions 8 can be about 0.3 μm and the length of the regions 8 can be about 5 μm.

[0019] In the drawings, the device according to the invention is illustrated in the case where the first conductivity type is p-type and the second conductivity type is n-type, however, the device according to the invention can also be realized where the first conductivity type is n-type and the second conductivity type is p-type.

Claims

1. a substrate (1) of a first conductivity type that forms the base of the semiconductor device; a lateral high voltage superjunction field effect transistor (JFET) on said substrate (1), said JFET comprising a plurality of parallel conductive layers (p; n), said JFET being isolated by a deep polycrystalline trench (4) of a first conductivity type on the source side (S) of said JFET; a first conductive layer (n1) of the second conductivity type of the parallel conductive layers (p; n) extending on the substrate (1, 2); On top of the first conductive layer (n1) of the second conductivity type are arranged a plurality of layers which together with the first conductive layer form the parallel conductive layer having a channel formed by a plurality of doped epitaxial layers (n2-n6) of the second conductivity type having on either side thereof a plurality of gate layers (p1-p5) of the first conductivity type; 1. A semiconductor device comprising: a first conductivity type semiconductor layer having a first conductivity type and a second conductivity type; a first conductivity type semiconductor layer having a first conductivity type and a second conductivity type semiconductor layer having a first conductivity type and a second conductivity type semiconductor layer having a second conductivity type; a second conductivity type semiconductor layer having a second conductivity type and a third conductivity type semiconductor layer having a second conductivity type; a second conductivity type semiconductor layer having a second conductivity type and a third conductivity type semiconductor layer having a second conductivity type and a fourth ...

2. A semiconductor device as described in claim 1, characterized in that the conductive layers (p2-p5) of the first conductivity type on the bottom layer (p1) have contiguous regions (8) having different lengths and distances (7) between each region and the deep polycrystalline trench (3) of the second conductivity type, thereby increasing the current passing through the semiconductor device for low drain voltages.

3. 2. The semiconductor device of claim 1, further comprising an insulating region (X) disposed on the substrate, the insulating region (X) comprising logic and analog control functions and insulated on both sides by the deep polycrystalline trench (4) of the first conductivity type.

4. 4. The semiconductor device according to claim 1, wherein the first conductivity type is p-type and the second conductivity type is n-type.

5. 4. The semiconductor device according to claim 1, wherein the first conductivity type is n-type and the second conductivity type is p-type.

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