Semiconductor Devices

Abstract

To provide a semiconductor device in which deformation of a connection member caused by pressure applied during sintering is suppressed, and a manufacturing method thereof.SOLUTION: A semiconductor device A1 includes a semiconductor element 10A having a principal surface electrode 11 (first electrode 111) formed on an element principal surface 101 of an element 10 and a back surface electrode 12 formed on an element back surface 102, a conductive member 22A facing the element back surface and having the back surface electrode conductively bonded via an element bonding layer 31A, an other conductive member disposed apart from the conductive member 22A and conductive to the principal surface electrode 11, and a lead member having a lead principal surface 51a facing the same direction as the element principal surface and including a connecting portion 513 connecting the principal surface electrode and the other conductive member. The lead member includes a protrusion 521 protruding from the lead principal surface 51a in a thickness direction z by a height H521, and is bonded to the principal surface electrode via a lead bonding layer 321. The protrusion overlaps the principal surface electrode when viewed in the thickness direction z. This configuration can suppress deformation of a connection member due to pressure during sintering.SELECTED DRAWING: Figure 13

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same. [Background technology]

[0002] Conventionally, lead solder has been used as a bonding material for bonding semiconductor elements to conductors due to its ease of use. However, from the perspectives of protecting the human body and reducing environmental impact, lead-free bonding materials are gradually replacing it. For example, Patent Document 1 discloses a semiconductor device using sintered metal as a bonding material. The semiconductor device described in Patent Document 1 includes a die, a lead frame, a clip, and sintered silver. The die is mounted on the lead frame. The lead frame includes a first portion and a second portion spaced apart from each other. The die is bonded to the first portion of the lead frame. The clip is a plate-shaped conductor. The clip is a connecting member that electrically connects the die and the second portion of the lead frame. The clip includes a first bonding portion bonded to the die, a second bonding portion bonded to the second portion of the lead frame, and a connecting portion connecting these bonding portions. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Special Publication No. 2018-504788 Summary of the Invention [Problem to be solved by the invention]

[0004] In conventional semiconductor devices, when joining a clip and a die, a sintering metal material (a sinterable silver film) formed between the clip and the die is sintered, and the sintering metal material is converted into sintered metal (sintered silver), thereby joining the clip and the die. In this sintering process, the clip is pressed with a pressure member, and the sintering metal material is pressurized by this pressure. Then, while pressed, the sintering metal material is heat-treated. In conventional semiconductor devices, because the connecting portion is hollow below the connecting portion, the pressing force applied during the sintering process can sometimes cause the connecting portion of the clip to bend. This deformation can lead to a decrease in the strength and conductivity of the clip, unintended contact, and other problems.

[0005] The present disclosure has been devised in view of the above-mentioned problems, and its purpose is to provide a semiconductor device and a manufacturing method thereof that can suppress deformation of connecting members due to pressure applied during sintering. [Means for solving the problem]

[0006] A semiconductor device provided by a first aspect of the present disclosure includes: a semiconductor element having an element main surface and an element back surface facing opposite to each other in a first direction, with a main surface electrode formed on the element main surface and a back surface electrode formed on the element back surface; a first conductor facing the element back surface and having the back surface electrode conductively joined; a second conductor arranged at a distance from the first conductor and conductively joined to the main surface electrode; and a connection member having a connection member main surface facing the same direction as the element main surface and connecting the main surface electrode and the second conductor, wherein the connection member includes a first protrusion protruding from the connection member main surface in the first direction and is joined to the main surface electrode via a first bonding layer, and the first protrusion overlaps the main surface electrode when viewed in the first direction.

[0007] A manufacturing method of a semiconductor device provided by a second aspect of the present disclosure comprises a semiconductor element having an element main surface and an element back surface facing opposite each other in a first direction, a first conductor and a second conductor arranged at a distance from each other, and a connection member having a connection member main surface facing one side of the first direction and including a first protrusion protruding from the connection member main surface in the first direction, and includes a connection member preparation process for preparing the connection member, a mounting process for mounting the semiconductor element on the first conductor, a sintering metal material formation process for forming a sintering metal material on the element main surface, a connection process for placing a portion of the connection member on the sintering metal material so that the connection member main surface faces in the same direction as the element main surface and so that the sintering metal material and the first protrusion overlap when viewed in the first direction, and a pressure and heating process for converting the sintering metal material into a sintered metal by pressing and heating the connection member with a pressure member from the side where the first protrusion is formed. [Effects of the Invention]

[0008] According to the semiconductor device and the manufacturing method thereof of the present disclosure, deformation of the connection member due to pressure applied during the sintering process can be suppressed. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a perspective view showing a semiconductor device according to a first embodiment. [Figure 2] The sealing resin is omitted from the perspective view shown in FIG. [Figure 3] FIG. 1 is a plan view showing a semiconductor device according to a first embodiment. [Figure 4] In the plan view shown in FIG. 3, the sealing resin is omitted. [Figure 5] FIG. 5 is a partially enlarged view of a part of FIG. 4. [Figure 6] FIG. 1 is a front view showing a semiconductor device according to a first embodiment. [Figure 7] FIG. 2 is a bottom view showing the semiconductor device according to the first embodiment. [Figure 8]FIG. 1 is a left side view showing a semiconductor device according to a first embodiment. [Figure 9] FIG. 1 is a right side view showing a semiconductor device according to a first embodiment. [Figure 10] FIG. 5 is a cross-sectional view taken along line XX in FIG. [Figure 11] FIG. 3 is an enlarged view of a main part of FIG. 2. [Figure 12] FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. [Figure 13] FIG. 13 is a partially enlarged view of a part of FIG. [Figure 14] FIG. 13 is a partially enlarged view of a part of FIG. [Figure 15] FIG. 3 is a diagram showing a step (lead preparation step) of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 16] FIG. 3 is a diagram showing a step (pressure and heat step) of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 17] FIG. 3 is a diagram showing a step (pressure and heat step) of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 18] FIG. 10 is an enlarged view showing a main part of a lead member according to a modified example. [Figure 19] FIG. 10 is a perspective view showing a semiconductor device according to a second embodiment. [Figure 20] FIG. 10 is a plan view showing a semiconductor device according to a second embodiment. [Figure 21] FIG. 21 is a partially enlarged view of a part of FIG. 20. [Figure 22] FIG. 22 is a cross-sectional view taken along line XXII-XXII in FIG. 20. [Figure 23] FIG. 23 is a partially enlarged view of a part of FIG. 22. [Figure 24] FIG. 10 is an enlarged cross-sectional view of a main part of a semiconductor device according to a modified example of the second embodiment. [Figure 25] FIG. 10 is an enlarged cross-sectional view of a main part of a semiconductor device according to a modified example of the second embodiment. [Figure 26] FIG. 10 is a perspective view showing a semiconductor device according to a third embodiment. [Figure 27]FIG. 10 is a plan view showing a semiconductor device according to a fourth embodiment. [Figure 28] FIG. 28 is a cross-sectional view taken along line XXVIII-XXVIII in FIG. 27. [Figure 29] FIG. 10 is a perspective view showing a semiconductor device according to a fifth embodiment. [Figure 30] FIG. 30 is a cross-sectional view taken along the line XXX-XXX in FIG. 29. [Figure 31] 10 is an enlarged view of a main part showing a protrusion of a lead member according to a modified example. FIG. [Figure 32] 10 is an enlarged view of a main part showing a protrusion of a lead member according to a modified example. FIG. [Figure 33] 10A and 10B are enlarged views of essential parts showing a method for joining lead members according to a modified example. DETAILED DESCRIPTION OF THE INVENTION

[0010] The semiconductor device and the method for manufacturing the semiconductor device according to the present disclosure will be described below with reference to the drawings.

[0011] 1 to 14 show a semiconductor device according to a first embodiment of the present disclosure. The semiconductor device A1 of the first embodiment includes a plurality of semiconductor elements 10, a support substrate 20, a plurality of conductive bonding layers 3, input terminals 41 and 42, an output terminal 43, a pair of gate terminals 44A and 44B, a pair of detection terminals 45A and 45B, a plurality of dummy terminals 46, a pair of side terminals 47A and 47B, an insulating member 49, a plurality of lead members 51, a plurality of wire members 6, and a sealing resin 7. Note that the input terminals 41 and 42, the output terminal 43, the pair of gate terminals 44A and 44B, the pair of detection terminals 45A and 45B, the plurality of dummy terminals 46, and the pair of side terminals 47A and 47B may be collectively referred to as terminals 40.

[0012] FIG. 1 is a perspective view showing the semiconductor device A1. FIG. 2 is a view in which the sealing resin 7 is omitted from the perspective view shown in FIG. 1. FIG. 3 is a plan view showing the semiconductor device A1. FIG. 4 is a view in which the sealing resin 7 is omitted from the plan view shown in FIG. 3. In FIG. 4, the sealing resin 7 is indicated by an imaginary line (two-dot chain line). FIG. 5 is a partially enlarged plan view of a portion of FIG. 4. FIG. 6 is a front view showing the semiconductor device A1. FIG. 7 is a bottom view showing the semiconductor device A1. FIG. 8 is a side view (left side view) showing the semiconductor device A1. FIG. 9 is a side view (right side view) showing the semiconductor device A1. FIG. 10 is a cross-sectional view taken along line XX in FIG. 4. FIG. 11 is an enlarged view of a main part of the perspective view shown in FIG. 2, including the lead member 51. FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. 11. FIG. 13 is a partially enlarged view of a portion of FIG. 12. FIG. 14 is a partially enlarged view of a portion of FIG. 12. 11 to 13, the wire members 6 are omitted.

[0013] For ease of explanation, in FIGS. 1 to 14, three mutually orthogonal directions are defined as a width direction x, a depth direction y, and a thickness direction z. The width direction x is the left-right direction in the plan view of the semiconductor device A1 (see FIGS. 3 and 4). The depth direction y is the up-down direction in the plan view of the semiconductor device A1 (see FIGS. 3 and 4). Note that, as necessary, one of the width directions x is referred to as the width direction x1, and the other of the width directions x is referred to as the width direction x2. Similarly, one of the depth directions y is referred to as the depth direction y1, the other as the depth direction y2, and one of the thickness directions z is referred to as the thickness direction z1, and the other as the thickness direction z2. Furthermore, the thickness direction z1 may sometimes be referred to as the bottom, and the thickness direction z2 may sometimes be referred to as the top. The thickness direction z corresponds to the "first direction" in the present disclosure. Furthermore, in this embodiment, the width direction x corresponds to the "third direction" in the present disclosure, and the depth direction y corresponds to the "second direction" in the present disclosure.

[0014] Each of the semiconductor elements 10 is made of a semiconductor material primarily composed of SiC (silicon carbide). The semiconductor material is not limited to SiC and may be Si (silicon), GaAs (gallium arsenide), GaN (gallium nitride), or the like. In this embodiment, each semiconductor element 10 is a metal-oxide-semiconductor field-effect transistor (MOSFET). The semiconductor elements 10 are not limited to MOSFETs and may be field-effect transistors including metal-insulator-semiconductor FETs (MISFETs), bipolar transistors such as insulated gate bipolar transistors (IGBTs), or IC chips such as large-scale integrated circuits (LSIs). In this embodiment, each semiconductor element 10 is the same element and is an n-channel MOSFET. Each semiconductor element 10 has a rectangular shape when viewed in the thickness direction z (hereinafter also referred to as "planar view"), but is not limited thereto. Each semiconductor element 10 has a thickness of approximately 350 to 370 μm. However, the thickness of each semiconductor element 10 is not limited to this.

[0015] As shown in FIGS. 10 and 13, each of the multiple semiconductor elements 10 has an element main surface 101 and an element back surface 102. Although FIGS. 10 and 13 show a semiconductor element 10A, the semiconductor element 10B has an equivalent configuration. In each semiconductor element 10, the element main surface 101 and the element back surface 102 are spaced apart in the thickness direction z and face opposite each other. In this embodiment, the element main surface 101 faces the thickness direction z2, and the element back surface 102 faces the thickness direction z1.

[0016] Each of the plurality of semiconductor elements 10 has a main surface electrode 11, a back surface electrode 12, and an insulating film 13, as shown in FIGS.

[0017] The principal surface electrode 11 is provided on the element principal surface 101. As shown in FIG. 11 , the principal surface electrode 11 includes a first electrode 111 and a second electrode 112. In this embodiment, the first electrode 111 is a source electrode through which a source current flows. In addition, in this embodiment, the second electrode 112 is a gate electrode through which a gate voltage for driving each semiconductor element 10 is applied. The first electrode 111 is larger than the second electrode 112. In addition, although this embodiment shows a case where the first electrode 111 is configured as a single region, it may be divided into multiple regions.

[0018] The back electrode 12 is provided on the back surface 102 of the device. In this embodiment, the back electrode 12 is formed over the entire back surface 102 of the device. In this embodiment, the back electrode 12 is a drain electrode through which a drain current flows.

[0019] The insulating film 13 is provided on the element principal surface 101. The insulating film 13 has electrical insulation properties. The insulating film 13 surrounds the principal surface electrode 11 in a plan view. The insulating film 13 is formed by laminating, for example, a SiO2 (silicon dioxide) layer, a SiN4 (silicon nitride) layer, and a polybenzoxazole layer in this order from the element principal surface 101. Note that the insulating film 13 may be a polyimide layer instead of the polybenzoxazole layer.

[0020] The multiple semiconductor elements 10 include multiple semiconductor elements 10A and multiple semiconductor elements 10B. In this embodiment, the semiconductor device A1 configures a half-bridge switching circuit. The multiple semiconductor elements 10A configure an upper arm circuit in this switching circuit, and the multiple semiconductor elements 10B configure a lower arm circuit in this switching circuit. As shown in FIGS. 2 and 4, the semiconductor device A1 includes four semiconductor elements 10A and four semiconductor elements 10B. Note that the number of semiconductor elements 10 is not limited to this configuration and can be freely set depending on the performance required of the semiconductor device A1.

[0021] As shown in FIGS. 2, 4, 5, 11, and 13, each of the multiple semiconductor elements 10A is mounted on a support substrate 20 (a conductive member 22A, which will be described later). In this embodiment, the multiple semiconductor elements 10A are aligned in the depth direction y and spaced apart from one another. When each semiconductor element 10A is mounted on the conductive member 22A, the element back surface 102 faces the conductive member 22A. As shown in FIGS. 4, 5, 12, and 13, each semiconductor element 10A is conductively bonded to the support substrate 20 (the conductive member 22A) via a conductive bonding layer 3 (an element bonding layer 31A, which will be described later).

[0022] As shown in FIGS. 2, 4, 5, and 10, each of the multiple semiconductor elements 10B is mounted on a support substrate 20 (a conductive member 22B described later). In this embodiment, the multiple semiconductor elements 10B are aligned in the depth direction y and spaced apart from one another. When each semiconductor element 10B is mounted on the conductive member 22B, the element back surface 102 faces the conductive member 22B. As shown in FIGS. 4, 5, and 10, each semiconductor element 10B is conductively bonded to the support substrate 20 (the conductive member 22B) via a conductive bonding layer 3 (an element bonding layer 31B described later).

[0023] The support substrate 20 is a support member that supports a plurality of semiconductor elements 10. The support substrate 20 includes an insulating substrate 21, a plurality of conductive members 22, a pair of insulating layers 23A and 23B, a pair of gate layers 24A and 24B, and a pair of detection layers 25A and 25B.

[0024] As shown in Fig. 10, insulating substrate 21 has a plurality of conductive members 22 arranged thereon. Insulating substrate 21 has electrical insulation properties. The constituent material of insulating substrate 21 is, for example, ceramics with excellent thermal conductivity. Examples of such ceramics include AlN (aluminum nitride), SiN (silicon nitride), and Al2O3 (aluminum oxide). In this embodiment, insulating substrate 21 has a rectangular shape in a plan view.

[0025] As shown in FIG. 10 , the insulating substrate 21 has a main surface 211 and a back surface 212. The main surface 211 and the back surface 212 are spaced apart in the thickness direction z and face opposite directions. The main surface 211 faces the side in the thickness direction z where the multiple conductive members 22 are arranged, i.e., the thickness direction z2. The main surface 211, along with the multiple conductive members 22 and the multiple semiconductor elements 10, is covered by the sealing resin 7. The back surface 212 faces the thickness direction z1. As shown in FIGS. 7 and 10 , the back surface 212 is exposed from the sealing resin 7. A heat sink (not shown), for example, is connected to the back surface 212. The configuration of the insulating substrate 21 is not limited to that described above, and the insulating substrate 21 may be provided individually for each of the multiple conductive members 22.

[0026] Each of the plurality of conductive members 22 is a metal plate. The metal plate is made of Cu or a Cu alloy. The plurality of conductive members 22, together with the plurality of terminals 40, form conductive paths with the plurality of semiconductor elements 10. The plurality of conductive members 22 are spaced apart from one another and are each disposed on the main surface 211 of the insulating substrate 21. Each conductive member 22 is bonded to the main surface 211 with a bonding material such as silver paste or solder. The bonding material may be either a conductive material or an insulating material. In this embodiment, the dimension of the conductive member 22 in the thickness direction z is approximately 0.4 to 3.0 mm, but is not limited to this. The surface of each conductive member 22 may be covered with silver plating.

[0027] The plurality of conductive members 22 include conductive member 22A and conductive member 22B. In this embodiment, conductive members 22A and 22B are aligned in the width direction x on insulating substrate 21. As shown in FIGS. 2, 4, and 10, conductive member 22A is disposed further in the width direction x2 than conductive member 22B. Conductive member 22A has a main surface 221A facing the thickness direction z2, and a plurality of semiconductor elements 10A are mounted on main surface 221A. Conductive member 22B has a main surface 221B facing the thickness direction z2, and a plurality of semiconductor elements 10B are mounted on main surface 221B. In this embodiment, both conductive members 22A and 22B are rectangular in plan view. The configuration of the plurality of conductive members 22 is not limited to that described above and can be modified as appropriate based on the number and arrangement of the plurality of semiconductor elements 10. In this embodiment, the conductive member 22A corresponds to the "first conductor" in the present disclosure, and the conductive member 22B corresponds to the "second conductor" in the present disclosure.

[0028] The pair of insulating layers 23A, 23B have electrical insulation properties and are made of, for example, glass epoxy resin. As shown in FIGS. 2 and 4, the pair of insulating layers 23A, 23B are each strip-shaped and extend in the depth direction y. As shown in FIGS. 2 and 4, the insulating layer 23A is bonded to the main surface 221A of the conductive member 22A. The insulating layer 23A is positioned further in the width direction x2 than the plurality of semiconductor elements 10A. As shown in FIGS. 2 and 4, the insulating layer 23B is bonded to the main surface 221B of the conductive member 22B. The insulating layer 23B is positioned further in the width direction x1 than the semiconductor elements 10B.

[0029] The pair of gate layers 24A, 24B are conductive and are made of, for example, Cu. As shown in FIGS. 2 and 4, the pair of gate layers 24A, 24B are each strip-shaped and extend in the depth direction y. As shown in FIGS. 2 and 4, the gate layer 24A is disposed on the insulating layer 23A. The gate layer 24A is electrically connected to the second electrode 112 (gate electrode) of each semiconductor element 10A via a wire member 6 (a gate wire 61 described later). The gate layer 24B is disposed on the insulating layer 23B as shown in FIGS. 2 and 4. The gate layer 24B is electrically connected to the second electrode 112 (gate electrode) of each semiconductor element 10B via a wire member 6 (a gate wire 61 described later).

[0030] The pair of detection layers 25A, 25B are conductive and made of, for example, Cu. As shown in FIGS. 2 and 4, each of the pair of detection layers 25A, 25B has a strip shape extending in the depth direction y. As shown in FIGS. 2 and 4, the detection layer 25A is disposed on the insulating layer 23A together with the gate layer 24A. In a plan view, the detection layer 25A is located adjacent to the gate layer 24A on the insulating layer 23A and spaced apart from the gate layer 24A. In this embodiment, the detection layer 25A is disposed closer to the semiconductor elements 10A in the width direction x than the gate layer 24A. Therefore, the detection layer 25A is located on the width direction x1 side of the gate layer 24A. Note that the arrangement of the gate layer 24A and the detection layer 25A in the width direction x may be reversed. The detection layer 25A is electrically connected to the first electrode 111 (source electrode) of each semiconductor element 10A via a wire member 6 (a detection wire 62, described later). As shown in FIGS. 2 and 4, the detection layer 25B is disposed on the insulating layer 23B together with the gate layer 24B. In a plan view, the detection layer 25B is located next to the gate layer 24B on the insulating layer 23B and is spaced apart from the gate layer 24B. In this embodiment, the detection layer 25B is disposed closer to the semiconductor elements 10B than the gate layer 24B. Therefore, the detection layer 25B is located on the width direction x2 side of the gate layer 24B. Note that the arrangement of the gate layer 24B and the detection layer 25B in the width direction x may be reversed. The detection layer 25B is electrically connected to the first electrode 111 (source electrode) of each semiconductor element 10B via a wire member 6 (a detection wire 62, described later).

[0031] Each of the base portions 29 is electrically insulating and is made of, for example, ceramic. As shown in FIGS. 2 and 10 , each base portion 29 is bonded to the main surface 221A of the conductive member 22A. In this embodiment, each base portion 29 is rectangular in plan view. The base portions 29 are aligned in the depth direction y and spaced apart from one another. The dimension of each base portion 29 in the thickness direction z is approximately equal to the sum of the dimension of the input terminal 41 in the thickness direction z and the dimension of the insulating member 49 in the thickness direction z. A portion of the input terminal 42 is bonded to each base portion 29, supporting the input terminal 42. Therefore, each base portion 29 stabilizes the posture of the input terminal 42. In this embodiment, the semiconductor device A1 does not necessarily have to include multiple base portions 29.

[0032] Each of the multiple conductive bonding layers 3 is made of sintered metal formed by a sintering process. The constituent material of each conductive bonding layer 3 is, for example, sintered silver, but is not limited thereto and may be other sintered metals such as sintered copper. Each conductive bonding layer 3 is porous with numerous micropores. In this embodiment, the micropores are assumed to be voids, but the micropores may be filled with, for example, epoxy resin. That is, each conductive bonding layer 3 may be sintered metal containing epoxy resin. However, since a high epoxy resin content reduces the conductivity of the conductive bonding layer 3, the epoxy resin content is set taking into account the amount of current in the semiconductor device A1. The conductive bonding layer 3 can be formed by sintering a metal material for sintering. Note that in this embodiment, each conductive bonding layer 3 is shown to have a rectangular shape in the cross-sectional views shown in, for example, FIGS. 12 to 14 , but it may also have a trapezoidal shape, curved sides, or a fillet.

[0033] In this embodiment, the plurality of conductive bonding layers 3 include a plurality of element bonding layers 31A and 31B, a plurality of lead bonding layers 321 and 322, and a plurality of terminal bonding layers 33.

[0034] Each of the multiple element bonding layers 31A is for bonding a corresponding semiconductor element 10A to the conductive member 22A. Each element bonding layer 31A is interposed between the element back surface 102 of each semiconductor element 10A and the conductive member 22A, and electrically connects the back electrode 12 of the semiconductor element 10A to the conductive member 22A. Each element bonding layer 31A has a thickness of approximately 30 μm. However, the thickness of each element bonding layer 31A is not limited to this. In this embodiment, the element bonding layer 31A corresponds to the "third bonding layer" of the present disclosure.

[0035] Each of the plurality of element bonding layers 31B is for bonding a corresponding semiconductor element 10B to the conductive member 22B. Each element bonding layer 31B is interposed between the element back surface 102 of each semiconductor element 10B and the conductive member 22B, and electrically connects the back electrode 12 of the semiconductor element 10B to the conductive member 22B. Each element bonding layer 31B has a thickness of approximately 30 μm, similar to that of each element bonding layer 31A. However, the thickness of each element bonding layer 31B is not limited to this.

[0036] Each of the plurality of lead bonding layers 321 and 322 is for bonding a corresponding lead member 51.

[0037] Each of the plurality of lead bonding layers 321 is intended to bond a portion of each lead member 51 to each semiconductor element 10A. Each lead bonding layer 321 is interposed between the element main surface 101 of each semiconductor element 10A and a portion of each lead member 51 (first bonding portion 511 described below), and provides electrical continuity between the main surface electrode 11 (first electrode 111) of the semiconductor element 10A and the lead member 51. Each lead bonding layer 321 has a thickness of approximately 80 μm. However, the thickness of each lead bonding layer 321 is not limited to this. In this embodiment, the lead bonding layer 321 corresponds to the "first bonding layer" of the present disclosure.

[0038] Each of the plurality of lead bonding layers 322 is intended to bond a portion of each lead member 51 to the conductive member 22B. Each lead bonding layer 322 is interposed between a portion of each lead member 51 (a second bonding portion 512 described below) and a portion of the conductive member 22B, and provides electrical continuity between the lead member 51 and the conductive member 22B. Each lead bonding layer 322 has a thickness of approximately 80 μm. However, the thickness of each lead bonding layer 322 is not limited to this. In this embodiment, the lead bonding layer 322 corresponds to the "second bonding layer" of the present disclosure.

[0039] The multiple terminal bonding layers 33 are used to bond the input terminals 42 to the respective semiconductor elements 10B. Each terminal bonding layer 33 is interposed between a portion of each input terminal 42 (a protruding portion 421c described below) and the element main surface 101 of the semiconductor element 10B, and electrically connects the main surface electrode 11 (first electrode 111) of the semiconductor element 10B to the input terminal 42. Each terminal bonding layer 33 has a thickness of approximately 80 μm. However, the thickness of each terminal bonding layer 33 is not limited to this.

[0040] The two input terminals 41 and 42 are each a metal plate. The metal plate is made of Cu or a Cu alloy. In this embodiment, the dimension of each of the two input terminals 41 and 42 in the thickness direction z is 0.8 mm, but this is not limiting. As shown in FIGS. 4 and 10 , the two input terminals 41 and 42 are located closer to the width direction x2 of the semiconductor device A1. A power supply voltage, for example, is applied between the two input terminals 41 and 42. The power supply voltage may be applied to the input terminals 41 and 42 directly from a power supply (not shown), or may be applied via a bus bar (not shown) connected to sandwich the input terminals 41 and 42. A snubber circuit or the like may also be connected in parallel. The input terminal 41 is a positive electrode (P terminal), and the input terminal 42 is a negative electrode (N terminal). The input terminal 42 is spaced apart from both the input terminal 41 and the conductive member 22A in the thickness direction z.

[0041] As shown in FIGS. 4 and 10, the input terminal 41 has a pad portion 411 and a terminal portion 412.

[0042] The pad portion 411 is a portion of the input terminal 41 that is covered with the sealing resin 7. An end portion of the pad portion 411 on the width direction x1 side is comb-shaped and includes a plurality of comb teeth 411a. Each of the plurality of comb teeth 411a is conductively joined to the main surface 221A of the conductive member 22A. The joining method may be laser welding using a laser beam, ultrasonic joining, or joining using a conductive joining material.

[0043] The terminal portion 412 is a portion of the input terminal 41 that is exposed from the sealing resin 7. As shown in Figs. 7, 9, and 10, the terminal portion 412 extends from the sealing resin 7 in the width direction x2 in plan view.

[0044] As shown in FIGS. 4 and 10, the input terminal 42 has a pad portion 421 and a terminal portion 422.

[0045] The pad portion 421 is a portion of the input terminal 42 that is covered with the sealing resin 7. The pad portion 421 includes a connecting portion 421a, multiple extending portions 421b, and multiple protruding portions 421c. The connecting portion 421a is strip-shaped and extends in the depth direction y. The connecting portion 421a is connected to the terminal portion 422. The multiple extending portions 421b are strip-shaped and extend from the connecting portion 421a in the width direction x1. In this embodiment, each extending portion 421b extends from the connecting portion 421a until it overlaps the semiconductor element 10B in a planar view. The multiple extending portions 421b are aligned in the depth direction y and spaced apart from each other in a planar view. A portion of the surface of each extending portion 421b facing the thickness direction z1 contacts the corresponding base portion 29, and the extending portion 421b is supported by the conductive member 22A via the corresponding base portion 29. The plurality of protrusions 421c are portions that protrude from the tip end portion (edge ​​portion in the width direction x1) of each extension portion 421b in the thickness direction z1 from the extension portion 421b. Each protrusion 421c eliminates the difference in height between the extension portion 421b and the semiconductor element 10B in the thickness direction z. Each protrusion 421c is bonded to the semiconductor element 10B (principal surface electrode 11) via a terminal bonding layer 33.

[0046] The terminal portion 422 is a portion of the input terminal 42 that is exposed from the sealing resin 7. As shown in FIGS. 4 and 10, the terminal portion 422 extends from the sealing resin 7 in the width direction x2 in a plan view. The terminal portion 422 has a rectangular shape in a plan view. As shown in FIGS. 4 and 10, the terminal portion 422 overlaps the terminal portion 412 of the input terminal 41 in a plan view. The terminal portion 422 is spaced apart from the terminal portion 412 in the thickness direction z2. In this embodiment, the shape of the terminal portion 422 is the same as the shape of the terminal portion 412.

[0047] The output terminal 43 is a metal plate. The metal plate is made of, for example, Cu or a Cu alloy. As shown in FIGS. 2 and 4, the output terminal 43 is located closer to the width direction x1 of the semiconductor device A1. The AC power (voltage) converted by the multiple semiconductor elements 10 is output from the output terminal 43.

[0048] As shown in FIGS. 2 and 4, the output terminal 43 includes a pad portion 431 and a terminal portion 432.

[0049] The pad portion 431 is a portion of the output terminal 43 that is covered with the sealing resin 7. A portion of the pad portion 431 on the width direction x2 side is comb-shaped and includes a plurality of comb teeth 431a. Each of the plurality of comb teeth 431a is conductively joined to the main surface 221B of the conductive member 22B. The joining method may be laser welding using a laser beam, ultrasonic joining, or joining using a conductive joining material.

[0050] The terminal portion 432 is a portion of the output terminal 43 that is exposed from the sealing resin 7. The terminal portion 432 extends from the sealing resin 7 in the width direction x1, as shown in FIGS.

[0051] 1 to 7, the pair of gate terminals 44A, 44B are located adjacent to the respective conductive members 22A, 22B in the depth direction y. A gate voltage for driving the plurality of semiconductor elements 10A is applied to the gate terminal 44A. A gate voltage for driving the plurality of semiconductor elements 10B is applied to the gate terminal 44B.

[0052] As shown in FIGS. 4 and 5, each of the pair of gate terminals 44A, 44B has a pad portion 441 and a terminal portion 442. In each of the gate terminals 44A, 44B, the pad portion 441 is covered with the sealing resin 7. As a result, each of the gate terminals 44A, 44B is supported by the sealing resin 7. The surface of the pad portion 441 may be plated with silver, for example. The terminal portion 442 is connected to the pad portion 441 and is exposed from the sealing resin 7. The terminal portion 442 is L-shaped when viewed in the width direction x.

[0053] 1 to 7, the pair of detection terminals 45A, 45B are located adjacent to the pair of gate terminals 44A, 44B in the width direction x. The detection terminal 45A detects the voltage (voltage corresponding to the source current) applied to each of the principal surface electrodes 11 (first electrodes 111) of the multiple semiconductor elements 10A. The detection terminal 45B detects the voltage (voltage corresponding to the source current) applied to each of the principal surface electrodes 11 (first electrodes 111) of the multiple semiconductor elements 10B.

[0054] As shown in FIGS. 4 and 5, each of the pair of detection terminals 45A, 45B has a pad portion 451 and a terminal portion 452. In each of the detection terminals 45A, 45B, the pad portion 451 is covered with the sealing resin 7. As a result, each of the detection terminals 45A, 45B is supported by the sealing resin 7. The surface of the pad portion 451 may be plated with silver, for example. The terminal portion 452 is connected to the pad portion 451 and is exposed from the sealing resin 7. The terminal portion 452 is L-shaped when viewed in the width direction x.

[0055] As shown in FIGS. 1 to 7, the plurality of dummy terminals 46 are located on the opposite side of the pair of gate terminals 44A, 44B with respect to the pair of detection terminals 45A, 45B in the width direction x. In this embodiment, there are six dummy terminals 46. Three of the dummy terminals 46 are located on one side of the width direction x (width direction x2). The remaining three dummy terminals 46 are located on the other side of the width direction x (width direction x1). The plurality of dummy terminals 46 are not limited to the configuration described above. Furthermore, a configuration without the plurality of dummy terminals 46 may be adopted.

[0056] As shown in FIGS. 4 and 5 , each of the multiple dummy terminals 46 has a pad portion 461 and a terminal portion 462. The pad portion 461 of each dummy terminal 46 is covered with the sealing resin 7. As a result, the multiple dummy terminals 46 are supported by the sealing resin 7. The surface of the pad portion 461 may be silver-plated, for example. The terminal portion 462 is connected to the pad portion 461 and is exposed from the sealing resin 7. The terminal portion 462 is L-shaped when viewed in the width direction x. The shape of the terminal portion 462 is the same as the shape of each terminal portion 442 of the pair of gate terminals 44A, 44B and the shape of each terminal portion 452 of the pair of detection terminals 45A, 45B.

[0057] As shown in FIG. 4 , the pair of side terminals 47A, 47B are edge portions of the sealing resin 7 on the depth direction y1 side in a plan view and overlap each edge portion of the sealing resin 7 in the width direction x. The side terminal 47A is joined to the conductive member 22A and is covered with the sealing resin 7 except for its end face facing the width direction x2. The side terminal 47B is joined to the conductive member 22B and is covered with the sealing resin 7 except for its end face facing the width direction x1. In this embodiment, each of the side terminals 47A, 47B entirely overlaps the sealing resin 7 in a plan view. The side terminals 47A, 47B may be joined by laser welding, ultrasonic bonding, or bonding using a conductive bonding material. Each of the side terminals 47A, 47B is partially bent in a plan view and partially bent in the thickness direction z. Note that the configuration of each of the side terminals 47A, 47B is not limited thereto. For example, in a plan view, they may extend so as to protrude from the sealing resin 7. Furthermore, the semiconductor device A1 does not necessarily have to include the side terminals 47A and 47B.

[0058] 1 to 7, the pair of gate terminals 44A, 44B, the pair of detection terminals 45A, 45B, and the plurality of dummy terminals 46 are arranged along the width direction x in a plan view. In the semiconductor device A1, the pair of gate terminals 44A, 44B, the pair of detection terminals 45A, 45B, the plurality of dummy terminals 46, and the pair of side terminals 47A, 47B are all formed from the same lead frame.

[0059] The insulating member 49 has electrical insulation properties and is made of, for example, insulating paper. A portion of the insulating member 49 is a flat plate, and as shown in FIGS. 6, 9, and 10, is sandwiched in the thickness direction z between the terminal portion 412 of the input terminal 41 and the terminal portion 422 of the input terminal 42. In a plan view, the entire input terminal 41 overlaps the insulating member 49. In addition, in a plan view, a portion of the pad portion 421 and the entire terminal portion 422 of the input terminal 42 overlap the insulating member 49. The two input terminals 41 and 42 are insulated from each other by the insulating member 49. A portion of the insulating member 49 (the portion on the width direction x1 side) is covered with the sealing resin 7.

[0060] 4, the insulating member 49 has an intervening portion 491 and an extending portion 492. The intervening portion 491 is interposed between the terminal portion 412 of the input terminal 41 and the terminal portion 422 of the input terminal 42 in the thickness direction z. The intervening portion 491 is entirely sandwiched between the terminal portion 412 and the terminal portion 422. The extending portion 492 extends from the intervening portion 491 in the width direction x2 further than the terminal portion 412 and the terminal portion 422.

[0061] The plurality of lead members 51 connect each semiconductor element 10A and the conductive member 22B. Each lead member 51 has a rectangular shape extending in the width direction x in a plan view. Each lead member 51 is a plate-shaped connecting member. Each lead member 51 corresponds to the "connecting member" in the present disclosure. Each lead member 51 includes a first joint portion 511, a second joint portion 512, and a connecting portion 513.

[0062] The first bonding portion 511 is a portion bonded to the main surface electrode 11 (first electrode 111) of the semiconductor element 10A via the conductive bonding layer 3 (lead bonding layer 321). In a plan view, the first bonding portion 511 overlaps the first electrode 111 of the semiconductor element 10A, the lead bonding layer 321, and the semiconductor element 10A. In this embodiment, the dimension (thickness) of the first bonding portion 511 in the thickness direction z is approximately 160 to 200 μm. However, the thickness of the first bonding portion 511 is not limited to this.

[0063] The second bonding portion 512 is a portion bonded to the conductive member 22B via the conductive bonding layer 3 (lead bonding layer 322). The second bonding portion 512 overlaps the lead bonding layer 322 in a plan view. The thickness of the second bonding portion 512 is greater than the thickness of the first bonding portion 511. In this embodiment, the dimension (thickness) of the second bonding portion 512 in the thickness direction z is approximately 550 to 590 μm. However, the thickness of the second bonding portion 512 is not limited to this.

[0064] The connecting portion 513 is a portion that connects the first bonding portion 511 and the second bonding portion 512. The surface of the connecting portion 513 facing the thickness direction z2 is in contact with the sealing resin 7. The thickness of the connecting portion 513 is the same as the thickness of the first bonding portion 511. Therefore, in this embodiment, the dimension (thickness) of the connecting portion 513 in the thickness direction z is approximately 160 to 200 μm. However, the thickness of the connecting portion 513 is not limited to this. The connecting portion 513 overlaps the first bonding portion 511 when viewed in the width direction x.

[0065] Each lead member 51 has a lead main surface 51a. The lead main surface 51a faces the thickness direction z2. In this embodiment, the lead main surface 51a is substantially flat. The lead main surface 51a includes the surfaces of the first bonding portion 511, the second bonding portion 512, and the connecting portion 513, each facing the thickness direction z2. In this embodiment, the lead main surface 51a corresponds to the "connecting member main surface" of this disclosure.

[0066] Each lead member 51 includes a plurality of protrusions 521 and a plurality of protrusions 522 that protrude from the lead main surface 51a in the thickness direction z2. In a plan view, each of the plurality of protrusions 521 and 522 extends in the depth direction y and is trapezoidal in the depth direction y. Alternatively, each of the plurality of protrusions 521 and 522 may extend in the width direction x and be trapezoidal in the width direction x. In this embodiment, the plurality of protrusions 521 are arranged consecutively without any gaps in the depth direction y. Similarly, the plurality of protrusions 522 are arranged consecutively without any gaps in the depth direction y. The plurality of protrusions 521 and 522 may be formed by metal processing (e.g., rolling) using rollers. The method for forming the plurality of protrusions 521 and 522 is not limited to this, and may also be die molding, chemical processing (e.g., etching), or the like.

[0067] The plurality of protrusions 521 overlap the lead bonding layer 321, the first electrode 111 of the semiconductor element 10A, and the element bonding layer 31A in a plan view. The plurality of protrusions 521 are formed in the first bonding portion 511. Each of the protrusions 521 has a dimension (width) W in the width direction x. 521Each protrusion 521 has a dimension (height) H 521 is approximately 0.14 to 0.43 μm. The number and dimensions of the protrusions 521 are not particularly limited. In this embodiment, the protrusions 521 correspond to the "first protrusions" of the present disclosure. Each protrusion 521 includes a pair of side surfaces 521a, 521b and a top surface 521c.

[0068] The pair of side surfaces 521a, 521b are formed to rise from the lead main surface 51a. In this embodiment, each of the side surfaces 521a, 521b is inclined with respect to the lead main surface 51a. In this embodiment, the angle α (see FIG. 13) formed by the pair of side surfaces 521a, 521b is approximately 60 to 120°. Note that the angle α is not limited to this and may be, for example, an acute angle. The pair of side surfaces 521a, 521b are spaced apart in the width direction x and face opposite directions. In this embodiment, the pair of side surfaces 521a, 521b correspond to the "pair of first side surfaces" of the present disclosure.

[0069] The top surface 521c is connected to the pair of side surfaces 521a and 521b. The top surface 521c faces the same direction as the lead main surface 51a. The top surface 521c is flat. The multiple top surfaces 521c of the multiple protrusions 521 are located on a single plane. In this embodiment, the top surface 521c corresponds to the "first top surface" of the present disclosure.

[0070] The plurality of protrusions 522 overlap the lead bonding layer 322 in a plan view. The plurality of protrusions 522 are formed in the second bonding portion 512. Each of the protrusions 522 has approximately the same size as each of the protrusions 521. Therefore, each of the protrusions 522 has a dimension (width) W in the width direction x. 522 is 0.4 to 0.67 μm, and the dimension (height) H 522 is 0.14 to 0.43 μm. The number and dimensions of the protrusions 522 are not particularly limited. In this embodiment, the protrusions 522 correspond to the "second protrusions" of the present disclosure. Each protrusion 522 includes a pair of side surfaces 522a, 522b and a top surface 522c.

[0071] The pair of side surfaces 522a, 522b are formed to rise from the lead main surface 51a. In this embodiment, each of the side surfaces 522a, 522b is inclined with respect to the lead main surface 51a. In this embodiment, the angle β (see FIG. 14) formed by the pair of side surfaces 522a, 522b is approximately 60 to 120°. Note that the angle β is not limited to this and may be, for example, an acute angle. The pair of side surfaces 522a, 522b are spaced apart from each other in the width direction x and face opposite directions to each other. In this embodiment, the pair of side surfaces 522a, 522b correspond to the "pair of second side surfaces" of the present disclosure.

[0072] The top surface 522c is connected to the pair of side surfaces 522a, 522b. In this embodiment, the top surface 522c faces the same direction as the lead main surface 51a. The top surface 522c is flat. The multiple top surfaces 522c of the multiple protrusions 522 are located on a single plane. In this embodiment, the multiple top surfaces 521c and the multiple top surfaces 522c are located on a single plane. In this embodiment, the top surface 522c corresponds to the "second top surface" of the present disclosure.

[0073] Each of the plurality of wire members 6 is a so-called bonding wire. Each wire member 6 is conductive and is made of, for example, aluminum (Al), gold (Au), or copper (Cu). In this embodiment, the plurality of wire members 6 include a plurality of gate wires 61, a plurality of detection wires 62, a pair of first connecting wires 63, and a pair of second connecting wires 64, as shown in FIGS. 4 and 5 .

[0074] 4 and 5, one end of each of the plurality of gate wires 61 is joined to the second electrode 112 (gate electrode) of the semiconductor element 10, and the other end is joined to one of the pair of gate layers 24A, 24B. The plurality of gate wires 61 include those that connect the second electrode 112 of each semiconductor element 10A to the gate layer 24A, and those that connect the second electrode 112 of each semiconductor element 10B to the gate layer 24B.

[0075] 4 and 5, one end of each of the plurality of detection wires 62 is joined to the first electrode 111 (source electrode) of each semiconductor element 10, and the other end is joined to one of the pair of detection layers 25A, 25B. The plurality of detection wires 62 include those that connect the first electrode 111 of each semiconductor element 10A to the detection layer 25A, and those that connect the first electrode 111 of each semiconductor element 10B to the detection layer 25B.

[0076] 4 and 5, one of the pair of first connecting wires 63 connects the gate layer 24A and the gate terminal 44A, and the other connects the gate layer 24B and the gate terminal 44B. One of the first connecting wires 63 has one end joined to the gate layer 24A and the other end joined to the pad portion 441 of the gate terminal 44A, providing electrical continuity therebetween. The other first connecting wire 63 has one end joined to the gate layer 24B and the other end joined to the pad portion 441 of the gate terminal 44B, providing electrical continuity therebetween.

[0077] 4 and 5, one of the pair of second connecting wires 64 connects the detection layer 25A and the detection terminal 45A, and the other connects the detection layer 25B and the detection terminal 45B. One second connecting wire 64 has one end joined to the detection layer 25A and the other end joined to the pad portion 451 of the detection terminal 45A, providing electrical continuity therebetween. The other second connecting wire 64 has one end joined to the detection layer 25B and the other end joined to the pad portion 451 of the detection terminal 45B, providing electrical continuity therebetween.

[0078] 1, 3, 4, and 6 to 10, the sealing resin 7 covers the semiconductor elements 10, a portion of the support substrate 20, the conductive bonding layers 3, a portion of each terminal 40, the lead members 51, and the wire members 6. The sealing resin 7 is made of, for example, epoxy resin. As shown in FIGS. 1, 3, 4, and 6 to 10, the sealing resin 7 has a resin main surface 71, a resin back surface 72, and resin side surfaces 731 to 734.

[0079] The resin main surface 71 and the resin back surface 72 are spaced apart in the thickness direction z and face opposite directions from each other. The resin main surface 71 faces the thickness direction z2, and the resin back surface 72 faces the thickness direction z1. As shown in FIG. 7 , the resin back surface 72 has a frame shape surrounding the back surface 212 of the insulating substrate 21 in a plan view. The back surface 212 of the insulating substrate 21 is exposed from the resin back surface 72. Each of the multiple resin side surfaces 731 to 734 is connected to both the resin main surface 71 and the resin back surface 72 and is sandwiched between them in the thickness direction z. In this embodiment, the resin side surfaces 731, 732 are spaced apart in the width direction x and face opposite directions from each other. The resin side surface 731 faces the width direction x2, and the resin side surface 732 faces the width direction x1. Furthermore, the resin side surfaces 733, 734 are spaced apart in the depth direction y and face opposite directions from each other. The resin side surface 733 faces in the depth direction y2, and the resin side surface 734 faces in the depth direction y1.

[0080] In this embodiment, as shown in Figures 6, 7, and 10, the sealing resin 7 includes a plurality of recesses 75, each recessed from the resin rear surface 72 in the thickness direction z. Note that the sealing resin 7 does not necessarily include these recesses 75. Each of the recesses 75 extends in the depth direction y and is connected, in plan view, from an edge of the resin rear surface 72 in the depth direction y1 to an edge of the resin rear surface 72 in the depth direction y2. In this embodiment, the recesses 75 are formed three by three in each width direction x, sandwiching the rear surface 212 of the insulating substrate 21, in plan view.

[0081] Next, a method for manufacturing the semiconductor device A1 according to the first embodiment will be described.

[0082] First, the support substrate 20 is prepared. In the step of preparing the support substrate 20 (support substrate preparation step), a plurality of conductive members 22 (conductive members 22A, 22B) are bonded to an insulating substrate 21 at a distance from each other. Then, a pair of insulating layers 23A, 23B, a pair of gate layers 24A, 24B, a pair of detection layers 25A, 25B, and a plurality of base portions 29 are bonded to the conductive members 22A, 22B.

[0083] Next, a plurality of lead members 51 are prepared. In the step of preparing the lead members 51 (lead preparation step), a metal plate made of Cu or a Cu alloy is subjected to metal processing, such as rolling, to form the lead members 51 shown in FIG. 15. As shown in FIG. 15, in each of the plurality of protrusions 521, the edge of the side surface 521a in the thickness direction z2 is connected to the edge of the side surface 521b in the thickness direction z2, and the top surface 521c of the semiconductor device A1 is not included. Also, as shown in FIG. 15, in each of the plurality of protrusions 522, the edge of the side surface 522a in the thickness direction z2 is connected to the edge of the side surface 522b in the thickness direction z2, and the top surface 522c of the semiconductor device A1 is not included. The lead preparation step corresponds to the "connection member preparation step" of the present disclosure.

[0084] Next, a plurality of sintering metal materials 301 are formed. Each sintering metal material 301 serves as the base for the element bonding layers 31A and 31B. In this embodiment, a sintering silver paste is used as each sintering metal material 301. This sintering silver paste is a mixture of micro- or nano-sized silver particles in a solvent. In this embodiment, the solvent for the sintering silver does not contain (or contains very little) epoxy resin. In the step of forming the sintering metal materials 301 (first sintering metal material forming step), each sintering metal material 301 is applied to the conductive members 22A and 22B by, for example, screen printing using a mask. Note that each sintering metal material 301 applied to the conductive member 22A will later become the element bonding layer 31A of the semiconductor device A1, and each sintering metal material 301 applied to the conductive member 22B will later become the element bonding layer 31B of the semiconductor device A1. The method of forming the plurality of sintering metal materials 301 is not limited to the above-described screen printing. For example, the sintering metal material 301 may be applied by a dispenser. The thickness of the applied sintering metal material 301 is approximately 100 μm.

[0085] Next, a drying process is performed on the plurality of sintering metal materials 301. In this drying process (drying step), each sintering metal material 301 is heated at a temperature of approximately 130°C for approximately 20 minutes. Note that the heating conditions are not limited to these. This causes the solvent in each sintering metal material 301 to evaporate.

[0086] Next, one of the semiconductor elements 10A and 10B is mounted on each of the sintering metal materials 301. Specifically, one semiconductor element 10A is mounted on each of the sintering metal materials 301 formed on the conductive member 22A, and one semiconductor element 10B is mounted on each of the sintering metal materials 301 formed on the conductive member 22B. In the step of mounting the semiconductor elements 10A and 10B (mounting step), each semiconductor element 10A is mounted on the conductive member 22A with the conductive member 22A and the element back surface 102 of the semiconductor element 10A facing each other, and each semiconductor element 10B is mounted on the conductive member 22B with the conductive member 22B and the element back surface 102 of the semiconductor element 10B facing each other.

[0087] Next, a sintering metal material 302 is formed on each of the semiconductor elements 10A, 10B and the conductive member 22B. The sintering metal material 302 serves as the base for the lead bonding layers 321, 322 and the terminal bonding layer 33. In this embodiment, preformed sintering silver is used as each of the sintering metal materials 302. This preformed sintering silver is obtained by, for example, drying the above-mentioned paste-like sintering silver and then molding it into a predetermined shape. Note that the preformed sintering silver may also be dried after being molded into a predetermined shape. In the step of forming the sintering metal material 302 (second sintering metal material forming step), each of the plurality of sintering metal materials 302 is placed one by one on each of the semiconductor elements 10A, 10B and the conductive member 22B. Each sintering metal material 302 formed on each semiconductor element 10A will later become the lead bonding layer 321 of the semiconductor device A1, and each sintering metal material 302 formed on the conductive member 22B will later become the lead bonding layer 322 of the semiconductor device A1. Also, each sintering metal material 302 formed on each semiconductor element 10B will later become the terminal bonding layer 33 of the semiconductor device A1. The thickness of the sintering metal material 302 placed is approximately 110 μm. In this embodiment, the second sintering metal material forming step corresponds to the "sintering metal material forming step" of the present disclosure.

[0088] Next, each semiconductor element 10A is connected to the conductive member 22B using the lead members 51 prepared in the lead preparation step. In the step of connecting using the lead members 51 (connection step), the lead members 51 are placed on the sintering metal materials 302 so that, in a plan view, the plurality of protrusions 521 overlap the sintering metal materials 302 formed on each semiconductor element 10A, and the plurality of protrusions 522 overlap the sintering metal materials 302 formed on the conductive member 22B.

[0089] Next, the multiple terminals 40 are joined. When joining the input terminal 41, the comb-tooth portion 411a is joined to the main surface 221A of the conductive member 22A. This joining may be done by laser welding or ultrasonic bonding. When joining the output terminal 43, the comb-tooth portion 431a is joined to the main surface 221B of the conductive member 22B. This joining may be done by laser welding or ultrasonic bonding. When joining the input terminal 42, the input terminal 42 is joined onto the input terminal 41 with the insulating member 49 sandwiched therebetween. At this time, each edge portion of the multiple extension portions 421b of the input terminal 42 overlaps each semiconductor element 10B in a plan view. Furthermore, each of the multiple protrusions 421c of the input terminal 42 contacts the sintering metal material 302 formed on the conductive member 22B. The pair of gate terminals 44A, 44B, the pair of detection terminals 45A, 45B, the plurality of dummy terminals 46, and the pair of side terminals 47A, 47B are formed on and connected to one lead frame. Portions of the lead frame corresponding to the side terminals 47A, 47B are bonded to the main surface 221A of the conductive member 22A and the main surface 221B of the conductive member 22B, respectively. This bonding may be performed by laser welding or ultrasonic bonding.

[0090] Next, a pressure and heat treatment is performed to convert the sintering target metal materials 301, 302 into sintered metal. In this pressure and heat treatment process (pressure and heat treatment process), as shown in FIGS. 16 and 17 , a pressure member 80 presses each lead member 51 to apply pressure to the multiple sintering target metal materials 301, 302. At this time, the pressure member 80 contacts the multiple protrusions 521, 522 of each lead member 51. The pressing force of the pressure member 80 crushes the tips of the protrusions 521, 522, forming the top surfaces 521c, 522c. Furthermore, the input terminal 42 is pressed by the pressure member 80 or by a pressure member different from the pressure member 80, thereby applying pressure to the sintering target metal material 302. The sintering target metal materials 301, 302 pressurized via the lead member 51 and the sintering target metal material 302 pressurized via the input terminal 42 are then heated, for example, at a temperature of approximately 250°C for approximately 90 seconds. The heating conditions are not limited to these. As a result, the silver particles in each of the plurality of sintering metal materials 301, 302 are bonded to each other to form a sintered metal. The sintered metal interposed between the semiconductor element 10A and the conductive member 22A is the element bonding layer 31A of the semiconductor device A1, and the sintered metal interposed between the semiconductor element 10B and the conductive member 22B is the element bonding layer 31B of the semiconductor device A1. The sintered metal interposed between the lead member 51 and the semiconductor element 10A is the lead bonding layer 321 of the semiconductor device A1, and the sintered metal interposed between the lead member 51 and the conductive member 22B is the lead bonding layer 322 of the semiconductor device A1. The sintered metal interposed between the semiconductor element 10B and the input terminal 42 (pad portion 421) is the terminal bonding layer 33 of the semiconductor device A1.

[0091] Next, a plurality of wire members 6 are formed. In the process of forming the wire members 6 (wire forming process), for example, a well-known wire bonder is used. In the wire forming process, a plurality of gate wires 61 are formed, connecting the second electrode 112 of each semiconductor element 10A to the gate layer 24A, and a plurality of gate wires 61 are formed, connecting the second electrode 112 of each semiconductor element 10B to the gate layer 24B. In addition, a plurality of detection wires 62 are formed, connecting the first electrode 111 of each semiconductor element 10A to the detection layer 25A, and a plurality of detection wires 62 are formed, connecting the first electrode 111 of each semiconductor element 10B to the detection layer 25B. Furthermore, a first connection wire 63 is formed, connecting the gate layer 24A to the gate terminal 44A, and a first connection wire 63 is formed, connecting the gate layer 24B to the gate terminal 44B. Then, a second connection wire 64 is formed, connecting the detection layer 25A to the detection terminal 45A, and a second connection wire 64 is formed, connecting the detection layer 25B to the detection terminal 45B. The order in which the wire members 6 are formed is not particularly limited.

[0092] Next, the sealing resin 7 is formed. The process of forming the sealing resin 7 (resin forming process) is performed by, for example, transfer molding. The sealing resin 7 is, for example, an epoxy resin. In this embodiment, the sealing resin 7 is formed so as to cover the plurality of semiconductor elements 10, part of the support substrate 20, the plurality of conductive bonding layers 3, parts of the plurality of terminals 40, the plurality of lead members 51, and the plurality of wire members 6. A part of each terminal 40 and a part of the support substrate 20 (specifically, the back surface 212 of the insulating substrate 21) are exposed from the formed sealing resin 7.

[0093] 1 to 14 is manufactured by cutting unnecessary portions of the terminals 40 (for example, parts of the lead frame) and bending the terminals 40. Note that the manufacturing method described above is an example and is not limited thereto, and the order of steps may be changed as appropriate.

[0094] Next, the effects of the semiconductor device A1 and the manufacturing method thereof according to the first embodiment will be described.

[0095] The semiconductor device A1 includes lead members 51 having lead main surfaces 51a. Each lead member 51 has a protrusion 521 protruding from the lead main surface 51a in the thickness direction z2. During the pressurizing and heating process of the manufacturing method for the semiconductor device A1, the lead members 51 are pressed by a pressure member 80, thereby pressurizing the sintering metal material 302 formed on the semiconductor element 10A. At this time, the pressure member 80 abuts against the multiple protrusions 521 formed on the lead main surfaces 51a and presses down on each lead member 51. Therefore, the pressure member 80 does not contact the connecting portions 513. This allows the pressing force of the pressure member 80 to be concentrated on the first bonding portions 511. That is, the pressing force of the pressure member 80 is transmitted to the sintering metal material 301 formed under the multiple protrusions 521, thereby suppressing the pressure applied to the connecting portions 513. This prevents the connecting portions 513 from bending. Therefore, the semiconductor device A1 can suppress deformation of the lead members 51.

[0096] According to the semiconductor device A1, the sintering metal material 301 formed under each semiconductor element 10A and the sintering metal material 302 formed on each semiconductor element 10A are simultaneously subjected to pressure and heat treatment. That is, the element bonding layer 31A and the lead bonding layer 321 are simultaneously sintered. Therefore, the element bonding layer 31A and the lead bonding layer 321 are formed from the sintering metal materials 301, 302 by a single pressure and heat treatment, thereby improving the productivity of the semiconductor device A1.

[0097] According to the semiconductor device A1, each lead member 51 is formed with protrusions 522 protruding from the lead main surface 51a in the thickness direction z2. As a result, when pressure is applied by the pressure member 80, the pressure member 80 abuts against the multiple protrusions 522, and the pressing force of the pressure member 80 is transmitted to the sintering metal material 302 formed under the multiple protrusions 522. Therefore, the pressing force of the pressure member 80 can be concentrated on the sintering metal material 302 formed on the conductive member 22B. Furthermore, since multiple protrusions 522 are formed, a single application of pressure by the pressure member 80 can simultaneously transmit the pressing force to the sintering metal material 302 formed under the multiple protrusions 521, 522. Therefore, the sintering metal material 302 can be sintered into the lead bonding layers 321, 322 by a single pressure and heat treatment.

[0098] According to the semiconductor device A1, a plurality of protrusions 521, 522 are formed, and the plurality of protrusions 521, 522 make the lead main surface 51a partially uneven. The lead main surface 51a is in contact with the sealing resin 7. Therefore, the anchor effect can improve the adhesion between the lead member 51 and the sealing resin 7. Furthermore, the plurality of protrusions 521, 522 can increase the surface area of ​​the lead member 51. This makes it possible to improve heat dissipation.

[0099] According to the semiconductor device A1, each of the plurality of lead members 51 has a plurality of protrusions 521, 522. In the manufacturing method of the semiconductor device A1, when each lead member 51 is placed in the connecting step, the lead member 51 may be tilted due to manufacturing errors of the respective members or the semiconductor device A1. In this case, if each lead member 51 does not have a plurality of protrusions 521, 522, the pressure applied during the pressurizing and heating step may be concentrated on only one side of each lead member 51, and an appropriate pressure may not be applied to the other side. As a result, one of the plurality of sintering metal materials 301, 302 may be insufficiently pressurized, resulting in a decrease in the bonding strength of the conductive bonding layer 3. On the other hand, when each lead member 51 has a plurality of protrusions 521, 522 as in this embodiment, the amount of compression of the plurality of protrusions 521, 522 varies, as shown in FIG. 18 . In the example shown in FIG. 18 , the dimension of the side surface 521b in the thickness direction z of each protrusion 521 is smaller than the dimension of the side surface 521a in the thickness direction z. Furthermore, of two adjacent protrusions 521, the dimension of the side surface 521a in the thickness direction z of the protrusion 521 located on the width direction x2 side is smaller than the dimension of the side surface 521b in the thickness direction z of the protrusion 521 located on the width direction x1 side. The same applies to each protrusion 522. The top surfaces 521c of each protrusion 521 and the top surfaces 522c of each protrusion 522 are located on the same plane. Even in this case, an appropriate pressing force can be applied to both the first bonding portion 511 and the second bonding portion 512 of each lead member 51, and therefore, an appropriate pressing force can be applied to both the plurality of sintering metal materials 301 and 302. This prevents insufficient pressure from being applied to the plurality of sintering metal materials 301 and 302, thereby preventing a decrease in the bonding strength of the conductive bonding layer 3.

[0100] In particular, the inventors' research has shown that the angles α and β are both approximately 90° and the width W 521 ,W 522 are both approximately 0.67 μm, and the height H 521 ,H 522are both approximately 0.33 μm, there is little change in surface pressure relative to the amount of crushing of the protrusions 521, 522 by the pressure member 80. Therefore, by setting the dimensions of each of the protrusions 521, 522 as described above, it is possible to suppress variations in the degree of pressure applied to each of the lead members 51, even if the amount of crushing of the multiple protrusions 521, 522 of each of the lead members 51 differs.

[0101] In the above example, the case where each lead member 51 is inclined has been described, but the present invention is not limited to this, and the same applies to a case where there is variation in the height of the plurality of lead members 51. In other words, when there is variation in the height of the plurality of lead members 51, even if the amount of crushing of the protrusions 521, 522 by the pressure member 80 differs for each of the plurality of lead members 51, it is possible to apply an appropriate pressing force to each of the plurality of metal materials to be sintered 301, 302 for each of the plurality of lead members 51. In this case, the semiconductor device that can be manufactured has the height H of the protrusions 521, 522 for each of the plurality of lead members 51. 521 ,H 522 will be different.

[0102] According to the semiconductor device A1, the element bonding layers 31A, 31B are formed from a sintering metal material 301, which is a sintering silver paste. The sintering silver paste is cheaper than the sintering silver preform. Therefore, the manufacturing cost of the semiconductor device A1 can be reduced. Note that in this embodiment, the element bonding layers 31A, 31B may be formed from the sintering silver preform. That is, the sintering silver preform may be used as the sintering metal material 301. In this case, although the manufacturing cost of the semiconductor device A1 increases, the productivity can be improved because the drying process described above is not required.

[0103] Semiconductor devices according to other embodiments will be described below. In the following description, elements that are the same as or similar to those in the first embodiment will be given the same reference numerals, and descriptions thereof will be omitted.

[0104] 19 to 23 show a semiconductor device according to the second embodiment. A semiconductor device A2 according to the second embodiment is different from the semiconductor device A1 in the method of connecting the input terminal 42 and each semiconductor element 10B. Specifically, in the semiconductor device A1, the pad portion 421 of the input terminal 42 is conductively connected to each semiconductor element 10B via the terminal bonding layer 33, but in this embodiment, the pad portion 421 of the input terminal 42 and each semiconductor element 10B are connected by a lead member 53 different from the lead member 51.

[0105] FIG. 19 is a perspective view showing the semiconductor device A2, with the sealing resin 7 indicated by an imaginary line (two-dot chain line). FIG. 20 is a plan view showing the semiconductor device A2, with the sealing resin 7 indicated by an imaginary line (two-dot chain line). FIG. 21 is a partially enlarged view of a portion of FIG. 20. FIG. 22 is a cross-sectional view taken along line XXII-XXII in FIG. 20. FIG. 23 is a partially enlarged view of a portion of FIG. 22.

[0106] In this embodiment, the conductive bonding layer 3 includes a plurality of element bonding layers 31A and 31B and a plurality of lead bonding layers 321, 322, 341, and 342. Therefore, compared to the conductive bonding layer 3 of the first embodiment, the conductive bonding layer 3 of this embodiment does not include the terminal bonding layer 33, but further includes the lead bonding layers 341 and 342.

[0107] Each of the plurality of lead bonding layers 341 and 342 is for bonding a corresponding lead member 53 .

[0108] Each of the plurality of lead bonding layers 341 is intended to bond a portion of each lead member 53 to a corresponding semiconductor element 10B. Each lead bonding layer 341 is interposed between the element main surface 101 of each semiconductor element 10B and a portion of each lead member 53 (first bonding portion 531 described below), and provides electrical continuity between the main surface electrode 11 (first electrode 111) of the semiconductor element 10B and the corresponding lead member 53. Each lead bonding layer 341 has a thickness of approximately 80 μm. However, the thickness of each lead bonding layer 341 is not limited to this.

[0109] Each of the plurality of lead bonding layers 342 is intended to bond a portion of each lead member 53 to the input terminal 42. Each lead bonding layer 342 is interposed between a portion of each lead member 53 (a second bonding portion 532 described below) and the extending portion 421b of the input terminal 42, and provides electrical continuity between the lead member 53 and the input terminal 42. Each lead bonding layer 342 has a thickness of approximately 80 μm. However, the thickness of each lead bonding layer 342 is not limited to this.

[0110] In this embodiment, the pad portion 421 of the input terminal 42 does not include multiple protrusions 421c, and each of the multiple extension portions 421b does not overlap the conductive member 22B in plan view. In this embodiment, each extension portion 421b extends in the width direction x from each connecting portion 421a until it overlaps with each base portion 29 in plan view. Note that in this embodiment, each base portion 29 needs to be provided in order to support each extension portion 421b of the pad portion 421 of the input terminal 42.

[0111] The plurality of lead members 53 connect each semiconductor element 10B to the input terminal 42. Each lead member 53 has a rectangular shape extending in the width direction x in a plan view. Each lead member 53 includes a first joint portion 531, a second joint portion 532, and a connecting portion 533.

[0112] The first bonding portion 531 is a portion bonded to the main surface electrode 11 (first electrode 111) of the semiconductor element 10B via the conductive bonding layer 3 (lead bonding layer 341). In a plan view, the first bonding portion 531 overlaps the first electrode 111 of the semiconductor element 10B, the lead bonding layer 341, and the semiconductor element 10B. The thickness of the first bonding portion 531 is greater than the thickness of the second bonding portion 532.

[0113] The second bonding portion 532 is a portion bonded to the extending portion 421b of the input terminal 42 via the conductive bonding layer 3 (lead bonding layer 342). The second bonding portion 532 overlaps the lead bonding layer 342 in a plan view. The thickness of the second bonding portion 532 is smaller than the thickness of the first bonding portion 531. In this embodiment, the thickness of the second bonding portion 532 is approximately 160 to 200 μm. However, the thickness of the second bonding portion 532 is not limited to this.

[0114] The connecting portion 533 is a portion that connects the first bonding portion 531 and the second bonding portion 532. The surface of the connecting portion 533 facing the thickness direction z2 is in contact with the sealing resin 7. The thickness of the connecting portion 533 is the same as the thickness of the second bonding portion 532. Therefore, in this embodiment, the thickness of the connecting portion 533 is approximately 160 to 200 μm. However, the thickness of the connecting portion 533 is not limited to this. The connecting portion 533 overlaps the second bonding portion 532 when viewed in the width direction x.

[0115] Each lead member 53 has a lead main surface 53a. The lead main surface 53a faces the thickness direction z2. In this embodiment, the lead main surface 53a is substantially flat. The lead main surface 53a includes the surfaces of the first bonding portion 531, the second bonding portion 532, and the connecting portion 533, each of which faces the thickness direction z2.

[0116] Each lead member 53 includes a plurality of protrusions 541 and a plurality of protrusions 542 each protruding from a lead main surface 53a in the thickness direction z. Each of the plurality of protrusions 541, 542 extends in the depth direction y in a plan view and is trapezoidal when viewed in the depth direction y. The plurality of protrusions 541, 542 can be formed in the same manner as the plurality of protrusions 521, 522 of the lead member 51. For example, they can be formed by metal processing (e.g., rolling) using rollers.

[0117] The multiple protrusions 541 overlap the lead bonding layer 341, the first electrodes 111 of the semiconductor element 10B, and the element bonding layer 31B in a plan view. The multiple protrusions 541 are formed in the first bonding portion 531. Each protrusion 541 has a width x dimension (width) of approximately 0.4 to 0.67 μm and a thickness z dimension (height) of approximately 0.14 to 0.43 μm. Each protrusion 541 includes a pair of side surfaces 541a, 541b and a top surface 541c.

[0118] The pair of side surfaces 541a, 541b are formed to rise from the lead main surface 53a. In this embodiment, each of the side surfaces 541a, 541b is inclined with respect to the lead main surface 53a. In this embodiment, the angle formed by the pair of side surfaces 541a, 541b is approximately 60 to 120°. However, this angle is not limited to this and may be, for example, an acute angle. The pair of side surfaces 541a, 541b are spaced apart in the width direction x and face opposite directions.

[0119] The top surface 541c is connected to the pair of side surfaces 541a and 541b. The top surface 541c faces the same direction as the lead main surface 53a. The top surface 541c is flat. In this embodiment, the top surfaces 541c of the protrusions 541 are located on a single plane.

[0120] The multiple protrusions 542 overlap the lead bonding layer 342 in a plan view. The multiple protrusions 542 are formed in the second bonding portion 532. Each protrusion 542 has a width x dimension (width) of approximately 0.4 to 0.67 μm and a thickness z dimension (height) of approximately 0.14 to 0.43 μm. Each protrusion 542 includes a pair of side surfaces 542a, 542b and a top surface 542c.

[0121] The pair of side surfaces 542a, 542b are formed to rise from the lead main surface 53a. In this embodiment, each of the side surfaces 542a, 542b is inclined with respect to the lead main surface 53a. In this embodiment, the angle formed by the pair of side surfaces 542a, 542b is approximately 60 to 120°. However, this angle is not limited to this and may be, for example, an acute angle. The pair of side surfaces 542a, 542b are spaced apart in the width direction x and face opposite directions.

[0122] The top surface 542c is connected to the pair of side surfaces 542a and 542b. In this embodiment, the top surface 542c faces the same direction as the lead main surface 53a. The top surface 542c is flat. In this embodiment, the top surfaces 542c of the protrusions 542 are located on a single plane.

[0123] Next, the effects of the semiconductor device A2 according to the second embodiment will be described.

[0124] Similar to the semiconductor device A1, the semiconductor device A2 includes a lead member 51 having a protrusion 521 formed thereon. Therefore, similar to the semiconductor device A1 of the first embodiment, the semiconductor device A2 can suppress deformation of the lead member 51. Furthermore, other components of the semiconductor device A2 that have the same configuration as the semiconductor device A1 can achieve the same effects as the semiconductor device A1.

[0125] The semiconductor device A2 includes a lead member 53 having protrusions 541 and 542. With this configuration, similar to the lead member 51, the pressing force of the pressure member 80 can be concentrated on the first bonding portion 531 and the second bonding portion 532, thereby suppressing the pressure applied to the connecting portion 533. Therefore, the semiconductor device A2 can suppress deformation of the lead member 53.

[0126] In the second embodiment, the height difference between the upper surface of the input terminal 41 and the element main surface 101 of the semiconductor element 10B is eliminated by increasing the dimension of the first bonding portion 531 in the thickness direction z of each lead member 53. However, this is not limited to this. For example, this height difference may be eliminated by using a columnar conductor 59 as shown in FIGS. 24 and 25. FIGS. 24 and 25 are enlarged views of essential parts of a semiconductor device according to such a modification. FIG. 24 illustrates a case where the first bonding portion 531 has the same thickness as the second bonding portion 532. FIG. 25 illustrates a case where the lead member 53 has substantially the same shape as the lead member 51. In these modifications, the columnar conductor 59 may be a polygonal prism or a circular cylinder in a planar view. As shown in FIGS. 24 and 25, the columnar conductor 59 is bonded to the semiconductor element 10B via the conductor bonding layer 35 of the conductive bonding layer 3. The first bonding portion 531 of each lead member 53 is bonded to the top of the columnar conductor 59 (in the thickness direction z2) via a lead bonding layer 341. In these modified examples, deformation of each lead member 53 can also be suppressed. In particular, in the modified example in FIG. 25, each lead member 51 and each lead member 53 have the same shape, so the same parts can be used. In other words, there is no need to manufacture each lead member 51 and each lead member 53 in different shapes, which improves productivity.

[0127] FIG. 26 shows a semiconductor device according to a third embodiment. The semiconductor device A3 of the third embodiment differs from the first and second embodiments in the shape of the sealing resin 7. The rest of the semiconductor device is the same as the semiconductor devices A1 and A2. FIG. 26 is a perspective view showing the semiconductor device A3. In this embodiment, the width direction x corresponds to the "second direction" of the present disclosure, and the depth direction y corresponds to the "third direction" of the present disclosure.

[0128] In this embodiment, in a plan view, each edge portion of the sealing resin 7 in the depth direction y extends in the width direction x. The portions of the sealing resin 7 extending in the width direction x2 partially cover the two input terminals 41 and 42 and the insulating member 49. Furthermore, the portion of the sealing resin 7 extending in the width direction x1 partially covers the output terminal 43.

[0129] Similar to the semiconductor device A1, the semiconductor device A3 includes a lead member 51 having a protrusion 521 formed thereon. Therefore, similar to the semiconductor device A1 of the first embodiment, the semiconductor device A3 can suppress deformation of the lead member 51. Furthermore, other components of the semiconductor device A3 that have the same configuration as the semiconductor device A1 can achieve the same effects as the semiconductor device A1.

[0130] According to the semiconductor device A3, for example, the two input terminals 41 and 42, the output terminal 43, and a part of the insulating member 49 that protrude from the sealing resin 7 in the semiconductor device A1 can be protected.

[0131] 27 and 28 show a semiconductor device according to the fourth embodiment. The semiconductor device A4 according to the fourth embodiment differs from the semiconductor devices according to the first to third embodiments in the configuration of the support substrate 20. FIG. 27 is a plan view showing the semiconductor device A4, with the terminals 40, the wire members 6, and the sealing resin 7 omitted. FIG. 28 is a cross-sectional view taken along line XXVIII-XXVIII in FIG. 27.

[0132] The support substrate 20 of this embodiment is, for example, a structure called a DBC (Direct Bonded Copper) substrate. Note that a structure called a DBA (Direct Bonded Aluminum) substrate may be used instead of the DBC substrate. The support substrate 20 is at least partially covered with a sealing resin 7 (not shown). The support substrate 20 includes an insulating substrate 26, a main surface metal layer 27, and a back surface metal layer 28.

[0133] The insulating substrate 26 has electrical insulation properties. The constituent material of the insulating substrate 26 is ceramic, similar to the insulating substrate 21. The insulating substrate 26 may be an insulating resin sheet or the like. The insulating substrate 26 is covered with a sealing resin 7. The insulating substrate 26 has a main surface 26a and a back surface 26b that are spaced apart in the thickness direction z and face opposite each other.

[0134] The main surface metal layer 27 is formed so as to cover a portion of the main surface 26a. The main surface metal layer 27 is made of copper. If the support substrate 20 is a DBA substrate, the main surface metal layer 27 is made of aluminum. The main surface metal layer 27 is covered with a sealing resin 7. The main surface metal layer 27 is patterned and includes a plurality of pattern electrodes 271 to 275 that are spaced apart from one another. The patterning is performed by, for example, etching.

[0135] A plurality of semiconductor elements 10A are conductively bonded to the pattern electrode 271 via an element bonding layer 31A. The pattern electrode 271 is electrically connected to the back surface electrode 12 (drain electrode) of each semiconductor element 10A. A P terminal (corresponding to the input terminal 41), not shown, is connected to the pattern electrode 271, and a portion of the P terminal is exposed from the sealing resin 7.

[0136] A plurality of semiconductor elements 10B are conductively bonded to the pattern electrode 272 via the element bonding layer 31B, and a lead member 51 (second bonding portion 512) is also bonded to the pattern electrode 272. The pattern electrode 272 is electrically connected to the first electrode 111 (source electrode) of the main surface electrode 11 of each semiconductor element 10A. The pattern electrode 272 is also electrically connected to the back surface electrode 12 (drain electrode) of each semiconductor element 10B. An output terminal (corresponding to the output terminal 43) (not shown) is connected to the pattern electrode 272, and a portion of the output terminal is exposed from the sealing resin 7.

[0137] A lead member 53 (second bonding portion 532) is bonded to the pattern electrode 273. The pattern electrode 273 is electrically connected to the first electrode 111 (source electrode) of the main surface electrode 11 of each semiconductor element 10B. An N terminal (corresponding to the input terminal 42), not shown, is connected to the pattern electrode 273, and a portion of the N terminal is exposed from the sealing resin 7.

[0138] The pair of pattern electrodes 274 are electrically connected to the second electrodes 112 (gate electrodes) of the main surface electrodes 11 of the semiconductor elements 10A and 10B via wires (not shown). The pair of pattern electrodes 274 are each connected to a gate terminal (corresponding to the gate terminals 44A and 44B) (not shown), and the gate terminals are partially exposed from the sealing resin 7.

[0139] The pair of pattern electrodes 275 are electrically connected to the first electrodes 111 (source electrodes) of the principal surface electrodes 11 of the semiconductor elements 10A and 10B via wires (not shown). The pair of pattern electrodes 275 are each connected to a detection terminal (corresponding to the detection terminals 45A and 45B) (not shown), and the detection terminals are partially exposed from the sealing resin 7.

[0140] The back surface metal layer 28 is formed so as to cover at least a portion of the back surface 26b. The back surface metal layer 28 is made of copper. If the support substrate 20 is a DBA substrate, the back surface metal layer 28 is made of aluminum. The back surface metal layer 28 may be covered with the sealing resin 7, or the surface facing the thickness direction z1 may be exposed from the sealing resin 7.

[0141] In this embodiment, each lead member 51 and each lead member 53 have the same configuration.

[0142] The semiconductor device A4, like the semiconductor device A1, is provided with a lead member 51 having a protrusion 521 formed thereon. Therefore, like the semiconductor device A1 of the first embodiment, the semiconductor device A4 can suppress deformation of the lead member 51. Furthermore, other components of the semiconductor device A4 that have the same configuration as the semiconductor device A1 can achieve the same effects as the semiconductor device A1.

[0143] 29 and 30 show a semiconductor device according to the fifth embodiment. The semiconductor device A5 of the fifth embodiment differs from the first to fourth embodiments in that it is a discrete semiconductor including one semiconductor element 10. However, it is not limited to the semiconductor element 10, and various semiconductor elements such as diodes or ICs may be used. FIG. 29 is a perspective view showing the semiconductor device A5, with the sealing resin 7 indicated by an imaginary line (double-dashed line). FIG. 30 is a cross-sectional view taken along the line XXX-XXX in FIG. 29.

[0144] 29, the semiconductor device A5 has a so-called lead frame structure, and includes a lead frame 82. The constituent material of the lead frame 82 is not particularly limited, but may be, for example, Cu or a Cu alloy. The lead frame 82 includes a die pad portion 821 and a terminal portion 822.

[0145] The die pad portion 821 is a portion on which the semiconductor element 10 is mounted. In this embodiment, one semiconductor element 10 is mounted on the die pad portion 821, and the semiconductor element 10 is bonded via a conductive bonding layer 3 (element bonding layer 31). The die pad portion 821 is electrically connected to the back electrode 12 of the semiconductor element 10. In this embodiment, the die pad portion 821 corresponds to the "first conductor" of the present disclosure.

[0146] A portion of the terminal portion 822 is exposed from the sealing resin 7. The terminal portion 822 is electrically connected to the principal surface electrode 11 of the semiconductor element 10 via the lead member 51. In this embodiment, the terminal portion 822 corresponds to the "second conductor" of the present disclosure.

[0147] In this embodiment, one edge of the lead member 51 is joined to the main surface electrode 11 of the semiconductor element 10 via a lead joining layer 321, and the other edge is joined to the terminal portion 822 via a lead joining layer 322.

[0148] Similar to the semiconductor device A1, the semiconductor device A5 includes a lead member 51 having a protrusion 521 formed thereon. Therefore, similar to the semiconductor device A1 of the first embodiment, the semiconductor device A5 can suppress deformation of the lead member 51. Furthermore, other components of the semiconductor device A5 that have the same configuration as the semiconductor device A1 can achieve the same effects as the semiconductor device A1.

[0149] In the first to fifth embodiments, the multiple protrusions 521 are arranged continuously in the width direction x, but this is not limiting. For example, as shown in FIG. 31 , the protrusions 521 may be equally spaced at a predetermined interval Δd. The protrusions 521 do not have to be equally spaced. Even in this case, the protrusions 521 can suppress deformation of the lead member 51. Furthermore, not only the multiple protrusions 521 but also the multiple protrusions 522, 541, and 542 can be similarly deformed. FIG. 31 illustrates a semiconductor element 10A in which the first electrode 111 of the principal surface electrode 11 is divided into multiple regions by the insulating film 13.

[0150] In the first to fifth embodiments, the multiple protrusions 521 extend in the depth direction y in a plan view and have a trapezoidal shape in the depth direction y. However, this is not limiting. For example, the multiple protrusions 521 may have a semicircular shape in the depth direction y, extend in the width direction x in a plan view, or, as shown in FIG. 32, each protrusion 521 may have a truncated pyramidal shape. Even in this case, the protrusions 521 can suppress deformation of the lead member 51. Furthermore, not only the multiple protrusions 521 but also the multiple protrusions 522, 541, and 542 can deform in the same manner. Note that FIG. 32 illustrates a semiconductor element 10A in which the first electrode 111 of the principal surface electrode 11 is divided into multiple regions by the insulating film 13.

[0151] In the first to fifth embodiments, the first bonding portions 511, 531 and the second bonding portions 512, 532 of each lead member 51, 53 are bonded together by the conductive bonding layer 3. However, this is not limiting. For example, either the first bonding portions 511, 531 or the second bonding portions 512, 532 may be bonded by laser welding using a laser beam. Considering the influence on the semiconductor element 10, it is preferable to bond the second bonding portions 512, 532, which are not bonded to the principal surface electrodes 11 of the semiconductor element 10, by laser welding, rather than the first bonding portions 511, 531, which are bonded to the principal surface electrodes 11 of the semiconductor element 10. FIG. 33 illustrates a case in which the second bonding portion 512 of the lead member 51 according to the first embodiment is bonded by laser welding. In this modification, as shown in FIG. 33, the second bonding portion 512 does not have a protrusion 522, but has a weld mark M1 that can be formed by laser welding.

[0152] The semiconductor device and the manufacturing method thereof according to the present disclosure are not limited to the above-described embodiments. The specific configuration of each part of the semiconductor device according to the present disclosure and the specific processing of each step of the manufacturing method of the semiconductor device according to the present disclosure can be freely designed and modified in various ways.

[0153] [Appendix 1] a semiconductor element having a main surface and a back surface facing opposite to each other in a first direction, with a main surface electrode formed on the main surface and a back surface electrode formed on the back surface; a first conductor facing the back surface of the element and electrically connected to the back surface electrode; a second conductor disposed apart from the first conductor and electrically connected to the principal surface electrode; a connecting member having a connecting member main surface facing the same direction as the element main surface, connecting the main surface electrode and the second conductor; It is equipped with the connection member includes a first protrusion protruding from the connection member main surface in the first direction, and is bonded to the main surface electrode via a first bonding layer; The first protrusion overlaps the main surface electrode when viewed in the first direction. [Appendix 2] The first protrusion extends in a second direction perpendicular to the first direction when viewed in the first direction. 2. The semiconductor device according to claim 1. [Appendix 3] the first protrusion has a pair of first side surfaces rising from the main surface of the connection member, The pair of first side surfaces are spaced apart in a third direction perpendicular to the first direction and the second direction. 3. The semiconductor device according to claim 2. [Appendix 4] The pair of first side surfaces are inclined with respect to the main surface of the connection member. 4. The semiconductor device according to claim 3. [Appendix 5] The angle formed by the pair of first side surfaces is 60 to 120°. 5. The semiconductor device according to claim 4. [Appendix 6] The first protrusion further has a first top surface connected to the pair of first side surfaces. The semiconductor device according to any one of Supplementary Note 3 to Supplementary Note 5. [Appendix 7] The first top surface is flat. 7. The semiconductor device according to claim 6. [Appendix 8] The first top surface is inclined with respect to the main surface of the connection member. 8. The semiconductor device according to claim 7. [Appendix 9] The semiconductor device further includes a second bonding layer interposed between the connection member and the second conductor and electrically connecting the connection member and the second conductor. 9. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating film. [Appendix 10] the connecting member includes one or more second protrusions protruding from the connecting member main surface in the first direction, each of the one or more second protrusions overlaps the second bonding layer when viewed in the first direction; 10. The semiconductor device according to claim 9. [Appendix 11] The second protrusion extends in a second direction perpendicular to the first direction when viewed in the first direction. 11. The semiconductor device according to claim 10. [Appendix 12] the second protrusion has a pair of second side surfaces rising from the main surface of the connection member, The pair of second side surfaces are spaced apart in a third direction perpendicular to the first direction and the second direction. 12. The semiconductor device according to claim 11. [Appendix 13] The pair of second side surfaces are inclined with respect to the main surface of the connection member. 13. The semiconductor device according to claim 12. [Appendix 14] The angle formed by the pair of second side surfaces is 60 to 120°. 14. The semiconductor device according to claim 13. [Appendix 15] The second protrusion further has a second top surface connected to the pair of second side surfaces. 15. The semiconductor device according to any one of claims 12 to 14. [Appendix 16] the connecting member includes a first bonding portion bonded to the semiconductor element and a second bonding portion bonded to the second conductor, The dimension of the second joint portion in the first direction is larger than the dimension of the first joint portion in the first direction. 16. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer. [Appendix 17] the connecting member further includes a connecting portion that connects the first joint portion and the second joint portion, the main surface of the connection member is formed by the surfaces of the first joint portion, the second joint portion, and the connecting portion, which face one side of the first direction; 17. The semiconductor device according to claim 16. [Appendix 18] 18. The semiconductor device according to claim 17, wherein the connecting portion overlaps the first joint portion in a third direction perpendicular to the first direction. [Appendix 19] the semiconductor element is conductively bonded to the first conductor via a third bonding layer; 19. The semiconductor device according to any one of claims 1 to 18. [Appendix 20] The semiconductor element is a power MOSFET. 19. The semiconductor device according to claim 1. [Appendix 21] The first bonding layer is a sintered metal. 21. The semiconductor device according to claim 1. [Appendix 22] The semiconductor device further includes a sealing resin that covers the semiconductor element, the connecting member, the first bonding layer, at least a portion of the first conductor, and at least a portion of the second conductor. 22. The semiconductor device according to claim 1. [Appendix 23] a semiconductor element having a main surface and a rear surface facing opposite directions in a first direction; a first conductor and a second conductor spaced apart from each other; a connection member having a connection member main surface facing one side of the first direction and including a first protrusion protruding from the connection member main surface in the first direction; Equipped with a connection member preparation step of preparing the connection member; a mounting step of mounting the semiconductor element on the first conductor; a sintering metal material forming step of forming a sintering metal material on the element main surface; a connecting step of placing a portion of the connecting member on the metal material for sintering so that the main surface of the connecting member faces the same direction as the main surface of the element and so that the metal material for sintering and the first protrusion overlap when viewed in the first direction; a pressurizing and heating step of pressing the connection member with a pressing member from the side where the first protrusion is formed and heating the connection member to convert the metal material for sintering into a sintered metal; The method for manufacturing a semiconductor device includes the steps of:

Claims

1. a first semiconductor element and a second semiconductor element each having an element main surface and an element back surface facing in opposite directions in a first direction; a first conductor on which the first semiconductor element is mounted; a second conductor on which the second semiconductor element is mounted; a connecting member having a connecting member main surface facing the same direction as the element main surface and a connecting member back surface facing the element main surface, the connecting member connecting the first semiconductor element and the second conductor; It is equipped with the first conductor and the second conductor are arranged side by side in a second direction perpendicular to the first direction, the connecting member includes a first bonding portion bonded to the first semiconductor element, a second bonding portion bonded to the second conductor, and a connecting portion connecting the first bonding portion and the second bonding portion, the first joint portion and the second joint portion include a plurality of protrusions protruding toward a side toward which the main surface of the connection member faces in the first direction, The semiconductor device, wherein top surfaces of the plurality of protrusions are located higher in the first direction than a surface of the communication portion on the main surface side of the connection member.

2. The semiconductor device according to claim 1 , wherein the plurality of protrusions extend in a third direction perpendicular to the first direction and the second direction.

3. The semiconductor device according to claim 1 , wherein the plurality of protrusions are arranged in a grid pattern when viewed in the first direction.

4. 2. The semiconductor device according to claim 1, wherein the plurality of protrusions include a plurality of first protrusions that overlap the first semiconductor element when viewed in the first direction, and a plurality of second protrusions that overlap the second conductor when viewed in the first direction.

5. a first bonding layer that electrically connects the first semiconductor element and the connection member; The semiconductor device according to claim 4 , further comprising: a second bonding layer that electrically connects said second conductor and said connection member.

6. the plurality of first projections overlap the first bonding layer when viewed in the first direction, The semiconductor device according to claim 5 , wherein the plurality of second projections overlap the second bonding layer when viewed in the first direction.

7. The first joint portion includes the plurality of first protrusions, the second joint portion includes the plurality of second projections, The semiconductor device according to claim 4 , wherein the connecting portion overlaps between the first conductor and the second conductor when viewed in the first direction.

8. a first signal wiring portion that is electrically connected to the first semiconductor element; a second signal wiring portion that is electrically connected to the second semiconductor element, each of the first semiconductor element and the second semiconductor element is a switching element that performs a switching operation; the first signal wiring portion transmits a first control signal for controlling a switching operation of the first semiconductor element; the second signal wiring portion transmits a second control signal for controlling a switching operation of the second semiconductor element; 2. The semiconductor device according to claim 1, wherein each of said first signal wiring portion and said second signal wiring portion extends in a third direction perpendicular to said first direction and said second direction.

9. a first insulating layer supporting the first conductor; a second insulating layer supporting the second conductor; the first signal wiring portion is disposed on the first insulating layer, The semiconductor device according to claim 8 , wherein the second signal wiring portion is disposed on the second insulating layer.

10. a first signal terminal connected to the first signal wiring portion; 9. The semiconductor device according to claim 8, wherein the first signal terminal includes, when viewed in the second direction, a portion extending in the third direction and a portion bending from the portion in the first direction and extending in the first direction.

11. the first signal wiring portion is located on the opposite side of the first semiconductor element from the second semiconductor element in the second direction, The semiconductor device according to claim 8 , wherein the second signal wiring portion is located on an opposite side to the first semiconductor element in the second direction, with the second semiconductor element sandwiched therebetween.

12. By providing an additional first semiconductor element, a plurality of first semiconductor elements are provided; By providing an additional second semiconductor element, a plurality of second semiconductor elements are provided. The semiconductor device according to claim 1 .

13. the plurality of first semiconductor elements are arranged side by side in a third direction perpendicular to the first direction and the second direction, The semiconductor device according to claim 12 , wherein the plurality of second semiconductor elements are arranged side by side in the third direction.

14. The semiconductor device according to claim 1 , wherein each of said first semiconductor element and said second semiconductor element is a power MOSFET.

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