Semiconductor Devices

Abstract

To provide a semiconductor device in which the parasitic capacitance near a transistor is reduced, and a manufacturing method for the same.SOLUTION: A transistor 10 includes a first insulating layer 110, a first oxide semiconductor layer 121 thereon, a second oxide semiconductor layer 122 thereon, a source electrode layer 130 and a drain electrode layer 140 thereon, a second insulating layer 170 on the first insulating layer, the source electrode layer, and the drain electrode layer, a third insulating layer 175 thereon, a third oxide semiconductor layer 123 on the second oxide semiconductor layer, a gate insulating layer 150 thereon, and a gate electrode layer 160 thereon. The second insulating layer is an oxygen barrier layer and includes a region in contact with side surfaces of the first oxide semiconductor layer, the second oxide semiconductor layer, the source electrode layer, and the drain electrode layer. The third oxide semiconductor layer includes a region in contact with side surfaces of the second oxide semiconductor layer, the source electrode layer, the drain electrode layer, the second insulating layer, and the third insulating layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an article, a method, or a manufacturing method. Alternatively, the present invention relates to a process, a machine, , manufacture, or composition of matter. The present invention relates to, for example, a semiconductor device, a display device, a light-emitting device, a power storage device, an imaging device, and In particular, one embodiment of the present invention relates to a semiconductor device or a driving method thereof. or a method for producing the same.

[0002] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. The term generally refers to a semiconductor device. A transistor and a semiconductor circuit are examples of a semiconductor device. Display devices and electronic devices may include semiconductor devices. [Background technology]

[0003] The technology of constructing a transistor using a semiconductor film formed on a substrate with an insulating surface is attracting attention. The transistor is used in devices such as integrated circuits (ICs) and image display devices (display devices). Silicon is widely used as a semiconductor thin film that can be applied to transistors. Silicon-based semiconductor materials are widely known, but oxide semiconductors are also attracting attention. There are.

[0004] For example, indium (In), gallium (Ga), and A transistor using an amorphous oxide semiconductor containing zinc (Zn) is disclosed in Patent Document 1. There are. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-165528 Summary of the Invention [Problem to be solved by the invention]

[0006] As semiconductor elements continue to be miniaturized, parasitic capacitance near transistors becomes a major problem.

[0007] During transistor operation, the area near the channel (for example, between the source electrode and the drain electrode) If parasitic capacitance is present, it takes time for the parasitic capacitance to charge, slowing the transistor response. This reduces the performance and, ultimately, the response of the semiconductor device.

[0008] In addition, the various processes for forming transistors (especially film formation, processing, etc.) are becoming more and more difficult with each advance in miniaturization. It is becoming increasingly difficult to control this, and variations in the manufacturing process affect transistor characteristics, and has a significant impact on reliability.

[0009] Furthermore, as miniaturization progresses, pattern formation becomes difficult due to the resolution limit of exposure equipment, and Problems have arisen in the manufacturing of transistors, and the costs of capital investment are becoming enormous.

[0010] Therefore, one embodiment of the present invention aims to reduce parasitic capacitance near a transistor. Another object is to provide a semiconductor device with good electrical characteristics. Another object is to provide a highly reliable semiconductor device. Provides a manufacturing method for transistors or semiconductor devices that allows for pattern formation below the resolution limit Alternatively, the present invention aims to provide a method for manufacturing a transistor or a semiconductor device. One of the purposes is to reduce the variation in properties caused by the oxygen deficiency. Another object of the present invention is to provide a semiconductor device having a nitride semiconductor layer. Another object of the present invention is to provide a semiconductor device that can be formed in a short time. The object of the present invention is to provide a semiconductor device having a structure capable of reducing the interface state density in the vicinity of a compound semiconductor layer. Another object is to provide a semiconductor device with low power consumption. Another object is to provide a novel method for manufacturing a semiconductor device with reduced development costs. Another object is to provide a novel semiconductor device or the like. One of the objectives of the present invention is to provide a method for manufacturing the device.

[0011] The description of these problems does not preclude the existence of other problems. It is not necessary for the present invention to solve all of these problems. The above will be made clear from the description, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0012] One embodiment of the present invention is a semiconductor device including a first insulating layer, a first oxide semiconductor layer over the first insulating layer, and a first a second oxide semiconductor layer on the oxide semiconductor layer; a source electrode layer on the second oxide semiconductor layer; and a second insulating layer on the first insulating layer, the source electrode layer, and the drain electrode layer. an insulating layer, a third insulating layer on the second insulating layer, and a third oxide semiconductor layer on the second oxide semiconductor layer; a conductor layer, a gate insulating layer on the third oxide semiconductor layer, and a gate electrode layer on the gate insulating layer; , and the second insulating layer is an oxygen barrier layer, and the first oxide semiconductor layer, the second oxide semiconductor layer, a third oxide layer having a region in contact with the side surfaces of the semiconductor layer, the source electrode layer, and the drain electrode layer; The oxide semiconductor layer includes a second oxide semiconductor layer, a source electrode layer, a drain electrode layer, a second insulating layer, and a region in contact with the side surface of the third insulating layer.

[0013] Another embodiment of the present invention is a semiconductor device including a first insulating layer, a first oxide semiconductor layer over the first insulating layer, and a second insulating layer. a second oxide semiconductor layer on the first oxide semiconductor layer, and a source electrode on the second oxide semiconductor layer; a first conductive layer having a region in contact with the side surface of the second oxide semiconductor layer, a drain electrode layer, and the second oxide semiconductor layer; a first insulating layer, a second conductive layer, and a second insulating layer on the first insulating layer, the source electrode layer, and the drain electrode layer; a second insulating layer, a third insulating layer on the second insulating layer, and a third oxide semiconductor layer on the second oxide semiconductor layer; a gate insulating layer on the third oxide semiconductor layer; and a gate electrode on the gate insulating layer. the second insulating layer is an oxygen barrier layer, and the first electrode layer and the second electrode layer The third oxide semiconductor layer is in contact with the first insulating layer and the second insulating layer at the side surface thereof. A first oxide semiconductor layer, a second oxide semiconductor layer, a source electrode layer, a drain electrode layer, a second insulating layer, A semiconductor device having a region in contact with a side portion of an edge layer and a third insulating layer. be.

[0014] Another embodiment of the present invention is a semiconductor device including a first insulating layer, a first oxide semiconductor layer over the first insulating layer, and a second insulating layer. a second oxide semiconductor layer on the first oxide semiconductor layer, and a source electrode on the second oxide semiconductor layer; a first insulating layer, a source electrode layer, and a drain electrode layer; and a second insulating layer on the first insulating layer, the source electrode layer, and the drain electrode layer. a second insulating layer, a third insulating layer on the second insulating layer, and a source electrode layer and a drain electrode layer and a fourth insulating layer formed in contact with the side surfaces of the second insulating layer and the third insulating layer. a third oxide semiconductor layer on the second oxide semiconductor layer; and a gate electrode on the third oxide semiconductor layer. a gate insulating layer and a gate electrode layer on the gate insulating layer, the second insulating layer being an oxygen barrier layer a first oxide semiconductor layer, a second oxide semiconductor layer, a source electrode layer, and a drain electrode layer; The third oxide semiconductor layer has a region in contact with a side surface of the first insulating layer, the first oxide semiconductor layer, and the second oxide semiconductor layer. a second oxide semiconductor layer, a source electrode layer, a drain electrode layer, and a fourth insulating layer The semiconductor device is characterized by having a region that contacts the side surface of the edge layer.

[0015] In addition, it is preferable to use an aluminum oxide layer as the second insulating layer.

[0016] Another aspect of the present invention is a semiconductor device including a first conductive layer, a first insulating layer on the first conductive layer, and a first insulating layer. a first oxide semiconductor layer on the first oxide semiconductor layer; a second oxide semiconductor layer on the first oxide semiconductor layer; a source electrode layer and a drain electrode layer on the second oxide semiconductor layer, a first insulating layer, a source electrode layer, a drain electrode ... drain electrode layer, a source electrode layer, a drain electrode layer, a drain electrode layer, a drain electrode layer, a drain electrode layer, a drain electrode layer, a drain electrode layer, a drain electrode layer, a drain electrode layer, a a second insulating layer on the first electrode layer and the drain electrode layer; a third insulating layer on the second insulating layer; a third oxide semiconductor layer on the second oxide semiconductor layer; and a gate insulating film on the third oxide semiconductor layer. a gate electrode layer on the gate insulating layer; a third insulating layer; a third oxide semiconductor layer; a gate a fourth insulating layer on the gate electrode layer, the second insulating layer having an oxygen barrier a first oxide semiconductor layer, a second oxide semiconductor layer, a source electrode layer, and a drain electrode layer; The third oxide semiconductor layer is in contact with the side surface of the first insulating layer, the first oxide semiconductor layer, and the second oxide semiconductor layer. a second oxide semiconductor layer, a source electrode layer, a drain electrode layer, a second insulating layer, a third insulating layer, The fourth insulating layer has an area contacting the side surface of the edge layer, and the fourth insulating layer is an oxygen barrier layer. This is a semiconductor device.

[0017] It is also preferable to use an aluminum oxide film as the second insulating layer and the fourth insulating layer. It's nice.

[0018] Another embodiment of the present invention is a semiconductor device including: a first insulating layer; and a first oxide semiconductor film formed on the first insulating layer. a second oxide semiconductor film is formed over the first oxide semiconductor film, and a first heat treatment is performed. a first conductive film is formed over the second oxide semiconductor film; The first oxide semiconductor film and the second oxide semiconductor film are partly etched using the film. As a result, the first oxide semiconductor layer and the second oxide semiconductor layer are formed in an island shape, and the first A second insulating layer is formed on the insulating layer and the first conductive film, and when the second insulating layer is formed, the first A mixed layer of an insulating layer and a second insulating film is formed, and at the same time, an acid is introduced into the mixed layer or the first insulating layer. oxygen is added to the second oxide semiconductor layer, and second heat treatment is performed to diffuse oxygen into the second oxide semiconductor layer. A third insulating film is formed on the insulating layer, and the third insulating layer is subjected to a planarization process to form the third insulating layer. Then, the third insulating layer and the second insulating layer are selectively etched using a second mask. The first conductive film is selectively etched using the second mask and the second insulating layer. The source electrode layer and the drain electrode layer are formed by the above-mentioned method, and the third insulating layer and the second oxide semiconductor are formed by the above-mentioned method. A third oxide semiconductor film is formed on the conductor layer, and a fourth insulating film is formed on the third oxide semiconductor film. a second conductive film is formed on the fourth insulating film; and a second conductive film, a third insulating film, and a third insulating film are formed on the fourth insulating film. The third oxide semiconductor film is subjected to chemical mechanical polishing treatment to form a third oxide semiconductor layer, A method for manufacturing a semiconductor device, comprising forming a gate insulating layer and a gate electrode layer. be.

[0019] Another embodiment of the present invention is a semiconductor device including: a first insulating layer; and a first oxide semiconductor film formed on the first insulating layer. a second oxide semiconductor film is formed over the first oxide semiconductor film, and a first heat treatment is performed. a first conductive film is formed over the second oxide semiconductor film; The first oxide semiconductor film and the second oxide semiconductor film are selectively etched using the film. As a result, the first oxide semiconductor layer and the second oxide semiconductor layer are formed in an island shape, and the first A second insulating film is formed on the insulating layer and the first conductive film, and the first insulating film is formed on the second insulating film. forming a mixed layer of the insulating layer and the second insulating film, and adding oxygen to the mixed layer or the first insulating layer; Second heat treatment is performed to diffuse oxygen into the second oxide semiconductor layer. The oxygen vacancies in the layer are reduced, a third insulating film is formed on the second insulating film, and a flat insulating film is formed on the third insulating film. A planarization process is performed, and the third insulating film and a part of the second insulating film are etched using a second mask. The third insulating layer and the second insulating layer are formed by etching, and the first conductive layer, the third A fourth insulating film is formed on the insulating layer and anisotropically etched to form the second insulating layer and the A fourth insulating layer is formed in contact with the side surfaces of the third insulating layer, and the fourth insulating layer is used as a mask. By etching a part of the first conductive film, the source electrode and the drain electrode are formed. and forming a third oxide semiconductor film over the third insulating layer and the second oxide semiconductor layer. A fifth insulating film is formed over the third oxide semiconductor film, and a second conductive film is formed over the fifth insulating film. The second conductive film, the third insulating film, and the third oxide semiconductor film are subjected to chemical mechanical polishing treatment. By performing the above steps, a third oxide semiconductor layer, a gate insulating layer, and a gate electrode layer are formed. The present invention is a method for manufacturing a semiconductor device, characterized by the above-mentioned.

[0020] The second insulating film is preferably formed by sputtering using oxygen gas. stomach.

[0021] The second insulating film is formed by sputtering using an aluminum oxide target. It is preferable to form the film on a silicon oxide film under conditions containing 50% by volume or more of oxygen.

[0022] The second heat treatment is preferably performed at a temperature of 300° C. or higher and 450° C. or lower.

[0023] Moreover, a structure using a semiconductor device, a microphone, a speaker, and a housing can be used. [Effects of the Invention]

[0024] By using one embodiment of the present invention, parasitic capacitance near a transistor can be reduced. Alternatively, a semiconductor device having good electrical characteristics can be provided. Alternatively, a pattern can be formed below the resolution limit of an exposure device. It is possible to provide a method for manufacturing a transistor or a semiconductor device that can It is possible to reduce variations in the characteristics of transistors or semiconductor devices due to the manufacturing process. Alternatively, a semiconductor device including an oxide semiconductor layer with few oxygen vacancies can be provided. Alternatively, a semiconductor device that can be formed through a simple process can be provided. Alternatively, a semiconductor device having a structure capable of reducing interface states in the vicinity of an oxide semiconductor layer is provided. Alternatively, a semiconductor device with low power consumption can be provided. It is possible to provide a new method for manufacturing a semiconductor device with reduced development costs. A semiconductor device or the like can be provided. Or, a method for manufacturing the semiconductor device can be provided. can be done.

[0025] The description of these effects does not preclude the existence of other effects. The embodiment does not necessarily have to have all of these effects. , the specification, drawings, claims, etc., and It is possible to extract other effects from the claims and other descriptions. [Brief explanation of the drawings]

[0026] [Figure 1] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 2] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 3] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 4] 10A and 10B are band diagrams of an oxide semiconductor layer and an enlarged cross-sectional view of a transistor. [Figure 5] ALD film formation principle. [Figure 6] Schematic diagram of the ALD equipment. [Figure 7] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 8] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 9] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 10] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 11] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 12] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 13] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 14] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 15] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 16] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 17] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 18] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 19] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 20] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 21] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 22] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 23] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 24] Cs-corrected high-resolution TEM image of a cross section of CAAC-OS, and a schematic cross-sectional diagram of CAAC-OS. [Figure 25] Cs-corrected high-resolution TEM image of the CAAC-OS in the plane. [Figure 26] 10A and 10B illustrate structural analyses of a CAAC-OS and a single-crystal oxide semiconductor by XRD. [Figure 27] Electron diffraction pattern of CAAC-OS. [Figure 28] FIG. 1 shows the change in the crystalline part of an In-Ga-Zn oxide due to electron irradiation. [Figure 29] 1A and 1B are cross-sectional views and a circuit diagram of a semiconductor device. [Figure 30] 1A and 1B are cross-sectional views and a circuit diagram of a semiconductor device. [Figure 31] FIG. [Figure 32] FIG. 2 is a plan view showing pixels of the imaging device. [Figure 33] FIG. [Figure 34] FIG. [Figure 35] FIG. 2 is a diagram illustrating an example of the configuration of an RF tag. [Figure 36] FIG. 2 is a diagram illustrating an example of the configuration of a CPU. [Figure 37] Circuit diagram of a memory element. [Figure 38] 1A and 1B are diagrams illustrating a structural example of a display device and a circuit diagram of a pixel. [Figure 39] FIG. 2 is a diagram illustrating a display module. [Figure 40] FIG. 1 is a perspective view showing a cross-sectional structure of a package using a lead frame type interposer. [Figure 41] 1A to 1C illustrate electronic devices. [Figure 42] 1A to 1C illustrate electronic devices. [Figure 43] 1A to 1C illustrate electronic devices. [Figure 44] 1A to 1C illustrate electronic devices. DETAILED DESCRIPTION OF THE INVENTION

[0027] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention may be modified in various forms and details without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that the present invention can be modified in various ways. The present invention is not limited to the above-described embodiments. In the drawings, the same reference numerals are used to designate the same parts or parts having similar functions. The same elements in the drawings are used interchangeably, and repeated explanations may be omitted. In some cases, the timing may be omitted or changed as appropriate between different drawings.

[0028] For example, in this specification, when it is explicitly stated that X and Y are connected, In this case, X and Y are electrically connected, and X and Y are functionally connected. The case where X and Y are directly connected is also considered to be disclosed in this specification. Therefore, the present invention is not limited to the predetermined connection relationships, for example, the connection relationships shown in the drawings or text. Connections other than those shown in the drawings or text are also treated as if they were described in the drawings or text. do.

[0029] Here, X and Y are the object (for example, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, etc.). , etc.).

[0030] An example of a direct connection between X and Y is a circuit that allows electrical connection between X and Y. The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, When no external device (such as a diode, display element, light-emitting element, or load) is connected between X and Y, The elements that allow electrical connection between X and Y (e.g., switches, transistors, capacitors) elements, inductors, resistors, diodes, display elements, light-emitting elements, loads, etc.) , X and Y are connected.

[0031] An example of an electrical connection between X and Y is The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, One or more devices (such as diodes, display elements, light-emitting elements, and loads) can be connected between X and Y. It is possible. The switch has a function to control on / off. A switch can be in a conducting state (ON state) or a non-conducting state (OFF state), allowing current to flow. The switch has the function of controlling whether or not the current flows. When X and Y are electrically connected, This includes the case where Y is directly connected.

[0032] An example of a functional connection between X and Y is a function that allows the functional connection between X and Y. Circuits that perform the above functions (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (voltage power supply circuits (voltage boost circuits, voltage drop circuits, etc.), level shifter circuits that change the signal potential level, etc.) , voltage source, current source, switching circuit, amplifier circuit (which can increase the signal amplitude or current amount, etc.) circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation One or more circuits (e.g., memory circuits, control circuits, etc.) can be connected between X and Y. For example, even if another circuit is inserted between X and Y, the signal output from X If X is transmitted to Y, then X and Y are considered to be functionally connected. When X and Y are functionally connected, there is a direct connection between X and Y and a direct connection between X and Y. This also includes the case where the and are electrically connected.

[0033] In addition, if it is explicitly stated that X and Y are electrically connected, are electrically connected (i.e., there is another element or circuit between X and Y) X and Y are functionally connected (i.e., X and Y are functionally connected) and (When there is a functional connection between them via another circuit) and when X and Y are directly connected (i.e., when X and Y are connected without any other element or circuit between them) is considered to be disclosed in the present specification. If it is explicitly stated that it is connected, The same content is considered to be disclosed in the present specification.

[0034] For example, if the source (or first terminal, etc.) of the transistor is connected via Z1 (or (not shown), electrically connected to X, and the drain (or second terminal, etc.) of the transistor is connected to Z 2 (or not), and is electrically connected to Y, or the source of the transistor (or the first terminal, etc.) is directly connected to a part of Z1, and another part of Z1 is directly connected to X. The drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2. and another part of Z2 is directly connected to Y, It is possible to do so.

[0035] For example, "X and Y and the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor" The terminals of the transistor (or the first terminal) are electrically connected to each other. 1 terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y. It can be expressed as "connected to the source (or the first The first terminal of the transistor is electrically connected to X, and the drain of the transistor is electrically connected to the second terminal of the transistor. The transistor source (or first terminal, etc.) is electrically connected to Y, and the transistor source (or first terminal, etc.) is electrically connected to X. The drain (or second terminal, etc.) of the transistor, Y, is electrically connected in this order. " Alternatively, "X is the source (or first terminal, etc.) of the transistor. and the drain (or second terminal, etc.) are electrically connected to Y, and X, the source (or first terminal, etc.) of a transistor, the drain (or second terminal, etc.) of a transistor ), Y is provided in this order of connection. By specifying the order of connections in the circuit configuration using a simple expression method, Distinguish between the source (or first terminal, etc.) and the drain (or second terminal, etc.) of a transistor. The technical scope can be determined by the above.

[0036] Alternatively, for example, "the source (or first terminal, etc.) of a transistor" is electrically connected to X through at least a first connection path, and the first connection path is , the second connection path does not have a second connection path, and the second connection path is a The source (or first terminal, etc.) of the transistor and the drain (or second terminal, etc.) of the transistor The first connection path is a path via Z1, and the second connection path is a path between the first and second transistors. The drain (or second terminal, etc.) of the capacitor is electrically connected to Y through at least a third connection path. The third connection path does not have the second connection path, and the third The connection path is the path via Z2. The source (or first terminal, etc.) of the resistor is connected to the resistor via Z1 by at least the first connection path. and electrically connected to X, and the first connection path does not have a second connection path, The second connection path has a connection path through a transistor, and the drain of the transistor (or the second terminal, etc.) is connected to Y via Z2 by at least a third connection path. The third connection path does not have the second connection path. Alternatively, the source (or first terminal, etc.) of the transistor may be at least The first electrical path is electrically connected to X through Z1. The primary path does not have a second electrical path, and the second electrical path is a From the source (or first terminal, etc.) to the drain (or second terminal, etc.) of the transistor The drain (or second terminal, etc.) of the transistor is connected to at least a third The third electrical path is electrically connected to Y through Z2. , does not have a fourth electrical path, and the fourth electrical path is a drain of the transistor (or second terminal, etc.) to the source (or first terminal, etc.) of the transistor. Using the same expression as these examples, the circuit configuration By defining the connection path in Distinguishing between the first terminal (or the second terminal, etc.) and the drain (or the second terminal, etc.) to determine the technical scope. can be done.

[0037] These representation methods are merely examples, and the present invention is not limited to these representation methods. , Y, Z1, Z2 are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layer, etc.).

[0038] In addition, the circuit diagram shows independent components as if they are electrically connected to each other. Even if the components are different, one component may have the functions of multiple components. For example, when a part of the wiring also functions as an electrode, one conductive film functions as both the wiring and the electrode. Therefore, the electrode in this specification has the functions of both components. The term "electromagnetic connection" refers to a case where one conductive film has the functions of multiple components. This also falls within the scope of the above.

[0039] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention is not limited to the above embodiments, and various changes and modifications may be made in the form and details thereof without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that the present invention can be achieved by the following embodiments. It should not be construed as being limited to the contents of the description. The same reference numerals are used in different drawings to denote the same parts or parts having similar functions. A repeated explanation will be omitted.

[0040] <Notes regarding the description of the drawings> In this specification, the terms "above" and "below" that indicate the positional relationship between components are used. , are used for convenience in explanation with reference to the drawings. The meaning of the wording in the specification changes depending on the direction in which the configuration is depicted. It is not limited to this and can be rephrased appropriately depending on the situation.

[0041] In addition, the terms "above" and "below" refer to the positional relationship of the components directly above or below, and directly adjacent to each other. For example, if the expression is "electrode B on insulating layer A," Electrode B does not need to be formed directly on insulating layer A, but between insulating layer A and electrode B This does not exclude the inclusion of other components.

[0042] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case of -5° or more and 5° or less. "Line" refers to the state in which two straight lines are arranged at an angle between -30° and 30°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes the case where the angle is between 85° and 95°. This refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0043] In addition, in this specification, when the crystal is a trigonal or rhombohedral crystal, it is expressed as a hexagonal crystal system. .

[0044] In addition, in the drawings, the size, thickness of a layer, or area is shown arbitrarily for the convenience of explanation. Therefore, the drawings are not necessarily limited to the scale. The drawings are merely schematic illustrations for the purpose of illustration, and are not limited to the shapes or values ​​shown in the drawings.

[0045] In addition, in the drawings, top views (also called plan views or layout views) and perspective views, In order to clarify the drawings, some components may be omitted.

[0046] In addition, "the same" may mean having the same area or the same shape. Due to the manufacturing process, it is expected that the shapes will not be completely identical. This can be rephrased as being the same.

[0047] <Notes regarding possible paraphrases> In this specification and the like, when describing the connection relationship of a transistor, one of the source and the drain is referred to as "one of the source and drain" (or the first electrode, or the first terminal), and The other side of the drain is referred to as the "other side of the source or drain" (or second electrode, or second terminal). This means that the source and drain of a transistor are This is because it changes depending on the conditions. Regarding the names of the source and drain of a transistor, can be appropriately rephrased as source (drain) terminal, source (drain) electrode, etc. depending on the situation. It can be done.

[0048] In addition, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring." Furthermore, the terms "electrode" and "wiring" are used interchangeably to refer to the plural "electrodes" and "wirings." This also includes cases where the "line" is formed as a single unit.

[0049] In this specification, a transistor includes a gate, a drain, and a source. It is an element with at least three terminals. And, the drain (drain terminal, drain A channel is formed between the source (source terminal, source region or drain electrode) and the source (source terminal, source region or source electrode). The transistor has a channel region and allows current to flow through the drain, channel region, and source. It is possible.

[0050] Here, the source and drain vary depending on the structure or operating conditions of the transistor. Therefore, it is difficult to determine which is the source and which is the drain. The part that functions as a source and the part that functions as a drain are not called source or drain. One of the source and the drain is referred to as a first electrode, and the other of the source and the drain is referred to as a second electrode. It may be written.

[0051] In this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion of the elements. It should be noted that the numbers are added to avoid confusion and are not intended to be limiting.

[0052] In this specification, the substrate of the display panel is provided with, for example, an FPC (Flexible Printed Circuit). Switched Circuits) or TCP (Tape Carrier Packet ge) or COG (Chip On Glass) on the board A display device is sometimes called a display device when an IC (integrated circuit) is directly mounted on it.

[0053] Also, the words "film" and "layer" may be used interchangeably depending on the situation. For example, the term "conductive layer" can be replaced with "conductive film." ". Alternatively, for example, the term "insulating film" may be used. It may be possible to change the term to "insulating layer."

[0054] <Notes on definitions of terms> The definitions of each term used in this specification will be explained below.

[0055] In this specification, the term "trench" or "groove" refers to a thin, band-like depression. It refers to the

[0056] In this specification, when a film is referred to as silicon oxynitride, it is referred to as SiOxNy. In this case, x and y may be natural numbers or numbers with decimal points. Good too.

[0057] <About connection> In this specification, "A and B are connected" does not mean that A and B are directly connected. In addition to the above, it also includes those that are electrically connected. Connected means that there is an object between A and B that has some electrical effect. , which enables the transmission and reception of electrical signals between A and B.

[0058] These representation methods are merely examples, and the present invention is not limited to these representation methods. , Y, Z1, Z2 are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layer, etc.).

[0059] Note that the content (or even a part of the content) described in one embodiment may be used in conjunction with that embodiment. Other content (or even part of content) described in the context, and / or one or more other embodiments The contents (or a part of the contents) described in the embodiments may be applied, combined, or replaced. You can do things like drawing.

[0060] The contents described in the embodiments are explained in detail in each embodiment using various drawings. This refers to the content that is stated or the content that is stated using the text in the specification.

[0061] In addition, a drawing (or a part thereof) described in one embodiment may be different from another part of the drawing, Another figure (or a part thereof) described in the embodiment, and / or one or more By combining the figures (or a part thereof) described in other embodiments of the present invention, This allows for even more diagrams to be constructed.

[0062] (Embodiment 1) In this embodiment, a semiconductor device according to one embodiment of the present invention and a manufacturing method thereof will be described with reference to drawings. explain.

[0063] 1A, 1B, and 1C are top views and diagrams of a transistor 10 according to one embodiment of the present invention. 1(A) is a top view, and FIG. 1(B) is a cross-sectional view of the device shown in FIG. 1(A). FIG. 1(A) is a cross-sectional view between A1 and A2, and FIG. 1(C) is a cross-sectional view between A3 and A4. For clarity, some elements are shown enlarged, reduced, or omitted. The A1-A2 direction is called the channel length direction, and the dashed dotted line A3-A4 direction is called the channel width direction. There are cases where this happens.

[0064] The transistor 10 includes a substrate 100, an insulating layer 110, an oxide semiconductor layer 121, and an oxide The semiconductor layer 122, the oxide semiconductor layer 123, the source electrode layer 130, and the drain electrode layer 1 40, a gate insulating layer 150, a gate electrode layer 160, an insulating layer 170, and an insulating layer 175. The insulating layer 110 is formed on the substrate 100. The oxide semiconductor layer 121 has: The oxide semiconductor layer 122 is formed on the insulating layer 110. The source electrode layer 130 and the drain electrode layer 140 are formed on the oxide semiconductor layer 122. The insulating layer 170 is formed on the insulating layer 110 and is electrically connected to the oxide semiconductor layer 122. , the source electrode layer 130, and the drain electrode layer 140. The insulating layer 175 is formed on the insulating layer 170 and is in contact with the side surface of the oxide semiconductor layer 122. The oxide semiconductor layer 123 is in contact with the oxide semiconductor layer 123 at the portion. The oxide semiconductor layer 123 is formed on the side surface of the insulating layer 170 and the insulating layer 175. The gate electrode layer 130 contacts the side surface of the gate electrode layer 130, the side surface of the source electrode layer 130, and the side surface of the drain electrode layer 140. The gate insulating layer 150 is formed on the oxide semiconductor layer 123. The gate electrode layer 160 is It is formed on the insulating layer 150 .

[0065] In FIG. 1B, the gate electrode layer 160 is shown as a single layer. The transistor 10 may include a stack of the electrode layer 161 and the gate electrode layer 162. The end portions of the oxide semiconductor layer 123 and the gate insulating layer 150 are closer to each other than the gate electrode layer 160. The above-described structure also includes an oxide semiconductor layer 122 and an oxide semiconductor layer 123. Since the semiconductor layer 123 is in contact with the source electrode layer 130 and the drain electrode layer 140, During operation of the transistor 10, the oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123 are The conductive layer 123 has a high heat dissipation effect against heat generated within the conductive layer 123 .

[0066] In addition, when forming the second insulating film that will become the insulating layer 170, the transistor 10 The material of the insulating layer 110 and the material of the second insulating film are formed at the interface with the insulating layer 10. A mixed layer containing the gases and the like is formed, and oxygen (excess oxygen) is added to the mixed layer or the insulating layer 110. Further, by performing heat treatment, the oxygen is added to the oxide semiconductor layer. 121 and the oxide semiconductor layer 122, and The oxygen can compensate for the oxygen vacancies present in the layer 122. The transistor characteristics (for example, threshold voltage, reliability, etc.) can be improved.

[0067] The excess oxygen added during the formation of the second insulating film is generated by, for example, sputtering. The oxygen radiance is affected by the voltage, power, plasma, or substrate temperature applied during film formation. The excess oxygen exists in various forms, such as oxygen atoms, oxygen ions, or oxygen atoms. is a state that has more energy than the stable state, and penetrates into the insulating layer 110. It is possible.

[0068] The method for adding oxygen is not limited to the above method. It may have excess oxygen or may be formed by other methods (e.g., ion implantation, ion plasma) after film formation. A dipping method or the like may also be used.

[0069] As shown in the cross-sectional view of FIG. 1C, the transistor 10 has a channel width direction The gate electrode layer 160 is connected to the oxide semiconductor layer 121 and the oxide semiconductor layer 122 via the gate insulating layer 150. The conductive layer 122 faces the side surface of the oxide semiconductor layer 123. That is, the gate electrode layer 160 is electrically connected to the conductive layer 122. When pressure is applied, the oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 12 3 is surrounded by the electric field of the gate electrode layer 160 in the channel width direction. The structure of a transistor in which the semiconductor layer is surrounded by an electric field of 0 is called a surrounded channel. The transistor 10 has a cell structure using a trench. Since the gate electrode, source electrode, and drain electrode can be formed in a near-inverter, This method has excellent alignment accuracy and makes it possible to easily fabricate fine transistors. Such a structure is called a self-aligned s-channel FET (Self Aligned s -channel FET, SA s-channel FET) structure, or trench Gate s-channel FET(Trench gate s-channel F FET), or TGSA FET (Trench Gate Self Align) structure or GLSA FET (Gate Last Self Align FET) Call.

[0070] Here, the oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123 are combined. When the oxide semiconductor layer 120 is formed by combining these, a transistor having an SA s-channel structure is obtained. In the on-state, a channel is formed in the entire oxide semiconductor layer 120 (bulk). On the other hand, in the off state, the on-state current increases. Since the entire channel region is depleted, the off-current can be further reduced.

[0071] As a result, the oxide semiconductor layer 123, the gate insulating layer 150, and the gate electrode layer 124 are formed in the groove 174. When forming the transistor 10, the embedding property of each film can be improved. It can be easily produced.

[0072] Furthermore, since the transistor 10 has a TGSA structure, the gate electrode and the source electrode or reducing the parasitic capacitance occurring between the gate electrode and the drain electrode, thereby reducing the cutoff frequency of the transistor 10. This allows the transistor 10 to have a high-speed response, for example, by improving the wave number characteristics.

[0073] The position of the top surface of the source electrode layer 130 or the drain electrode layer 140 is the same as that of the gate electrode layer It may be lower than the position of the bottom surface of 160, may be the same as, or may be higher.

[0074] In addition, the transistor 10 may have a linear groove 174 as shown in FIG. 2B, the upper surface of the gate electrode layer 160 is higher than the upper surface of the insulating layer 175. The transistor 10 may be provided with an insulating film 150a, as shown in FIG. The third oxide semiconductor film 123a does not necessarily need to be subjected to planarization treatment. As shown in FIG. 3(A), the edge portions of the source electrode layer 130 and the drain electrode layer are oxide-coated. The insulating layer 122 may have a shape that is shorter or longer than the insulating layer 122 .

[0075] <Channel length> Note that the channel length is, for example, the length of a semiconductor (or transistor) in a top view of a transistor. The area where the gate electrode overlaps with the semiconductor (the part of the semiconductor through which current flows when the transistor is in the on state). or the source (source region or source electrode) in the region where the channel is formed This refers to the distance between the transistor and the drain (drain region or drain electrode). In a transistor, the channel length does not necessarily have the same value in all regions. The channel length of a transistor may not be determined to a single value. The channel length is one of the values, the maximum value, and the minimum value in the region where the channel is formed. Or the average value.

[0076] <About channel width> The channel width is the width of the semiconductor (or transistor) when it is in the on state. This refers to the length of the area where the gate electrode overlaps with the current-carrying part of a transistor. In a transistor, the channel width does not necessarily have the same value in all regions. The channel width of a transistor may not be determined to a single value. The channel width is any one value, maximum value, minimum value or the like in the region where the channel is formed. or the average value.

[0077] Depending on the structure of the transistor, the channel in the region where the channel is actually formed may be The effective channel width (hereinafter referred to as the effective channel width) and the The channel width (hereinafter referred to as apparent channel width) may differ from the actual channel width. For example, In a transistor having a three-dimensional structure, the effective channel width is The apparent channel width becomes larger than that shown in For example, in a transistor with a fine, three-dimensional structure, The ratio of the channel region formed on the side of the semiconductor to the channel region formed In this case, the apparent channel width shown in the top view may be larger. The effective channel width where the channel is actually formed is larger than the actual channel width.

[0078] In the case of a transistor having a three-dimensional structure, the effective channel width is measured. For example, it may be difficult to estimate the effective channel width from the design value. In order to obtain this, it is necessary to assume that the shape of the semiconductor is known. If is not known accurately, it is difficult to accurately measure the effective channel width.

[0079] <SCWについて> Therefore, in this specification, in a top view of a transistor, a semiconductor and a gate electrode are overlapped. The apparent channel width in the region is called the "surrounding channel width (SCW)." In this specification, it is sometimes referred to as "Dedicated Channel Width." When we refer to channel width, it refers to enclosed channel width or apparent channel width. In this specification, when simply referring to the channel width, it may refer to the effective channel width. It may refer to the channel width. The upper channel width, the enclosed channel width, etc. are obtained by taking a cross-sectional TEM image. The value can be determined, such as by analysis.

[0080] The field effect mobility of the transistor and the current value per channel width are calculated. In this case, the effective channel width is calculated using the enclosed channel width. The value may differ from that calculated using the channel width.

[0081] <Improved characteristics through miniaturization> To increase the integration density of semiconductor devices, miniaturization of transistors is essential. It is known that the electrical characteristics of transistors deteriorate as the channel width shrinks. When the value is reduced, the on-state current decreases.

[0082] For example, in the transistor of one embodiment of the present invention shown in FIG. 1, as described above, the channel is formed A third oxide semiconductor layer 123 is formed to cover the oxide semiconductor layer 122 formed on the first oxide semiconductor layer 121. Therefore, the channel formation layer and the gate insulating layer do not come into contact with each other. This can suppress the scattering of carriers at the interface between the layer and the gate insulating layer, The on-state current can be increased.

[0083] In the transistor of one embodiment of the present invention, the oxide semiconductor layer 122 serving as a channel Since the gate electrode layer 160 is formed so as to electrically surround the panel in the width direction, the oxide In addition to the gate electric field from the vertical direction, the semiconductor layer 1223 is also subjected to the gate electric field from the side direction. That is, the gate electric field is applied to the entire oxide semiconductor layer. As a result, the current flows through the entire oxide semiconductor layer 122, which further increases the on-state current. can be.

[0084] In the transistor of one embodiment of the present invention, the oxide semiconductor layer 123 is By forming the oxide semiconductor layer 122, it is possible to prevent the formation of an interface state. By making the semiconductor layer 122 the layer positioned in the middle, the influence of impurities mixed in from above and below can be eliminated. Therefore, in addition to the improvement in the on-state current of the transistor, This makes it possible to stabilize the threshold voltage and reduce the S value (subthreshold value). Therefore, Icut (current when gate voltage VG is 0V) can be reduced, and power consumption In addition, the threshold voltage of the transistor is stabilized, The long-term reliability of the semiconductor device can be improved.

[0085] In this embodiment, the oxide semiconductor layer 120 is used in the channel. However, one aspect of the embodiment of the present invention is not limited to this. Depending on the circumstances, the channel, its vicinity, source region, drain region, etc. Depending on the material, silicon (including strained silicon), germanium, silicon germanium, silicon carbide Cu, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, organic It may be formed of a material having a semiconductor or the like.

[0086] <Transistor configuration> The structure of a transistor in this embodiment will be described below.

[0087] <<Substrate 100>> The substrate 100 may be, for example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, etc. In addition, a single crystal semiconductor substrate made of silicon or silicon carbide, a multi-crystal crystalline semiconductor substrate, compound semiconductor substrate made of silicon germanium, SOI (Semiconductor It is also possible to use a conductor-on-insulator substrate, A semiconductor element may be provided on one of these substrates. The substrate 100 is not limited to being a simple support material, but also includes a substrate on which other devices such as transistors are formed. In this case, the gate electrode layer 160 and the source electrode layer 13 of the transistor 0, and one of the drain electrode layers 140 is electrically connected to the other devices mentioned above. That's fine.

[0088] A flexible substrate may be used as the substrate 100. As a method for providing a transistor, a transistor is formed on a non-flexible substrate, and then a transistor is formed on the substrate. There is also a method of peeling off the substrate and transferring it to the substrate 100, which is a flexible substrate. A peeling layer may be provided between the substrate and the transistor. Alternatively, a sheet, film, or foil containing the material may be used. In addition, the substrate 100 has the property of returning to its original shape when the bending or pulling is stopped. Alternatively, the substrate 100 may have a property of not returning to its original shape. is, for example, 5 μm or more and 700 μm or less, preferably 10 μm or more and 500 μm or less, and The thickness of the substrate 100 is preferably 15 μm or more and 300 μm or less. Furthermore, by making the substrate 100 thinner, it is possible to reduce the weight of the substrate 100 when using glass or the like. It has the property of being stretchable even when bent or pulled, and of returning to its original shape when bending or pulling is stopped. Therefore, the semiconductor device on the substrate 100 may be subjected to a shock due to being dropped or the like. In other words, a robust semiconductor device can be provided.

[0089] The substrate 100, which is a flexible substrate, may be made of, for example, a metal, an alloy, a resin, or glass. The substrate 100, which is a flexible substrate, has a linear expansion coefficient of The lower the temperature, the more preferable it is, since deformation due to the environment is suppressed. For example, the linear expansion coefficient is 1×10 -3 / K or less, 5×10 -5 / K or less, or 1×10 -5 The resin may be, for example, polyester or polyolefin. Polyimide, polycarbonate, acrylic Aramid, in particular, has a linear expansion coefficient of Since the resistance is low, it is suitable for the substrate 100, which is a flexible substrate.

[0090] Insulating layer 110 The insulating layer 110 serves to prevent the diffusion of impurities from the substrate 100 and also serves to prevent the oxide semiconductor from diffusing. The insulating layer 110 can supply oxygen to the conductor layer 120. It is preferable that the insulating film contains oxygen in an amount greater than the stoichiometric composition. For example, it is more preferable that the amount of released oxygen converted into oxygen atoms by the TDS method is 1.0 x10 19 atoms / cm 3The membrane is the above. The surface temperature is in the range of 100°C to 700°C or 100°C to 500°C. As described above, when the substrate 100 is a substrate on which other devices are formed, In this case, the insulating layer 110 is formed so as to have a flat surface. It can be polished by chemical mechanical polishing (CMP) method. It is preferable to carry out a smoothing treatment.

[0091] <Oxide semiconductor layers 121, 122, and 123> The oxide semiconductor layer 122 is an oxide semiconductor film containing In or Zn, and is typically In-Ga oxide, In-Zn oxide, In-Mg oxide, Zn-Mg oxide, In-M -Zn oxide (M is Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, or Nd ) is available.

[0092] The oxide semiconductor layers 121, 122, and 123 are formed of The oxide semiconductor that can be used contains at least indium (In) or zinc (Zn). It is preferable that the oxide contains both In and Zn. In order to reduce the variations in the electrical characteristics of semiconductor transistors, Preferably, it includes a riser.

[0093] Stabilizers include gallium (Ga), tin (Sn), hafnium (Hf), and aluminum. Aluminum (Al) or zirconium (Zr). Also, other stabilizers The lanthanides are lanthanum (La), cerium (Ce), and praseodymium (P r), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium ( Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium Er, Thulium, Ytterbium, Lutetium, etc. .

[0094] When the oxide semiconductor layer 123 is an In-M-Zn oxide, the atomic ratio of In to M is is preferably 25 atomic % or more of In and less than 75 atomic % of M, Preferably, In is 34 atomic % or more and M is less than 66 atomic %.

[0095] The content of indium, gallium, etc. in the oxide semiconductor layer 123 is determined by time-of-flight secondary ion Mass spectrometry (TOF-SIMS), X-ray electron spectroscopy (XPS), ICP mass spectrometry (IC P-MS) can be used for comparison.

[0096] The oxide semiconductor layer 122 has an energy gap of 2 eV or more, preferably 2.5 eV or more. More preferably, the voltage is 3 eV or more, so that the off-state current of the transistor 10 can be reduced. can.

[0097] The thickness of the oxide semiconductor layer 122 is 3 nm to 200 nm, preferably 3 nm to 100 nm. 0 nm or less, and more preferably 3 nm or more and 50 nm or less.

[0098] The oxide semiconductor layer 121 and the oxide semiconductor layer 123 constitute the oxide semiconductor layer 122. Therefore, the oxide semiconductor layer 12 is an oxide semiconductor film composed of one or more elements. 2 and the oxide semiconductor layer 122 and the oxide semiconductor layer 124, the interface scattering occurs. Therefore, the movement of carriers is not hindered at the interface, and the transistor The field effect mobility of the sintered body 10 is increased.

[0099] The oxide semiconductor layer 121 and the oxide semiconductor layer 123 are typically made of In—Ga oxide, In -Zn oxide, In-Mg oxide, Ga-Zn oxide, Zn-Mg oxide, In-MZ n oxides (M is Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, or Nd) and the energy level of the conduction band minimum is closer to the vacuum level than that of the oxide semiconductor layer 122. Typically, the energy of the conduction band minimum of the oxide semiconductor layer 121 and the oxide semiconductor layer 123 is , the difference in energy between the oxide semiconductor layer 122 and the conduction band minimum is 0.05 eV or more, 7 eV or more, 0.1 eV or more, or 0.2 eV or more and 2 eV or less, 1 eV or less, 0 That is, the oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123 are not more than 0.5 eV, or not more than 0.4 eV. The difference between the electron affinity of the oxide semiconductor layer 123 and the electron affinity of the oxide semiconductor layer 122 is 0.05 e V or more, 0.07 eV or more, 0.1 eV or more, or 0.2 eV or more and 2 eV or less, The electron affinity is 1 eV or less, 0.5 eV or less, or 0.4 eV or less. This indicates the difference in energy between the level and the bottom of the conduction band.

[0100] The oxide semiconductor layer 121 and the oxide semiconductor layer 123 may be formed of Al, Ti, Ga, Y, Zr, or S. By having In, La, Ce, Mg, or Nd in a higher atomic ratio than In, the following effects can be achieved: (1) The oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123 may have an effect. (2) The energy gap of the oxide semiconductor layer 121 is increased. (3) To block impurities from the outside. 4) Higher insulating properties compared to the oxide semiconductor layer 122. (5) Al, Ti, Ga, Y , Zr, Sn, La, Ce, Mg, or Nd are metal elements that bond strongly with oxygen. Therefore, Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, or Nd should be used at a higher concentration than In. By having a low atomic ratio, oxygen deficiency is less likely to occur.

[0101] Note that the oxide semiconductor layers 121 and 123 have a higher conductivity than the oxide semiconductor layer 122. Since it has high insulating properties, it has the same function as a gate insulating layer.

[0102] When the oxide semiconductor layer 121 and the oxide semiconductor layer 123 are made of In-M-Zn oxide, Zn The atomic ratio of In and M excluding O is preferably 50 atomic percent In. % or less, M is 50 atomic % or more, and more preferably In is 25 atomic % or more. Bottom, M must be 75 atomic% or more.

[0103] The oxide semiconductor layer 121 and the oxide semiconductor layer 123 are made of In-M-Zn oxide (M is Al , Ti, Ga, Y, Zr, Sn, La, Ce, Mg, or Nd), oxide semiconductor Compared with the oxide semiconductor layer 122, the M(Al , Ti, Ga, Y, Zr, Sn, La, Ce, Mg, or Nd) atomic ratio is high, and Generally, the amount of the atoms contained in the oxide semiconductor layer 123 is preferably 1.5 times or more. The atomic ratio is preferably at least two times, more preferably at least three times higher. Since indium bonds more strongly with oxygen than indium, oxygen vacancies occur in the oxide semiconductor layer 121 and the oxide semiconductor layer 122. The oxide semiconductor layer 121 and the oxide semiconductor layer 123 have a function of suppressing the generation of the oxide semiconductor layer 121 and the oxide semiconductor layer 123. The oxide semiconductor layer 123 is an oxide semiconductor film in which oxygen vacancies are less likely to occur than in the oxide semiconductor layer 122. be.

[0104] In addition, the oxide semiconductor layer 122 is more ion-conductive than the oxide semiconductor layer 121 and the oxide semiconductor layer 123. In oxide semiconductors, the s orbitals of heavy metals are mainly carriers. By increasing the In content, more s orbitals overlap. Therefore, oxides with a composition in which In is greater than M are oxides with a composition in which In is equal to or less than M. Therefore, when the oxide semiconductor layer 122 contains indium, the mobility of the oxide semiconductor layer 122 is higher than that of the oxide semiconductor layer 122. By using a large amount of oxide, it is possible to realize a transistor with high field effect mobility. Cut.

[0105] The oxide semiconductor layer 122 is an In-M-Zn oxide (M is Al, Ti, Ga, Y, Z). In the case of the oxide semiconductor layer 122, the oxide semiconductor layer 122 is formed by adding an element selected from the group consisting of r, Sn, La, Ce, Mg, and Nd. In the target used for this purpose, the atomic ratio of the metal elements is In:M:Zn=x1:y1:z If x1 / y1 is 1 / 3 or more and 6 or less, and z1 / It is preferable that y1 is 1 / 3 or more and 6 or less, and more preferably 1 or more and 6 or less. When y1 is 1 or more and 6 or less, the oxide semiconductor layer 122 can have a CAAC-OS (CA xis Aligned Crystalline Oxide Semiconductor A typical example of the atomic ratio of the target metal elements is: In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, 2:1:1.5, 2: Examples include 1:2.3, 2:1:3, 3:1:2, 4:2:3, 4:2:4.1, etc.

[0106] The oxide semiconductor layer 121 and the oxide semiconductor layer 123 are made of In-M-Zn oxide (M is A In the case of Zn, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, or Nd), oxide semiconductor In the target used for depositing the oxide semiconductor layer 121 and the oxide semiconductor layer 123, If the atomic ratio of elements is In:M:Zn=x2:y2:z2, then x2 / y2 <x1 / y1で It is preferable that z2 / y2 is 1 / 3 or more and 6 or less, and more preferably 1 or more and 6 or less. By setting z2 / y2 to 1 or more and 6 or less, the oxide semiconductor layer 121 and the oxide semiconductor The number of atoms of the target metal element is small. Typical examples of ratios are In:M:Zn=1:3:2, 1:3:4, 1:3:6, 1:3: 8, 1:4:4, 1:4:5, 1:4:6, 1:4:7, 1:4:8, 1:5:5, 1: Examples include 5:6, 1:5:7, 1:5:8, 1:6:8, 1:6:4, 1:9:6, etc.

[0107] The atomic ratios of the oxide semiconductor layer 121 and the oxide semiconductor layer 123 are each calculated using an error. The above atomic ratios may vary by plus or minus 40%.

[0108] The oxide semiconductor layer 123 may be made of a metal oxide, for example, aluminum oxide (AlOx), or an oxide. Gallium oxide (GaOx), hafnium oxide (HfOx), silicon oxide (SiOx), It can also be replaced with germanium oxide (GeOx) or zirconia (ZrOx). Alternatively, the metal oxide may be provided over the oxide semiconductor layer 123.

[0109] The atomic ratio is not limited to these, and an appropriate atomic ratio may be selected depending on the required semiconductor characteristics. Just use the following.

[0110] The oxide semiconductor layer 121 and the oxide semiconductor layer 123 may have the same composition. The compound semiconductor layer 121 and the oxide semiconductor layer 123 are formed by sputtering. The atomic ratio of the metal elements is In:Ga:Zn=1:3:2, 1:3:4, or 1:4:5 Alternatively, an In-Ga-Zn oxide may be used.

[0111] Alternatively, the oxide semiconductor layer 121 and the oxide semiconductor layer 123 may have different compositions. The oxide semiconductor layer 121 is formed by sputtering a metal element atom of a target used in a sputtering method. The oxide semiconductor layer was formed by using In-Ga-Zn oxide with a numerical ratio of In:Ga:Zn=1:3:4. The atomic ratio of the target metal elements is In:Ga:Zn=1:3:2. Ga-Zn oxide may also be used.

[0112] The thicknesses of the oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123 are It is preferable that the thickness is 3 nm or more and 100 nm or less, or 3 nm or more and 50 nm or less.

[0113] Here, the thickness of the oxide semiconductor layer 122 is at least as large as that of the oxide semiconductor layer 121. It may be formed thinly, the same thickness, or thickly. When the conductor layer 122 is thickened, the on-current of the transistor can be increased. The oxide semiconductor layer 121 loses the effect of suppressing the generation of interface states in the oxide semiconductor layer 122. For example, the thickness of the oxide semiconductor layer 122 is set to a value not larger than that of the oxide semiconductor layer 122. 121 thickness, more than 1 time, or more than 2 times, or more than 4 times, or 6 times Furthermore, when it is not necessary to increase the on-state current of the transistor, The thickness of the oxide semiconductor layer 121 may be equal to or greater than the thickness of the oxide semiconductor layer 122. For example, If the insulating layer 110 or the insulating layer 175 contains excess oxygen, the oxygen is removed by heat treatment. The oxygen vacancies in the oxide semiconductor layer 122 can be reduced by the diffusion of oxygen atoms. The electrical characteristics of the device can be stabilized.

[0114] In addition, like the oxide semiconductor layer 121, the oxide semiconductor layer 123 is also It is sufficient if the thickness is such that the effect of suppressing the generation of interface states is not lost. The thickness of the oxide semiconductor layer 123 may be equal to or less than that of the conductor layer 121. , the electric field due to the gate electrode layer 160 (or the gate electrode layer 161 or the gate electrode layer 162) Since the oxide semiconductor layer 123 is thin, the For example, the oxide semiconductor layer 123 is preferably formed to have a thickness equal to or larger than the thickness of the oxide semiconductor layer 122. Note that the thickness of the oxide semiconductor layer 123 is not limited to this, and may be any thickness other than the thickness of the gate insulating layer. Taking into consideration the breakdown voltage of the insulating layer 150, the value may be appropriately set according to the voltage at which the transistor is driven. stomach.

[0115] The oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123, When the compositions of the two materials are different, the interface can be observed by scanning transmission electron microscope (STEM). Observation using a transmission electron microscope It may be possible to do this.

[0116] <About hydrogen concentration> contained in the oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123 Hydrogen reacts with oxygen that bonds with metal atoms to form water, and the oxygen is released from the lattice (or When hydrogen enters the oxygen vacancy, the In some cases, rear electrons are generated. Also, some of the hydrogen atoms bond with oxygen atoms that bond with metal atoms. When hydrogen is bonded to an atom, it may generate electrons, which act as carriers. A transistor including an oxide semiconductor having such a conductivity type tends to be normally on.

[0117] Therefore, the oxide semiconductor layer 121, the oxide semiconductor layer 122, the oxide semiconductor layer 123, and At the interface between the metal and the silicon dioxide, it is preferable that oxygen vacancies and hydrogen are reduced as much as possible. For example, the oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123 and at each interface, secondary ion mass spectroscopy (SIMS) The hydrogen concentration obtained by ion mass spectrometry was 1×10 16 atoms / cm 3 Over 2×10 20 atoms / cm 3 Less than 1 × 10 16 atoms / cm 3 5x10 or more 19 atoms / cm 3 Less than or equal to 1× 10 16 atoms / cm 3 More than 1×10 19 atoms / cm 3 The following is more preferably is 1 x 10 16 atoms / cm 3 5x10 or more 18 atoms / cm 3The following shall be done: As a result, the transistor 10 has an electrical characteristic in which the threshold voltage is positive (no This is also called the "marry-off" characteristic.

[0118] <Carbon and silicon concentrations> In addition, the oxide semiconductor layer 121, the oxide semiconductor layer 122, the oxide semiconductor layer 123, and the oxide semiconductor layer 124 are When silicon or carbon, which is one of the group 14 elements, is present at the interface between the two, oxides form. Oxygen vacancies in the semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123 As a result, the oxide semiconductor layer 121 and the oxide semiconductor layer 122 are formed. The oxide semiconductor layer 122, the oxide semiconductor layer 123, and the silicon and carbon at their interfaces. For example, the oxide semiconductor layer 121 and the oxide semiconductor layer 1 22, the oxide semiconductor layer 123, the oxide semiconductor layer 124, and S at their interfaces. The silicon and carbon concentrations obtained by IMS are 1×10 16 atoms / cm 3 1 x10 19 atoms / cm 3 Less than 1 × 10 16 atoms / cm 3 5 or more x10 18 atoms / cm 3 or less, more preferably 1 × 10 16 atoms / cm 3 Over 2×10 18 atoms / cm 3 As a result, the transistor The transistor 10 has an electrical characteristic in which the threshold voltage is positive (also called a normally-off characteristic). do.

[0119] <About alkali metal concentrations> In addition, alkali metals and alkaline earth metals generate carriers when bonded with oxide semiconductors. This may result in an increase in the off-state current of the transistor. The oxide semiconductor layer 121, the oxide semiconductor layer 122, the oxide semiconductor layer 123, and each of the It is preferable to reduce the concentration of alkali metals or alkaline earth metals at the interface. For example, the oxide semiconductor layer 121, the oxide semiconductor layer 122, the oxide semiconductor layer 123, and At each interface, alkali metal or aluminum was detected by secondary ion mass spectrometry. The concentration of potassium earth metals is 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 It is desirable that the transistor 10 has a threshold voltage of 0.01 V or less. It can have electrical characteristics where the lowest voltage is positive (also called normally-off characteristics). do.

[0120] <Regarding nitrogen concentration> In addition, the oxide semiconductor layer 121, the oxide semiconductor layer 122, the oxide semiconductor layer 123, and the oxide semiconductor layer 124 are When nitrogen is present at the interface between the two, electrons acting as carriers are generated, increasing the carrier density. As a result, an n-type region is formed. The transistor tends to be normally on. Nitrogen is formed in the compound semiconductor layer 122, the oxide semiconductor layer 123, and their interfaces. For example, the oxide semiconductor layer 121 and the oxide semiconductor layer 1 22, the oxide semiconductor layer 123, and the nitride obtained by SIMS at the interface between them. The element concentration is 1 x 10 15 atoms / cm3 5x10 or more 19 atoms / cm 3 below, Preferably 1 x 10 15 atoms / cm 3 5x10 or more 18 atoms / cm 3 below, More preferably 1 × 10 15 atoms / cm 3 More than 1×10 18 atoms / cm 3 Below or less, more preferably 1 × 10 15 atoms / cm 3 5x10 or more 17 atoms / c m 3 This allows the transistor 10 to have a threshold voltage that is higher than the planar threshold voltage. The device can have electrical characteristics (also called normally-off characteristics) that are suitable for use in semiconductor devices.

[0121] <About carrier density> The impurities in the oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123 are removed. By reducing the oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer Therefore, the carrier density of the oxide semiconductor layer 121 and the oxide semiconductor layer 123 can be reduced. The compound semiconductor layer 122 and the oxide semiconductor layer 123 have a carrier density of 1×10 15 pcs / c m 3 Less than 1 × 10 13 pieces / cm 3 Less than 8 × 10, more preferably 11 pieces / cm 3 less than 1×10 11 pieces / cm 3 less than 1 x 10 10 pieces / cm 3 Less than 1 x 10 -9 pieces / cm 3 That's all.

[0122] The oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123 are made of an insulator. By using an oxide semiconductor film with a low impurity concentration and a low density of defect states, it is possible to achieve better electrical conductivity. Here, a transistor with low impurity concentration and defects can be fabricated. A low level density (low oxygen vacancy) is called high purity intrinsic or substantially high purity intrinsic. High-purity intrinsic or substantially high-purity intrinsic oxide semiconductors have few carrier generation sources. Therefore, the carrier density can be reduced in some cases. The transistor in which the channel region is formed has electrical characteristics in which the threshold voltage is positive (no Also known as marrow-off characteristics.) Also, high-purity intrinsic or substantially high-purity intrinsic Since the oxide semiconductor film has a low density of defect states, the density of trap states may also be low. In addition, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low off-state current. The voltage between the source and drain electrodes (drain voltage) is extremely small, ranging from 1V to 10V. In the range, the off-state current is below the measurement limit of the semiconductor parameter analyzer, that is, 1× 10 -13 Therefore, the oxide semiconductor film has a channel density of 0.25 A or less. The transistors in which the hole region is formed have small fluctuations in electrical characteristics and are highly reliable. This may result in a problem.

[0123] In addition, a transistor using the purified oxide semiconductor film as described above for a channel formation region can be fabricated. The off-state current of the transistor is extremely small. For example, when the voltage between the source and drain is 0.1 V, 5 V or about 10V, the off-state current normalized by the transistor channel width It is possible to reduce the current density to several yA / μm to several zA / μm.

[0124] The oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123 are, for example, The non-single crystal structure may be, for example, a CAAC-OS or a polycrystalline structure, which will be described later. In non-single crystalline structures, the amorphous structure is the most defective. The defect density is high in CAAC-OS, and the defect density is lowest in CAAC-OS.

[0125] The oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123 are, for example, The oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123 each having a microcrystalline structure may have a microcrystalline structure. The oxide semiconductor layer 123 contains, for example, microcrystals with a size of 1 nm or more and less than 10 nm in the film. Alternatively, the oxide film and the oxide semiconductor film having a microcrystalline structure may have an amorphous phase. It is a mixed phase structure with a crystalline portion of m or more and less than 10 nm.

[0126] The oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123 are, for example, The oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123 each having an amorphous structure may be used. The oxide semiconductor layer 123 has, for example, a disordered atomic arrangement and does not contain crystalline components. Alternatively, the amorphous oxide film has a completely amorphous structure and does not have a crystalline portion. .

[0127] The oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123 are A mixed film having two or more structural regions of CAAC-OS, microcrystalline structure, and amorphous structure. The mixed film may have, for example, an amorphous structure region, a microcrystalline structure region, and a CA There is a single layer structure having an AC-OS region. Alternatively, there is a mixed film, for example, an amorphous The structure has a stacked structure of a region with a crystal structure, a region with a microcrystalline structure, and a region with a CAAC-OS structure.

[0128] The oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123 are For example, it may have a single crystal structure.

[0129] The oxide semiconductor film is formed by forming an oxide semiconductor layer 122 in which oxygen vacancies are less likely to occur than in the oxide semiconductor layer 122. By providing the insulating films above and below the oxide semiconductor layer 122, oxygen vacancies in the oxide semiconductor layer 122 can be reduced. In addition, the oxide semiconductor layer 122 can be formed by using a metal element. The oxide semiconductor layer 121 and the oxide semiconductor layer 123 each having one or more of the elements are in contact with each other. The interface between the semiconductor layer 121 and the oxide semiconductor layer 122, the interface between the oxide semiconductor layer 122 and the oxide semiconductor The interface state density at the interface with the insulating layer 110 is extremely low. After the heating, heat treatment is performed to transfer the oxygen to the oxide semiconductor layer 121. Oxygen moves to the layer 122, but at this time, oxygen is not easily captured in the interface state, and the efficiency is improved. It is possible to transfer oxygen contained in the oxide semiconductor layer 121 to the oxide semiconductor layer 122. As a result, oxygen vacancies in the oxide semiconductor layer 122 can be reduced. In addition, oxygen is also added to the oxide semiconductor layer 121. That is, the localized oxygen vacancies in at least the oxide semiconductor layer 122 can be reduced. The position density can be reduced.

[0130] In addition, the oxide semiconductor layer 122 may be formed of an insulating film having a different constituent element (for example, a silicon oxide film). When the semiconductor comes into contact with the gate insulating layer, an interface state is formed, and the interface state forms a channel. In such a case, a second transistor with a different threshold voltage appears, However, the apparent threshold voltage of the oxide semiconductor The oxide semiconductor layer 121 and the oxide semiconductor layer 122 each containing one or more metal elements Since the oxide semiconductor layer 123 is in contact with the oxide semiconductor layer 122, the oxide semiconductor layer 121 and the oxide semiconductor layer 1 and an interface between the oxide semiconductor layer 123 and the oxide semiconductor layer 122. It becomes difficult to achieve.

[0131] The oxide semiconductor layer 121 and the oxide semiconductor layer 123 are respectively connected to the insulating layer 110 and the gate electrode. The constituent elements of the insulating layer 150 are mixed into the oxide semiconductor layer 122, and an impurity level is formed. It also functions as a barrier film to prevent leakage.

[0132] For example, the insulating layer 110 or the gate insulating layer 150 may be an insulating film containing silicon. In this case, the silicon in the gate insulating layer 150 or the insulating layer 110 and the gate insulating layer 150 The carbon that may be mixed in the oxide semiconductor layer 121 or the oxide semiconductor layer 123 is introduced into the oxide semiconductor layer 121 or the oxide semiconductor layer 123 at the interface. Impurities such as silicon and carbon may be mixed into the oxide semiconductor layer 1 to a thickness of several nanometers. When the electron enters the electron-doped nucleus, an impurity level is formed. The impurity level acts as a donor and generates an electron, resulting in n It can become stylized.

[0133] However, when the thickness of the oxide semiconductor layer 121 and the oxide semiconductor layer 123 is greater than several nm, If the impurities such as silicon and carbon are not mixed in, they will not reach the oxide semiconductor layer 122. Therefore, the influence of the impurity level is reduced.

[0134] Therefore, by providing the oxide semiconductor layers 121 and 123, This can reduce variations in the electrical characteristics of the capacitor, such as its threshold voltage.

[0135] In addition, the gate insulating layer 150 and the oxide semiconductor layer 122 come into contact with each other, and a channel is formed at the interface. If the interface is too thick, interface scattering occurs at the interface, reducing the field-effect mobility of the transistor. However, the oxide semiconductor layer 122 contains one or more metal elements. 21, since the oxide semiconductor layer 123 is provided in contact with the oxide semiconductor layer 122, At the interfaces between the conductor layer 122 and the oxide semiconductor layer 121 and between the conductor layer 122 and the oxide semiconductor layer 123, the carriers are scattered. This makes it difficult for disorder to occur, and the field-effect mobility of the transistor can be increased.

[0136] In this embodiment, the amount of oxygen vacancies in the oxide semiconductor layer 122 and the oxide semiconductor layer The amount of oxygen vacancies in the oxide semiconductor layer 121 and the oxide semiconductor layer 123 in contact with the oxide semiconductor layer 122 is reduced. As a result, the density of localized states in the oxide semiconductor layer 122 can be reduced. As a result, the transistor 10 described in this embodiment has little fluctuation in threshold voltage and high reliability. Furthermore, the transistor 10 described in this embodiment has excellent electrical characteristics. It has characteristics.

[0137] Note that an insulating film containing silicon is often used as a gate insulating layer of a transistor. For the above reasons, the region serving as a channel of the oxide semiconductor layer is It can be said that a structure that does not come into contact with the gate insulating layer, such as a gate electrode, is preferable. When a channel is formed at the interface between the insulating layer and the oxide semiconductor layer, carriers are scattered at the interface. This can cause a decrease in the field-effect mobility of the transistor. It is preferable that the region of the oxide semiconductor layer that serves as a channel be separated from the gate insulating layer. .

[0138] Therefore, the oxide semiconductor layer 120 is made of the oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123. By using a stacked structure of the oxide semiconductor layer 123, a channel can be formed in the oxide semiconductor layer 123. This allows the formation of a transistor with high field-effect mobility and stable electrical characteristics. It is possible.

[0139] The oxide semiconductor does not necessarily have to be a three-layer structure, but may be a single-layer structure, a two-layer structure, a four-layer structure, or even a five-layer structure. In the case of using a single layer, the oxide semiconductor layer 122 shown in this embodiment may be formed as a single layer. A layer corresponding to the above may be used.

[0140] <Band diagram> Here, a band diagram will be described. For ease of understanding, the band diagram is shown with the insulating layer 110, An oxide semiconductor layer 121, an oxide semiconductor layer 122, an oxide semiconductor layer 123, and a gate insulating film The energy (Ec) of the conduction band minimum of the edge layer 150 is shown.

[0141] As shown in FIGS. 4A and 4B, an oxide semiconductor layer 121, an oxide semiconductor layer 122, In the oxide semiconductor layer 123, the energy of the conduction band minimum changes continuously. The elements constituting the oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123 are This is also understood from the fact that oxygen easily diffuses between them. The oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123 are stacked layers of films with different compositions. Although it is a layered structure, it can also be said to be physically continuous.

[0142] The oxide semiconductor film, which is stacked with the same main component, is not simply stacked but is joined continuously. In this case, the energy of the conduction band edge changes continuously between layers. The interface between each layer is fabricated so that a U-Shape Well structure is formed. There are no impurities that form defect levels such as trap centers or recombination centers in the If impurities are present between the layers of the laminated multilayer film, The continuity of the energy band is lost, and carriers are trapped or annihilated by recombination at the interface. It ends up like this.

[0143] Note that in FIG. 4B, the oxide semiconductor layer 121 and the oxide semiconductor layer 123 have the same Ec. Although one case is shown, each case may be different.

[0144] As shown in FIGS. 4B and 4C, the oxide semiconductor layer 122 serves as a well, and the transistor In the case of the gate electrode 10, it can be seen that a channel is formed in the oxide semiconductor layer 122. The energy of the conduction band minimum changes continuously from the oxide semiconductor layer 122 as the bottom. The channel of the door structure can also be called a buried channel.

[0145] The oxide semiconductor layer 121 and the oxide semiconductor layer 123 are formed on an insulating film such as a silicon oxide film. Trap levels due to impurities and defects can be formed near the interface with the film. The oxide semiconductor layer 122 and the oxide semiconductor layer 123 are formed on the substrate 121 and the oxide semiconductor layer 123. However, the oxide semiconductor layer 121 or the oxide semiconductor layer When the energy difference between Ec of the oxide semiconductor layer 123 and Ec of the oxide semiconductor layer 122 is small, Electrons in the compound semiconductor layer 122 may exceed the energy difference and reach the trap level. The electrons that become negative charges are captured by the trap levels, and negative charges form at the insulating film interface. A constant charge is generated, and the threshold voltage of the transistor shifts in the positive direction. During long-term storage tests of transistors, traps are not fixed, causing fluctuations in characteristics. There are concerns.

[0146] Therefore, in order to reduce the fluctuation in the threshold voltage of the transistor, the oxide semiconductor layer 121 and an energy difference between Ec of the oxide semiconductor layer 123 and the oxide semiconductor layer 122. The energy difference between them is preferably 0.1 eV or more. More preferably, it is 0.2 eV or more.

[0147] The oxide semiconductor layer 121, the oxide semiconductor layer 122, and the oxide semiconductor layer 123 each contain a crystalline It is preferable that the crystal contains a portion. In particular, by using a crystal oriented in the c-axis, it is possible to obtain a stable transistor. It is possible to impart specific electrical properties.

[0148] In the band diagram shown in FIG. 4B, the oxide semiconductor layer 123 is not provided. An In-Ga oxide (for example, an In-Ga-O oxide having an atomic ratio of 1.0 to 1.0) is provided between the compound semiconductor layer 123 and the gate insulating layer 150. Alternatively, gallium oxide may be used. Alternatively, a gate electrode may be formed between the oxide semiconductor layer 123 and the gate electrode while the oxide semiconductor layer 123 is present. Alternatively, an In-Ga oxide may be provided between the insulating layers 150. Alternatively, gallium oxide may be provided. That's fine.

[0149] The oxide semiconductor layer 122 has a higher electrical conductivity than the oxide semiconductor layer 121 and the oxide semiconductor layer 123. For example, an oxide having a high electron affinity is used as the oxide semiconductor layer 122. The oxide semiconductor layer 121 and the oxide semiconductor layer 123 have an electron affinity of 0.07 eV or more and 1.3 eV or more. Preferably, the voltage is 0.1 eV or more and 0.7 eV or less, and more preferably, the voltage is 0.2 eV or more and 0.4 eV or less. Oxides with a molecular weight of 1000 eV or less can be used.

[0150] The transistor described in this embodiment includes at least one metal element included in the oxide semiconductor layer 122. Since the oxide semiconductor layer 121 and the oxide semiconductor layer 123 are included, The interface between the conductor layer 121 and the oxide semiconductor layer 122, and the interface between the oxide semiconductor layer 123 and the oxide semiconductor layer 124 are Therefore, the oxide semiconductor layer 121 and the oxide semiconductor layer 122 are hardly formed at the interface with each other. By providing the nitride semiconductor layer 123, the electrical characteristics of the transistor, such as the threshold voltage, can be improved. Variability and fluctuation can be reduced.

[0151] <<Source Electrode Layer 130, Drain Electrode Layer 140>> The source electrode layer 130 and the drain electrode layer 140 are made of copper (Cu), tungsten (W), molybdenum (Mo), and the like. Ribdenum (Mo), gold (Au), aluminum (Al), manganese (Mn), titanium (T i), Tantalum (Ta), Nickel (Ni), Chromium (Cr), Lead (Pb), Tin (Sn) , iron (Fe), cobalt (Co), ruthenium (Ru), platinum (Pt), iridium (I r), strontium (Sr), or alloys, or materials that mainly consist of these A single layer or a laminate of conductive layers containing compounds such as oxygen, nitrogen, fluorine, silicon, etc. For example, when stacking, the lower side in contact with the oxide semiconductor layer 122 The conductive layer (for example, the source electrode layer 131 and the drain electrode layer 141 shown in FIG. 15) is oxygen. The upper conductive layer (for example, the source electrode layer 132 shown in FIG. 15, the drain electrode layer 132) has a material that is easy to bond to the upper conductive layer. The layer electrode layer 142 may be made of a material that is highly resistant to oxidation. It is preferable to use a high melting point material such as tungsten or molybdenum, which has both electrical and mechanical properties. It is also preferable to form the wiring board from a low-resistance conductive material such as aluminum or copper. When a manganese-Mn alloy is used, manganese oxide is formed at the interface with the insulator containing oxygen, and the manganese oxide The fluorine is preferable because it has the function of suppressing the diffusion of Cu.

[0152] In addition, when a conductive material that easily bonds with oxygen is brought into contact with an oxide semiconductor layer, The oxygen in the oxide semiconductor layer diffuses to the conductive material, which is more likely to bond with oxygen. Oxygen vacancies occur in the area near the contact with the source electrode layer or the drain electrode layer, and a small amount of oxygen is released into the film. The hydrogen contained in the region enters the oxygen vacancy, causing the region to become significantly n-type. Therefore, the n-type region can be used as the source or drain of a transistor. This can be done.

[0153] For example, a laminated structure using W as the lower conductive layer and Pt as the upper conductive layer may be used. By doing so, the oxide semiconductor in contact becomes n-type, and the conductive layer in contact with the insulating layer 170 This can prevent oxidation of the conductive layer.

[0154] Gate insulating layer 150 The gate insulating layer 150 contains oxygen (O), nitrogen (N), fluorine (F), aluminum (Al ), magnesium (Mg), silicon (Si), gallium (Ga), germanium (Ge ), yttrium (Y), zirconium (Zr), lanthanum (La), neodymium (Nd) , hafnium (Hf), tantalum (Ta), titanium (Ti), and the like. For example, aluminum oxide (AlOx), magnesium oxide (MgOx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), silicon nitride oxide (SiNxOy) , silicon nitride (SiNx), gallium oxide (GaOx), germanium oxide (GeOx ), yttrium oxide (YOx), zirconium oxide (ZrOx), lanthanum oxide (La Ox), neodymium oxide (NdOx), hafnium oxide (HfOx) and tantalum oxide ( The gate insulating layer 150 may be an insulating film containing one or more of TaOx. The gate insulating layer 150 may be a laminate of the above materials. It may contain zirconium (Zr) or the like as an impurity.

[0155] Next, an example of the stacked structure of the gate insulating layer 150 will be described. The gate insulating layer 150 is For example, it contains oxygen, nitrogen, silicon, hafnium, etc. Specifically, hafnium oxide and preferably includes silicon oxide or silicon oxynitride.

[0156] Hafnium oxide has a higher dielectric constant than silicon oxide and silicon oxynitride. Therefore, the physical film thickness can be increased relative to the equivalent oxide film thickness, so the equivalent oxide film thickness can be increased to 10 nm or less. Even when the thickness is set to 5nm or less, the leakage current due to the tunnel current can be reduced. That is, a transistor with a small off-state current can be realized. Hafnium oxide with a crystalline structure has a higher dielectric constant than hafnium oxide with an amorphous structure. Therefore, in order to obtain a transistor with a small off-state current, It is preferable to use hafnium oxide, which has a crystal structure such as monoclinic or cubic. However, one embodiment of the present invention is not limited to these.

[0157] By the way, the surface on which hafnium oxide having a crystalline structure is formed has interface states due to defects. The interface states may function as trap centers. When hafnium oxide is placed close to the channel region of a transistor, the interface states This may cause deterioration of the electrical characteristics of the transistor. To achieve this, another film is placed between the channel region of the transistor and the hafnium oxide. It may be preferable to separate the membranes from each other by using a The film having the buffer function may be a film included in the gate insulating layer 150, or may be an oxide semiconductor. The film may be a film included in the conductive film. That is, the film having a buffer function may be silicon oxide. , silicon oxynitride, oxide semiconductor, or the like can be used. The film may contain, for example, a semiconductor having a larger energy gap than the semiconductor that will be the channel region. Alternatively, an insulator is used. Alternatively, the film having a buffer function may be, for example, a film that serves as a channel region. Use a semiconductor or insulator that has a smaller electron affinity than the semiconductor that is used. The film to be formed may contain, for example, a semiconductor having a higher ionization energy than the semiconductor that will be the channel region. Conductors or insulators are used.

[0158] On the other hand, the interface states (trap By trapping charge in the charge center, the threshold voltage of the transistor can be controlled. In order to make the charge exist stably, for example, the channel region and hafnium oxide If an insulator with a larger energy gap than hafnium oxide is placed between the hafnium and the Alternatively, if a semiconductor or insulator with a smaller electron affinity than hafnium oxide is placed, Alternatively, a film with a buffer function may be made of hafnium oxide with a larger ionization energy than hafnium oxide. By using such an insulator, the interface state This makes it difficult for the trapped charge to be released, and the charge can be retained for a long period of time. can.

[0159] Examples of such insulators include silicon oxide and silicon oxynitride. In order to trap charges in the interface state in the gate insulating layer 150, the gate potential is Electrons can be moved toward the polar layer 160. , 125°C or higher and 450°C or lower, typically 150°C or higher and 300°C or lower), The potential of the electrode layer 160 is set higher than the potential of the source electrode layer 130 and the drain electrode layer 140. It is sufficient to maintain the temperature for at least one second, typically at least one minute.

[0160] In this way, a transistor in which a desired number of electrons are trapped in the interface states of the gate insulating layer 150 or the like is formed. The threshold voltage of the gate electrode layer 160 is shifted to the positive side. By adjusting the time for capturing electrons, the amount of electrons captured (the amount of change in threshold voltage) can be controlled. If charges can be trapped, they can be trapped in the gate insulating layer 150. A laminated film having a similar structure may be used for other insulating layers.

[0161] Gate electrode layer 160 The gate electrode layer 160 may include, for example, aluminum (Al), titanium (Ti), chromium (C r), cobalt (Co), nickel (Ni), copper (Cu), yttrium (Y), zirconium Zirconium (Zr), Molybdenum (Mo), Ruthenium (Ru), Silver (Ag), Tantalum (T Conductive films such as tungsten (W) and tungsten (A) can be used. The electrode layer 160 can be a stack of layers. For example, as shown in FIG. The gate electrode layer 161 and the gate electrode layer 163 may be made of the above-mentioned materials. A conductive film containing nitrogen, such as a nitride of a material, may also be used.

[0162] Insulating layer 170 The insulating layer 170 contains oxygen (O), nitrogen (N), fluorine (F), aluminum (Al), ma Magnesium (Mg), silicon (Si), gallium (Ga), germanium (Ge), Tritium (Y), Zirconium (Zr), Lanthanum (La), Neodymium (Nd), Huff The metals may include niobium (Hf), tantalum (Ta), titanium (Ti), etc. , aluminum oxide (AlOx), magnesium oxide (MgOx), silicon oxide (Si Ox), silicon oxynitride (SiOxNy), silicon nitride oxide (SiNxOy), nitride Silicon (SiNx), gallium oxide (GaOx), germanium oxide (GeOx), acid Yttrium oxide (YOx), zirconium oxide (ZrOx), lanthanum oxide (LaOx) , neodymium oxide (NdOx), hafnium oxide (HfOx) and tantalum oxide (TaO The insulating layer 170 can be formed of a laminate of the above materials. may be.

[0163] The insulating layer 170 preferably includes an aluminum oxide film. It has a blocking effect that prevents impurities such as hydrogen and moisture, as well as oxygen, from passing through the membrane. Therefore, the aluminum oxide film can be used during the manufacturing process of the transistor. After manufacturing, oxidation of impurities such as hydrogen and moisture, which are factors that cause fluctuations in the electrical characteristics of transistors, Preventing contamination of the compound semiconductor layer 121 and the oxide semiconductor layer 122, and preventing the oxide of oxygen, which is the main component material Prevention of release from the semiconductor layer 121 and the oxide semiconductor layer 122, and unnecessary release of oxygen from the insulating layer 110 It is suitable for use as a protective film having the important effect of preventing release.

[0164] The insulating layer 170 is preferably a film having an oxygen supplying ability. When the second insulating film is formed, a mixed layer is formed, and the mixed layer or the insulating layer 110 is oxidized. The oxygen diffuses into the oxide semiconductor by the subsequent heat treatment, and the oxide semiconductor It can compensate for oxygen deficiency in the body, and improve transistor characteristics (e.g., threshold voltage). , reliability, etc.) can be improved.

[0165] In addition, another insulating layer may be provided above or below the insulating layer 170. For example, an oxide Magnesium, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, oxide Gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, An insulating film containing one or more of neodymium oxide, hafnium oxide, and tantalum oxide may be used. Oxygen (O), nitrogen (N), fluorine (F), aluminum (Al), magnesium (Mg), silicon (Si), gallium (Ga), germanium (Ge), yttrium (Y), zirconium (Zr), lanthanum (La), neodymium (Nd), hafnium (H For example, aluminum oxide can be used. Aluminum (AlOx), magnesium oxide (MgOx), silicon oxide (SiOx), acid Silicon oxide nitride (SiOxNy), silicon oxide nitride (SiNxOy), silicon nitride ( SiNx), gallium oxide (GaOx), germanium oxide (GeOx), yttria YOx, Zirconium oxide (ZrOx), Lanthanum oxide (LaOx), Neo oxide NdOx, hafnium oxide (HfOx) and tantalum oxide (TaOx) The insulating layer 170 may be a laminate of the above materials. It is preferable that the insulating layer 170 has more oxygen than the stoichiometric composition. The oxygen released from the edge layer passes through the gate insulating layer 150 and enters the channel of the oxide semiconductor layer 120. Since the oxygen vacancies formed in the channel formation region can be diffused into the hole formation region, Therefore, it is possible to obtain stable electrical characteristics of the transistor. This can be done.

[0166] Insulating layer 175 The insulating layer 175 contains oxygen (O), nitrogen (N), fluorine (F), aluminum (Al), ma Magnesium (Mg), silicon (Si), gallium (Ga), germanium (Ge), Tritium (Y), Zirconium (Zr), Lanthanum (La), Neodymium (Nd), Huff The metals may include niobium (Hf), tantalum (Ta), titanium (Ti), etc. , magnesium oxide (MgOx), silicon oxide (SiOx), silicon oxynitride (Si OxNx), silicon oxynitride (SiNxOx), silicon nitride (SiNx), gallium oxide ium oxide (GaOx), germanium oxide (GeOx), yttrium oxide (YOx), oxide Zirconium (ZrOx), lanthanum oxide (LaOx), neodymium oxide (NdOx), acid Hafnium oxide (HfOx), tantalum oxide (TaOx), aluminum oxide (AlO The insulating layer 175 can be formed of a laminate of the above materials. The insulating layer preferably contains more oxygen than in the stoichiometric composition. .

[0167] Alternatively, the insulating layer 175 may be made of a low-dielectric-constant material (low-k material). , silicon oxide (SiOF) containing a few percent of fluorine (F), and silicon dioxide (SiOF) containing a few percent of carbon (C). Silicon dioxide (SiOC), fluorinated silicate glass (FSG), organic silicate glass Silsesquioxane (OSG), Hydrogenated Silsesquioxane (HSQ), Methylsilsesquioxane (M SQ), organic polymers, polyimides, fluororesins (polytetrafluoroethylene, etc.), The insulating layer 175 can be formed using amorphous carbon to which fluorine is added. Additionally, the capacitance associated with the transistor 10 can be further reduced by using low-k materials. can be done.

[0168] <Transistor manufacturing method> Next, a method for manufacturing the semiconductor device according to this embodiment will be described with reference to FIGS. Note that the parts that overlap with those explained in the above transistor configuration will be omitted. The A1-A2 direction shown in FIGS. 7 to 13 corresponds to the channel shown in FIGS. 1(A) and 1(B). 7 to 13 is also referred to as the direction of the length of the cable. ) and the channel width direction shown in FIG. 1(C).

[0169] In this embodiment, each layer constituting a transistor (an insulating layer, an oxide semiconductor layer, a conductive layer The methods used for deposition include sputtering, chemical vapor deposition (CVD), vacuum deposition, and pulsed laser deposition. Alternatively, it can be formed by a coating method or a printing method. The film formation method includes sputtering and plasma-enhanced chemical vapor deposition (PECVD). ) method is a typical example, but thermal CVD method is also acceptable. Metal Chemical Vapor Deposition (ALD) and Atomic Layer Deposition (ALD) may also be used.

[0170] <Thermal CVD method> The thermal CVD method is a film formation method that does not use plasma, so defects are generated by plasma damage. This has the advantage that it will not be

[0171] In the thermal CVD method, the source gas and oxidant are simultaneously fed into the chamber. By reacting the material near or on the substrate under atmospheric or reduced pressure, the material is deposited on the substrate. Film formation may also be performed.

[0172] Furthermore, thermal CVD methods such as MOCVD and ALD are disclosed in the embodiments described above. It is possible to form various films such as metal films, semiconductor films, and inorganic insulating films. When forming a Ga-Zn-O film, trimethylindium, trimethylgallium, and dimethyl zinc can be used. The chemical formula of trimethylindium is I The chemical formula for trimethylgallium is Ga(CH3)3. 。 Also, the chemical formula of dimethyl zinc is Zn(CH3)2. Also, these combinations are not limited to this, and triethyl gallium (chemical formula Ga(C2H5 )3) can be used instead of trimethyl gallium, and diethyl zinc (chemical formula Zn(C2H5 )2) can be used instead of dimethyl zinc.

[0173] <ALD method> In a film forming apparatus using a conventional CVD method, one or more raw material gases (precursors) for the reaction are simultaneously supplied to the chamber during film formation. In a film forming apparatus using the ALD method, the precursors for the reaction are sequentially introduced into the chamber, and film formation is performed by repeating the order of gas introduction. For example, by switching each switching valve (also called a high-speed valve), two or more types of precursors are sequentially supplied to the chamber, and an inert gas (such as argon or nitrogen) is introduced after the first precursor so that the plurality of types of precursors do not mix. Then, the second precursor is introduced. Alternatively, after discharging the first precursor by evacuation instead of introducing an inert gas, the second precursor can be introduced. FIGS. 5(A), (B), (C), and (D) show the film forming process of the ALD method. The first precursor 6 01 is adsorbed on the surface of the substrate (see FIG. 5(A)), and the first single layer is formed (see FIG. 5(B )). At this time, metal atoms and the like contained in the precursor can bond with the hydroxyl groups present on the substrate surface.

[0174] The alkyl groups such as methyl groups and ethyl groups may be bonded to the metal atoms. After exhausting the first precursor 601, the second precursor 602 introduced reacts with it (see FIG. 5(C)), and the second single layer is laminated on the first single layer to form a thin film. (See FIG. 5(D)). At this time, metal atoms and the like contained in the precursor can bond with the hydroxyl groups present on the substrate surface. The alkyl groups such as methyl groups and ethyl groups may be bonded to the metal atoms. After exhausting the first precursor 601, the second precursor 602 introduced reacts with it (see FIG. 5(C)), and the second single layer is laminated on the first single layer to form a thin film. (See FIG. 5(D)). At this time, metal atoms and the like contained in the precursor can bond with the hydroxyl groups present on the substrate surface. (See FIG. 5(D)). For example, if an oxidizing agent is included as the second precursor, a metal atom or an alkyl group bonded to a metal atom present in the first precursor; and an oxidizing agent A chemical reaction occurs between the first precursor and the second precursor, forming an oxide film. If a gas containing hydrogen is used, a metal film can be formed by a reduction reaction.

[0175] The ALD method is a film formation method based on surface chemical reactions, in which precursors are adsorbed onto the surface to be filmed, A self-limiting mechanism acts, and the resulting layer is formed. For example, trimethylaluminum Such precursors react with the hydroxyl groups (OH groups) present on the surface of the film to be formed. Since only surface reactions occur due to the precursor coming into contact with the surface to be coated, the thermal energy Metal atoms in the precursor can be adsorbed onto the surface to be film-formed through the precursor. Casa has a high vapor pressure, is thermally stable before film formation, and does not self-decompose. It has the characteristics of rapid chemical adsorption. In addition, the precursor is introduced as a gas, so the exchange If the precursors introduced into each other have enough time to diffuse, high aspect ratios can be achieved. Even in areas with irregularities, a film can be formed with good coverage.

[0176] In addition, in the ALD method, the gas introduction order is controlled and repeated multiple times until the desired thickness is achieved. By repeating this process, a thin film with excellent step coverage can be formed. The thickness can be precisely adjusted by changing the number of times the nozzle is turned on. By increasing the pressure, the film formation speed can be increased and the impurity concentration in the film can be reduced. can be done.

[0177] In addition, the ALD method includes ALD using heat (thermal ALD method), ALD using plasma ( In thermal ALD, thermal energy is used to induce the reaction of precursors. The plasma ALD method involves reacting precursors in a radical state. do.

[0178] The ALD method can deposit extremely thin films with high precision. Surface coating is possible even on uneven surfaces. High rate and high film density.

[0179] <Plasma ALD> In addition, by forming a film using the plasma ALD method, it is possible to achieve a high degree of uniformity compared to the ALD method using heat (thermal ALD method). The plasma ALD method allows deposition at temperatures even lower than 100°C. The film can be formed without decreasing the film formation rate. Since the plasma can generate radicals, it is possible to form films of not only oxides but also nitrides. can be done.

[0180] In addition, plasma ALD can enhance the oxidizing power of the oxidizing agent. When forming a film, the precursors remaining in the film or the organic compounds desorbed from the precursors It is possible to reduce carbon, chlorine, hydrogen, etc. in the film, and impurities It is possible to have a film with a low concentration of ions.

[0181] In addition, when performing plasma ALD, radical species are generated and ICP (Inductively Coupled Plasma) Plasma is generated at a distance from the substrate, such as when the plasma is generated at a distance from the substrate. It is also possible to generate plasma damage to the substrate or the film on which the protective film is formed. This can reduce the page size.

[0182] From the above, by using the plasma ALD method, the process temperature can be lowered compared to other film-forming methods, and the surface coverage rate can be increased, and the film can be formed. Thereby, the intrusion of water and hydrogen from the outside can be suppressed.

[0183] <Explanation of the ALD apparatus> Fig. 6(A) shows an example of a film-forming apparatus using the ALD method. The film-forming apparatus using the ALD method includes a film-forming chamber (chamber 1701), raw material supply units 1711a and 1711b, high-speed valves 1712a and 1712b which are flow controllers, raw material inlet ports 1713a and 1713b, a raw material discharge port 1714, and an exhaust device 1715. The raw material inlet ports 1713a and 1713b installed inside the chamber 1701 are connected to the raw material supply units 1711a

[0184] and 1711b respectively through supply pipes and valves, and the raw material discharge port 1714 is connected to the exhaust device 1715 through a

[0185] discharge pipe, valves, and a pressure regulator Inside the chamber, there is a substrate holder 1716 equipped with a heater, and the film-forming substrate 1700 is placed on the substrate holder.

[0186] Although an example in which two raw material supply units 1711a and 1711b There is no particular limitation, and three or more valves may be provided. 12b can be precisely controlled by time, and either the source gas or the inert gas can be supplied. The high-speed valves 1712a and 1712b are flow rate controllers for the source gas. It can also be said to be a flow rate controller for inert gas.

[0187] In the film formation apparatus shown in FIG. 6(A), a film formation substrate 1700 is carried onto a substrate holder 1716. After the chamber 1701 is sealed, the substrate holder 1716 is heated by a heater to form a film. The substrate 1700 is heated to a desired temperature (for example, 100° C. or higher or 150° C. or higher), and the source gas supply of inert gas, exhaust by exhaust device 1715, and exhaust by exhaust device 1715. By repeating this process, a thin film is formed on the substrate surface.

[0188] In the film forming apparatus shown in FIG. 6(A), the raw material supply units 1711a and 1711b are provided with By appropriately selecting the raw materials (volatile organometallic compounds, etc.), One selected from aluminum (Al), tantalum (Ta), zirconium (Zr), etc. Depositing an insulating layer containing an oxide (including a composite oxide) containing the above elements. Specifically, an insulating layer containing hafnium oxide and an insulating layer containing aluminum oxide can be formed. an insulating layer comprising hafnium silicate; or an insulating layer comprising aluminum It is possible to form an insulating layer containing ammonium silicate. The raw materials (volatile organometallic compounds, etc.) are supplied to the raw material supply unit 1711a and the raw material supply unit 1711b. By appropriately selecting the layer, a metal layer such as a tungsten layer or a titanium layer, or a titanium nitride layer, etc. It is also possible to deposit thin films such as nitride layers.

[0189] For example, when a hafnium oxide layer is formed using a film forming apparatus that uses the ALD method, a solvent and liquids containing hafnium precursor compounds (hafnium alkoxides, tetrakisdimethyl The raw material gas is vaporized hafnium amide (such as TDMAH) and acid In this case, two kinds of gases are used: The first source gas supplied from the source supply unit 1711b is TDMAH, and the second source gas supplied from the source supply unit 1711c is TDMAH. The raw material gas becomes ozone. The chemical formula of tetrakisdimethylamidohafnium is Hf [N(CH3)2]4. Other materials include tetrakis(ethylmethylamine). Nitrogen has the function of eliminating charge trapping levels. Therefore, when the source gas contains nitrogen, a hafnium oxide film with a low charge trap level density can be formed. It is possible.

[0190] For example, when forming an aluminum oxide layer using a film forming apparatus that uses the ALD method, A raw material gas containing a catalyst and a liquid containing an aluminum precursor compound (such as TMA) is vaporized, and an oxidizing agent is added. In this case, two kinds of gases are used, one of which is a gas containing HCl and the other is H2O. The first source gas is TMA, and the second source gas supplied from the source supply unit 1711b is H 2O. The chemical formula for trimethylaluminum is Al(CH3)3. Other liquid materials include tris(dimethylamido)aluminum and triisobutylaluminum. Aluminum, aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedione) Examples include:

[0191] For example, when forming a silicon oxide film using a film forming device that uses ALD, The chlorine contained in the adsorbed material is removed, and the oxidizing gas (O2 , nitrous oxide) radicals are supplied to react with the adsorbate.

[0192] For example, when forming a tungsten film using a film forming device that uses ALD, WF6 gas is used. The initial tungsten film is formed by repeatedly introducing WF6 and B2H6 gases. The tungsten film is formed by simultaneously introducing B2H6 gas and H2 gas. Alternatively, SiH4 gas may be used.

[0193] For example, an oxide semiconductor film, such as In-Ga-Zn-O, can be formed using a film formation device that uses ALD. When forming a film, In(CH3)3 gas and O3 gas are introduced in sequence and repeatedly to form an In- Then, Ga(CH3)3 gas and O3 gas are introduced simultaneously to form a GaO layer. Then, Zn(CH3)2 and O3 gases are introduced simultaneously to form a ZnO layer. The order of these layers is not limited to this example. Also, by mixing these gases, In-Ga-O Alternatively, a mixed compound layer such as an In-Zn-O layer or a Ga-Zn-O layer may be formed. Instead of O3 gas, H2O gas obtained by bubbling with an inert gas such as Ar may be used. However, it is preferable to use O3 gas, which does not contain H. Also, instead of In(CH3)3 gas, In addition, instead of Ga(CH3)3 gas, In(C2H5)3 gas may be used. Zn(CH3)2 gas may also be used.

[0194] <<Multi-chamber film deposition equipment>> Also, a multi-chamber manufacturing apparatus having at least one film forming apparatus shown in FIG. An example is shown in FIG. 6(B).

[0195] The manufacturing equipment shown in FIG. 6(B) can continuously form laminated films without exposing them to the atmosphere. We aim to prevent impurities from being mixed in and improve throughput.

[0196] The manufacturing apparatus shown in FIG. 6(B) includes a load chamber 1702, a transfer chamber 1720, a pre-treatment chamber 1703, The system has at least a chamber 1701, which is a film-forming chamber, and an unloading chamber 1706. The chambers of the manufacturing equipment (including the load chamber, processing chamber, transfer chamber, deposition chamber, unload chamber, etc.) In order to prevent moisture from adhering, the container is filled with an inert gas (such as nitrogen gas) with a controlled dew point. It is preferable to keep the pressure reduced, and it is desirable to maintain the pressure reduced.

[0197] In addition, chambers 1704 and 1705 use the same ALD method as chamber 1701. It may be a film forming apparatus, a film forming apparatus using a plasma CVD method, or a sputtering apparatus. The deposition apparatus may be a deposition apparatus using a deposition method, or a metal organic chemical vapor deposition (MOCVD) method. Organic Chemical Vapor Deposition (OCCVD) method The film forming apparatus may be used.

[0198] For example, the chamber 1704 is a film forming device that uses a plasma CVD method. The following is an example of a film deposition system using the MOCVD method as the 1705. show.

[0199] In FIG. 6B, the top view of the transfer chamber 1720 is shown as an example of a hexagonal shape, but it may be changed depending on the number of layers of the laminated film. If necessary, a manufacturing device having a polygonal shape or more and connected to more chambers may be used. In addition, although the top surface shape of the substrate is shown as a rectangle in FIG. 6(B), it is not particularly limited. Although FIG. 6(B) shows an example of a single wafer type, a batch type film formation in which multiple substrates are formed at once is also possible. It may also be a device.

[0200] <Formation of Insulating Layer 110> First, an insulating layer 110 is formed on a substrate 100. The insulating layer 110 is formed by a plasma CVD method, a thermal For example, aluminum oxide is deposited by CVD (MOCVD, ALD) or sputtering. Nitride, magnesium oxide, silicon oxide, silicon oxynitride, gallium oxide, gallium oxide Al, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, halide oxide Oxide insulating films such as tantalum oxide and tantalum oxide, silicon nitride, silicon nitride oxide, and nitride nitride insulating film such as aluminum nitride, aluminum oxide nitride, or a mixture of these materials It may also be a laminate of the above materials, and at least afterwards, The upper layer of the stack in contact with the first oxide semiconductor film that becomes the oxide semiconductor layer 121 is the oxide semiconductor layer 1 It is preferable to form the electrode 22 from a material containing excess oxygen that can be a source of oxygen to the electrode 22 .

[0201] For example, the insulating layer 110 is formed by plasma CVD using silicon oxynitride having a thickness of 100 nm. A membrane can be used.

[0202] Next, heat treatment may be performed to remove water, hydrogen, and the like contained in the insulating layer 110. As a result, the concentration of water, hydrogen, etc. contained in the insulating layer 110 can be reduced, and the heat treatment This reduces the amount of water, hydrogen, and the like that diffuses into the first oxide semiconductor film that will be formed later. can be done.

[0203] <Formation of First Oxide Semiconductor Film and Second Oxide Semiconductor Film> Next, a first oxide semiconductor film, which will later become the oxide semiconductor layer 121, is formed on the insulating layer 110. A second oxide semiconductor film is formed to be the oxide semiconductor layer 122. The second oxide semiconductor film is formed by a sputtering method, an MOCVD method, a PLD method, or the like. It is more preferable to form the film by sputtering, since the film can be formed by sputtering. Sputtering, DC sputtering, AC sputtering, etc. can be used. In the facing target method (facing electrode method, vapor phase sputtering method, VDSP (Vapo It is formed by the (also called) (Fr Deposition Spattering) method. This can reduce plasma damage during film formation.

[0204] For example, when the first oxide semiconductor film is formed by a sputtering method, Each chamber is equipped with a cladding to remove as much water as possible, which is an impurity for oxide semiconductors. A high vacuum (5×10) was achieved using an adsorption type vacuum pump such as an ion pump. -7 Pa~1 x10 -4 The substrate on which the film is to be formed can be heated to 100°C or higher, preferably It is preferable that the pump can be heated to 400°C or higher. By combining this with a pump, gas containing carbon components and moisture does not flow back into the chamber from the exhaust system. It is also preferable to combine a turbomolecular pump and a cryopump. An exhaust system having a different structure may also be used.

[0205] In order to obtain a high-purity intrinsic oxide semiconductor, not only is it necessary to evacuate the chamber to a high vacuum, but also to It is also necessary to increase the purity of sputtering gases. Oxygen gas and argon gas used as sputtering gases are , the dew point is -40°C or less, preferably -80°C or less, more preferably -100°C or less By using a highly purified gas, it is possible to prevent moisture and the like from being taken into the oxide semiconductor film as much as possible. This can be prevented.

[0206] The sputtering gas is a rare gas (typically argon), oxygen, or a mixture of rare gas and oxygen. In the case of a mixture of rare gas and oxygen, the ratio of the oxygen gas to the rare gas is It is preferable to increase the ratio.

[0207] Note that when the oxide semiconductor film is formed by, for example, a sputtering method, the substrate temperature The temperature is 150°C or higher and 750°C or lower, preferably 150°C or higher and 450°C or lower, and more preferably The oxide semiconductor film is formed at a temperature of 200°C or higher and 420°C or lower. A film can be formed.

[0208] The first oxide semiconductor film is made of a material so as to have a smaller electron affinity than the second oxide semiconductor film. You can choose the price.

[0209] In addition, the second oxide semiconductor film is more insulating than the first oxide semiconductor film and the third oxide semiconductor film. In the oxide semiconductor, the s orbital of the heavy metal is mainly carried by the carrier. By increasing the In content, more s orbitals overlap, which contributes to rear conduction. Therefore, oxides with a composition in which In is more abundant than Ga have compositions in which In is equal to or less than Ga. Therefore, the oxide semiconductor layer 122 has a higher mobility than an oxide containing indium. By using oxides with a high content of , it is possible to realize transistors with high mobility. do.

[0210] In addition, the first oxide semiconductor film and the second oxide semiconductor film are formed by, for example, a sputtering method. When forming the first oxide semiconductor film, a multi-chamber sputtering device is used. The first oxide semiconductor film and the second oxide semiconductor film can be successively formed without being exposed to the air. In this case, unnecessary impurities may enter the interface between the first oxide semiconductor film and the second oxide semiconductor film. As a result, the interface state density can be reduced. This makes it possible to stabilize the electrical characteristics of the transistor, especially the characteristics in reliability tests.

[0211] In addition, in the first oxide semiconductor film to which oxygen is added, When the oxide semiconductor layer 122 is damaged, it becomes a main conductive path. The oxide semiconductor layer 123 can be kept away from the damaged portion, and as a result, the transistor This makes it possible to stabilize the electrical characteristics, particularly the characteristics in reliability tests.

[0212] For example, the first oxide semiconductor film is formed by sputtering In:Ga:Zn=1 A 20 nm thick oxide semiconductor film was formed using a target with an atomic ratio of 3:4. The second oxide semiconductor film can be formed by sputtering. Oxide film formed to a thickness of 15 nm using a target with a Ga:Zn=1:1:1 (atomic ratio) A semiconductor film can be used.

[0213] Furthermore, by heat treatment after the formation of the first oxide semiconductor film and the second oxide semiconductor film, Therefore, the amount of oxygen vacancies in the nitride semiconductor film can be reduced.

[0214] Next, first heat treatment is performed to transfer part of oxygen to the second oxide semiconductor film. The oxygen vacancies in the oxide semiconductor film can be reduced. The oxide semiconductor film is referred to as the second oxide semiconductor film. The first heat treatment can also reduce oxygen deficiency. Hydrogen, water, and the like contained in the oxide semiconductor film and the second oxide semiconductor film can be released. As a result, the oxygen-added first oxide semiconductor film and the oxygen-added second oxide semiconductor film can be The content of impurities can be reduced.

[0215] The temperature of the first heat treatment is 250°C or higher and lower than the substrate strain point, preferably 300°C or higher and 650°C or lower. °C or less, and more preferably 350°C or more and 550°C or less.

[0216] The first heat treatment is carried out using a rare gas such as helium, neon, argon, xenon, or krypton, or or in an inert gas atmosphere containing nitrogen. Alternatively, after heating in an inert gas atmosphere, Atmosphere or dry air (dew point is -80°C or less, preferably -100°C or less, preferably - Heating may be carried out in an air atmosphere at a temperature of 120°C or less, or under reduced pressure. In addition to the dry air, it is preferable that the inert gas and oxygen gas do not contain hydrogen, water, etc. Typically, the dew point is -80°C or less, preferably -100°C or less. Treatment time ranges from 3 minutes to 24 hours.

[0217] In the first heating process, heat transfer from a heating element such as a resistance heating element is used instead of an electric furnace. A device that heats the object to be treated by induction or heat radiation may be used. For example, a GRTA ( Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Ra RTA (Rapid Thermal Anneal) equipment, etc. The LRTA device uses a halogen lamp, a metal Halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps The object to be treated is heated by the radiation of light (electromagnetic waves) emitted from a lamp such as a high-pressure mercury lamp. The GRTA device is a device that performs the first heat treatment using high-temperature gas. The hot gas is a noble gas such as argon, or an inert gas such as nitrogen. .

[0218] Note that the first heat treatment is performed to form the oxide semiconductor layers 121 and 122, which will be described later. This may be done after etching.

[0219] For example, after heat treatment at 450°C for 1 hour in a nitrogen atmosphere, The heat treatment can be carried out at 450°C for 1 hour.

[0220] Through the above steps, oxygen vacancies in the oxide semiconductor film are reduced, and impurities such as hydrogen and water are also reduced. In addition, an oxide semiconductor film with a reduced density of localized states can be formed. Cut.

[0221] <Formation of the first conductive film> Next, a first electrode layer 130 and a first electrode layer 140 are formed on the oxide semiconductor layer 123. The first conductive film is formed by sputtering, chemical vapor deposition (CVD) Metal organic chemical vapor deposition (MOCVD), metal chemical vapor deposition, atomic layer deposition (ALD), etc. or plasma-enhanced chemical vapor deposition (PECVD), evaporation, pulsed laser deposition. It can be formed by using a PLD method or the like.

[0222] The material of the first conductive film is copper (Cu), tungsten (W), molybdenum (Mo), gold (A u), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), Nickel (Ni), chromium (Cr), lead (Pb), tin (Sn), iron (Fe), cobalt ( Co), ruthenium (Ru), platinum (Pt), iridium (Ir), strontium (S r) materials, or alloys, or conductive materials containing compounds with these as the main components It is preferable that the oxide semiconductor layer 1 be a single layer or a stacked layer. The lower conductive layer in contact with 22 has a material that easily bonds with oxygen, and the upper conductive layer has an oxidation-resistant material. In addition, tungsten (W) is a material that is both heat-resistant and electrically conductive. It is preferable to use a high melting point material such as aluminum (Al) or molybdenum (Mo). It is preferable to form the insulating film from a low-resistance conductive material such as aluminum (Al) or copper (Cu). When a manganese-Mn alloy is used, a film containing manganese oxide is formed at the interface with the insulator containing oxygen, and the oxide Manganese dioxide is preferred because it has the function of suppressing the diffusion of Cu.

[0223] For example, a tungsten film having a thickness of 20 to 100 nm is formed on the first conductive layer by sputtering. It can be formed as a film.

[0224] The conductive layer 130b, which is formed by processing the first conductive film in a later step, In this case, it has a function as a hard mask and a function as a source electrode layer and a drain electrode layer. This eliminates the need for an additional film formation process, thereby shortening the semiconductor manufacturing process. .

[0225] <Formation of Oxide Semiconductor Layer 121 and Oxide Semiconductor Layer 122> Next, a resist mask is formed by a lithography process. The first conductive film is selectively etched to form the conductive layer 130b. After removing the resist on Ob, the conductive layer 130b is used as a hard mask to form a second oxide semiconductor The oxide semiconductor layer 122 and the oxide semiconductor layer 132 are selectively etched. The compound semiconductor layer 121 can be formed in an island shape (see FIG. 7). For this purpose, a dry etching method can be used. By etching the oxide semiconductor layer using the resist mask as a mask, the etching speed is improved compared to the resist mask. The edge roughness of the oxide semiconductor layer after etching can be reduced.

[0226] For example, methane gas and argon gas are used as etching gases, and the resist mask and The first oxide semiconductor film and the second oxide semiconductor film are selectively etched using a hard mask. By this, the oxide semiconductor layer 121 and the oxide semiconductor layer 122 can be formed. do.

[0227] <Deposition of the second insulating film> Next, a second insulating film is formed on the insulating layer 110 and the conductive layer 130b.

[0228] The second insulating film and the third insulating film are formed by plasma CVD, thermal CVD (MOCVD, ALD) For example, aluminum oxide (SiOx), magnesium oxide (MgO) Sium (MgOx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), Gallium oxide (GaOx), germanium oxide (GeOx), yttrium oxide (YOx ), zirconium oxide (ZrOx), lanthanum oxide (LaOx), neodymium oxide (NdO oxide insulating films such as hafnium oxide (HfOx) and tantalum oxide (TaOx) , silicon nitride (SiNx), silicon oxide nitride (SiNxOy), aluminum nitride ( AlNx), aluminum oxide nitride (AlNxOy), or other nitride insulating films The insulating film 10 may be formed using a mixed material of the above materials.

[0229] The second insulating film is formed by depositing an aluminum oxide film by sputtering. It is also desirable to use aluminum oxide as the sputtering target. It is also desirable that the gas used during film formation contains oxygen gas.

[0230] When the aluminum oxide film is formed, a mixed layer 171 is formed at the interface with the insulating layer 110. do.

[0231] For example, the oxygen gas used in forming the second insulating film is the same as that applied in forming the film by sputtering. Due to the influence of the applied voltage, power, plasma, and substrate temperature, oxygen radicals, oxygen ions, Oxygen atoms exist in various states and have higher energy states than the stable state. At this time, oxygen (excess oxygen, exO) 172 is added to the insulating layer 110 or the mixture. It is added in layer 171 (see FIG. 8).

[0232] Next, a second heat treatment may be performed. The second heat treatment is typically performed at a temperature of 150° C. or higher. Less than the plate strain point, preferably 250°C or more and 500°C or less, more preferably 300°C or more and 45°C or less The heat treatment can be performed at a temperature of 0° C. or lower. The oxygen 172 diffuses and moves to the oxide semiconductor layer 122 . This allows oxygen to be supplied to compensate for any oxygen deficiencies that may exist (see FIG. 9).

[0233] For example, by sputtering, using an aluminum oxide (AlOx) target, The second insulating film is formed using a sputtering gas containing 50% by volume of oxygen gas. The thickness can be 20 nm to 40 nm. As a treatment, it can be treated at 400°C for 1 hour in an oxygen atmosphere.

[0234] <Oxygen addition> Furthermore, the method for manufacturing the transistor 10 is not limited to the above method. The oxygen addition treatment may be performed on the insulating layer 110 or on the first insulating layer 110. This may be performed on the oxide semiconductor film, or the third oxide semiconductor film 123a described later. The oxygen to be generated may be any of oxygen radicals, oxygen atoms, oxygen atomic ions, oxygen molecular ions, etc. The oxygen doping method may be an ion doping method, an ion implantation method, or the like. plasma immersion ion implantation, etc.

[0235] When ion implantation is used as a method for adding oxygen, oxygen atomic ions can be used. Alternatively, oxygen molecular ions may be used. When oxygen molecular ions are used, the amount of oxygen added to the film increases. The oxygen molecular ions are released from the surface of the film to which the oxygen is added. The oxygen molecules are separated into oxygen atoms and added as oxygen atom ions. Since energy is used, when oxygen molecular ions are added to the membrane to which the oxygen is added, The energy per oxygen atom ion in This is lower than when oxygen is added to the film. Therefore, damage to the film to which the oxygen is added is reduced. It can be reduced.

[0236] In addition, when oxygen molecular ions are implanted, the oxygen is more easily absorbed than when oxygen atomic ions are implanted. The energy per atomic ion is low, so it is possible to implant oxygen molecular ions. This allows for a higher acceleration voltage and therefore a higher throughput. In addition, by using oxygen molecular ions for implantation, compared to when oxygen atomic ions are used, It is possible to halve the dose to add the same amount of oxygen atomic ions. As a result, the throughput of the manufacturing process can be increased.

[0237] In addition, when oxygen is added to the film to which oxygen is added, oxygen atoms are added to the film to which oxygen is added. The oxygen is added under the conditions that the peak of the concentration profile of the molecular ions is located. It is preferable to add oxygen to the film to be formed. As a result, compared to the case of implanting oxygen atomic ions, In addition, the acceleration voltage during implantation can be lowered, reducing damage to the film to which the oxygen is added. That is, the amount of defects in the film to which oxygen is added can be reduced, As a result, the change in the electrical characteristics of the transistor can be suppressed. This reduces damage to the film that is being processed, and suppresses fluctuations in the electrical characteristics of the transistor. It can be controlled.

[0238] Also, a plasma method is used in which a film to which oxygen is added is exposed to plasma generated in an atmosphere containing oxygen. By plasma immersion ion implantation (PIA), oxygen is added to the film to which the oxygen is added. The oxygen-containing atmosphere may be oxygen, ozone, nitrous oxide, nitrogen dioxide, or the like. The atmosphere contains a chemical gas. By exposing the film to which oxygen is to be added to the plasma, oxygen is added to the film to which oxygen is to be added. It is possible to increase the amount of added gas, which is preferable. An example of an apparatus for performing such plasma treatment is shown below. As an example, there is an ashing device.

[0239] For example, the acceleration voltage is 5 kV and the dose is 1 × 10 16 / cm 2 The oxygen molecule ions The first oxide semiconductor film can be doped by an on-implantation method.

[0240] The oxide semiconductor layer 122 is formed by a combination of the above steps and the subsequent heat treatment. The amount of oxygen vacancies can be reduced. The film density is lower than that of the film of

[0241] <Deposition of the third insulating film> Next, a third insulating film is formed on the second insulating film. The third insulating film is formed by a plasma CVD method. Thermal CVD (MOCVD, ALD), sputtering, or spin coating methods For example, aluminum oxide (SiOx), magnesium oxide (MgOx), silicon oxide Silicon (SiOx), silicon oxynitride (SiOxNy), gallium oxide (GaOx), Germanium oxide (GeOx), yttrium oxide (YOx), zirconium oxide (Zr Ox), lanthanum oxide (LaOx), neodymium oxide (NdOx), hafnium oxide (Hf Oxide insulating films such as tantalum oxide (TaOx), silicon nitride (SiNx) , silicon oxynitride (SiNxOy), aluminum nitride (AlNx), aluminum oxynitride It is formed using a nitride insulating film such as nitridium (AlNxOy) or a mixture of these materials. Alternatively, the material may be a laminate of the above materials.

[0242] Alternatively, the third insulating film may be made of a material with a low dielectric constant (low-k material). , silicon oxide (SiOF) containing a few percent of fluorine (F), and silicon dioxide (SiOF) containing a few percent of carbon (C). Silicon dioxide (SiOC), fluorinated silicate glass (FSG), organic silicate glass Silsesquioxane (OSG), Hydrogenated Silsesquioxane (HSQ), Methylsilsesquioxane (M SQ), organic polymers, fluororesin (polytetrafluoroethylene), polyimide, fluorine It can be formed by using amorphous carbon to which oxygen is added.

[0243] The second heat treatment may be performed after the third insulating film is formed.

[0244] <Planarization of the third insulating film> Next, the third insulating film is planarized to form an insulating layer 175b. MP (Chemical Mechanical Polishing) method, dry etching This can be done by using a chipping method, a reflow method, etc. Also, it can be planarized by using a CMP method. In this case, a film having a different composition from the third insulating film is introduced on the third insulating film, thereby The thickness of the insulating layer 175 within the substrate surface after the MP process can be made uniform.

[0245] Note that the second heat treatment may be performed after the third insulating film is planarized.

[0246] <Formation of Groove, Source Electrode Layer 130, and Gate Insulating Layer 150> Next, a resist mask 176 is formed on the insulating layer 175b by a lithography process (FIG. 10). Note that after applying an organic film onto the insulating layer 175b, or after applying a resist The lithography process may be performed after applying an organic film. It contains cholesteryl methyl ether, ethyl lactate, etc., and is an anti-reflective coating (BA) RC (Bottom Anti-Reflective Coating) function In addition, it is known to have the effect of improving the adhesion between the resist and the film, improving the resolution, etc. can.

[0247] When a transistor having an extremely short channel length is formed, at least the source electrode layer 130, in the region dividing the conductive layer 130b which becomes the drain electrode layer 140, an electron beam Resist mask processing using methods suitable for fine line processing such as lithography, immersion lithography, and EUV lithography Then, the region is etched by the etching process. When forming a resist mask using light, a positive resist is used as the resist mask. If there is such a structure, the exposure area can be minimized and throughput can be improved. By using this method, it is possible to reduce the channel length to 100 nm or less, or even to 30 nm or less. It is possible to form a transistor. Alternatively, it is possible to use light with extremely short wavelengths (e.g., extreme ultraviolet light). (EUV: Extreme Ultraviolet) and exposure techniques using X-rays, etc. Fine processing may be performed by techniques.

[0248] Using the resist mask, grooves are formed in the insulating layer 175b by dry etching. As the etching process proceeds selectively, a groove 174 is formed in the insulating layer 175. do.

[0249] Subsequently, the exposed conductive layer 130b is selectively etched in a manner that divides it, and the source electrode layer 1 30, the drain electrode layer 140 can be formed (see FIG. 11).

[0250] After the source electrode layer 130 and the drain electrode layer 140 are formed, etching residues are removed. By this cleaning process, the source electrode layer 130, This can prevent short circuits in the drain electrode layer 140. Alkaline solutions such as tetramethylammonium hydroxide This can be done using an acidic solution such as diluted hydrofluoric acid, oxalic acid, or phosphoric acid. The cleaning process etches a part of the oxide semiconductor layer 122, and the oxide semiconductor layer 1 A recess is formed in 22.

[0251] The oxide semiconductor layer 121, the oxide semiconductor layer 122, the source electrode layer 130, the drain electrode layer 131, and the like are The order of forming the source electrode layer 130 can be changed. A groove 174 for forming a drain electrode is first formed, and then the oxide semiconductor layer 121, An oxide semiconductor layer 122 may be formed.

[0252] For example, after the silicon oxynitride film formed as the second insulating film is planarized, the silicon oxynitride film is A resist mask is formed on the carbon film, and the resist mask and a gas containing carbon and fluorine are The silicon oxynitride is opened by dry etching using chlorine, The conductive layer 130b is dry-etched using a fluorine-based gas to form a source electrode Layer 130 and drain electrode layer 140 can be formed.

[0253] <Formation of Third Oxide Semiconductor Film 123a> Next, the oxide semiconductor layer 122 is formed on the insulating layer 175. The third oxide semiconductor film 123a is formed by depositing the first oxide semiconductor film 123a. The third oxide semiconductor film 123a can be formed by a method similar to that for forming the first oxide semiconductor film. A material can be selected so as to have a smaller electron affinity than the oxide semiconductor film of 2.

[0254] For example, the third oxide semiconductor film 123a may be formed by sputtering In:Ga: Oxide semiconductor film deposited to a thickness of 5 nm using a target with a Zn=1:3:2 (atomic ratio) can be used.

[0255] <Formation of insulating film 150a> Next, a fourth insulating film 150a that will become the gate insulating layer 150 is formed on the oxide semiconductor film 123a. The fourth insulating film 150a is made of, for example, aluminum oxide (AlOx), magnesium oxide (MgO), or the like. Magnesium (MgOx), silicon oxide (SiOx), silicon oxynitride (SiOxNy) , silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide aluminum, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide and tantalum oxide The fourth insulating film 150a may be a laminate of the above materials. The fourth insulating film 150a may be formed by a sputtering method, a CVD method (plasma CVD method, MOCVD method, etc.). The fourth insulating layer can be formed by using a method such as a CVD method, an ALD method, or an MBE method. The insulating film 150a can be formed as an insulating film by appropriately using the same method as that for the insulating layer 110. .

[0256] For example, the fourth insulating film 150a is formed by depositing silicon oxynitride to a thickness of 10 n by plasma CVD. m can be formed.

[0257] <Formation of Conductive Film 160a> Next, a second conductive film 160a that will become a gate electrode layer 160 is formed on the fourth insulating film 150a. (See FIG. 12.) The second conductive film 160a is made of, for example, aluminum (Al). , Titanium (Ti), Chromium (Cr), Cobalt (Co), Nickel (Ni), Copper (Cu) , yttrium (Y), zirconium (Zr), molybdenum (Mo), ruthenium (Ru ), silver (Ag), gold (Au), platinum (Pt), tantalum (Ta), tungsten (W), Alternatively, an alloy material containing these as its main component can be used. Sputtering method, CVD method (plasma CVD method, MOCVD method, ALD method, etc.), MBE method, The second conductive film 160a can be formed by vapor deposition, plating, etc. Alternatively, a conductive film containing nitrogen may be used, and a laminate of the above conductive film and a conductive film containing nitrogen may be used. The second conductive film 160a may be a single layer or a multilayer.

[0258] For example, the conductive film 160a is formed by depositing titanium nitride at 10 nm and tungsten at 10 nm by the ALD method. A 150 nm layered structure can be achieved by the CVD method.

[0259] <Flattening process> Next, a planarization process is performed using a CMP method, dry etching method, etc. The planarization process may be terminated when the third insulating film 150a is exposed. However, the process may be terminated when the third oxide semiconductor film 123a is exposed, or when the insulating layer 175 is The process may be terminated when the gate electrode layer 160 and the gate insulating layer 150 are exposed. Thus, an oxide semiconductor layer 123 can be formed (see FIG. 13).

[0260] Note that the oxide semiconductor film 123a or the insulating film 150a is formed over the planarized insulating layer 175. In the case where the oxide semiconductor film 1 has a resist mask, the oxide semiconductor film 1 may be processed using a resist mask. A resist mask is formed on the insulating film 23a or the insulating film 150a by a lithography process. The mask has an area larger than the upper surface of the gate electrode layer 160. The insulating film 150a and the oxide semiconductor film 123a are selectively etched, and the gate insulating layer 150, an oxide semiconductor layer 123 can be formed.

[0261] The transistor 10 is provided with the oxide semiconductor layer 123, which is less likely to have oxygen vacancies. This suppresses oxygen desorption from the side surfaces of the oxide semiconductor layer 123 in the channel width direction. As a result, the electrical characteristics are improved and reliability is improved. This makes it possible to realize a transistor with high performance.

[0262] Next, a third heat treatment may be performed. The heat treatment is typically performed at a temperature of 150° C. or higher. Less than the strain point, preferably 250°C or more and 500°C or less, more preferably 300°C or more and 450°C or less By this heat treatment, the insulating layer (for example, the insulating layer 175) can be doped with the The oxygen diffuses and moves to the oxide semiconductor layer 122. This allows oxygen to be supplied to compensate for the oxygen deficiency that occurs.

[0263] For example, heat treatment can be performed at 400° C. for 1 hour in an oxygen atmosphere.

[0264] Through the above steps, the localized state density of the oxide semiconductor film is reduced, and the oxide semiconductor film has excellent electrical characteristics. It is possible to fabricate transistors. In addition, the electrical characteristics of transistors can be evaluated by aging and stress testing. A highly reliable transistor with little fluctuation can be manufactured.

[0265] <Modification 1 of Transistor 10: Transistor 11> Regarding the transistor 11, which has a different shape from the transistor 10 shown in FIG. 1, we will use FIG. 14 to explain.

[0266] 14(A), 14(B), and 14(C) are a top view and a cross-sectional view of the transistor 11. 14(A) is a top view of the transistor 11, and FIG. 14(B) is a top view of the transistor 11. 14(B) is a cross-sectional view taken along the dashed line A1-A2 of FIG. 14(B), and FIG. 14(C) is a cross-sectional view taken along the dashed line A3-A4 of FIG.

[0267] The transistor 11 has side surfaces (channel regions) of the oxide semiconductor layers 121 and 122. the side surfaces of the source electrode layer 130, the drain electrode layer 140, the side surfaces of the insulating layer 110, and The transistor 10 has a conductive layer 135 in contact with the upper surface and the lower surface of the insulating layer 170. The conductive layer 135 has a sidewall shape as shown in FIG.

[0268] Conductive layer 135 The conductive layer 135 may be made of copper (Cu), tungsten (W), molybdenum (Mo), or gold (Au). , aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), nickel Ni, chromium (Cr), lead (Pb), tin (Sn), iron (Fe), cobalt (Co ), ruthenium (Ru), platinum (Pt), iridium (Ir), strontium (Sr) or alloys made of these materials, or oxygen, nitrogen, fluorine, It is preferable to use a single layer or a multilayer of conductive layers containing compounds such as silicon. When stacking, the lower conductive layer in contact with the oxide semiconductor layer 122 is likely to bond with oxygen. The upper conductive layer may have a material with high oxidation resistance. It is preferable to use a high melting point material such as tungsten or molybdenum, which has both high melting point and high electrical conductivity. It is also preferable to form the wiring board from a low-resistance conductive material such as aluminum or copper. When a Cu-Mn alloy is used, manganese oxide is formed at the interface with the insulator containing oxygen, and the manganese oxide The use of a fluorine-containing compound is preferred because it has the function of suppressing the diffusion of Cu.

[0269] The conductive layer 135 is provided to contact the oxide semiconductor layer 121 and the oxide semiconductor layer 122. This increases the area of ​​the conductive layer, thereby increasing the on-current.

[0270] <Modification 2 of Transistor 10: Transistor 12> Regarding the transistor 12 having a different shape from the transistor 10 shown in FIG. 1, 6 will be used to explain.

[0271] 15(A), 15(B), and 15(C) are a top view and a cross-sectional view of the transistor 12. 15(A) is a top view of the transistor 12, and FIG. 15(B) is a top view of the transistor 12. 15(B) is a cross-sectional view taken along the dashed line A1-A2, and FIG. 15(C) is a cross-sectional view taken along the dashed line A3-A4.

[0272] The transistor 12 comprises a conductive layer 165 under the insulating layer 110, an insulating layer 175, an oxide semiconductor The insulating layer 177 is formed on the upper surface of the gate electrode layer 160. This differs from the transistor 10 in this respect.

[0273] Conductive layer 165 The conductive layer 165 can function as a bottom gate. The same potential as that of the gate electrode layer 160 can be applied, or a different potential can be applied. The conductive layer 165 may be made of, for example, copper (Cu), tungsten (W), molybdenum (Mo), or gold. (Au), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta ), nickel (Ni), chromium (Cr), lead (Pb), tin (Sn), iron (Fe), cobalt Co (Co), ruthenium (Ru), platinum (Pt), iridium (Ir), strontium (Sr) element or alloy, or oxygen, nitrogen, A single layer or a multilayer of a conductive layer containing a compound such as fluorine or silicon is preferable. For example, the conductive layer 166 may be made of a material that is highly resistant to oxidation. 67 uses high-melting-point materials such as tungsten and molybdenum, which are both heat-resistant and conductive. It is also preferable to form the wiring board from a low-resistance conductive material such as aluminum or copper. It's nice.

[0274] Insulating layer 177 The insulating layer 177 contains oxygen (O), nitrogen (N), fluorine (F), aluminum (Al), Magnesium (Mg), silicon (Si), gallium (Ga), germanium (Ge), Tritium (Y), Zirconium (Zr), Lanthanum (La), Neodymium (Nd), Huff The metals may include niobium (Hf), tantalum (Ta), titanium (Ti), etc. , aluminum oxide (AlOx), magnesium oxide (MgOx), silicon oxide (Si Ox), silicon oxynitride (SiOxNy), silicon nitride oxide (SiNxOy), nitride Silicon (SiNx), gallium oxide (GaOx), germanium oxide (GeOx), acid Yttrium oxide (YOx), zirconium oxide (ZrOx), lanthanum oxide (LaOx) , neodymium oxide (NdOx), hafnium oxide (HfOx) and tantalum oxide (TaO The insulating layer 177 can be formed of a laminate of the above materials. may be.

[0275] The insulating layer 177 preferably includes an aluminum oxide film. It has a blocking effect that prevents impurities such as hydrogen and moisture, as well as oxygen, from passing through the membrane. Therefore, the aluminum oxide film can be used during the manufacturing process of the transistor. After manufacturing, oxidation of impurities such as hydrogen and moisture, which are factors that cause fluctuations in the electrical characteristics of transistors, Preventing contamination of the compound semiconductor layer 121 and the oxide semiconductor layer 122, and preventing the oxide of oxygen, which is the main component material Prevention of release from the semiconductor layer 121 and the oxide semiconductor layer 122, and unnecessary release of oxygen from the insulating layer 175 It is suitable for use as a protective film having the important effect of preventing release.

[0276] The insulating layer 177 is preferably a film having an oxygen supplying ability. It is preferable to form the insulating layer 177 by sputtering. A mixed layer is formed at the interface with the insulating layer 175, and oxygen 17 2 can be added.

[0277] The transistor 12 can be subjected to third heat treatment after the insulating layer 177 is formed. The heat treatment in step 3 is typically performed at a temperature of 150° C. or higher and lower than the substrate distortion point, preferably 250° C. or higher and 5 The third heating temperature can be set to 00°C or lower, and more preferably 300°C or higher and 450°C or lower. By the treatment, the dopant in the insulating layer 175 diffuses, and the oxide semiconductor layer 121 and the oxide semiconductor The oxygen migrates to the oxide semiconductor layer 122 and compensates for the oxygen vacancies present in the oxide semiconductor layer 122. It is possible.

[0278] The third heat treatment can also serve as the second heat treatment. 10, the oxygen 172 added to the insulating layer 175 is 23, the oxide semiconductor layer 121, etc., and moves to the oxide semiconductor layer 122, Oxygen deficiencies present in the conductor layer 122 can be compensated for with oxygen (see FIG. 16). .

[0279] This improves the transistor characteristics (for example, threshold value, reliability, etc.) of the transistor 12. It can be done.

[0280] As shown in FIG. 17, the transistor 12 has a structure in which transistors are arranged in parallel (transistor 17. Furthermore, the transistor 13 can be As shown in FIG. 18, an insulating layer 180 is formed on the insulating layer 170, and a conductive layer 181 is formed on the gate electrode layer 160. 90 (conductive layer 191, conductive layer 192), and the gate electrode layer 160 and the conductive layer 190 are electrically connected. The structure may be electrically connected.

[0281] The insulating layer 180 can be made of the same material as the insulating layer 175. Layer 190 may be formed of materials similar to gate electrode layer 160 .

[0282] The transistor 13 can increase the on-current while exhibiting good transistor characteristics. do.

[0283] This embodiment mode may be appropriately combined with other embodiment modes and examples shown in this specification. It is possible.

[0284] (Embodiment 2) In this embodiment, a transistor having a structure different from that of the transistor 10 described in the first embodiment is used. A method for manufacturing the stator 14 and the transistor 14 will be described.

[0285] <Transistor 14> 19A, 19B, and 19C show the upper and lower portions of the transistor 14 according to one embodiment of the present invention. 19(A) is a top view, and FIG. 19(B) is a cross-sectional view of FIG. 19(A). Figure 19(C) is a cross-sectional view between dashed lines A1 and A2 in Figure 19(A), and Figure 19(C) is a cross-sectional view between dashed lines A3 and A4 in Figure 19(A). In addition, in FIG. 19(A), some elements may be enlarged, reduced, or omitted for clarity. The dashed dotted line A1-A2 direction is the channel length direction, and the dashed dotted line A3- The A4 direction may be referred to as the channel width direction.

[0286] The transistor 14 has a groove 17 as shown in FIGS. 19(A), 19(B), and 19(C). 4, an insulating layer 185 is provided on the upper surfaces of the source electrode layer 130 and the drain electrode layer 140. The insulating layer 185 is different from the transistor 10 in that it is formed by insulating layers 170 and 175. The oxide semiconductor layer 123 is in contact with the side surface of the insulating layer 185 and is located above the insulating layer 185 .

[0287] Insulating layer 185 The insulating layer 185 contains oxygen (O), nitrogen (N), fluorine (F), aluminum (Al), Magnesium (Mg), silicon (Si), gallium (Ga), germanium (Ge), Tritium (Y), Zirconium (Zr), Lanthanum (La), Neodymium (Nd), Huff The metals may include niobium (Hf), tantalum (Ta), titanium (Ti), etc. , magnesium oxide (MgOx), silicon oxide (SiOx), silicon oxynitride (Si OxNx), silicon oxynitride (SiNxOx), silicon nitride (SiNx), gallium oxide ium oxide (GaOx), germanium oxide (GeOx), yttrium oxide (YOx), oxide Zirconium (ZrOx), lanthanum oxide (LaOx), neodymium oxide (NdOx), acid Hafnium oxide (HfOx), tantalum oxide (TaOx), aluminum oxide (AlO The insulating layer 185 can be formed of a laminate of the above materials. The insulating layer preferably contains more oxygen than in the stoichiometric composition. .

[0288] Alternatively, the insulating layer 185 may be made of a low-dielectric-constant material (low-k material). , silicon oxide (SiOF) containing a few percent of fluorine (F), and silicon dioxide (SiOF) containing a few percent of carbon (C). Silicon dioxide (SiOC), fluorinated silicate glass (FSG), organic silicate glass Silsesquioxane (OSG), Hydrogenated Silsesquioxane (HSQ), Methylsilsesquioxane (M SQ), organic polymers, polyimides, fluororesins (polytetrafluoroethylene), fluorine The insulating layer 185 can be formed by using amorphous carbon to which oxygen is added. By using low-k materials, the capacitance associated with the transistor 14 can be further reduced. can.

[0289] The transistor 14 has the insulating layer 185, which allows processing below the resolution limit of the device. This allows for finer processing, reducing development costs such as introducing new equipment. It is possible.

[0290] <Method for manufacturing transistor 14> A method for manufacturing the transistor 14 will be described below. For steps similar to those for the transistor 10, the same explanation is used.

[0291] As shown in FIGS. 20A and 20B, after forming the insulating layer 170 and the insulating layer 175b, the groove A resist mask 176 for forming a portion of the transistor 1 is formed. Compared to the conventional method, the groove dimensions can be made wider (the design rules can be relaxed).

[0292] Next, the insulating layer 175b is selectively etched using the resist mask 176, and the insulating layer 1 Form 75.

[0293] Next, a fourth insulating film is formed to become the insulating layer 185. The fourth insulating film is formed by plasma CVD. , thermal CVD method (MOCVD method, ALD method), sputtering method, spin coating method, etc. It can be formed by:

[0294] Next, an etch-back process is performed using a dry etching method to form an insulating layer 185. .

[0295] Next, the insulating layer 185 is used as a hard mask until the oxide semiconductor layer 122 is exposed. The conductive layer 130b is selectively etched to remove the source electrode layer 130 and the drain electrode layer 140. (See Figure 21).

[0296] Next, a third oxide semiconductor film 123a, a third insulating film 150a, and a conductive film 160a are formed in this order. 22) and planarization treatment is performed to fabricate the transistor 14 (see FIG. 23). (see).

[0297] This embodiment mode may be appropriately combined with other embodiment modes and examples shown in this specification. It is possible.

[0298] (Embodiment 3) <Oxide semiconductor structure> In this embodiment, a structure of an oxide semiconductor will be described.

[0299] Oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor, polycrystalline oxide semiconductor Conductor, nc-OS (nanocrystalline oxide semiconductor) ctor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous li Examples include amorphous oxide semiconductors, amorphous oxide semiconductors, and amorphous oxide semiconductors.

[0300] From another point of view, oxide semiconductors are classified into amorphous oxide semiconductors and other crystalline oxide semiconductors. Crystalline oxide semiconductors are divided into single-crystal oxide semiconductors, CAAC-O S, polycrystalline oxide semiconductor, nc-OS, etc.

[0301] The definition of an amorphous structure is generally that it is not fixed in a metastable state and is isotropic. It is known that the bond angle is flexible and the bond is short-range. It can also be described as a structure that has order but does not have long-range order.

[0302] On the other hand, in the case of an essentially stable oxide semiconductor, it is possible to obtain a completely amorphous structure. It cannot be called an oxide semiconductor because it is not isotropic. The oxide semiconductor (for example, having a periodic structure in a microscopic region) is converted into a completely amorphous oxide. It cannot be called a semiconductor. However, a-like OS is a device that can achieve periodicity in a microscopic area. Although it has a structure, it has voids and is an unstable structure. Its physical properties are similar to those of an amorphous oxide semiconductor.

[0303] <caac-os> First, let me explain about CAAC-OS.

[0304] CAAC-OS is an oxide semiconductor having multiple crystal parts (also called pellets) aligned along the c-axis. It is a type of conductor.

[0305] Transmission Electron Microscope (TEM) The CAAC-OS bright-field image and diffraction pattern were analyzed by a combined analysis image (high resolution) When observing the high-resolution TEM image, multiple pellets can be confirmed. In the high-resolution TEM image, the boundaries between pellets, i.e., grain boundaries, are clearly visible. Therefore, it is difficult to clearly identify the CAAC-OS. It can be said that the decrease in electron mobility caused by this is unlikely to occur.

[0306] The CAAC-OS observed by TEM will be described below. This shows a high-resolution TEM image of a cross section of CAAC-OS observed from a direction approximately parallel to the sample surface. For high-resolution TEM imaging, spherical aberration correction (SAC) is required. The spherical aberration correction function was used to obtain a high-resolution TEM image. In particular, it is called a Cs-corrected high-resolution TEM image. This is performed using an atomic resolution analytical electron microscope such as the JEM-ARM200F manufactured by Nippon Denshi Co., Ltd. This can be done.

[0307] FIG. 24(B) shows an enlarged Cs-corrected high-resolution TEM image of region (1) in FIG. 24(A). From Figure 24(B), it can be seen that the metal atoms are arranged in layers in the pellet. The arrangement of each metal atom layer is determined by the surface on which the CAAC-OS film is to be formed (also referred to as the surface on which the film is to be formed). The surface reflects the unevenness of the top surface and is parallel to the surface on which the CAAC-OS is formed or the top surface.

[0308] As shown in Figure 24(B), CAAC-OS has a characteristic atomic arrangement. The characteristic atomic arrangement is shown by auxiliary lines in Figure 24(B) and Figure 24(C). Therefore, the size of each pellet can be 1 nm or more, or 3 nm or more. It can be seen that the size of the gap caused by the tilt between the plate and the pellet is about 0.8 nm. Therefore, the pellets can also be called nanocrystals (nc). In addition, CAAC-OS is also used for CANC (C-Axis Aligned Nanocry The oxide semiconductor may also be called an oxide semiconductor having a crystalline structure.

[0309] Here, based on the Cs-corrected high-resolution TEM image, the pellet of CAAC-OS on the substrate 5120 was The layout of the 5100 is shown diagrammatically as a stack of bricks or blocks. (See FIG. 24(D)). The inclination between the pellets observed in FIG. 24(C) The location where the crack occurs corresponds to the area 5161 shown in FIG. 24(D).

[0310] In addition, Fig. 25(A) shows the Cs of the plane of the CAAC-OS observed from a direction approximately perpendicular to the sample surface. Corrected high-resolution TEM images are shown for regions (1), (2), and (3) in Figure 25(A). Enlarged Cs-corrected high-resolution TEM images are shown in Fig. 25(B), Fig. 25(C), and Fig. 25(D), respectively. 25(D). From Fig. 25(B), Fig. 25(C) and Fig. 25(D), the pellet It can be seen that the metal atoms are arranged in a triangular, square, or hexagonal shape. However, no regularity is observed in the arrangement of metal atoms between different pellets.

[0311] Next, the CA analyzed by X-ray diffraction (XRD) We will explain AC-OS. For example, CAAC-OS with InGaZnO4 crystals When structural analysis is performed using the out-of-plane method, the results are as shown in Figure 26(A). A peak may appear at a diffraction angle (2θ) of around 31°. Since the crystal orientation of CAAC-OS is attributed to the (009) plane of nO4, the crystal orientation of CAAC-OS is considered to be c-axis oriented. It can be seen that the c-axis is oriented in a direction substantially perpendicular to the surface on which the film is formed or the upper surface.

[0312] In addition, in the structural analysis of CAAC-OS using the out-of-plane method, 2θ is 31° In addition to the peaks around 2θ around 36°, a peak may also appear. The peaks around the center of the crystal grains indicate that some of the CAAC-OS grains do not have a c-axis orientation. The more preferable CAAC-OS is the structure solution by the out-of-plane method. In the analysis, a peak is observed at 2θ of approximately 31°, but no peak is observed at 2θ of approximately 36°.

[0313] On the other hand, in-plan X-ray irradiation is performed on the CAAC-OS in a direction approximately perpendicular to the c-axis. When structural analysis is performed using the e method, a peak appears at 2θ around 56°. This peak is due to In It is attributed to the (110) plane of the GaZnO4 crystal. In the case of CAAC-OS, 2θ is set to 56 The sample was fixed at approximately 100°, and the analysis was performed while rotating the sample around the normal vector of the sample surface (φ axis). Even if a φ scan is performed, no clear peak appears as shown in Figure 26(B). However, in the case of a single crystal oxide semiconductor such as InGaZnO4, 2θ is fixed at around 56° and φ is When scanning is performed, the peaks attributable to the crystal plane equivalent to the (110) plane are as shown in Figure 26(C). Therefore, from the structural analysis using XRD, it is clear that CAAC-OS has the following structure: It can be seen that the orientation of the a-axis and b-axis is irregular.

[0314] Next, we will explain the CAAC-OS analyzed by electron diffraction. For CAAC-OS with nO4 crystals, a probe diameter of 300 nm was placed parallel to the sample surface. When an electron beam is incident, a diffraction pattern (selected area transmission electron diffraction) like that shown in Figure 27(A) is generated. This diffraction pattern may show the InGaZnO4 This includes spots due to the (009) plane of the crystal. Therefore, electron diffraction also reveals The pellets contained in the CAAC-OS have a c-axis orientation, and the c-axis is approximately on the surface to be formed or on the upper surface. On the other hand, for the same sample, the probe is oriented perpendicular to the sample surface. The diffraction pattern when an electron beam with a diameter of 300 nm was incident is shown in Figure 27(B). (B) shows a ring-shaped diffraction pattern. Therefore, electron diffraction also reveals It is clear that the a-axis and b-axis of the pellets contained in the CAAC-OS do not have any orientation. The first ring in FIG. 27(B) is the (010) plane of the InGaZnO4 crystal. The second ring in Figure 27(B) is thought to be due to the (100) plane. This is thought to be due to the (110) plane.

[0315] As described above, the CAAC-OS is an oxide semiconductor with high crystallinity. Crystallinity can be reduced by the inclusion of impurities or the formation of defects, so we take the opposite view. CAAC-OS can be considered an oxide semiconductor with few impurities and defects (such as oxygen vacancies).

[0316] The impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. For example, oxygen is more likely to be present than metal elements such as silicon that make up oxide semiconductors. Elements with strong bonding strength with the oxide semiconductor remove oxygen from the oxide semiconductor, thereby changing the atomic arrangement of the oxide semiconductor. In addition, heavy metals such as iron and nickel, argon, and niobium Carbon dioxide and other compounds have a large atomic radius (or molecular radius), so they can easily arrange the atoms of oxide semiconductors. This causes disorder and reduces crystallinity.

[0317] When an oxide semiconductor has impurities or defects, its characteristics may change due to light, heat, etc. For example, impurities contained in an oxide semiconductor can act as carrier traps or In addition, oxygen vacancies in oxide semiconductors can become carrier traps. In some cases, they act as carrier generation sources by capturing hydrogen.

[0318] CAAC-OS, which has few impurities and oxygen vacancies, is an oxide semiconductor with low carrier density. Specifically, 8 × 10 11 / cm 3 Less than 1 x 10 11 / cm 3 Less than, More preferably, 1×10 10 / cm 3 Less than 1 x 10 -9 / cm 3 More than a career Such an oxide semiconductor can be a highly pure intrinsic or CAAC-OS is essentially a highly pure intrinsic oxide semiconductor. The state density is low, that is, the oxide semiconductor has stable characteristics.

[0319] <nc-os> Next, we will explain nc-OS.

[0320] In the high-resolution TEM image, nc-OS is divided into two regions: one where crystals can be clearly seen and the other where crystals can be clearly seen. The nc-OS has regions where no crystalline parts can be confirmed. The size is often between 1 nm and 10 nm, or between 1 nm and 3 nm. The oxide semiconductor with a crystal size of 10 nm or more and 100 nm or less is called a microcrystalline oxide. For example, in high-resolution TEM images, the grain boundaries of nc-OS are It may not be possible to clearly identify the nanocrystals. Therefore, the crystalline part of nc-OS is referred to as the pellet below. There may be cases where this happens.

[0321] nc-OS is a material that can be used in microscopic areas (e.g., areas between 1 nm and 10 nm, especially areas between 1 nm and 3 nm). The atomic arrangement is periodic in the region of less than 100 nm. There is no regularity in the crystal orientation between the dots. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, nc-OS may be distinguished from a-like OS or amorphous oxide semiconductor. For example, for nc-OS, there are cases where it is difficult to distinguish between X particles with a diameter larger than that of the pellet. When using X-rays, peaks indicating crystal planes are not detected in the out-of-plane analysis. In addition, for nc-OS, a probe diameter larger than the pellet (for example, 50n When electron diffraction is performed using an electron beam (over 1000 nm), a diffraction pattern resembling a halo pattern is observed. On the other hand, for nc-OS, the size of the pellet is close to or smaller than the pellet. When nanobeam electron diffraction is performed using an electron beam with a diameter of n, spots are observed. When nanobeam electron diffraction is performed on c-OS, a circular (ring-shaped) bright spot appears. In some cases, a ring-shaped area is observed. In addition, multiple spots are observed within the ring-shaped area. There are cases where this happens.

[0322] In this way, the crystal orientation between the pellets (nanocrystals) is not regular, and therefore, nc- OS with RANC (Random Aligned nanocrystals) oxide semiconductors, or NANCs (Non-Aligned Nanocrystals) ) can also be referred to as an oxide semiconductor.

[0323] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. nc-OS has a lower defect state density than a-like OS and amorphous oxide semiconductors. However, there is no regularity in the crystal orientation between different pellets in nc-OS. , the nc-OS has a higher density of defect states than the CAAC-OS.

[0324] <a-like OS> The a-like OS is an oxide semiconductor with a structure between the nc-OS and amorphous oxide semiconductor. It is a conductor.

[0325] In a-like OS, pores may be observed in high-resolution TEM images. In the high-resolution TEM image, there are areas where crystals can be clearly seen and areas where crystals cannot be seen. and areas where it is not possible to

[0326] Because of the porosity, the a-like OS has an unstable structure. To demonstrate that the OS has an unstable structure compared with CAAC-OS and nc-OS. , showing the structural changes caused by electron irradiation.

[0327] The samples to be irradiated with electrons were a-like OS (referred to as sample A), nc-OS ( Prepare CAAC-OS (referred to as sample B) and CAAC-OS (referred to as sample C). The sample is also an In-Ga-Zn oxide.

[0328] First, high-resolution cross-sectional TEM images of each sample are acquired. It can be seen that all of the samples have crystalline parts.

[0329] The determination of which part is to be regarded as one crystal part can be made as follows. For example, The unit cell of the InGaZnO4 crystal has three In-O layers and one Ga-Zn-O layer. It is known that the structure has a total of nine layers, including six layers, stacked in layers in the c-axis direction. The spacing between these adjacent layers is approximately the same as the lattice spacing (also called the d value) of the (009) plane. The value is calculated to be 0.29 nm from crystal structure analysis. The area where the spacing is 0.28 nm or more and 0.30 nm or less is considered to be the crystal part of InGaZnO4. The lattice fringes correspond to the ab plane of the InGaZnO4 crystal.

[0330] Figure 28 shows an example of investigating the average size of the crystal parts (22 to 45 locations) of each sample. However, the length of the lattice fringes mentioned above is the size of the crystal part. It can be seen that the crystalline part of eOS grows in size according to the cumulative amount of electron irradiation. As shown in Figure 28 (1), the initial TEM observation showed a size of about 1.2 nm. The crystal part (also called the initial nucleus) was sized at 4.2 × 10 8 e - / nm 2 On the other hand, in the nc-OS, the size of the crystals grows to about 2.6 nm. For CAAC-OS, the cumulative electron dose from the start of electron irradiation was 4.2 × 10 8 e - / nm 2 It can be seen that there is no change in the size of the crystals within the range of As shown in (2) and (3) in 28, the nc-OS and The sizes of the crystal parts of the CAAC-OS and CAAC-OS are approximately 1.4 nm and 2.1 nm, respectively. You will realize something.

[0331] In this way, the growth of crystalline parts can be observed in a-like OS due to electron irradiation. On the other hand, in the case of nc-OS and CAAC-OS, the growth of the crystals due to electron irradiation is almost nonexistent. In other words, a-like OS is not as good as nc-OS and CAAC-O. It can be seen that the structure is unstable compared to S.

[0332] In addition, due to its porosity, a-like OS is more flexible than nc-OS and CAAC-OS. Specifically, the density of a-like OS is lower than that of a single crystal with the same composition. The density of nc-OS and CAAC is 78.6% or more and less than 92.3% of that of the original. The density of the -OS is 92.3% or more but less than 100% of the density of a single crystal of the same composition. It is difficult to form an oxide semiconductor film having a density of less than 78% of that of the oxide semiconductor film.

[0333] For example, in an oxide semiconductor with an atomic ratio of In:Ga:Zn=1:1:1, The density of single-crystal InGaZnO4 with a rhombohedral crystal structure is 6.357 g / cm 3 It becomes. For example, in an oxide semiconductor that satisfies the atomic ratio of In:Ga:Zn=1:1:1, , the density of a-like OS is 5.0 g / cm 3 More than 5.9g / cm 3 It is less than For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, The density of nc-OS and that of CAAC-OS are 5.9 g / cm 3 More than 6.3g / cm 3 It will be less than.

[0334] In some cases, single crystals with the same composition do not exist. In such cases, crystals with different compositions at any ratio are used. By combining single crystals, the density equivalent to a single crystal of the desired composition is estimated. The density corresponding to a single crystal of a desired composition can be obtained by combining single crystals of different compositions. The density should be as low as possible. It is preferable to estimate by combining different types of single crystals.

[0335] As described above, oxide semiconductors have a variety of structures, each of which has a variety of properties. The oxide semiconductor may be, for example, an amorphous oxide semiconductor, an a-like OS, an nc-OS, A laminated film containing two or more CAAC-OS materials may also be used.

[0336] (Fourth embodiment) In this embodiment, an example of a circuit using a transistor of one embodiment of the present invention is shown in a drawing. Please refer to the following for explanation.

[0337] <Cross-sectional structure> FIG. 29A is a cross-sectional view of a semiconductor device of one embodiment of the present invention. In FIG. The 1-X2 direction indicates the channel length direction, and the Y1-Y2 direction indicates the channel width direction. The semiconductor device shown in FIG. 2 has a transistor 2200 using a first semiconductor material in the lower part, In FIG. 29(A), a transistor 2100 using a second semiconductor material is provided in the semiconductor layer. As the transistor 2100 using the second semiconductor material, the transistor exemplified in the above embodiment may be used. The left side of the dashed line is the channel of the transistor. The right side is a cross section in the longitudinal direction, and the left side is a cross section in the channel width direction.

[0338] The first and second semiconductor materials preferably have different band gaps. For example, the first semiconductor material may be a semiconductor material other than an oxide semiconductor (silicon (including strained silicon)). (including), germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum arsenide the second semiconductor (e.g., gallium gallium, indium phosphide, gallium nitride, organic semiconductors, etc.); The body material can be an oxide semiconductor. On the other hand, transistors using oxide semiconductors can easily operate at high speed. The transistor can be an excellent substrate by applying the transistor exemplified in the above embodiment. It is possible to obtain threshold characteristics and make a fine transistor. The fast switching speed allows for high-speed operation, and the low off-state current reduces leakage current.

[0339] The transistor 2200 may be an n-channel transistor or a p-channel transistor. Either of these transistors may be used, and an appropriate transistor may be used depending on the circuit. The transistor of one embodiment of the present invention using a nitride semiconductor is used, and other materials and structures are not limited to these. However, the specific configuration of the semiconductor device does not need to be limited to that shown here.

[0340] In the structure shown in FIG. 29A, an insulator 2201 and an insulator The transistor 2100 is connected via the transistor 2207. A plurality of wirings 2202 are provided between the transistor 2100 and the A plurality of plugs 2203 embedded in the substrate allow wiring provided on the upper and lower layers to be The electrodes are electrically connected to the insulator 2204 covering the transistor 2100. , and a wiring 2205 is provided on the insulator 2204 .

[0341] In this way, stacking two types of transistors reduces the area occupied by the circuit, Multiple circuits can be arranged at higher density.

[0342] Here, when a silicon-based semiconductor material is used for the transistor 2200 provided in the lower layer, The hydrogen in the insulator provided near the semiconductor film of the transistor 2200 is converted into silicon dung. This has the effect of terminating the ring bond and improving the reliability of the transistor 2200. When an oxide semiconductor is used for the transistor 2100 provided in the upper layer, the transistor 21 Hydrogen in the insulator provided near the semiconductor film of 00 generates carriers in the oxide semiconductor. This may be one of the factors that cause the reliability of the transistor 2100 to decrease. Therefore, the upper layer of the transistor 2200 made of silicon-based semiconductor material is oxidized. When the transistor 2100 using a compound semiconductor is stacked, hydrogen diffusion between them It is particularly effective to provide an insulator 2207 that has the function of preventing the insulator 220 7 improves the reliability of the transistor 2200 by trapping hydrogen in the lower layer. In addition, the diffusion of hydrogen from the lower layer to the upper layer is suppressed, and thus the transistor 2100 At the same time, reliability can be improved.

[0343] The insulator 2207 may be, for example, aluminum oxide, aluminum oxynitride, or gallium oxide. gallium oxide nitride, yttrium oxide, yttrium oxide nitride, hafnium oxide, Hafnium nitride, yttria-stabilized zirconia (YSZ), etc. can be used.

[0344] In addition, a transistor 2100 including an oxide semiconductor film is formed so as to cover the transistor 2100. It is preferable to form a blocking film on the surface of the substrate 2100, which has the function of preventing hydrogen diffusion. The blocking film can be made of the same material as the insulator 2207, and in particular, It is preferable to use aluminum oxide. The aluminum oxide film is formed by removing impurities such as hydrogen and moisture. It has a high blocking effect, preventing both pure substances and oxygen from passing through the membrane. Therefore, an aluminum oxide film is used as the blocking film covering the transistor 2100. This prevents oxygen from being released from the oxide semiconductor film included in the transistor 2100. In addition, water and hydrogen can be prevented from entering the oxide semiconductor film. The locking film may be used by laminating the insulator 2204 or by placing the insulator 2204 under the insulator 2204. It may also be provided in.

[0345] The transistor 2200 is not limited to a planar transistor, but may be any of various types. It can be a transistor. For example, it can be a transistor such as a FIN (fin) type, a TRI-GATE (tri-gate) type, etc. An example of a cross-sectional view in that case is shown in FIG. 29(D). An insulator 2212 is provided on a semiconductor substrate 2211. The semiconductor substrate 2211 has a thin convex portion (also referred to as a fin) at its tip. Note that an insulator may be provided on the convex portion. The insulator functions as a mask for preventing the semiconductor substrate 2 211 from being etched when forming the convex portion. Note that the convex portion does not necessarily have a thin tip. For example, it may be a convex portion having a substantially rectangular parallelepiped shape, or a convex portion having a thick tip. A gate insulator 2214 is provided on the convex portion of the semiconductor substrate 2211, and a gate electrode 2213 is provided thereon. Source regions and drain regions 2215 are formed in the semiconductor substrate 2211. Here, an example in which the semiconductor substrate 2211 has a convex portion is shown, but the semiconductor device according to one aspect of the present invention is not limited to this. For example, an SOI substrate may be processed to form a semiconductor region having a convex portion. <回路構成例>

[0346] In the above configuration, various circuits can be configured by appropriately connecting the electrodes of the transistor 2100 and the transistor 2200. Hereinafter, an example of a circuit configuration that can be realized by using a semiconductor device according to one aspect of the present invention will be described.

[0347] <CMOSインバータ回路> The circuit diagram shown in FIG. 29(B) is a so-called CMOS in which a p-channel type transistor 2200 and an n-channel type transistor 2100 are connected in series and their gates are connected. ​​​​​​​​​​The configuration of the S inverter is shown.

[0348] <CMOSアナログスイッチ> The circuit diagram shown in FIG. 29C shows the transistors 2100 and 2200. In FIG. 29(A), the source and drain of each of the transistors X1- The X2 direction indicates the channel length direction, and the Y1-Y2 direction indicates the channel width direction. This allows it to function as a so-called CMOS analog switch.

[0349] <Example of storage device> By using a transistor according to one embodiment of the present invention, it is possible to preserve stored contents even when power is not supplied. An example of a semiconductor device (memory device) that can be stored and has no limit on the number of times it can be written is shown in FIG. Shown below.

[0350] The semiconductor device shown in FIG. 30A includes a transistor 3200 using a first semiconductor material and a second semiconductor material. The semiconductor device includes a transistor 3300 and a capacitor 3400 made of two semiconductor materials. Note that the transistor described in Embodiments 1 and 2 is used as the transistor 3300. You can be there.

[0351] 30(B) is a cross-sectional view of the semiconductor device shown in FIG. In the figure, a configuration in which a back gate is provided in the transistor 3300 is shown. It may be configured not to provide.

[0352] FIG. 30(A) shows a configuration in which the intermediate layer 2210 is conductive. When 2210 is insulating, the transistor is connected to the wiring 3005 as shown in FIG. 2200 and transistor 2100 are connected.

[0353] The transistor 3300 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. The transistor 3300 has a small off-state current, so that This means that the memory contents can be retained for a longer period of time without requiring a refresh operation. Alternatively, the semiconductor memory device may be one in which the frequency of refresh operations is extremely low. This makes it possible to sufficiently reduce power consumption.

[0354] In FIG. 30A, a first wiring 3001 is electrically connected to a source electrode of a transistor 3200. The second wiring 3002 is electrically connected to the drain electrode of the transistor 3200. The third wiring 3003 is connected to the source electrode or drain of the transistor 3300. The fourth wiring 3004 is electrically connected to one of the drain electrodes of the transistor 3300. The gate electrode of the transistor 3200 is electrically connected to the transistor 3200. The other of the source electrode and the drain electrode of the transistor 3300 and the capacitor 3400 The fifth wiring 3005 is electrically connected to one of the electrodes of the capacitor 3400. are electrically connected.

[0355] In the semiconductor device shown in FIG. 30A, the potential of the gate electrode of the transistor 3200 can be held. By taking advantage of this feature, it is possible to write, store, and read information as follows: do.

[0356] Writing and holding of information will be described. First, the potential of the fourth wiring 3004 is changed by a transistor. The transistor 3300 is turned on by applying a potential to the transistor 3300. As a result, the potential of the third wiring 3003 is applied to the gate electrode of the transistor 3200 and and the capacitance element 3400. That is, the gate of the transistor 3200 is supplied with a predetermined Here, the charges that give two different potential levels (hereafter referred to as Either a low level charge or a high level charge is given. After that, the potential of the fourth wiring 3004 is set to a potential that turns off the transistor 3300. By turning off the transistor 3300, the gate of the transistor 3200 The charge given to is retained (retention).

[0357] Since the off-state current of the transistor 3300 is extremely small, the gate The charge is retained for a long time.

[0358] Next, reading of information will be described. A predetermined potential (constant potential) is applied to the first wiring 3001. In this state, when an appropriate potential (read potential) is applied to the fifth wiring 3005, the transistor Depending on the amount of charge held in the gate of the capacitor 3200, the second wiring 3002 assumes different potentials. Generally, if the transistor 3200 is an n-channel type, the gate of the transistor 3200 is The apparent threshold voltage V when a high level charge is applied to the port electrode th_H teeth, When a low level charge is applied to the gate electrode of transistor 3200, Threshold V th_L Here, the apparent threshold voltage is the This refers to the potential of the fifth wiring 3005 required to turn on the transistor 3200. Therefore, the potential of the fifth wiring 3005 is V th_H and V th_L potential between By setting V0, the charge applied to the gate of the transistor 3200 can be determined. For example, when a high level charge is applied in a write operation, the fifth wiring The potential of 3005 is V0 (>V th_H ), transistor 3200 is in the "ON state" When a low-level charge is applied, the potential of the fifth wiring 3005 becomes V0 ( <V th_L ), transistor 3200 remains in the "off state." Therefore, the stored information can be read by determining the potential of the second wiring 3002. can be done.

[0359] When memory cells are arranged in an array, only the information in the desired memory cell can be read. If the information is not read out in this way, the gate state is not affected. The potential at which transistor 3200 is in the "off state" regardless of the th_H twist A small potential may be applied to the fifth wiring 3005. The potential at which transistor 3200 is in the "on" state, i.e., V th_L Larger power The position can be given to the fifth wiring 3005.

[0360] The semiconductor device shown in FIG. 30(C) is different from the semiconductor device shown in FIG. 30(A) in that the transistor 3200 is not provided. In this case, the same operations as above are performed to write and store information. It is possible.

[0361] Next, the reading of information will be described. When the transistor 3300 is turned on, The third wiring 3003 in the free state and the capacitor element 3400 are electrically connected to each other. Charge is redistributed between the capacitors 3400. As a result, the potential of the third wiring 3003 changes. The amount of change in the potential of the third wiring 3003 is determined by the potential of the first terminal of the capacitor 3400 ( Alternatively, it takes on different values ​​depending on the charge stored in the capacitor element 3400.

[0362] For example, the potential of the first terminal of the capacitor 3400 is V, the capacitance of the capacitor 3400 is C, and the potential of the third terminal of the capacitor 3400 is V. The capacitance component of the third wiring 3003 before the charge is redistributed is CB. If the potential is VB0, the potential of the third wiring 3003 after the charge is redistributed is (CB× Therefore, the state of the memory cell is If the potential of the first terminal of the transistor 3400 is in two states, V1 and V0 (V1>V0), The potential of the third wiring 3003 when the potential V1 is held (=(CB×VB0+C×V1) / (CB+C)) is the potential (=(C It can be seen that this is higher than B×VB0+C×V0) / (CB+C)).

[0363] Then, the potential of the third wiring 3003 is compared with a predetermined potential, thereby reading out information. can be done.

[0364] In this case, the first semiconductor material is applied to a drive circuit for driving the memory cell. A transistor is used, and a transistor in which a second semiconductor material is applied as the transistor 3300 is used. The transistor may be stacked on the driver circuit.

[0365] In the semiconductor device described in this embodiment, an oxide semiconductor is used in the channel formation region. By using extremely small transistors, memory contents can be retained for an extremely long period of time. In other words, the refresh operation becomes unnecessary or the refresh operation is This allows the frequency of operations to be reduced significantly, resulting in a significant reduction in power consumption. In addition, when there is no power supply (however, it is desirable that the potential is fixed), However, it is possible to retain the stored contents for a long period of time.

[0366] Furthermore, the semiconductor device described in this embodiment mode does not require a high voltage for writing data. There is no problem of degradation of the capacitor. For example, unlike conventional non-volatile memory, the floating gate There is no need to inject electrons into the floating gate or extract electrons from the floating gate. The problem of deterioration of the gate insulating layer does not occur at all. The device does not have the limit on the number of times it can be rewritten, which is a problem with conventional non-volatile memory, and Furthermore, the on / off state of the transistor determines the amount of information Since writing is performed, high speed operation can be easily achieved.

[0367] In this specification, the terms "active elements" and "passive elements" are used interchangeably. For all terminals of elements such as capacitors and resistors, the connection destination must be specified. However, a person skilled in the art may be able to compose an aspect of the invention. Even if the destination is not specified, one aspect of the invention can be said to be clear. When the content is described in this specification, etc., one aspect of the invention that does not specify the connection destination is In particular, if the terminal is connected to multiple If several cases are possible, there is no need to limit the connection destination of the terminal to a specific location. Therefore, active elements (transistors, diodes, etc.) and passive elements (capacitance elements, resistance elements) By specifying the connection destinations for only some of the terminals of a device (such as a semiconductor device), This may constitute an aspect of the invention.

[0368] In this specification and the like, if at least the connection destination of a certain circuit is specified, it is understood by those skilled in the art. It may be possible for a person skilled in the art to identify an invention. A person skilled in the art may be able to identify an invention by at least specifying the function. In other words, if the function is specified, it can be said that one aspect of the invention is clear. It may be possible to determine that one aspect of the invention is described in the present specification. Therefore, even if the function of a circuit is not specified, specifying the connection destination can be considered an aspect of an invention. and can constitute one aspect of the invention. Even if the connection destination of a certain circuit is not specified, if the function is specified, it can be considered as one aspect of the invention. What is disclosed can constitute an aspect of the invention.

[0369] In this specification, etc., in a drawing or text that describes one embodiment, It is possible to extract a part of it and use it to constitute an aspect of the invention. If a drawing or text describing a certain part is included, the drawing or text of that part is omitted. The above content is also disclosed as one aspect of the invention and constitutes one aspect of the invention. Therefore, for example, active elements (transistors, diodes) etc.), wiring, passive elements (capacitive elements, resistive elements etc.), conductive layers, insulating layers, semiconductor layers, organic Drawings in which materials, inorganic materials, components, devices, operating methods, manufacturing methods, etc. are described singly or plurally Or in a passage, a part thereof may be extracted to constitute an aspect of the invention For example, from a circuit diagram composed of N (N is an integer) circuit elements (transistors, capacitor elements, etc.), it is possible to extract M (M is an integer, M < N) circuit elements (transistors, capacitor elements, etc.) to constitute an aspect of the invention Another example is that from a cross-sectional view composed of N (N is an integer) layers, it is possible to extract M (M is an integer, M < N) layers to constitute an aspect of the invention. Still another example is that from a flowchart composed of N (N is an integer) elements, it is possible to extract M (M is an integer, M < N) elements to constitute an aspect of the invention s(N is an integer) to constitute an aspect of the invention ) of the elements to constitute an aspect of the invention

[0370] <Imaging device> Hereinafter, an imaging device according to an aspect of the present invention will be described

[0371] FIG. 31(A) is a plan view showing an example of an imaging device 200 according to an aspect of the present invention. The imaging device 200 includes a pixel section 210, a peripheral circuit 260 for driving the pixel section 210, and peripheral circuits 270, 280, and 290 The pixel section 210 has a plurality of pixels 211 arranged in a matrix of p rows and q columns (p and q are integers of 2 or more). (p and q are integers of 2 or more). The peripheral circuits 260, 270, 280, and 290 are each connected to a plurality of pixels 211 and have a function of supplying signals for driving the plurality of pixels 211 to drive. In this specification, etc., all of the peripheral circuits 260, 270, 280, and 290 may be referred to as "peripheral circuits" or "driving circuits" to drive. In this specification, etc., all of the peripheral circuits 260, 270, 280, and 290 may be referred to as "peripheral circuits" or "driving circuits" occasionally For example, peripheral circuit 260 can be considered a part of the peripheral circuit.

[0372] The imaging device 200 preferably includes a light source 291. The light source 291 emits detection light P It can emit 1.

[0373] The peripheral circuits include at least a logic circuit, a switch, a buffer, an amplifier, or a converter. The peripheral circuits may be disposed on the substrate on which the pixel section 210 is formed. In addition, a part or all of the peripheral circuits may be implemented as semiconductor devices such as ICs. The peripheral circuits are peripheral circuits 260, 270, 280, and 29. One or more of the 0s may be omitted.

[0374] As shown in FIG. 31B, in the pixel section 210 of the imaging device 200, By arranging the pixels 211 at an angle, the pixel The pixel interval (pitch) in the column direction can be shortened. This can further improve the quality of the images captured.

[0375] <Pixel configuration example 1> One pixel 211 included in the imaging device 200 is composed of a plurality of sub-pixels 212, and each sub-pixel The pixel 212 is combined with a filter (color filter) that transmits light of a specific wavelength band. By doing so, it is possible to obtain information for realizing a color image display.

[0376] FIG. 32(A) is a plan view showing an example of a pixel 211 for acquiring a color image. The pixel 211 shown in 32(A) is provided with a color filter that transmits the red (R) wavelength band. The sub-pixel 212 (hereinafter also referred to as "sub-pixel 212R") transmits light in the green (G) wavelength band. A sub-pixel 212 (hereinafter also referred to as "sub-pixel 212G") provided with a color filter A sub-pixel 212 (hereinafter referred to as a "sub-pixel") is provided with a color filter that transmits light in the blue (B) wavelength band. The sub-pixel 212 can function as a photosensor. This can be done.

[0377] The subpixels 212 (subpixels 212R, 212G, and 212B) are connected to the wiring 23 1, electrically connected to wiring 247, wiring 248, wiring 249, and wiring 250. The pixel 212R, the sub-pixel 212G, and the sub-pixel 212B are each connected to an independent wiring 25 3. In this specification, for example, the pixel 211 in the nth row is connected to The wiring 248 and the wiring 249 are respectively denoted as wiring 248[n] and wiring 249[n]. For example, the wiring 253 connected to the pixel 211 in the mth column is designated as wiring 253[m]. In FIG. 32A, the sub-pixel 212R of the pixel 211 in the m-th column is written as follows: The wiring 253 connected to the subpixel 212G is the wiring 253[m]R. The wiring 253 connected to the line 253[m]G and the subpixel 212B is referred to as wiring 253[m]B. The subpixel 212 is electrically connected to the peripheral circuit via the wiring.

[0378] In addition, the imaging device 200 has color filters 211 that transmit the same wavelength bands of adjacent pixels. The sub-pixels 212 provided with the switches are electrically connected to each other via switches. 32(B), arranged in n rows (n is an integer between 1 and p) and m columns (m is an integer between 1 and q) a sub-pixel 212 of the pixel 211 and a sub-pixel 213 arranged in the n+1th row and mth column adjacent to the pixel 211; 32B shows an example of connection of the sub-pixels 212 of the pixel 211. The sub-pixel 212R arranged in the n+1th row and mth column is a switch. The sub-pixels 212G and n+1 are connected via the sub-pixels 201 and 202. The sub-pixels 212G arranged in rows and columns m are connected via the switches 202. The sub-pixel 212B arranged in the row and column m and the sub-pixel 212B arranged in the row and column n+1 are switched. The network is connected via a switch 203.

[0379] The color filters used for the subpixels 212 are not limited to red (R), green (G), and blue (B). color filters that transmit cyan (C), yellow (Y) and magenta (M) light, respectively. A single pixel 211 may have sub-pixels for detecting light of three different wavelength bands. By providing 212, a full color image can be obtained.

[0380] Alternatively, color filters that transmit red (R), green (G), and blue (B) light are installed. In addition to the sub-pixel 212, a sub-pixel having a color filter that transmits yellow (Y) light is provided. Pixel 211 may be used with pixel 212. Alternatively, cyan (C), yellow (Y), In addition to the sub-pixel 212 provided with a color filter that transmits light of blue (Y) and magenta (M), The pixel 21 has a sub-pixel 212 provided with a color filter that transmits blue (B) light. One pixel 211 may have sub-pixels 2 that detect light in four different wavelength bands. By providing the lens 12, the color reproducibility of the acquired image can be further improved.

[0381] Also, for example, in FIG. 32A, the sub-pixel 212 for detecting the red wavelength band, the sub-pixel 213 for detecting the green wavelength band, The ratio of the number of sub-pixels 212 detecting the blue wavelength band to the number of sub-pixels 212 detecting the blue wavelength band ( For example, the pixel ratio (or light receiving area ratio) does not have to be 1:1:1. ) may be a Bayer array with red:green:blue=1:2:1. The light area ratio may be red:green:blue=1:6:1.

[0382] The number of sub-pixels 212 provided in the pixel 211 may be one, but it is preferable that there are two or more. By providing two or more sub-pixels 212 that detect the same wavelength band, redundancy is increased, and the imaging device This can improve the reliability of the device 200.

[0383] In addition, IR (IR: Infrared) filters absorb or reflect visible light and transmit infrared light. By using a filter, it is possible to realize an imaging device 200 that detects infrared light.

[0384] In addition, an ND (Neutral Density) filter (neutral density filter) is used. This prevents output saturation that occurs when a large amount of light is incident on the photoelectric conversion element (light receiving element). By combining ND filters with different light reduction levels, This allows for a wider dynamic range of the device.

[0385] In addition to the above-mentioned filter, a lens may be provided in the pixel 211. An example of the arrangement of the pixel 211, the filter 254, and the lens 255 will be described using a cross-sectional view. By providing the lens 255, the photoelectric conversion element can efficiently receive incident light. Specifically, as shown in FIG. 33(A), a lens 255 and a filter 25 formed in the pixel 211 4 (filter 254R, filter 254G and filter 254B), and pixel circuit 2 30 or the like, light 256 can be made incident on the photoelectric conversion element 220.

[0386] However, as shown in the area surrounded by the dashed line, part of the light 256 indicated by the arrow is reflected by the wiring 257. Therefore, as shown in Figure 33(B), A lens 255 and a filter 254 are arranged on the conversion element 220 side, and the photoelectric conversion element 220 It is preferable that the light 256 is received efficiently from the photoelectric conversion element 220 side. By making the light incident on the photoelectric conversion element 220, an imaging device 200 with high detection sensitivity is provided. can be done.

[0387] As the photoelectric conversion element 220 shown in FIG. 33, a pn-type junction or a pin-type junction is formed. A photoelectric conversion element may also be used.

[0388] The photoelectric conversion element 220 is made of a material that has the function of absorbing radiation and generating electric charges. The material having the function of absorbing radiation and generating charges may be a ceramic. Lead, lead iodide, mercury iodide, gallium arsenide, cadmium telluride, cadmium zinc alloy etc.

[0389] For example, if selenium is used for the photoelectric conversion element 220, in addition to visible light, ultraviolet light, and infrared light, Photoelectric conversion element 2 that has a light absorption coefficient over a wide wavelength range, including X-rays and gamma rays 20 can be achieved.

[0390] Here, one pixel 211 included in the imaging device 200 has a sub-pixel 212 shown in FIG. 2. The pixel 212 may have a first filter.

[0391] <Pixel configuration example 2> In the following, a transistor using silicon and a transistor using an oxide semiconductor will be described. An example of configuring a pixel using the above will be described.

[0392] 34(A) and 34(B) are cross-sectional views of elements that constitute the imaging device.

[0393] The imaging device shown in FIG. 34(A) is a silicon-based transistor provided on a silicon substrate 300. a transistor 351 using an oxide semiconductor and stacked over the transistor 351; The transistor 352 and the transistor 353 are provided on the silicon substrate 300. Each transistor includes a photodiode 360 ​​having an anode 361 and a cathode 362. The photodiodes 360 are electrically connected to various plugs 370 and wiring 371. The anode 361 of the photodiode 360 ​​has a low resistance region 363. 370 and has an electrical connection therethrough.

[0394] The imaging device also includes a transistor 351 and a photodiode 352 provided on the silicon substrate 300. A layer 310 having an electrode 360 ​​and a layer 371 provided in contact with the layer 310. 20 and a layer 320, which are provided in contact with the layer 320 and have a transistor 352 and a transistor 353. and a layer 330 provided in contact with the layer 330 and having wiring 372 and wiring 373. It has 40.

[0395] In the example of the cross-sectional view of FIG. 34(A), the transistor 3 is formed on the silicon substrate 300. The light receiving surface of the photodiode 360 ​​is located on the opposite side to the surface on which the photodiode 51 is formed. This configuration ensures an optical path without being affected by various transistors and wiring. Therefore, it is possible to form pixels with a high aperture ratio. The light-receiving surface of the gate 360 ​​may be the same as the surface on which the transistor 351 is formed.

[0396] When a pixel is formed using a transistor, the layer 310 is Alternatively, the layer 310 may be omitted and the pixel may be formed only by a transistor. .

[0397] In the cross-sectional view of FIG. 34(A), a photodiode 360 ​​provided in the layer 310 and a The transistor 330 can be formed so as to overlap with the transistor 330. In other words, the resolution of the imaging device can be increased.

[0398] In addition, in FIG. 34(B), the imaging device has a photodiode 365 on the layer 340 side. In FIG. 34(B), for example, the layer 310 may have a structure in which: The layer 320 has a silicon transistor 351 and a silicon transistor 352. 71, and the layer 330 includes a transistor 352 using an oxide semiconductor layer, and a transistor 3 53, and the layer 340 has a photodiode 365, and the photodiode 365 The semiconductor layer 63, the semiconductor layer 64, and the semiconductor layer 65 are formed. It is electrically connected to wiring 374 via 370.

[0399] By using the element configuration shown in FIG. 34(B), the aperture ratio can be increased.

[0400] The photodiode 365 is made of an amorphous silicon film or a microcrystalline silicon film. The photodiode 365 may be an n-type semiconductor. The layer 368, the i-type semiconductor layer 367, and the p-type semiconductor layer 366 are stacked in this order. It is preferable to use amorphous silicon for the i-type semiconductor layer 367. The p-type semiconductor layer 366 and the n-type semiconductor layer 368 are provided with dopants that impart their respective conductivity types. Amorphous silicon or microcrystalline silicon containing a pentapent can be used. The photodiode 365, which uses silicon as a photoelectric conversion layer, has high sensitivity in the visible light wavelength range. High sensitivity and easy detection of weak visible light.

[0401] This embodiment mode may be appropriately combined with other embodiment modes and examples shown in this specification. It is possible.

[0402] (Embodiment 5) <RFタグ> In this embodiment, an RF device including a transistor or a memory device described in the previous embodiment is used. The tag will be described with reference to FIG.

[0403] The RF tag in this embodiment has a memory circuit inside, and stores necessary information in the memory circuit. It transmits and receives information to and from the outside using non-contact means, such as wireless communication. Due to these characteristics, RF tags are used as individual devices to identify items by reading their individual information. It can be used for biometric authentication systems. High reliability is required.

[0404] The structure of an RF tag will be described with reference to Fig. 35. Fig. 35 is a block diagram showing an example of the structure of an RF tag. FIG.

[0405] As shown in FIG. 35, an RF tag 800 includes a communicator 801 (also known as an interrogator, reader / writer, etc.). 8, which receives a radio signal 803 transmitted from an antenna 802 connected to the The RF tag 800 also includes a rectifier circuit 805, a constant voltage circuit 806, and a demodulator circuit 808. 07, a modulation circuit 808, a logic circuit 809, a memory circuit 810, and a ROM 811. In addition, the reverse current of the transistor showing the rectification action included in the demodulation circuit 807 is sufficiently suppressed. A material capable of achieving this, for example, an oxide semiconductor, may be used. This suppresses the degradation of rectification caused by reverse current and prevents the output of the demodulation circuit from saturating. In other words, the output of the demodulation circuit can be made closer to linearity with respect to the input of the demodulation circuit. The data transmission format is a pair of coils arranged facing each other and communicating through mutual induction. electromagnetic coupling, electromagnetic induction, which communicates by induced electromagnetic fields; and radio wave communication. The RF tag 800 shown in this embodiment can be used with any of these methods. It can also be used for

[0406] Next, the configuration of each circuit will be explained. The rectifier circuit 802 is used to transmit and receive a radio signal 803 to and from the antenna 802. 05 rectifies an input AC signal generated by receiving a radio signal through an antenna 804. For example, half-wave double voltage rectification is performed, and the rectified signal is smoothed by a capacitive element provided in the subsequent stage. The rectifier circuit 805 is a circuit for generating an input potential by rectifying the input side or A limiter circuit may be provided on the output side. When the internally generated voltage is large, it is necessary to prevent power above a certain level from being input to the subsequent circuit. This is a circuit for controlling the

[0407] The constant voltage circuit 806 generates a stable power supply voltage from the input potential and supplies it to each circuit. The constant voltage circuit 806 may have a reset signal generating circuit inside. The reset signal generation circuit uses the rising edge of the stable power supply voltage to reset the logic circuit 80. This is a circuit for generating the reset signal for 9.

[0408] The demodulation circuit 807 demodulates the input AC signal by detecting its envelope and generates a demodulated signal. The modulation circuit 808 is a circuit for modulating the data output from the antenna 804. This is a circuit for performing modulation based on the received signal.

[0409] The logic circuit 809 is a circuit for analyzing and processing the demodulated signal. It is a circuit that holds input information, and includes a row decoder, column decoder, memory area, etc. The ROM 811 stores a unique number (ID) and outputs it according to the processing. This is a circuit for

[0410] The above-mentioned circuits can be selected or removed as needed.

[0411] Here, the memory circuit described in the above embodiment can be used as the memory circuit 810. The memory circuit of one embodiment of the present invention can retain data even when power is cut off. The memory circuit of one embodiment of the present invention can be suitably used for an RF tag. The power (voltage) required for writing is significantly lower than that of conventional non-volatile memory, It is also possible not to cause a difference in the maximum communication distance during reading and writing. Further, it is possible to suppress malfunction or miswriting due to insufficient power during data writing.

[0412] Also, the memory circuit according to one aspect of the present invention can be used as a non-volatile memory, so it can also be applied to the ROM811. In that case, it is preferable for the producer to separately prepare a command for writing data into the ROM811 and prevent the user from freely rewriting it. By writing the unique number before shipment and then shipping the product, it becomes possible to assign unique numbers not to all the manufactured RF tags but only to the good products to be shipped, and it becomes easy to manage customers corresponding to the products after shipment without the unique numbers of the products after shipment being discontinuous. [[ID=​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​tion decoder 1193, interrupt controller 1194, timing controller 1195, register 1196, register controller 1197, bus interface 1 198, rewritable ROM 1199, and ROM interface 1189 The substrate 1190 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. 199 and the ROM interface 1189 may be provided on separate chips. The CPU shown in Figure 36 is merely an example of a simplified configuration. There are various configurations depending on the application. For example, the CPU or arithmetic circuit shown in Figure 36 A configuration including the above is considered as one core, and multiple cores are included, and each core operates in parallel. The number of bits that the CPU can handle in the internal arithmetic circuit and data bus is For example, it can be 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0417] The instructions input to the CPU via the bus interface 1198 are After being input to the decoder 1193 and decoded, the ALU controller 1192 Rupture controller 1194, register controller 1197, timing controller It is entered into 1195.

[0418] ALU controller 1192, interrupt controller 1194, register controller The timing controller 1197 and the timing controller 1195 control various Specifically, the ALU controller 1192 controls the operation of the ALU 1191. The interrupt controller 1194 also generates a signal for the CPU program. During execution, interrupt requests from external I / O devices and peripheral circuits are handled according to their priority and mask status. The register controller 1197 determines the address of the register 1196 and processes it. It generates a process and reads and writes register 1196 depending on the CPU state.

[0419] The timing controller 1195 controls the ALU 1191 and the ALU controller 119 2, an instruction decoder 1193, an interrupt controller 1194, and It generates a signal to control the timing of the operation of the register controller 1197. The timing controller 1195 generates an internal clock signal based on the reference clock signal. The internal clock generator supplies an internal clock signal to the various circuits.

[0420] In the CPU shown in FIG. 36, a register 1196 is provided with a memory cell. The transistors described in any of Embodiments 1 to 3 can be used as the memory cells of 1196. can.

[0421] In the CPU shown in FIG. 36, the register controller 1197 receives the data from the ALU 1191. According to the instruction, the holding operation is selected in register 1196. In the memory cell of 96, data is held by a flip-flop or a capacitance Select whether to hold data by the element. When selected, the power supply voltage is applied to the memory cells in the register 1196. If data retention in the capacitor is selected, rewriting data to the capacitor This allows the supply of power supply voltage to the memory cells in the register 1196 to be stopped. .

[0422] <Recording circuit> FIG. 37 is an example of a circuit diagram of a storage element that can be used as the register 1196. The memory element 1200 includes a circuit 1201 in which stored data is volatilized when the power is cut off, and a circuit 1202 in which stored data is volatilized when the power is cut off. A non-volatile circuit 1202, a switch 1203, a switch 1204, and a logic element The circuit includes a transistor 1206, a capacitor 1207, and a circuit 1220 having a selection function. 1202 includes a capacitor element 1208, a transistor 1209, a transistor 1210, The memory element 1200 may include a diode, a resistor, an inductor, etc., as needed. It may further include other elements such as a capacitor.

[0423] Here, the memory device described in the above embodiment can be used for the circuit 1202. When the supply of power supply voltage to the memory element 1200 is stopped, the transistor 120 The gate of the transistor 9 is supplied with a ground potential (0V) or a potential that turns off the transistor 1209. For example, the first gate of the transistor 1209 is connected to the load such as a resistor. The circuit is configured to be grounded.

[0424] The switch 1203 uses a transistor 1213 of one conductivity type (for example, n-channel type). The switch 1204 is configured as a transistor of a conductivity type opposite to the one conductivity type (for example, a p-channel type). An example using a transistor 1214 is shown. Here, the first terminal of the switch 1203 The input corresponds to one of the source and drain of the transistor 1213, and the second input of the switch 1203. The terminal of corresponds to the other of the source and drain of the transistor 1213, and the switch 1203 A control signal RD input to the gate of the transistor 1213 switches the first terminal and the second terminal Conduction or non-conduction between the terminals (i.e., the on or off state of transistor 1213) The first terminal of the switch 1204 is connected to the source and drain of the transistor 1214. The second terminal of the switch 1204 corresponds to one of the inputs, and the second terminal of the switch 1204 corresponds to the source of the transistor 1214. The other drain of the switch 1204 is connected to the gate of the transistor 1214. The control signal RD determines whether conduction or non-conduction (i.e., traction) occurs between the first and second terminals. The on or off state of transistor 1214 is selected.

[0425] One of the source and drain of the transistor 1209 is connected to a pair of electrodes of the capacitor 1208. The connection point is electrically connected to one of the gate electrodes of the transistor 1210 and the gate of the transistor 1210. The node M2 ​​is connected to the source or drain of the transistor 1210. The other is electrically connected to a wiring (for example, a GND line) that can supply 1203 (one of the source and drain of the transistor 1213) The second terminal of the switch 1203 (the source and drain of the transistor 1213) is connected to the The other terminal of the switch 1204 (one of the source and drain terminals of the transistor 1214) The second terminal of the switch 1204 (the source of the transistor 1214) is electrically connected to the The other of the source and drain terminals is electrically connected to the wiring that can supply the power supply potential VDD. The second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) ) and the first terminal of the switch 1204 (one of the source and drain of the transistor 1214) ), an input terminal of the logic element 1206, and one of a pair of electrodes of the capacitor 1207. are electrically connected. Here, the connection point is referred to as node M1. The other of the electrodes may be configured to have a constant potential input thereto. It can be configured so that a power supply potential (GND, etc.) or a high power supply potential (VDD, etc.) is input. The other of the pair of electrodes of the capacitor 1207 is connected to a line that can supply a low power supply potential. The other of the pair of electrodes of the capacitor 1208 is electrically connected to a line (for example, a GND line). For example, a low power supply potential (such as GND) can be input. ) or a high power supply potential (such as VDD) can be input to the capacitor element 120. The other of the pair of electrodes 8 is connected to a wiring (e.g., GND) that can supply a low power supply potential. The power supply is electrically connected to the power supply line.

[0426] The capacitors 1207 and 1208 are used to reduce the parasitic capacitance of transistors and wirings. It is possible to omit it by actively using it.

[0427] A control signal WE is input to the first gate (first gate electrode) of the transistor 1209. The switches 1203 and 1204 are connected to a control signal RD, which is different from the control signal WE. A conductive state or a non-conductive state between the first terminal and the second terminal is selected by When the first terminal and the second terminal of one switch are in a conductive state, the first terminal and the second terminal of the other switch are in a conductive state. There is no conduction between terminals 2.

[0428] In the transistor 1209 in FIG. 37, the second gate electrode (second gate electrode: back The first gate receives a control signal WE, and the second gate receives a control signal WE. The control signal WE2 can be input to the output. The control signal WE2 is a signal with a constant potential. The constant potential may be, for example, the ground potential GND or the solenoid voltage of the transistor 1209. At this time, the control signal WE2 is set to a potential smaller than the source potential of the transistor. This is the potential signal for controlling the threshold voltage of 1209, and is the voltage when the gate voltage VG is 0V. In addition, the control signal WE2 is the same potential signal as the control signal WE. The transistor 1209 may be a transistor without a second gate. A resistor can also be used.

[0429] The other of the source and drain of the transistor 1209 is connected to a data line held in the circuit 1201. In FIG. 36, the signal output from the circuit 1201 is The example shown is input to the other of the source and drain of the switch 1203. The signal output from the second terminal (the other of the source and drain of the transistor 1213) is The logic value is inverted by the logic element 1206 to become an inverted signal, and is output via the circuit 1220. and input to the circuit 1201.

[0430] In FIG. 37, the second terminal of the switch 1203 (the source and drain of the transistor 1213) The signal output from the other of the two trains is routed through logic element 1206 and circuit 1220. The example shown is an input to the circuit 1201, but is not limited to this. The signal output from the other of the source and drain of the transistor 1213 is inverted. For example, the following may be included in the circuit 1201: When there is a node that holds a signal whose logical value is the inverse of the signal input from the input terminal The second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) A signal output from the node can be input to the node.

[0431] In addition, in FIG. 37, among the transistors used in the memory element 1200, The transistors other than the transistor 1209 are formed by a layer or a substrate 119 made of a semiconductor other than an oxide semiconductor. For example, a transistor with a channel formed in a silicon layer or The transistor may have a channel formed in a silicon substrate. All the transistors used in 1200 are transistors whose channels are formed in an oxide semiconductor layer. Alternatively, the memory element 1200 may be implemented by any other element than the transistor 1209. The other transistors may also include a transistor in which the channel is formed using an oxide semiconductor layer. The transistor has a channel formed in a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor. The transistor may also be a transistor that is

[0432] For example, a flip-flop circuit can be used for the circuit 1201 in FIG. The logic element 1206 may be, for example, an inverter or a clocked inverter. It is possible.

[0433] In the semiconductor device according to one embodiment of the present invention, while a power supply voltage is not supplied to the memory element 1200, The data stored in the circuit 1201 is transferred to the capacitor 120 provided in the circuit 1202. It can be held by 8.

[0434] Further, a transistor in which a channel is formed in an oxide semiconductor layer has an extremely small off-state current. For example, the off-state current of a transistor whose channel is formed in an oxide semiconductor layer is The off-state current is significantly lower than that of a transistor whose channel is formed in silicon. Therefore, by using this transistor as the transistor 1209, Even when the power supply voltage is not supplied to 200, the signal held in the capacitor element 1208 remains constant for a long period of time. In this way, the memory element 1200 can maintain its stored contents (data) even when the supply of power supply voltage is stopped. It is possible to hold the data.

[0435] Furthermore, by providing the switches 1203 and 1204, the precharge operation Since the memory element is characterized by performing the above operation, after the power supply voltage is restarted, the circuit 1201 This reduces the time required to restore the original data.

[0436] In the circuit 1202, the signal held by the capacitor 1208 is Therefore, the supply of the power supply voltage to the memory element 1200 is resumed. After that, the signal held by the capacitor element 1208 is transferred to the state ( The state can be converted to an ON state or an OFF state and read out from the circuit 1202. Therefore, even if the potential corresponding to the signal held in the capacitor element 1208 fluctuates slightly, the original signal can be accurately read out.

[0437] Such a storage element 1200 may be used as a register or cache memory of a processor. By using it in a storage device, it is possible to prevent the loss of data in the storage device due to a power supply interruption. In addition, after the supply of power voltage is resumed, the state before the power supply was stopped can be restored in a short time. Therefore, the entire processor, or one or more components of the processor, can stop power supply for a short time in multiple logic circuits, reducing power consumption. It can be suppressed.

[0438] In this embodiment, the storage element 1200 is used as a CPU. 200 is equipped with a DSP (Digital Signal Processor), custom L LSIs such as SI and PLD (Programmable Logic Devices), R It can also be applied to F (Radio Frequency) tags.

[0439] This embodiment mode may be appropriately combined with other embodiment modes and examples shown in this specification. It is possible.

[0440] (Embodiment 7) In this embodiment, a structural example of a display device using a transistor according to one embodiment of the present invention will be described. explain.

[0441] <Display device circuit configuration example> FIG. 38A is a top view of a display device of one embodiment of the present invention, and FIG. 38B is a top view of a display device of one embodiment of the present invention. A pixel circuit that can be used when a liquid crystal element is applied to a pixel of a display device of one embodiment will be described. 38C is a circuit diagram showing a pixel of a display device according to one embodiment of the present invention. 1 is a circuit diagram illustrating a pixel circuit that can be used when an organic EL element is applied. .

[0442] The transistors arranged in the pixel portion can be formed according to any of Embodiments 1 to 3. In addition, since the transistor can be easily made into an n-channel type, it is possible to use an n-channel transistor in the driver circuit. A part of the driver circuit that can be configured with a channel transistor is connected to the transistor of the pixel portion. In this way, the transistors shown in the above embodiment modes are formed in the pixel portion and the driver circuit. By using the photoresist, a highly reliable display device can be provided.

[0443] An example of a top view of an active matrix display device is shown in Figure 38(A). On the display panel 700, a pixel section 701, a first scanning line driving circuit 702, a second scanning line driving circuit 70 3, a signal line driver circuit 704. A plurality of signal lines are connected to the pixel portion 701 via the signal line driver circuit 704, and a plurality of scanning lines are connected to the first scanning line driving circuit 702 and the second scanning line driving circuit 703. The scanning lines are arranged in a direction extending from the scanning line driving circuit 703. In each of the display devices, pixels each having a display element are arranged in a matrix. The substrate 700 is a connection part such as an FPC (Flexible Printed Circuit). It is connected to a timing control circuit (also called a controller or control IC) via

[0444] In FIG. 38A, a first scanning line driver circuit 702, a second scanning line driver circuit 703, a signal line The driver circuit 704 is formed on the same substrate 700 as the pixel portion 701. This reduces the number of components, such as the drive circuit, that are required on the board 7, thereby reducing costs. If a driver circuit is provided outside the 00, the wiring must be extended, and the number of connections between the wiring increases. When a driver circuit is provided on the same substrate 700, the number of connections between the wirings can be reduced. This can improve reliability or yield. Any one of the circuit 702, the second scanning line driver circuit 703, and the signal line driver circuit 704 is mounted on the substrate 70. 0 or may be provided outside the substrate 700.

[0445] <Liquid crystal display device> An example of the circuit configuration of a pixel is shown in Figure 38(B). 1 shows a pixel circuit that can be applied to a pixel of a display device.

[0446] This pixel circuit can be applied to a configuration in which one pixel has multiple pixel electrode layers. The pixel electrode layer is connected to different transistors, and each transistor is driven by a different gate signal. This allows individual pixels in a multi-domain design to The signals applied to the electrode layers can be controlled independently.

[0447] The scan line 712 of the transistor 716 and the scan line 713 of the transistor 717 have different On the other hand, the signal line 714 is separated so that a gate signal can be applied. The transistor 716 and the transistor 717 share the same The transistor 717 can be any of the transistors described in any of Embodiments 1 to 3. This makes it possible to provide a highly reliable liquid crystal display device.

[0448] The transistor 716 is electrically connected to a first pixel electrode. The second pixel electrode is electrically connected to the first pixel electrode 7. The first pixel electrode and the second pixel electrode are The first pixel electrode and the second pixel electrode are separated from each other. For example, the first pixel electrode may be V-shaped.

[0449] The gate electrode of the transistor 716 is connected to the scanning line 712, and the gate electrode of the transistor 717 is connected to the scanning line 712. The gate electrode is connected to the scanning line 713. Different gate signals are applied to the scanning lines 712 and 713. By giving a signal to the transistor 716 and the transistor 717, the operation timing is made different. The orientation of the molecules can be controlled.

[0450] Also, the capacitor wiring 710, the gate insulating layer functioning as a dielectric, and the first pixel electrode layer or A storage capacitor may be formed by a capacitor electrode electrically connected to the second pixel electrode layer.

[0451] In the multi-domain design, one pixel has a first liquid crystal element 718 and a second liquid crystal element 719. The first liquid crystal element 718 is composed of a first pixel electrode layer, a counter electrode layer, and a liquid crystal layer therebetween. The second liquid crystal element 719 is composed of a second pixel electrode layer, a counter electrode layer, and a liquid crystal layer therebetween. can be.

[0452] Note that the pixel circuit shown in FIG. 38(B) is not limited to this. For example, The pixel circuit is newly equipped with switches, resistors, capacitors, transistors, sensors, or logic elements. Circuits etc. may be added.

[0453] <Organic EL display device> Another example of the circuit configuration of a pixel is shown in Figure 38(C). 1 shows the pixel structure of the device.

[0454] In an organic EL element, when a voltage is applied to the light-emitting element, electrons are released from one of the pair of electrodes. Holes are injected from the other side into the layer containing the light-emitting organic compound, causing a current to flow. The recombination of electrons and holes causes the light-emitting organic compound to form an excited state, which This mechanism is what causes this type of luminescence. The element is called a current-excited light-emitting element.

[0455] FIG. 38(C) is a diagram showing an example of an applicable pixel circuit. This example shows how two transistors are used in one pixel. Adjustment drive can be applied.

[0456] Regarding the configuration of applicable pixel circuits and pixel operation when digital time gray scale driving is applied, and explain.

[0457] The pixel 720 includes a switching transistor 721, a driving transistor 722, and a light-emitting element The switching transistor 721 has a gate electrode 724 and a capacitor element 723. The source electrode layer is connected to the scanning line 726, and the first electrode (the source electrode layer and the drain electrode layer) The second electrode (the other of the source electrode layer and the drain electrode layer) is connected to the signal line 725. ) is connected to the gate electrode layer of the driving transistor 722. 22, the gate electrode layer is connected to a power supply line 727 via a capacitor element 723, and the first electrode is connected to a power supply line 727. The second electrode is connected to the first electrode (pixel electrode) of the light emitting element 724. The second electrode of the light emitting element 724 corresponds to the common electrode 728. It is electrically connected to a common potential line formed on the substrate.

[0458] The switching transistor 721 and the driving transistor 722 are the same as those in the first embodiment. The transistors described in Sections 1 to 3 can be used appropriately. An EL display device can be provided.

[0459] The potential of the second electrode (common electrode 728) of the light-emitting element 724 is set to a low power supply potential. The power supply potential is a potential lower than the high power supply potential supplied to the power supply line 727, for example, GND , 0V, etc. can be set as the low power supply potential. The high power supply potential and the low power supply potential are set so that the potential difference is equal to or greater than the threshold voltage. By applying a voltage to the light emitting element 724, a current flows through the light emitting element 724, causing it to emit light. The forward voltage in 4 refers to the voltage required to achieve the desired brightness, and is at least the forward threshold. Includes low voltages.

[0460] The capacitor 723 can be saved by substituting the gate capacitance of the driving transistor 722. It can be omitted.

[0461] Next, a signal input to the driving transistor 722 will be described. In this case, the driving transistor 722 is either fully on or fully off. A video signal such as this is input to the driving transistor 722. In order to operate the drive transistor 722 in the linear region, a voltage higher than the voltage of the power supply line 727 is applied to the drive transistor 722. A signal line 725 is connected to the gate electrode layer of the transistor 722. A voltage equal to or greater than the threshold voltage Vth of the input transistor 722 is applied.

[0462] When analog gradation driving is performed, the gate electrode layer of the driving transistor 722 is connected to the light emitting element 72 4 plus the threshold voltage Vth of the driving transistor 722. Note that a video signal is input so that the driving transistor 722 operates in the saturation region. The driving transistor 722 is operated in the saturation region. In order to achieve this, the potential of the power supply line 727 is set higher than the gate potential of the driving transistor 722. By converting the video signal into an analog signal, a current corresponding to the video signal is supplied to the light emitting element 724. It is possible to perform analog gradation driving.

[0463] The configuration of the pixel circuit is not limited to the pixel configuration shown in FIG. (C) The pixel circuit shown in FIG. 1 includes a switch, a resistor, a capacitor, a sensor, a transistor, or a logic element. A logic circuit or the like may be added.

[0464] When the transistor illustrated in the above embodiment is applied to the circuit illustrated in FIG. The source electrode (first electrode) is on the low potential side, and the drain electrode (second electrode) is on the high potential side. Furthermore, the potential of the first gate electrode is controlled by a control circuit or the like. The second gate electrode is supplied with a potential lower than that applied to the source electrode by a wiring (not shown). The potentials exemplified above may be inputted by applying a voltage to the electrode.

[0465] For example, in this specification and the like, the term "display element," "display device having a display element," "light emitting element," "light emitting device," "light emitting element ... A light-emitting device, which is a device having a light-emitting element and a light-emitting element, can be used in various forms or in various The display element, the display device, the light-emitting element or the light-emitting device may include, for example, For example, EL (electroluminescence) elements (EL elements containing organic and inorganic materials, organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs) etc.), transistors (transistors that emit light according to the current), electron-emitting elements, liquid crystal elements , electronic ink, electrophoretic element, grating light valve (GLV), plasma display PDP, MEMS (Micro Electro Mechanical Systems), Digital Micromirror Device (DMD), DMS (Digital Micro Shutter), M IRASOL®, an IMOD (Interference Modulation) element , electrowetting element, piezoelectric ceramic display, carbon nanotube In addition to these, the device has at least one of an electric or magnetic display element. The display medium has contrast, brightness, reflectance, transmittance, etc. that change due to electrochemical effects. An example of a display device using an EL element is an EL display. An example of a display device using electron-emitting elements is a field emission display ( FED) or SED type flat panel display (SED: Surface-conductive tion Electron-emitter Display). An example of a display device using the liquid crystal display (transmissive liquid crystal display, semi-transmissive liquid crystal display) is LCD display, reflective LCD display, direct view LCD display, projection LCD display Examples of display devices using electronic ink or electrophoretic elements include Examples include electronic paper.

[0466] This embodiment mode may be appropriately combined with other embodiment modes and examples shown in this specification. It is possible.

[0467] (Embodiment 8) In this embodiment, a display module to which a semiconductor device of one embodiment of the present invention is applied will be described with reference to FIG. 29 will be used for explanation.

[0468] <Display module> The display module 6000 shown in FIG. 39 is made up of an upper cover 6001 and a lower cover 6002. In between, touch panel 6004 connected to FPC6003 and touch panel 6005 connected to FPC6005 Display panel 6006, backlight unit 6007, frame 6009, printed circuit board 6010 and a battery 6011. The reader 6011, the touch panel 6004, etc. may not be provided.

[0469] The semiconductor device of one embodiment of the present invention is, for example, a display panel 6006 or a printed circuit board. The present invention can be used for integrated circuits mounted on a substrate.

[0470] The upper cover 6001 and the lower cover 6002 are connected to the touch panel 6004 and the display panel. The shape and dimensions can be changed as appropriate to fit the size of the cable 6006.

[0471] The touch panel 6004 is a resistive or capacitive touch panel. 6006. In addition, the opposing substrate (sealing substrate) of the display panel 6006 It is also possible to provide the display panel 6 with a touch panel function. It is also possible to add an optical sensor to each pixel of the 006 to add an optical touch panel function. Alternatively, a touch sensor electrode is provided in each pixel of the display panel 6006, and a capacitance method is used. It is also possible to add a touch panel function.

[0472] The backlight unit 6007 includes a light source 6008. It may be provided at the end of the unit 6007 and configured to use a light diffusion plate.

[0473] The frame 6009 has a function of protecting the display panel 6006 and also functions to prevent electrical shock from The frame 600 also functions as an electromagnetic shield to block electromagnetic waves generated by the frame. 9 may also function as a heat sink.

[0474] The printed circuit board 6010 includes a power supply circuit, a signal circuit for outputting a video signal, and a clock signal. The power supply circuit is provided with a signal processing circuit. Alternatively, a separately provided battery 6011 may be used. In this case, the battery 6011 can be omitted.

[0475] In addition, the display module 6000 may include components such as a polarizing plate, a retardation plate, and a prism sheet. It may also be provided in addition.

[0476] This embodiment mode may be appropriately combined with other embodiment modes and examples shown in this specification. It is possible.

[0477] (Embodiment 9) In this embodiment, an example of use of a semiconductor device according to one embodiment of the present invention will be described.

[0478] <Package using lead frame type interposer> Figure 40(A) shows the cross-sectional structure of a package using a lead frame type interposer. The package shown in FIG. 40A is a perspective view of a semiconductor device according to one embodiment of the present invention. A corresponding chip 1751 is mounted on the interposer 1750 by wire bonding. The terminals 1752 are connected to the chip 17 of the interposer 1750. The chip 1751 is mounted on the surface on which the mold resin 51 is mounted. 1753, but the sealing is performed with a part of each terminal 1752 exposed. Make sure that this is done.

[0479] The module configuration of an electronic device (mobile phone) in which a package is mounted on a circuit board is shown in Figure 1. 40(B). The mobile phone module shown in FIG. 40(B) is a printed wiring board 18 18. The display element 1801 includes a package 1802 and a battery 1804. A printed wiring board 1801 is connected to a panel 1800 on which a device is provided by an FPC 1803. It has been implemented.

[0480] This embodiment mode may be appropriately combined with other embodiment modes and examples shown in this specification. It is possible.

[0481] (Embodiment 10) In this embodiment, electronic devices and lighting devices according to embodiments of the present invention will be described with reference to drawings. do.

[0482] <Electronic equipment> Electronic devices and lighting devices can be manufactured using the semiconductor device of one embodiment of the present invention. By using the semiconductor device of one embodiment, highly reliable electronic devices and lighting devices can be manufactured. The semiconductor device of one embodiment of the present invention is used in an electronic device or a lighting device in which the detection sensitivity of a touch sensor is improved. You can create devices.

[0483] Examples of electronic devices include television sets (also known as televisions or television receivers). (c), computer monitors, digital cameras, digital video cameras, digital Photo frames, mobile phones (also called mobile phones or mobile phone devices), portable game consoles, mobile phones Examples include portable information terminals, audio playback devices, and large game machines such as pachinko machines.

[0484] Furthermore, when the electronic device or lighting device of one embodiment of the present invention is flexible, it can be mounted on the inner wall of a house or a building. Or it can be incorporated into the exterior wall or along the curved surface of the interior or exterior of a car. do.

[0485] Furthermore, the electronic device of one embodiment of the present invention may include a secondary battery and may be configured to use wireless power transmission. It is preferable that the secondary battery can be charged.

[0486] As the secondary battery, for example, a lithium polymer battery (lithium ion battery) using a gel electrolyte is used. Lithium-ion secondary batteries such as lithium polymer batteries, lithium-ion batteries, nickel-metal hydride batteries , nickel-cadmium battery, organic radical battery, lead-acid battery, air secondary battery, nickel-zinc battery, silver-zinc battery Batteries and the like are examples.

[0487] The electronic device according to one embodiment of the present invention may include an antenna. By doing so, it is possible to display images and information on the display unit. If present, the antenna may be used for contactless power transfer.

[0488] FIG. 41A shows a portable game machine, which includes a housing 7101, a housing 7102, a display portion 7103, Display unit 7104, microphone 7105, speaker 7106, operation keys 7107, stylus The semiconductor device according to one embodiment of the present invention is built in the housing 7101. The display portion 7103 or the display portion 7104 can be used for an integrated circuit, a CPU, etc. By using the light-emitting device according to one embodiment of the present invention, the user experience is excellent and deterioration of quality is reduced. It is possible to provide a portable game machine that is less likely to cause such a problem. The portable game machine has two display units 7103 and 7104. The number of display units that the device has is not limited to this.

[0489] FIG. 41B shows a smartwatch, which includes a housing 7302, a display unit 7304, and operation buttons. 7311, 7312, a connection terminal 7313, a band 7321, a clasp 7322, etc. The semiconductor device according to one embodiment of the present invention includes a memory, a CPU, and the like built in the housing 7302. It can be used for.

[0490] FIG. 41C shows a portable information terminal, which includes a display portion 7502 incorporated in a housing 7501. , operation button 7503, external connection port 7504, speaker 7505, microphone 7506 , a display portion 7502, and the like. It can be used for mobile memory, CPU, etc. built into the display unit 7. The 502 can achieve extremely high definition, so it can provide full high definition despite being small to medium sized. , 4k, or 8k, and you can get a very clear image. can.

[0491] FIG. 41D shows a video camera, which includes a first housing 7701, a second housing 7702, a display unit 77 03, operation keys 7704, a lens 7705, a connection part 7706, etc. The lens 7705 and the display unit 7703 are provided in the first housing 7701. The first housing 7701 and the second housing 7702 are connected to each other. The first housing 7701 and the second housing 7702 are connected by a portion 7706, and the angle between the first housing 7701 and the second housing 7702 is The image on the display unit 7703 can be changed by the connection unit 7706. 6, and a configuration in which the switching is performed according to the angle between the first housing 7701 and the second housing 7702. The imaging device of one embodiment of the present invention may be provided at the focal point of the lens 7705. In the semiconductor device according to one embodiment of the present invention, the integrated circuit device built in the first housing 7701 can be It can be used in integrated circuits, CPUs, etc.

[0492] FIG. 41(E) shows a digital signage system, which is a display unit 7902 installed on a utility pole 7901. The display device according to one embodiment of the present invention can be used as a control circuit for the display portion 7902. This can be done.

[0493] FIG. 42(A) shows a notebook personal computer, which includes a housing 8121 and a display unit 8122. , a keyboard 8123, a pointing device 8124, etc. Such a semiconductor device can be applied to a CPU or memory built into the housing 8121. The display portion 8122 can be made very high-definition, so it can be used in small and medium-sized It can display 8K images while still providing extremely clear images.

[0494] FIG. 42(B) shows the exterior of the car 9700. FIG. 42(C) shows the driver's seat of the car 9700. The automobile 9700 includes a body 9701, wheels 9702, a dashboard 9703, a light fixture, and a The semiconductor device of one embodiment of the present invention includes a display portion of the automobile 9700 and For example, the display portion 9710 shown in FIG. The semiconductor of one embodiment of the present invention can be provided in the display portion 9715.

[0495] The display portion 9710 and the display portion 9711 are display devices provided on a windshield of an automobile, The display device or the input / output device of one embodiment of the present invention is a display device or By forming the electrodes of the input / output device using a light-transmitting conductive material, A so-called see-through display device or input / output device that allows the opposite side to be seen through. If it is a see-through display device or an input / output device, the operation of the car 9700 can be Therefore, the display device or input / output device according to one embodiment of the present invention can be used without obstructing the view even when the display device is turned on. The power device can be installed on the windshield of the automobile 9700. or an input / output device, a display device, or a transistor for driving the input / output device, etc. In this case, organic transistors using organic semiconductor materials and transistors using oxide semiconductors are used. A light-transmitting transistor such as a light-transmitting transistor may be used.

[0496] The display unit 9712 is a display device provided in a pillar part. By displaying an image from the imaging means on the display unit 9712, the view blocked by the pillars can be compensated for. The display unit 9713 is a display device provided in the dashboard. For example, an image captured by an imaging means provided on the vehicle body is displayed on the display unit 9713. This allows the driver to compensate for the obstructed view of the dashboard. By projecting images from the installed imaging means, blind spots can be compensated for and safety can be improved. In addition, by projecting images that complement the invisible parts, it is possible to make the sense of incongruity appear more natural. Safety checks can be performed without any hassle.

[0497] FIG. 42(D) shows the interior of a car with bench seats for the driver and passenger. The display unit 9721 is a display device or an input / output device provided in the door. For example, an image captured by an imaging means provided on the vehicle body is displayed on the display unit 9721, The display unit 9722 can complement the view blocked by the handle. The display unit 9723 is a display device provided in the center of the seat surface of the bench seat. The display device is installed on the seat or backrest, and the display device is The heat generated by the display device can also be used as a seat heater.

[0498] The display unit 9714, the display unit 9715, or the display unit 9722 displays navigation information, odometer, tachometer, mileage, fuel level, gear status, air conditioning settings, etc. It is possible to provide various information. In addition, it is possible to change the display items and layout displayed on the display unit. The above information can be displayed on the display unit 9. 710 to 9713, 9721, and 9723. In addition, the display units 9710 to 9715 and the display units 9721 to 9723 are illuminated. The display units 9710 to 9715 and the display unit The display portions 9721 to 9723 can also be used as a heating device.

[0499] 43(A) shows the appearance of the camera 8000. The camera 8000 has a housing 8001 , a display unit 8002, operation buttons 8003, a shutter button 8004, a connection unit 8005, etc. In addition, a lens 8006 can be attached to the camera 8000.

[0500] The coupling section 8005 has electrodes and is connected to the finder 8100 (to be described later) as well as a strobe device, etc. can be connected.

[0501] Here, the camera 8000 is used, and the lens 8006 is removed from the housing 8001 and replaced. However, the lens 8006 and the housing may be integrated.

[0502] An image can be taken by pressing the shutter button 8004. The display unit 8002 has a function as a touch panel, and an image is taken by touching the display unit 8002. It is also possible to

[0503] The display device or the input / output device of one embodiment of the present invention can be applied to the display portion 8002. do.

[0504] FIG. 43(B) shows an example in which a finder 8100 is attached to a camera 8000. are.

[0505] The finder 8100 includes a housing 8101, a display portion 8102, a button 8103, and the like.

[0506] The housing 8101 has a coupling portion that engages with the coupling portion 8005 of the camera 8000. The finder 8100 can be attached to the camera 8000. The display unit 8102 displays images received from the camera 8000 via the electrodes. It can be done.

[0507] The button 8103 functions as a power button. The display of 102 can be switched on and off.

[0508] The semiconductor device of one embodiment of the present invention is applied to an integrated circuit and an image sensor in the housing 8101. It can be used.

[0509] In addition, in Figures 43(A) and (B), the camera 8000 and the finder 8100 are separate electronic devices. The camera 8000 is configured to have a detachable housing 8001. A finder equipped with a display device or an input / output device according to one embodiment may be built in.

[0510] FIG. 43(C) shows the appearance of the head mounted display 8200.

[0511] The head-mounted display 8200 includes a mounting part 8201, a lens 8202, and a main body 820 3, a display unit 8204, a cable 8205, etc. The mounting unit 8201 also has a battery It has a built-in Teri 8206.

[0512] A cable 8205 supplies power from a battery 8206 to the main body 8203. 3 is equipped with a wireless receiver and the like, and displays video information such as received image data on a display unit 8204. In addition, the camera installed in the main body 8203 can record the movements of the user's eyeballs and eyelids. The user's viewpoint is input by capturing the user's viewpoint and calculating the coordinates of the user's viewpoint based on that information. It can be used as a force means.

[0513] Furthermore, the wearing section 8201 may be provided with a plurality of electrodes at positions that come into contact with the user. The main body 8203 detects the current flowing through the electrodes in accordance with the movement of the user's eyeballs, The device may have a function to recognize the user's gaze. By doing so, the attachment unit 8201 may have a function of monitoring the pulse of the user. It may have various sensors such as a temperature sensor, a pressure sensor, an acceleration sensor, etc. and may have a function of displaying the user's biological information on the display unit 8204. Further, it may detect the movement of the user's head, etc. and change the video displayed on the display unit 8204 according to the movement. The semiconductor device according to one aspect of the present invention can be applied to the integrated circuit inside the main body 8203.

[0514] The semiconductor device according to one aspect of the present invention can be applied to the integrated circuit inside the main body 8203.

[0515] This embodiment can be implemented in appropriate combination with at least some of the other embodiments described in this specification.

[0516] (Embodiment 11) In this embodiment, a usage example of an RF tag using the semiconductor device according to one aspect of the present invention will be described with reference to FIG. 44.

[0517] <Usage Example of RF Tag> The uses of RF tags are extensive. For example, banknotes, coins, securities, bearer bonds, documents (such as driver's licenses and resident cards, see FIG. 44(A)), vehicles (such as bicycles, see FIG. 44(B)), packaging containers (such as wrapping paper and bottles, see FIG. 44(C)), recording media (DVDs and video tapes, etc.), personal items around the body (such as bags and glasses, see FIG. 44(D)), foods, plants, animals, the human body, clothing, daily necessities, medical products including drugs and medicines, or electronic devices (liquid crystal display devices, EL display devices, television sets, or mobile phones), etc. It can be used by being provided on such articles or on nameplates attached to each article (see FIGS. 44(E) and 44(F)). An RF tag 4000 according to one aspect of the present invention can be attached to or embedded in the surface of an object. [[ID=#]]

[0518] An RF tag 4000 according to one aspect of the present invention can be attached to or embedded in the surface of an object. For example, if it is a book, it is embedded in the paper, and if it is a package made of organic resin, it is embedded in the paper. For example, the RF tag is embedded in the organic resin and fixed to each product. The 4000 is small, thin, and lightweight, so even after being fixed to an item, it does not change the design of the item itself. In addition, banknotes, coins, securities, bearer bonds, or certificates By providing an RF tag 4000 according to one aspect of the present invention to a product or the like, an authentication function can be provided. By utilizing this authentication function, it is possible to prevent counterfeiting. The present invention can be applied to various items, such as items, recording media, personal belongings, food, clothing, household goods, or electronic devices. By attaching RF tags according to the above, the efficiency of systems such as inspection systems can be improved. Furthermore, even in the case of vehicles, the RF tag according to one aspect of the present invention can be attached. This can improve security against theft and the like.

[0519] As described above, an RF tag using a semiconductor device according to one embodiment of the present invention is By using it for each of the above applications, it is possible to reduce the operating power consumption, including the writing and reading of information. Therefore, it is possible to extend the maximum communication distance. It can also store information for an extremely long period of time, making it suitable for applications where writing and reading are infrequent. It can be suitably used.

[0520] This embodiment mode may be appropriately combined with other embodiment modes and examples shown in this specification. It is possible. [Explanation of symbols]

[0521] 10 transistors 11 Transistor 12 transistors 13 Transistor 14 Transistor 63 Semiconductor layer 64 Semiconductor layer 65 Semiconductor layer 100 boards 110 Insulating layer 120 Oxide semiconductor layer 121 Oxide semiconductor layer 122 Oxide semiconductor layer 123 Oxide semiconductor layer 123a Oxide semiconductor film 124 Oxide semiconductor layer 130 Source electrode layer 130b conductive layer 131 Source electrode layer 132 Source electrode layer 135 Conductive Layer 140 Drain electrode layer 141 Drain electrode layer 142 Drain electrode layer 150 Gate insulating layer 150a insulating film 160 gate electrode layer 160a Conductive film 161 gate electrode layer 162 gate electrode layer 163 gate electrode layer 165 Conductive Layer 166 Conductive Layer 167 Conductive Layer 170 Insulating Layer 171 Mixed layer 172 Oxygen 174 Groove 175 Insulating Layer 175b insulating layer 176 Resist Mask 177 Insulating Layer 180 insulating layer 185 Insulating Layer 190 Conductive Layer 191 Conductive layer 192 Conductive Layer 200 Imaging device 201 Switch 202 Switch 203 Switch 210 Pixel section 211 pixels 212 subpixels 212B subpixel 212G subpixel 212R subpixel 220 Photoelectric conversion element 230 pixel circuit 231 Wiring 247 Wiring 248 Wiring 249 Wiring 250 Wiring 253 Wiring 254 filters 254B filter 254G filter 254R filter 255 Lens 256 light 257 Wiring 260 Peripheral Circuits 270 Peripheral Circuits 280 Peripheral Circuits 290 Peripheral Circuits 291 Light source 300 silicon substrate 310 layers 320 layers 330 layers 340 layers 351 Transistor 352 transistors 353 Transistor 360 photodiode 361 Anode 362 cathode 363 Low resistance region 365 Photodiode 366 Semiconductor Layer 367 Semiconductor Layer 368 Semiconductor Layer 370 Plug 371 Wiring 372 Wiring 373 Wiring 374 Wiring 601 Precursor 602 Precursor 700 boards 701 Pixel section 702 Scanning line driving circuit 703 Scanning line driving circuit 704 Signal Line Driver Circuit 710 Capacitance wiring 712 scan lines 713 scan lines 714 signal line 716 Transistor 717 Transistor 718 Liquid Crystal Devices 719 Liquid Crystal Devices 720 pixels 721 Switching Transistor 722 Drive transistor 723 Capacitor 724 Light-emitting element 725 signal line 726 scan lines 727 Power line 728 Common electrode 800 RF tags 801 Communication Device 802 antenna 803 wireless signal 804 Antenna 805 Rectifier circuit 806 Constant voltage circuit 807 Demodulation Circuit 808 Modulation Circuit 809 Logic Circuit 810 Memory circuit 811 ROM 1189 ROM interface 1190 PCB 1191 ALU 1192 ALU controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 registers 1197 Register Controller 1198 Bus Interface 1199 ROM 1200 memory elements 1201 Circuit 1202 Circuit 1203 Switch 1204 Switch 1206 Logic Elements 1207 Capacitor element 1208 Capacitor 1209 Transistor 1210 transistor 1213 Transistor 1214 transistor 1220 circuits 1223 Oxide semiconductor layer 1700 Substrate to be coated 1701 Chamber 1702 Road Room 1703 Pre-treatment room 1704 Chamber 1705 Chamber 1706 Unloading Room 1711a Raw material supply section 1711b Raw material supply section 1712a High Speed ​​Valve 1712b High Speed ​​Valve 1713a Raw material inlet 1713b Raw material inlet 1714 Raw material discharge port 1715 Exhaust system 1716 PCB holder 1720 Transport Room 1750 Interposer 1751 chips 1752 terminal 1753 Molding resin 1800 panels 1801 Printed wiring board 1802 Package 1803 FPC 1804 battery 2100 transistors 2200 transistors 2201 Insulator 2202 Wiring 2203 Plug 2204 Insulator 2205 Wiring 2207 Insulators 2210 Middle Class 2211 Semiconductor substrate 2212 Insulator 2213 Gate electrode 2214 Gate insulator 2215 Drain Region 3001 Wiring 3002 Wiring 3003 Wiring 3004 Wiring 3005 Wiring 3200 transistors 3300 transistors 3400 Capacitor 4000 RF tags 5100 pellets 5120 board 5161 area 6000 Display Module 6001 Top cover 6002 Lower cover 6003 FPC 6004 Touch Panel 6005 FPC 6006 Display Panel 6007 Backlight Unit 6008 Light source 6009 Frame 6010 printed circuit board 6011 Battery 7101 Housing 7102 Housing 7103 Display section 7104 Display section 7105 Microphone 7106 Speaker 7107 Operation key 7108 Stylus 7302 Housing 7304 Display section 7311 Operation button 7312 Operation button 7313 Connection terminal 7321 Band 7322 Gold 7501 Case 7502 Display section 7503 Operation button 7504 External connection port 7505 Speaker 7506 Microphone 7701 Housing 7702 Case 7703 Display section 7704 Operation key 7705 Lens 7706 Connection 7901 Electric pole 7902 Display section 8000 Camera 8001 Case 8002 Display section 8003 Operation button 8004 Shutter button 8005 Joint 8006 Lens 8100 Finder 8101 Housing 8102 Display section 8103 Button 8121 Housing 8122 Display section 8123 keyboard 8124 pointing device 8200 Head Mounted Display 8201 Mounting part 8202 Lens 8203 Main unit 8204 Display section 8205 Cable 8206 Battery 9700 Automobiles 9701 Body 9702 wheels 9703 Dashboard 9704 Light 9710 Display section 9711 Display section 9712 Display section 9713 Display section 9714 Display section 9715 Display section 9721 Display section 9722 Display section 9723 Display section

Claims

1. A first transistor having silicon in a channel formation region; a second transistor including an oxide semiconductor in a channel formation region and having a first gate and a second gate; a capacitance element; a gate of the first transistor, one of a source and a drain of the second transistor, and one electrode of the capacitor element are electrically connected to each other; a first conductive layer having a region located above a channel formation region of the first transistor and functioning as a gate of the first transistor; a first insulating layer having a region located above the first conductive layer; a second conductive layer having a region located above the first insulating layer and functioning as the second gate of the second transistor; an oxide semiconductor layer having a region located above the second conductive layer and including a channel formation region of the second transistor; a second insulating layer having a region located above the oxide semiconductor layer; a third conductive layer having a region in contact with a top surface of the second insulating layer and a region overlapping with the oxide semiconductor layer and having a function of supplying a potential to the first gate of the second transistor; a fourth conductive layer having a region in contact with an upper surface of the second insulating layer and electrically connected to one of the source and drain of the second transistor; a third insulating layer having a region located above the third conductive layer and a region located above the fourth conductive layer; a fifth conductive layer having a region located above the third insulating layer and functioning as one electrode of the capacitor; a sixth conductive layer having a region located above the fifth conductive layer and functioning as the other electrode of the capacitor element; The fifth conductive layer is electrically connected to the first conductive layer via the fourth conductive layer.

2. A first transistor having silicon in a channel formation region; a second transistor including an oxide semiconductor in a channel formation region and having a first gate and a second gate; a capacitance element; a gate of the first transistor, one of a source and a drain of the second transistor, and one electrode of the capacitor element are electrically connected to each other; a first conductive layer having a region located above a channel formation region of the first transistor and functioning as a gate of the first transistor; a first insulating layer having a region located above the first conductive layer; a second conductive layer having a region located above the first insulating layer and functioning as the second gate of the second transistor; an oxide semiconductor layer having a region located above the second conductive layer and including a channel formation region of the second transistor; a second insulating layer having a region located above the oxide semiconductor layer; a third conductive layer having a region in contact with a top surface of the second insulating layer and a region overlapping with the oxide semiconductor layer and having a function of supplying a potential to the first gate of the second transistor; a fourth conductive layer having a region in contact with an upper surface of the second insulating layer and electrically connected to one of the source and drain of the second transistor; a third insulating layer having a region located above the third conductive layer and a region located above the fourth conductive layer; a fifth conductive layer having a region located above the third insulating layer and functioning as one electrode of the capacitor; a sixth conductive layer having a region located above the fifth conductive layer and functioning as the other electrode of the capacitor element; the fifth conductive layer is electrically connected to the first conductive layer via the fourth conductive layer; the sixth conductive layer has a region overlapping with a channel formation region of the first transistor and a region overlapping with a channel formation region of the second transistor.

Images