Switching element

Abstract

This invention suppresses concentration of current in the vicinity of respective connecting regions. Provided is a switching element, wherein, when a semiconductor substrate is viewed from above, connecting regions connecting a body region and a deep region constitute a plurality of columns arrayed rectilinearly along a second direction. Intersecting parts between an inter-trench semiconductor layer and the columns include connecting intersecting parts where the connecting regions are provided, and non-connecting intersecting parts where no connecting region is provided. A standard number of non-connecting intersecting parts are arranged in intervals between neighboring connecting intersecting parts. The standard number is 5, 6, or 7. If the Chebyshev distance is counted in units of intersecting parts, then the Chebyshev distance to the connecting intersecting parts is 1 in each of the non-connecting intersecting parts.

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application is a related application of Japanese Patent Application No. 2023-023477, filed on February 17, 2023, and claims priority based on this Japanese patent application, the entire contents of which are incorporated herein by reference.

[0002] The technology disclosed in this specification relates to a switching element.

[0003] Japanese Patent Publication No. 2022-083790 (hereinafter referred to as Patent Document 1) discloses a trench gate type switching element. In this switching element, multiple p-type deep layers are provided inside an n-type drift layer. In the thickness direction of the semiconductor substrate, each deep layer is located below the lower end of the trench. Note that, in the thickness direction of the semiconductor substrate, each deep layer may be located in a range that includes the lower end of the trench. Furthermore, the switching element of Patent Document 1 has multiple p-type connection regions. Each connection region connects each deep layer to a p-type body layer. By providing the deep layers and connection regions in this way, it is possible to suppress the electric field applied to the gate insulating film covering the lower end of the trench.

[0004] In Patent Document 1, when the semiconductor substrate is viewed from above, the connection regions are dispersed and arranged so as to maintain a predetermined interval in the x and y directions. In other words, when the semiconductor substrate is viewed from above, the connection regions are dispersed and arranged so that the density of the connection regions is low.

[0005] Inside the switching element, a diode (known as a body diode) is formed at the interface between the p-type body layer and the n-type drift layer. When the voltage applied to the body diode switches from the forward direction to the reverse direction, a recovery current flows through the switching element, causing a recovery surge. If the density of the connection region is low, as in Patent Document 1, the recovery surge can be suppressed. Summary of the Invention

[0006] During operation of a switching element, a recovery current or an avalanche current may flow from the drift region to each connection region. In the switching element of Patent Document 1, when a recovery current or an avalanche current flows through the drift region, the current tends to concentrate near each connection region. This specification proposes a technology for suppressing current concentration near each connection region in a switching element in which multiple connection regions are distributed.

[0007] The first switching element disclosed in this specification includes a semiconductor substrate, a gate insulating film, a gate electrode, and a source electrode. A plurality of trenches are provided on the upper surface of the semiconductor substrate, each extending linearly in a first direction on the upper surface of the semiconductor substrate and spaced apart in a second direction intersecting the first direction on the upper surface of the semiconductor substrate. The gate insulating film covers the inner surface of each trench. The gate electrode is disposed in each trench and insulated from the semiconductor substrate by the gate insulating film. The source electrode is in contact with the upper surface of the semiconductor substrate. The semiconductor substrate includes a plurality of inter-trench semiconductor layers sandwiched between the plurality of trenches. Each inter-trench semiconductor layer includes an n-type source region in contact with the gate insulating film and the source electrode, and a p-type body region below the source region in contact with the gate insulating film. The semiconductor substrate includes a drift region, a plurality of deep regions, and a plurality of connection regions. The drift region is distributed across the lower portions of the plurality of inter-trench semiconductor layers and is an n-type region in contact with the gate insulating film below the body region in each inter-trench semiconductor layer. The plurality of deep regions are arranged in an area surrounded by the drift region, spaced apart from the body region and located lower than the body region, and are p-type regions located in an area including the lower end of the trench in the thickness direction of the semiconductor substrate or located lower than the lower end of the trench. The plurality of connection regions are p-type regions connecting the body region and the deep region. When viewed from above, the semiconductor substrate is configured such that a plurality of columns of the connection regions are linearly arranged at intervals along the second direction, and the columns are arranged at intervals in the first direction. When viewed from above, the semiconductor substrate has intersections between the plurality of inter-trench semiconductor layers and the columns, each of which has a connection intersection where the connection region is provided and a non-connection intersection where the connection region is not provided. In the first direction and the second direction, the connection intersections and the non-connection intersections are repeatedly arranged according to a reference pattern.Within a range in which the connection intersections and the non-connection intersections are repeatedly arranged according to the reference pattern, the connection intersections and the non-connection intersections satisfy the following conditions: In each of the inter-trench semiconductor layers, the connection intersections are arranged in the first direction with a reference number of the non-connection intersections arranged in the spaces between adjacent connection intersections. In the row, the connection intersections are arranged in the second direction with the reference number of the non-connection intersections arranged in the spaces between adjacent connection intersections. The reference number is 5, 6, or 7. When the Chebyshev distance is counted in units of the intersections, the Chebyshev distance to the connection intersection at each non-connection intersection is 1.

[0008] In a switching element, if a non-connection intersection exists that is extremely far from the connection intersection, recovery current and avalanche current are unlikely to flow near the non-connection intersection that is extremely far from the connection intersection. In this case, the density of recovery current and avalanche current increases near the connection region. In contrast, in the first switching element disclosed in this specification, within the area where connection intersections and non-connection intersections are repeatedly arranged according to the reference pattern, the Chebyshev distance from each non-connection intersection to the connection intersection is 1. In other words, there are no non-connection intersections that are extremely far from the connection intersection. Therefore, in this switching element, current concentration near each connection region is suppressed.

[0009] The second switching element disclosed in this specification includes a semiconductor substrate, a gate insulating film, a gate electrode, and a source electrode. A plurality of trenches are provided on the upper surface of the semiconductor substrate, each extending linearly in a first direction on the upper surface of the semiconductor substrate and spaced apart in a second direction intersecting the first direction on the upper surface of the semiconductor substrate. The gate insulating film covers the inner surface of each trench. The gate electrode is disposed in each trench and insulated from the semiconductor substrate by the gate insulating film. The source electrode is in contact with the upper surface of the semiconductor substrate. The semiconductor substrate includes a plurality of inter-trench semiconductor layers sandwiched between the plurality of trenches. Each inter-trench semiconductor layer includes an n-type source region in contact with the gate insulating film and the source electrode, and a p-type body region below the source region in contact with the gate insulating film. The semiconductor substrate includes a drift region, a plurality of deep regions, and a plurality of connection regions. The drift region is distributed across the lower portions of the plurality of inter-trench semiconductor layers and is an n-type region in contact with the gate insulating film below the body region in each inter-trench semiconductor layer. The plurality of deep regions are arranged in an area surrounded by the drift region, spaced apart from the body region and located lower than the body region, and are p-type regions located in an area including the lower end of the trench in the thickness direction of the semiconductor substrate or located lower than the lower end of the trench. The plurality of connection regions are p-type regions connecting the body region and the deep region. When viewed from above, the semiconductor substrate is configured such that the connection regions are linearly arranged in a plurality of rows spaced apart along the second direction, and the rows are spaced apart in the first direction. When viewed from above, the semiconductor substrate has intersections between the plurality of inter-trench semiconductor layers and the rows, each of which has a connection intersection where the connection region is provided and a non-connection intersection where the connection region is not provided. The connection intersections and the non-connection intersections are repeatedly arranged according to a reference pattern in the first and second directions. The reference pattern is a pattern in which five of the connection intersections and five of the non-connection intersections are arranged in a first direction and five of the non-connection intersections are arranged in a second direction.When the position of each intersection in the reference pattern is expressed by coordinates in the first and second directions, the reference pattern is a pattern in which the connecting intersections are located at positions (1,1), (2,4), (3,3), (4,2), and (5,5) and the non-connecting intersections are located at other positions, or a pattern equivalent thereto.

[0010] The above-mentioned "equivalent pattern" is a pattern obtained by flipping or sliding vertically or horizontally a "pattern in which the connecting intersections are located at positions (1,1), (2,4), (3,3), (4,2), and (5,5) and the non-connecting intersections are located at other positions."

[0011] In the second switching element disclosed in this specification, current concentration in the vicinity of each connection region is suppressed. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is a perspective view including a vertical cross section along the x direction and the y direction of a switching element according to a first embodiment. [Figure 2] 7 is a cross-sectional view showing a vertical cross section along the y direction at a position including a deep region of the switching element of the first embodiment (the position of line II-II in FIG. 6). [Figure 3] 7 is a cross-sectional view showing a vertical cross section along the y direction at a position (position of line III-III in FIG. 6) that does not include a deep region of the switching element of the first embodiment. [Figure 4] 7 is a cross-sectional view showing a vertical cross section along the x direction at a position (position of line IV-IV in FIG. 6) that does not include the trench of the switching element of Example 1. FIG. [Figure 5] 7 is a cross-sectional view showing a vertical cross section along the x direction at a position including a trench of the switching element of the first embodiment (the position of line VV in FIG. 6). FIG. [Figure 6] FIG. 2 is a plan view showing the arrangement of connection intersections and non-connection intersections of the switching element of the first embodiment. [Figure 7] FIG. 2 is a diagram showing a reference pattern P. [Figure 8]FIG. 10 is a diagram showing a plurality of reference patterns P arranged adjacent to each other. [Figure 9] FIG. 10 is a diagram showing an arrangement pattern of a comparative example. [Figure 10] FIG. 10 is a perspective view including a vertical cross section along the x direction and the y direction of a switching element according to a first modified example. [Figure 11] FIG. 10 is a perspective view including a vertical cross section along the x direction and the y direction of a switching element according to a second embodiment. [Figure 12] FIG. 10 is a plan view showing the arrangement of connection intersections and non-connection intersections of a switching element according to a second embodiment. [Figure 13] FIG. 11 is a perspective view including a vertical cross section along the x direction and the y direction of a switching element according to a third embodiment. [Figure 14] FIG. 11 is a plan view showing the arrangement of connection intersections and non-connection intersections of a switching element according to a third embodiment. [Figure 15] FIG. 10 is a perspective view including a vertical cross section along the x direction and the y direction of a switching element according to a fourth embodiment. [Figure 16] FIG. 10 is a plan view showing the arrangement of connection intersections and non-connection intersections of a switching element according to a fourth embodiment. [Figure 17] FIG. 10 is a perspective view including a vertical cross section along the x direction and the y direction of a switching element according to a second modified example. [Figure 18] FIG. 10 is a diagram showing a reference pattern Q when the reference number is 6. [Figure 19] FIG. 10 is a diagram showing a reference pattern R when the reference number is 7. [Figure 20] FIG. 10 is a diagram showing a reference pattern S when the reference number is 4. DETAILED DESCRIPTION OF THE INVENTION

[0013] In one example configuration of the first switching element, the deep regions may extend linearly along the second direction and be spaced apart in the first direction so that each deep region extends along the corresponding column when the semiconductor substrate is viewed from above.

[0014] In one example of the configuration of the first switching element, each of the connection regions may be in contact with the gate insulating film on a side surface of the trench located on both sides thereof.

[0015] In this configuration, the inversion layer formed in the body layer at the intersection where each connection region exists does not function as a channel. According to the configuration disclosed in this specification, the connection regions can be distributed, so that intersections that do not function as channels can be distributed. Therefore, the main current that flows when the switching element is on can be distributed within the semiconductor substrate.

[0016] In one example of the configuration of the first switching element, a p-type contact region that connects the body region and the source electrode may be provided above each of the connection regions. [Example]

[0017] The switching element 10 of the first embodiment shown in FIG. 1 includes a semiconductor substrate 12. The semiconductor substrate 12 is made of SiC. However, the semiconductor substrate 12 may be made of other semiconductors such as Si or GaN. Hereinafter, a direction parallel to the upper surface 12a of the semiconductor substrate 12 is referred to as the x-direction, a direction parallel to the upper surface 12a and perpendicular to the x-direction is referred to as the y-direction, and the thickness direction of the semiconductor substrate 12 is referred to as the z-direction. The upper surface 12a of the semiconductor substrate 12 is provided with a plurality of trenches 14. Each trench 14 extends linearly in the x-direction on the upper surface 12a. The trenches 14 are spaced apart in the y-direction on the upper surface 12a. The inner surface of each trench 14 is covered with a gate insulating film 16. A gate electrode 18 is disposed in each trench 14. Each gate electrode 18 is insulated from the semiconductor substrate 12 by the gate insulating film 16. An interlayer insulating film 20 is disposed in each trench 14. Each interlayer insulating film 20 covers the upper surface of the gate electrode 18.

[0018] As shown in Figures 2 to 5, a source electrode 22 is provided on the upper part of the semiconductor substrate 12. Note that the source electrode 22 is not shown in Figure 1. The source electrode 22 covers the upper surface of the interlayer insulating film 20 and the upper surface 12a of the semiconductor substrate 12. The source electrode 22 is insulated from the gate electrode 18 by the interlayer insulating film 20. A drain electrode 24 is provided on the lower part of the semiconductor substrate 12. The drain electrode 24 covers the lower surface 12b of the semiconductor substrate 12.

[0019] FIG. 6 shows the upper surface 12a of the semiconductor substrate 12. As described above, on the upper surface 12a, a plurality of trenches 14 extending linearly in the x direction are arranged at intervals in the y direction. Furthermore, the inter-trench semiconductor layer 30 shown in FIG. 6 represents a semiconductor layer sandwiched between two trenches 14 (i.e., a semiconductor layer arranged between two trenches 14). Each inter-trench semiconductor layer 30 extends linearly in the x direction on the upper surface 12a. Each inter-trench semiconductor layer 30 is arranged at intervals in the y direction on the upper surface 12a.

[0020] As shown in FIG. 1, the semiconductor substrate 12 includes a source region 40, a body region 42, a drift region 44, and a drain region 46.

[0021] The source region 40 is an n-type region having a high n-type impurity concentration. The source region 40 is disposed in the inter-trench semiconductor layer 30. As shown in FIGS. 2 and 3 , the source region 40 contacts the source electrode 22 in the inter-trench semiconductor layer 30. The source region 40 contacts the gate insulating film 16 on the side surfaces of the trenches 14 provided on both sides of the inter-trench semiconductor layer 30.

[0022] The body region 42 is a p-type region having a low p-type impurity concentration. The body region 42 is disposed in the inter-trench semiconductor layer 30. As shown in FIGS. 2 and 3 , the body region 42 is disposed in the inter-trench semiconductor layer 30, and is disposed below the source region 40. The body region 42 contacts the gate insulating film 16 below the source region 40. That is, the body region 42 contacts the gate insulating film 16 on the side surfaces of the trenches 14 provided on both sides of the inter-trench semiconductor layer 30.

[0023] The drift region 44 is an n-type region having a low n-type impurity concentration. As shown in FIGS. 2 and 3 , the drift region 44 is distributed across the lower portions of multiple inter-trench semiconductor layers 30. As shown in FIG. 3 , the upper end of the drift region 44 extends into each inter-trench semiconductor layer 30. The drift region 44 contacts the body region 42 from below within each inter-trench semiconductor layer 30. The drift region 44 contacts the gate insulating film 16 below the body region 42. That is, the drift region 44 contacts the gate insulating film 16 on the side surfaces of the trenches 14 provided on both sides of each inter-trench semiconductor layer 30.

[0024] The drain region 46 is an n-type region having a high n-type impurity concentration. The n-type impurity concentration of the drain region 46 is higher than the n-type impurity concentration of the drift region 44. As shown in FIGS. 2 to 5, the drain region 46 contacts the drift region 44 from below. The drain region 46 contacts the drain electrode 24 on the lower surface 12b of the semiconductor substrate 12.

[0025] The semiconductor substrate 12 has multiple p-type deep regions 50. As shown in FIGS. 2 and 4, each deep region 50 is disposed within a range surrounded by a drift region 44. Each deep region 50 is disposed below the body region 42 with a gap therebetween. The drift region 44 is distributed in the gap between each deep region 50 and the body region 42. In FIG. 6, the hatched area indicates the distribution range of the deep regions 50. As shown in FIG. 6, when the semiconductor substrate 12 is viewed from above, each deep region 50 extends linearly in the y direction. When the semiconductor substrate 12 is viewed from above, each deep region 50 is disposed with a gap therebetween in the x direction. As shown in FIGS. 1, 2, and 5, each deep region 50 is disposed within a range including the lower end of the trench 14 in the z direction. Therefore, each deep region 50 contacts the gate insulating film 16 at the lower end of each trench 14.

[0026] As shown in FIG. 1, the semiconductor substrate 12 has a plurality of connection regions 52 and a plurality of contact regions 54. As shown in FIGS. 1, 2, and 4, the connection region 52 is a p-type region that connects the body region 42 and the deep region 50. The contact region 54 is a p-type region that connects the body region 42 and the source electrode 22. That is, the contact region 54 extends upward from the body region 42 and contacts the source electrode 22 at its upper end. In this embodiment, the contact region 54 and the connection region 52 extend continuously in the z-direction. That is, the contact region 54 is located above the connection region 52. The semiconductor substrate 12 has a plurality of sets of the contact region 54 and the deep region 50. Each deep region 50 is connected to the source electrode 22 via the connection region 52 and the contact region 54.

[0027] In FIG. 6, the hatched area indicates a set of connection regions 52 and contact regions 54. The set of connection regions 52 and contact regions 54 is partially provided above the deep region 50. When the semiconductor substrate 12 is viewed from above as shown in FIG. 6, the multiple connection regions 52 are arranged to form multiple rows 53 that extend linearly in the y direction. In FIG. 6, the rows 53 extending in the y direction overlap with the deep region 50. The multiple rows 53 are arranged at intervals in the x direction.

[0028] The intersections 60 shown in FIG. 6 are portions where the inter-trench semiconductor layers 30 intersect with the columns 53 when the semiconductor substrate 12 is viewed from above. As described above, each inter-trench semiconductor layer 30 extends linearly in the x direction, and each column 53 extends linearly in the y direction. Therefore, when the semiconductor substrate 12 is viewed from above, a plurality of intersections 60 are arranged in a matrix along the x and y directions. As shown in FIG. 6, a set of a connection region 52 and a contact region 54 is provided at some of the plurality of intersections 60. As shown in FIGS. 1, 2, and 6, each connection region 52 contacts the gate insulating film 16 on the side surfaces of the trenches 14 located on both sides of the intersection 60. Furthermore, the contact regions 54 contact the gate insulating film 16 on the side surfaces of the trenches 14 located on both sides of the intersection 60. Hereinafter, an intersection 60 provided with a connection region 52 will be referred to as a connection intersection 60a, and an intersection 60 without a connection region 52 will be referred to as a non-connection intersection 60b.

[0029] The reference pattern P in FIG. 6 shows an arrangement pattern of connection intersections 60a and non-connection intersections 60b. The connection intersections 60a and non-connection intersections 60b are arranged so that the reference pattern P is repeated in the x and y directions. FIG. 7 also shows a schematic diagram of the reference pattern P. Each cell in FIG. 7 represents an intersection 60. In FIG. 7, the hatched cells represent connection intersections 60a, and the blank cells represent non-connection intersections 60b. FIG. 8 also shows a plurality of reference patterns P arranged in a matrix in the x and y directions. In FIG. 8, the central reference pattern P is indicated by reference symbol P1, and the surrounding reference patterns P are indicated by reference symbols P2 to P9. The reference pattern P is set so as to satisfy the following conditions 1 to 3 within the range in which the connection intersections 60a and non-connection intersections 60b are repeatedly arranged according to the reference pattern P.

[0030] (Condition 1) In each inter-trench semiconductor layer 30, the connection intersections 60a are arranged at regular intervals in the x direction, and five non-connection intersections 60b are arranged within each interval. That is, as shown in Figures 7 and 8, in any inter-trench semiconductor layer 30, the connection intersections 60a are arranged at intervals in the x direction so that one connection intersection 60a appears for every five non-connection intersections 60b.

[0031] (Condition 2) In each column 53, the connecting intersections 60a are arranged at regular intervals in the y direction, and five non-connecting intersections 60b are arranged within each interval. That is, as shown in Figures 7 and 8, in each column 53, the connecting intersections 60a are arranged at intervals in the y direction so that one connecting intersection 60a appears for every five non-connecting intersections 60b.

[0032] (Condition 3) Within the range in which the reference pattern P continues, the Chebychev distance from each non-connection intersection 60b to the connection intersection 60a (more specifically, to the nearest connection intersection 60a) is 1 for every non-connection intersection 60b.

[0033] The Chebyshev distance referred to here is a value counted for each intersection 60. For example, in FIG. 8, non-connection intersection 60b-1 is adjacent to connection intersection 60a in the y direction, so the Chebyshev distance of non-connection intersection 60b-1 to connection intersection 60a is 1. Also, in FIG. 8, non-connection intersection 60b-2 is adjacent to connection intersection 60a in the x direction, so the Chebyshev distance of non-connection intersection 60b-2 to connection intersection 60a is 1. In FIG. 8, non-connection intersection 60b-3 is diagonally adjacent to connection intersection 60a, so the Chebyshev distance of non-connection intersection 60b-3 to connection intersection 60a is 1. In FIG. 8, the non-connection intersection 60b-4 is adjacent to the connection intersection 60a of the adjacent reference patterns P3 and P5, so the Chebyshev distance of the non-connection intersection 60b-4 to the connection intersection 60a is 1. In FIG. 8, the non-connection intersection 60b-5 is diagonally adjacent to the connection intersection 60a of the adjacent reference pattern P5, so the Chebyshev distance of the non-connection intersection 60b-5 to the connection intersection 60a is also 1. All of the non-connection intersections 60b in the central reference pattern P1 shown in FIG. 8 have a Chebyshev distance of 1 to the connection intersection 60a. Thus, within the range in which the reference patterns P are continuous, all of the non-connection intersections 60b in the reference pattern P have a Chebyshev distance of 1 to the connection intersection 60a.

[0034] In the following, the position of each cell in the reference pattern P in FIG. 7 is represented by coordinates (x, y). In FIG. 7, the leftmost column 53 is represented by x=1, and the rightmost column 53 is represented by x=6. In FIG. 7, the bottommost row is represented by y=1, and the topmost row is represented by y=6. In the reference pattern P, the cells with coordinates (1, 6), (2, 4), (3, 2), (4, 5), (5, 3), and (6, 1) are connected intersections 60a, and the other cells are unconnected intersections 60b. By following this reference pattern P, the Chebyshev distance of each unconnected intersection 60b within a range where the reference pattern P is continuous can be set to 1.

[0035] The switching element 10 of the first embodiment is a so-called MOSFET (metal-oxide-semiconductor field effect transistor). Under normal circumstances, a higher potential is applied to the drain electrode 24 than to the source electrode 22. When a potential higher than the gate threshold is applied to the gate electrode 18, an inversion layer is formed in the body region 42, and the inversion layer connects the source region 40 and the drift region 44. This turns on the switching element 10, and current flows from the drain electrode 24 to the source electrode 22. Note that at the connection intersections 60a, the contact regions 54 and the connection regions 52 are provided above and below the body region 42, so almost no current flows through the connection intersections 60a. At the non-connection intersections 60b, current flows through the inversion layer. In the switching element 10 of the first embodiment, only some of the multiple intersections 60 are connection intersections 60a, and the remaining intersections 60 are non-connection intersections 60b. Because the number of connection intersections 60a is small, current can flow densely through the semiconductor substrate 12 when the switching element 10 is turned on. Therefore, the on-resistance of the switching element 10 is low.

[0036] When the potential of the gate electrode 18 is reduced to a potential lower than the gate threshold, the switching element 10 is turned off, and the current stops. When the switching element 10 is turned off, a reverse voltage is applied to the pn junction at the interface between the body region 42 and the drift region 44, causing a depletion layer to extend from the body region 42 to the drift region 44. Furthermore, because the deep region 50 is connected to the body region 42 by the connection region 52, the potential of the deep region 50 is approximately equal to the potential of the body region 42. Therefore, a reverse voltage is applied to the pn junction at the interface between the deep region 50 and the drift region 44, causing a depletion layer to extend from the deep region 50 to the drift region 44. The depletion layer extending from the deep region 50 prevents a high electric field from being applied to the gate insulating film 16 at the bottom end of each trench 14.

[0037] A higher potential may be applied to the source electrode 22 than to the drain electrode 24. In this case, a diode (known as a body diode) formed by the pn junction at the interface between the body region 42 and the drift region 44 turns on, causing a current to flow from the source electrode 22 to the drain electrode 24. When the body diode is on, holes flow from the body region 42 to the drift region 44, resulting in a large number of holes in the drift region 44. When the potential of the drain electrode 24 subsequently becomes higher than the potential of the source electrode 22, the body diode turns off. As a result, the holes in the drift region 44 flow into the deep region 50, as indicated by arrow 100 in FIG. 2 . The holes that flow from the drift region 44 to the deep region 50 then flow to the source electrode 22 via the connection region 52 and the contact region 54. The current generated when the body diode turns off is called a recovery current. As shown in FIG. 2 , a recovery current is more likely to flow to the drift region 44 at the connection intersection 60a where the connection region 52 is provided than at the non-connection intersection 60b where the connection region 52 is not provided.

[0038] Furthermore, an overvoltage may be applied to the switching element 10 in a direction in which the drain electrode 24 has a higher potential than the source electrode 22. In this case, an avalanche current is generated in the drift region 44. The avalanche current flows to the deep region 50 as indicated by arrow 100 in FIG. 2. The avalanche current that flows from the drift region 44 to the deep region 50 flows to the source electrode 22 via the connection region 52 and the contact region 54. As shown in FIG. 2, avalanche current is more likely to flow to the drift region 44 at the connection intersection 60a where the connection region 52 is provided than at the non-connection intersection 60b where the connection region 52 is not provided.

[0039] As described above, at the connection intersection 60a, the recovery current and the avalanche current flow more easily in the drift region 44 than at the non-connection intersection 60b. At the non-connection intersection 60b, the recovery current and the avalanche current flow less easily the farther the distance to the connection intersection 60a is.

[0040] FIG. 9 shows the layout pattern of the connection intersections 60a and non-connection intersections 60b of the switching element of the comparative example. In the layout pattern shown in FIG. 9, the Chebyshev distance from the non-connection intersection 60b-6 to the connection intersection 60a is 2. As such, recovery current and avalanche current are unlikely to flow through the non-connection intersection 60b-6, which has a long Chebyshev distance to the connection intersection 60a. Therefore, in the layout pattern of FIG. 9, recovery current and avalanche current are likely to concentrate at the connection intersection 60a. Therefore, the switching element of the comparative example has low recovery and avalanche resistance. In contrast, in the switching element 10 of the first embodiment, as shown in FIG. 8, the Chebyshev distance from the connection intersection 60a to all non-connection intersections 60b within the range where the reference pattern P is continuous is 1. Therefore, in the switching element 10 of the first embodiment, recovery current and avalanche current are unlikely to concentrate at the connection intersection 60a. Therefore, the switching element 10 of Example 1 has high recovery resistance and avalanche resistance. Therefore, the structure of the switching element 10 of Example 1 can achieve higher reliability.

[0041] 10, a gap may be provided between the connection region 52 and the gate insulating film 16, with the drift region 44 distributed within that gap. Also, as shown in FIG. 10, a gap may be provided between the contact region 54 and the gate insulating film 16, with the source region 40 provided within that gap. With this configuration, when the switching element is turned on, a current also flows through the connection intersection 60a. Therefore, the on-resistance of the switching element can be further reduced. [Example]

[0042] 11 and 12 show a switching element 200 according to a second embodiment. In the second embodiment, each deep region 50 extends linearly in the x direction. The deep regions 50 are arranged at intervals in the y direction. Each deep region 50 is arranged below the center of the inter-trench semiconductor layer 30 in the y direction.

[0043] Each deep region 50 is connected to the source electrode 22 via a connection region 52 and a contact region 54. As shown in Fig. 12, the connection regions 52 are arranged to form multiple rows 53 that extend linearly in the y direction. The multiple rows 53 are arranged at intervals in the x direction.

[0044] As shown in FIG. 12, a set of a connection region 52 and a contact region 54 is provided at some of the multiple intersections 60. As in the first embodiment, the connection intersections 60a and the non-connection intersections 60b are arranged according to the same reference pattern P as in FIGS. 7 and 8. That is, the connection intersections 60a and the non-connection intersections 60b are arranged so as to satisfy the above-mentioned conditions 1 to 3. Therefore, in the second embodiment, within the range where the reference pattern P is continuous, there is no non-connection intersection 60b whose Chebyshev distance to the connection intersection 60a is 2 or more. Therefore, in the switching element 200 of the second embodiment, recovery current and avalanche current are unlikely to concentrate at the connection intersections 60a. The structure of the switching element of the second embodiment can achieve high reliability.

[0045] 10, the drift region 44 may be distributed between the connection region 52 and the gate insulating film 16. Also, the source region 40 may be provided between the contact region 54 and the gate insulating film 16, similar to FIG. [Example]

[0046] 13 and 14 show a switching element 300 according to a third embodiment. In the third embodiment, each deep region 50 extends linearly in the x direction. The deep regions 50 are spaced apart in the y direction. Each deep region 50 is disposed in the lower portion of a trench 14.

[0047] Each deep region 50 is connected to the source electrode 22 via a connection region 52 and a contact region 54. As shown in Fig. 14, the connection regions 52 are arranged to form multiple rows 53 that extend linearly in the y direction. The multiple rows 53 are arranged at intervals in the x direction.

[0048] As shown in FIG. 14, a set of a connection region 52 and a contact region 54 is provided at some of the multiple intersections 60. As in the first embodiment, the connection intersections 60a and the non-connection intersections 60b are arranged according to the same reference pattern P as in FIGS. 7 and 8. That is, the connection intersections 60a and the non-connection intersections 60b are arranged so as to satisfy the above-mentioned conditions 1 to 3. Therefore, in the third embodiment, within the range where the reference pattern P is continuous, there is no non-connection intersection 60b whose Chebyshev distance to the connection intersection 60a is 2 or more. Therefore, in the switching element 300 of the third embodiment, recovery current and avalanche current are unlikely to concentrate at the connection intersections 60a. The structure of the switching element of the third embodiment can achieve high reliability. [Example]

[0049] 15 and 16 show a switching element 400 of Example 4. The switching element 400 of Example 4 has two types of deep regions 50x and 50y. Each deep region 50y extends linearly in the y direction. The multiple deep regions 50y are arranged at intervals in the x direction. Each deep region 50y is arranged at a depth that includes the lower end of the trench 14. Each deep region 50x is arranged below each deep region 50y. Each deep region 50x extends linearly in the x direction. The multiple deep regions 50x are arranged at intervals in the y direction. The upper end of each deep region 50x is arranged at a depth that overlaps the lower end of each deep region 50y. Each deep region 50x and each deep region 50y are connected to each other at their intersections.

[0050] Each deep region 50y is connected to the source electrode 22 via a connection region 52 and a contact region 54. As shown in FIG. 16, the connection regions 52 are arranged to form multiple rows 53 that extend linearly in the y direction. In FIG. 16, the rows 53 extending in the y direction overlap with the deep regions 50y. The multiple rows 53 are arranged at intervals in the x direction.

[0051] As shown in FIG. 16, a set of a connection region 52 and a contact region 54 is provided at some of the multiple intersections 60. As in the first embodiment, the connection intersections 60a and the non-connection intersections 60b are arranged according to the same reference pattern P as in FIGS. 7 and 8. That is, the connection intersections 60a and the non-connection intersections 60b are arranged so as to satisfy the above-mentioned conditions 1 to 3. Therefore, in the fourth embodiment, within the range where the reference pattern P is continuous, there is no non-connection intersection 60b whose Chebyshev distance to the connection intersection 60a is 2 or more. Therefore, in the switching element 400 of the fourth embodiment, recovery current and avalanche current are unlikely to concentrate at the connection intersections 60a. The structure of the switching element of the fourth embodiment can achieve high reliability.

[0052] In addition, in Example 4, the deep regions 50x and 50y extend along the x and y directions. Therefore, the deep regions 50x and 50y in each unconnected intersection 60b are connected to the connection region 52 by a current path whose Chebyshev distance is within 1. In this way, the deep regions 50x and 50y in each unconnected intersection 60b are connected to the connection region 52 by a short current path, so that the potentials of the deep regions 50x and 50y can be stabilized.

[0053] In the fourth embodiment, the deep region 50y is disposed above the deep region 50x. However, the deep region 50x may be disposed above the deep region 50y. Furthermore, the deep region 50x and the deep region 50y may be disposed at the same depth.

[0054] In the above-described first to fourth embodiments, each deep region 50 is disposed at a depth that includes the lower end of the trench 14. However, each deep region 50 may be disposed below the lower end of the trench 14. For example, in the first embodiment, each deep region 50 may be disposed below the lower end of the trench 14, as shown in FIG.

[0055] In addition, in the above-described Examples 1 to 4, the contact regions 54 are provided above the connection regions 52. However, the positions of the connection regions 52 and the contact regions 54 may be shifted in the x direction. Also, the number of connection regions 52 and the number of contact regions 54 may be different.

[0056] In the above-described first to fourth embodiments, the connection intersections 60a and the non-connection intersections 60b are arranged according to the reference pattern P shown in Figures 7 and 8. However, the connection intersections 60a and the non-connection intersections 60b may be arranged in any manner as long as they follow a reference pattern that satisfies the above-described conditions 1 to 3. For example, a reference pattern obtained by shifting the reference pattern P shown in Figures 7 and 8 in the x and y directions may be used, a reference pattern obtained by rotating the reference pattern P by 90 degrees or 180 degrees to the right or left may be used, or a reference pattern obtained by flipping the reference pattern P vertically or horizontally may be used.

[0057] In the above-described Examples 1 to 4, five non-connection intersections 60b were arranged in the spaces between the connection intersections 60a in the x and y directions. That is, the number of non-connection intersections 60b arranged in the spaces (i.e., the reference number) was 5. However, the reference number may be 6 or 7. That is, six or seven non-connection intersections 60b may be arranged in the spaces between the connection intersections 60a in the x and y directions. When the reference number is 6, the connection intersections 60a and the non-connection intersections 60b may be arranged according to the reference pattern Q shown in FIG. 18. In the reference pattern Q, the cells with coordinates (1,7), (2,5), (3,3), (4,1), (5,6), (6,4), and (7,2) are the connection intersections 60a, and the other cells are the non-connection intersections 60b. Within the range in which the reference pattern Q is repeated, the Chebyshev distance to the connection intersections 60a is 1 for all the non-connection intersections 60b in the reference pattern Q. When the reference number is 7, the connection intersections 60a and non-connection intersections 60b may be arranged according to the reference pattern R shown in FIG. 19. In the reference pattern R, the cells with coordinates (1,8), (2,3), (3,6), (4,1), (5,4), (6,7), (7,2), and (8,5) are the connection intersections 60a, and the other cells are the non-connection intersections 60b. Within the range where the reference pattern R is repeated, the Chebyshev distance to the connection intersections 60a for all the non-connection intersections 60b in the reference pattern R is 1. Furthermore, reference patterns obtained by shifting the reference patterns Q and R in the x and y directions may be used. Reference patterns obtained by rotating the reference patterns Q and R 90 degrees or 180 degrees to the right or left may be used. Reference patterns obtained by flipping the reference patterns Q and R vertically or horizontally may also be used.

[0058] The reference number may also be four. That is, four non-connection intersections 60b may be arranged at intervals between connection intersections 60a in the x and y directions. When the reference number is four, the connection intersections 60a and non-connection intersections 60b may be arranged according to the reference pattern S shown in FIG. 20. In the reference pattern S, the cells with coordinates (1,1), (2,4), (3,3), (4,2), and (5,5) are connection intersections 60a, and the other cells are non-connection intersections 60b. Within the range in which the reference pattern S is repeated, the Chebyshev distance to the connection intersections 60a for all non-connection intersections 60b in the reference pattern S is 1. Furthermore, a reference pattern obtained by shifting the reference pattern S in the x and y directions may be adopted, or a reference pattern obtained by rotating the reference pattern S 90 degrees or 180 degrees to the right or left may be adopted, or a reference pattern obtained by flipping the reference pattern S vertically or horizontally may be adopted.

[0059] The configurations of the techniques disclosed in this specification are listed below. (Configuration 1) A switching element, a semiconductor substrate having a plurality of trenches formed on an upper surface of the semiconductor substrate, each of the trenches extending linearly in a first direction on the upper surface of the semiconductor substrate, and each of the trenches being spaced apart in a second direction intersecting the first direction on the upper surface of the semiconductor substrate; a gate insulating film covering the inner surface of each trench; a gate electrode disposed in each of the trenches and insulated from the semiconductor substrate by the gate insulating film; a source electrode in contact with the top surface of the semiconductor substrate; and the semiconductor substrate has a plurality of inter-trench semiconductor layers sandwiched between a plurality of the trenches, Each inter-trench semiconductor layer is an n-type source region in contact with the gate insulating film and the source electrode; a p-type body region below the source region and in contact with the gate insulating film; and The semiconductor substrate is an n-type drift region that is distributed across lower portions of the plurality of inter-trench semiconductor layers and that is in contact with the gate insulating film below the body region in each inter-trench semiconductor layer; a plurality of p-type deep regions that are arranged in a range surrounded by the drift region, that are spaced apart from the body region and lower than the body region, and that are arranged in a range that includes a lower end of the trench or lower than the lower end of the trench in a thickness direction of the semiconductor substrate; a plurality of p-type connection regions connecting the body region and the deep region; and When the semiconductor substrate is viewed from above, the connection regions are arranged in a plurality of rows in a linear manner at intervals along the second direction, and the rows are arranged at intervals in the first direction, When the semiconductor substrate is viewed from above, intersections between a plurality of the inter-trench semiconductor layers and a plurality of the columns have connection intersections where the connection regions are provided and non-connection intersections where the connection regions are not provided, the connecting intersections and the non-connecting intersections are repeatedly arranged according to a reference pattern in the first direction and the second direction; Within a range in which the connection intersections and the non-connection intersections are repeatedly arranged according to the reference pattern, the connection intersections and the non-connection intersections satisfy the following condition, i.e., In each of the inter-trench semiconductor layers, the connection intersections are arranged in the first direction with a reference number of the non-connection intersections being arranged in the spaces between the adjacent connection intersections. In the row, the connection intersections are arranged in the second direction with the reference number of non-connection intersections being arranged in the spaces between adjacent connection intersections. the reference number is 5, 6 or 7; When counting the Chebyshev distance in units of the intersections, the Chebyshev distance to the connected intersection at each non-connected intersection is 1; Satisfy the condition that Switching element. (Configuration 2) A switching element as described in configuration 1, wherein multiple deep regions extend linearly along the second direction and are spaced apart in the first direction so that each deep region extends along a corresponding column when the semiconductor substrate is viewed from above. (Configuration 3) 3. The switching element according to configuration 1 or 2, wherein each of the connection regions is in contact with the gate insulating film on the side surfaces of the trench located on both sides thereof. (Configuration 4) 4. The switching element according to any one of configurations 1 to 3, wherein a p-type contact region that connects the body region and the source electrode is provided above each of the connection regions.

[0060] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The claimed technology includes various modifications and variations of the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings simultaneously achieves multiple objectives, and achieving one of these objectives itself has technical utility.

Claims

1. A switching element, A semiconductor substrate (12) having a plurality of trenches (14) formed on an upper surface of the semiconductor substrate, each of the trenches extending linearly in a first direction on the upper surface of the semiconductor substrate, and each of the trenches being spaced apart in a second direction on the upper surface of the semiconductor substrate that intersects with the first direction; a gate insulating film (16) covering the inner surface of each trench; a gate electrode (18) disposed in each of the trenches and insulated from the semiconductor substrate by the gate insulating film; a source electrode (22) in contact with the top surface of the semiconductor substrate; and The semiconductor substrate has a plurality of inter-trench semiconductor layers (30) sandwiched between a plurality of the trenches, Each inter-trench semiconductor layer is an n-type source region (40) in contact with the gate insulating film and the source electrode; a p-type body region (42) below the source region and in contact with the gate insulating film; and The semiconductor substrate is an n-type drift region (44) distributed across the lower portions of the plurality of inter-trench semiconductor layers and contacting the gate insulating film below the body region in each inter-trench semiconductor layer; a plurality of p-type deep regions (50) that are arranged in a range surrounded by the drift region, that are spaced apart from the body region and that are lower than the body region, and that are arranged in a range that includes a lower end of the trench in the thickness direction of the semiconductor substrate or that are lower than the lower end of the trench; a plurality of p-type connection regions (52) connecting the body region and the deep region; and When the semiconductor substrate is viewed from above, a plurality of rows (53) are configured in which the connection regions are linearly arranged at intervals along the second direction, and the plurality of rows are arranged at intervals in the first direction, When the semiconductor substrate is viewed from above, intersections (60) between a plurality of the inter-trench semiconductor layers and a plurality of the columns have connection intersections (60a) where the connection regions are provided and non-connection intersections (60b) where the connection regions are not provided, In the first direction and the second direction, the connection intersections and the non-connection intersections are repeatedly arranged according to a reference pattern (P), Within a range in which the connection intersections and the non-connection intersections are repeatedly arranged according to the reference pattern, the connection intersections and the non-connection intersections satisfy the following condition, i.e., In each of the inter-trench semiconductor layers, the connection intersections are arranged in the first direction with a reference number of the non-connection intersections disposed in the spaces between the adjacent connection intersections. In the row, the connection intersections are arranged in the second direction with the reference number of non-connection intersections being arranged in the spaces between adjacent connection intersections. - the reference number is 5, 6 or 7; When counting the Chebyshev distance in units of the intersections, at each non-connected intersection, the Chebyshev distance to the connected intersection is 1; Satisfy the condition that Switching element.

2. 2. The switching element of claim 1, wherein the deep regions extend linearly along the second direction and are spaced apart in the first direction so that each deep region extends along a corresponding column when the semiconductor substrate is viewed from above.

3. 3. The switching element according to claim 1, wherein each of the connection regions is in contact with the gate insulating film on the side surfaces of the trench located on both sides of the connection region.

4. 3. The switching element according to claim 1, wherein a p-type contact region that connects the body region and the source electrode is provided above each of the connection regions.

5. A switching element, a semiconductor substrate having a plurality of trenches formed on an upper surface of the semiconductor substrate, each of the trenches extending linearly in a first direction on the upper surface of the semiconductor substrate, and each of the trenches being spaced apart in a second direction intersecting the first direction on the upper surface of the semiconductor substrate; a gate insulating film covering the inner surface of each trench; a gate electrode disposed in each of the trenches and insulated from the semiconductor substrate by the gate insulating film; a source electrode in contact with the top surface of the semiconductor substrate; and the semiconductor substrate has a plurality of inter-trench semiconductor layers sandwiched between a plurality of the trenches, Each inter-trench semiconductor layer is an n-type source region in contact with the gate insulating film and the source electrode; a p-type body region below the source region and in contact with the gate insulating film; and The semiconductor substrate is an n-type drift region distributed across lower portions of the plurality of inter-trench semiconductor layers and in contact with the gate insulating film below the body region in each inter-trench semiconductor layer; a plurality of p-type deep regions that are arranged in a range surrounded by the drift region, that are spaced apart from the body region and lower than the body region, and that are arranged in a range that includes a lower end of the trench or lower than the lower end of the trench in a thickness direction of the semiconductor substrate; a plurality of p-type connection regions connecting the body region and the deep region; and When the semiconductor substrate is viewed from above, the connection regions are arranged in a plurality of rows in a linear manner at intervals along the second direction, and the rows are arranged at intervals in the first direction, When the semiconductor substrate is viewed from above, intersections between a plurality of the inter-trench semiconductor layers and a plurality of the columns have connection intersections where the connection regions are provided and non-connection intersections where the connection regions are not provided, the connecting intersections and the non-connecting intersections are repeatedly arranged according to a reference pattern in the first direction and the second direction; the reference pattern is a pattern in which five of the connection intersections and five of the non-connection intersections are arranged in a first direction and five of the non-connection intersections are arranged in a second direction, When the positions of the intersections in the reference pattern are expressed by coordinates in a first direction and a second direction, the reference pattern is a pattern in which the connection intersections are located at positions (1,1), (2,4), (3,3), (4,2), and (5,5) and the non-connection intersections are located at other positions, or a pattern equivalent thereto. Switching element.

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