Semiconductor Devices

Abstract

To provide a semiconductor device capable of achieving Pb-free and the suppression of cracks in a semiconductor chip with a simple process when electronic components are highly densely mounted in a compact package.SOLUTION: A semiconductor device includes a semiconductor chip 1, a control circuit chip 3, a capacitor 2, a chip upper electrode 4, a first lead frame 7, a second lead frame 7B, a lead electrode 10, and a base electrode 9. The chip upper electrode is joined, to an upper face of the semiconductor chip, with a joining material that does not contain lead, and the first lead frame is joined, to a lower face of the semiconductor chip, with a joining material that does not contain lead. The end portion of the junction between the chip upper electrode and the semiconductor chip is located inside than the end portion of the semiconductor chip, and the end portion of the first lead frame is located outside than the end portion of the semiconductor chip. The control circuit chip and the capacitor are joined to the second lead frame, respectively. The semiconductor device has an external shape of 20 mm or less, and the thickness of the first lead frame is greater than the thickness of the second lead frame.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] Semiconductor devices used in switching circuits and rectifier circuits are widely used in automobiles, industrial equipment, etc. Because these semiconductor devices are used in products such as automobiles where mounting space is limited, they are becoming increasingly compact and highly dense, with multiple electronic components mounted in a single package. For example, a semiconductor device used for rectifying the AC output of an automotive alternator includes a semiconductor chip, a base, leads, and a conductive bonding material that bonds them together.

[0003] The types of semiconductor chips that are the main components of semiconductor devices include diodes and MOSFETs (Metal Oxide Semiconductor Field-Effect Transistors). These semiconductor chips are usually bonded to different electrodes on the top and bottom surfaces. Pb-based solder containing Pb (lead) has traditionally been used as a bonding material for bonding the semiconductor chip to the top and bottom electrodes. However, in recent years, efforts to reduce the environmental impact have been promoted to eliminate the use of Pb. A typical Pb-free joining material is Sn-based solder, which is primarily composed of Sn. However, Sn-based solder generally has a higher elasticity than Pb-based solder, and temperature changes during the manufacturing process tend to increase the stress generated in semiconductor chips, making them more susceptible to cracking. In particular, in double-sided mounting structures in which electrodes are bonded to both the top and bottom surfaces of a semiconductor chip, stress tends to increase because the semiconductor chip is constrained from the top and bottom surfaces during temperature changes.

[0004] As background art in this technical field, for example, the techniques of Patent Document 1 and Patent Document 2 are disclosed.

[0005] The abstract of Patent Document 1 states, "[Problem] To provide a semiconductor device that can be easily realized at low cost without requiring complex manufacturing processes, and an alternator using the same. [Solution] A semiconductor device comprising a base 21 having a pedestal 24, leads 22 having lead headers 25, and an electronic circuit body 100, with the electronic circuit body between the base and the leads, the pedestal connected to a first surface of the electronic circuit body, and the lead header connected to a second surface of the electronic circuit body, the electronic circuit body including a transistor circuit chip 11 having a switching element, a control circuit chip 12 that controls the switching element, a drain frame 14, and a source frame 15, which are integrally covered with resin 16, and either the drain frame or the source frame is connected to the base, and either the source frame or the drain frame is connected to the leads," disclosing semiconductor device technology. Patent Document 1 discloses a structure in which a plurality of electronic components, such as transistor circuit chips and capacitors, are densely mounted in one small package.

[0006] Furthermore, the abstract of Patent Document 2 states, "[Problem] To provide a semiconductor device formed with lead-free solder that can suppress the occurrence of cracks in a semiconductor chip. [Solution] To provide a semiconductor device comprising: a semiconductor chip 21; a die pad 12 facing the back surface of the semiconductor chip 21; an intermetallic compound 19 mainly composed of Cu-Sn arranged between the peripheral portion of the back surface of the semiconductor chip 21 and the die pad 12; an Sn-based solder 18 mainly composed of Sn arranged between the central portion of the back surface of the semiconductor chip 21 and the die pad 12; and a joining member 17 that joins the back surface of the semiconductor chip 21 to the facing die pad 12," thereby disclosing a technology for constructing a semiconductor device using Sn-based solder. As described above, Patent Document 2 discloses a technique for suppressing the occurrence of cracks in semiconductor chips even when Sn-based solder is used. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Publication No. 2017-98276 [Patent Document 2] Japanese Patent Application Laid-Open No. 2008-34514 Summary of the Invention [Problem to be solved by the invention]

[0008] However, Patent Document 1 does not mention anything about making the product Pb-free. In other words, it does not disclose any technical issues or countermeasures that accompany making the product Pb-free. Furthermore, in the aforementioned Patent Document 2, a technique for suppressing cracks in semiconductor chips using Sn-based solder in relation to Pb-free soldering is disclosed. However, there is a problem in that the joining of the semiconductor chip and the die pad requires a complicated process of laminating an Ag layer and Sn-based solder between them and providing an intermetallic compound mainly composed of Cu-Sn on both sides of the laminated layer.

[0009] The present invention was devised in view of the above-mentioned problems, and has as its objective (purpose) to provide a semiconductor device that is Pb-free and that suppresses cracks in the semiconductor chip through a simple process when electronic components are densely mounted in a small package. [Means for solving the problem]

[0010] In order to solve the above problems and achieve the object of the present invention, the following configuration is provided. That is, the semiconductor device of the present invention is a semiconductor device comprising: a semiconductor chip; a control circuit chip for driving the semiconductor chip; a capacitor for supplying power to the control circuit chip; a chip upper electrode disposed on the upper part of the semiconductor chip; a first lead frame disposed on the lower part of the semiconductor chip; a second lead frame disposed on the lower part of the control circuit chip and the capacitor; a lead electrode connected to the chip upper electrode; and a base electrode connected to the first lead frame, wherein the chip upper electrode is bonded to the upper surface of the semiconductor chip with a bonding material that does not contain lead, and the first lead frame is bonded to the lower surface of the semiconductor chip. the control circuit chip and the capacitor are bonded to the second lead frame with a lead-free bonding material, the end of the bonding portion of the chip upper electrode with the semiconductor chip is located inside the end of the semiconductor chip, the first lead frame is formed in a plate shape, the end of the first lead frame is located outside the end of the semiconductor chip, the second lead frame is formed in a plate shape, the control circuit chip and the capacitor are each bonded to the second lead frame, the outline of the semiconductor device projected in a plane from the lead electrode in the direction of the base electrode is 20 mm or less, and the thickness of the first lead frame is greater than the thickness of the second lead frame.

[0011] Other means will be described in the description of the preferred embodiment of the invention. [Effects of the Invention]

[0012] According to the present invention, when electronic components are densely mounted in a small package, a semiconductor device can be provided that is Pb-free and suppresses cracks in the semiconductor chip while ensuring packaging density through a simple process. [Brief explanation of the drawings]

[0013] [Figure 1] 1 is a diagram schematically illustrating an example of a cross-sectional structure of a semiconductor device according to a first embodiment of the present invention. [Figure 2]FIG. 1 is a diagram showing an example of a first cross-sectional structure near a first lead frame on which a semiconductor chip of an internal package is arranged in a semiconductor device according to a first embodiment of the present invention, and a second cross-sectional structure near a second lead frame on which a control circuit chip is arranged. [Figure 3] 10A and 10B are diagrams showing an example of deformation at the chip bonding end portion during cooling in the bonding process when the first lead frame is thin, with a thickness T of less than 0.5 mm. [Figure 4] 10A and 10B are diagrams showing an example of the results of a stress analysis performed by the finite element method to verify the stress reduction effect of a semiconductor chip. [Figure 5A] 6A and 6B are diagrams illustrating an example of the structural relationship between a semiconductor device according to a second embodiment of the present invention and fins. [Figure 5B] FIG. 10 is a diagram showing an example of the structure of a horseshoe-shaped fin as an external member, viewed from above. DETAILED DESCRIPTION OF THE INVENTION

[0014] Hereinafter, modes for carrying out the present invention (hereinafter referred to as "embodiments") will be described with reference to the drawings as appropriate. The drawings referred to in the following description are intended to show the embodiments in a simplified manner, and therefore the scale, spacing, and positional relationships of each component may be exaggerated, or some components may be omitted from the illustration. Furthermore, the present invention is not limited to the embodiments described herein, and various combinations and improvements are possible within the scope of the present invention.

[0015] First Embodiment The configuration of a semiconductor device according to a first embodiment of the present invention will be described with reference to FIGS.

[0016] <Cross-sectional structure of semiconductor device> FIG. 1 is a diagram schematically showing an example of a cross-sectional structure of a semiconductor device 100 according to a first embodiment of the present invention. In FIG. 1, a semiconductor device 100 is configured to include a base electrode 9, a lead electrode 10, and an internal package 12. The inner package 12 includes a semiconductor chip 1, a capacitor 2, a control circuit chip (control circuit element) 3, a chip upper electrode 4, a first lead frame (chip lower electrode) 7, and a second lead frame (lower electrodes) 7B and 7B2.

[0017] The semiconductor chip 1 is configured to include a semiconductor element, for example, a metal oxide semiconductor field-effect transistor (MOSFET). When the semiconductor chip 1 is used as, for example, a rectifier circuit element (rectifier semiconductor chip), terminal electrodes are provided on the upper surface (first main surface) and lower surface (second main surface) of the semiconductor chip 1. That is, it is a double-sided mounting structure in which terminal electrodes (solder electrodes) are connected to the top and bottom of the semiconductor chip (rectifier semiconductor chip) 1. A chip upper electrode 4 is arranged above the semiconductor chip 1 (as viewed from the paper), and a plate-shaped first lead frame (chip lower electrode) 7 is arranged below the semiconductor chip 1 (as viewed from the paper). The terminal electrodes on the upper surface of the semiconductor chip 1 and the chip upper electrodes 4, and the terminal electrodes on the lower surface of the semiconductor chip 1 and the first lead frame (chip lower electrodes) 7 are bonded together with a chip bonding material (bonding material, solder) 5, which is a Pb-free material that does not contain lead.

[0018] Furthermore, the inner package 12 or the first lead frame 7 and the base electrode 9 are connected by an inter-electrode bonding material 11 . Furthermore, the chip upper electrode 4, which is a block-shaped electrode, is connected to the lead electrode 10 via the inter-electrode bonding material 11. By virtue of such electrical connection, the semiconductor device 100 including the semiconductor chip 1 functions as, for example, the above-mentioned rectifying element between the base electrode 9 and the lead electrode 10 .

[0019] The control circuit chip 3 and the capacitor 2 are disposed on second lead frames (lower electrodes) 7B, 7B2 formed in a plate shape. Although it has been described as a "second lead frame formed in a plate shape," the actual second lead frame (7B, 7B2) does not have a simple shape such as a square or circle when viewed from above, but has a shape in which areas with and without metal are intertwined in a plan view. This "shape in which areas with and without metal are intertwined in a plan view" will be referred to as a "complex shape" as appropriate. By placing the control circuit chip 3 and capacitor 2 at various predetermined positions in the complex shape of this second lead frame (7B, 7B2), electrical connections are made between the above elements (components) to form the desired control circuit. For example, the capacitor 2 is arranged and connected so as to store electric charge and supply power (voltage, power) to the circuit elements of the control circuit chip 3.

[0020] The complex shape of the second lead frame (7B, 7B2) is realized, for example, by etching (patterning) a metal plate into a predetermined shape. In addition, in the cross-sectional view of FIG. 1, the second lead frame 7B and the second lead frame 7B2 are depicted as being separated from each other, but in reality they are configured as a continuous structure at points not shown. Note that the configuration of the second lead frame 7B and the second lead frame 7B2 in the cross-sectional view in Figure 1 is just one example, and in reality, various circuit configurations can be realized by selecting various forms of the complex shape (pattern) of the second lead frame (7B, 7B2) and appropriately arranging various elements (components).

[0021] In addition, one end electrode arranged on the upper part of the second lead frame (lower electrode) 7B is connected by a wire (bonding wire) 6 to a terminal electrode provided on the upper part of the semiconductor chip 1, which is different from the terminal electrode connected to the chip upper electrode 4. As described above, the semiconductor chip 1 is used as, for example, a rectifying element. In this case, a control signal from the control circuit chip 3 is transmitted to the semiconductor chip 1 via the wire 6 to control the rectifying characteristics of the semiconductor chip 1 as a rectifying element. As described above, when the semiconductor chip 1 is configured with a MOSFET, the potential of the gate electrode of the MOSFET of the semiconductor chip 1 is controlled by the control signal from the control circuit chip 3 .

[0022] In the internal package 12, the semiconductor chip 1, capacitor 2, control circuit chip 3, chip upper electrode 4, first lead frame 7, second lead frame (7B, 7B2), chip bonding material 5, and wire 6 are sealed with resin 8A for electrical insulation and protection, and to stabilize the arrangement.

[0023] The lower side of the internal package 12 is placed on the base electrode 9 as viewed from the plane of the drawing, and the upper side is held down by the lead electrode 10. As described above, the internal package 12 and the base electrode 9, and the internal package 12 and the lead electrode 10 are joined by the inter-electrode joining material 11. Furthermore, the upper side of the base electrode 9, the inner package 12, and the lead electrode 10 except for the portion of the lead electrode that protrudes upward are resin-sealed (molded) with resin 8B for electrical insulation and protection.

[0024] The chip upper electrode 4, first lead frame 7, second lead frame (7B, 7B2), base electrode 9, and lead electrode 10 are preferably made of copper or a copper alloy, which has excellent electrical and thermal conductivity. As a second embodiment, details of which will be described later with reference to FIGS. 5A and 5B, the semiconductor device 100 of the first embodiment shown in FIG. 1 may be used by being press-fitted into an external member having a hole. At this time, a clamping force or a pressing force acts on the base electrode 9. For this reason, the base electrode 9 is preferably made of a high-strength material such as an alloy of copper and zirconium.

[0025] 1, the outer dimension D of the semiconductor device 100 in the direction from the lead electrode 10 to the base electrode 9, i.e., when the semiconductor device 100 is projected from the top, may need to be reduced in size in preparation for cases where the mounting space is limited. Therefore, the outer dimension D is usually set to 20 mm or less. The semiconductor device 100 is approximately circular when viewed from the top where the lead electrode 10 is located. Similarly, in order to accommodate cases where there are constraints on mounting space in the height direction of the semiconductor device 100, each component of the semiconductor device 100 is designed to be as thin as possible while still ensuring sufficient performance, reliability (including crack suppression), heat dissipation, etc. As described above, the semiconductor device 100 in FIG. 1 is mainly described as a small semiconductor device having an outer dimension D of 20 mm or less.

[0026] <Cross-sectional structure of the semiconductor chip, the upper electrode of the chip, and the vicinity of the lower electrode of the chip> Figure 2 is a diagram schematically showing an example of a first cross-sectional structure 21 near the first lead frame 7 on which the semiconductor chip 1 of the internal package 12 in the semiconductor device (100) of the first embodiment of the present invention is arranged, and a second cross-sectional structure 22 near the second lead frames 7B, 7B2 on which the control circuit chip 3 is arranged. Next, a description will be given of the first cross-sectional structure 21 and the second cross-sectional structure 22. For convenience of explanation, the second cross-sectional structure 22 will be described first, and then the first cross-sectional structure 21 will be described in detail.

[0027] <<Second Cross-Sectional Structure 22 Near Second Lead Frames 7B and 7B2>> The second cross-sectional structure 22 shown in the left region of the internal package 12 in FIG. 2 will be described. In a second cross-sectional structure 22 in the left region of the inner package 12 in FIG. 2, second lead frames 7B and 7B2, a control circuit chip 3, and a capacitor 2 are arranged. As shown in second cross-sectional structure 22, second lead frames 7B and 7B2 are arranged from below, and the control circuit chip 3 and capacitor 2 are arranged on the upper surface thereof. In this arrangement process, the above-mentioned components are joined, and the second lead frames 7B and 7B2, control circuit chip 3, and capacitor 2 are also electrically connected.

[0028] 2, the thickness (plate thickness) of the second lead frames 7B and 7B2 is T1. As described above, the second lead frame 7B2 is connected to the second lead frame 7B at a point not shown in the cross-sectional view. However, if it is necessary to configure the second lead frame 7B and the second lead frame 7B2 apart at the location shown in the cross-sectional view, the distance between the second lead frame 7B2 and the second lead frame 7B shall be at least the distance S.

[0029] Furthermore, the distance S corresponds to the minimum etching width of the second lead frame (7B, 7B2). The second lead frame (7B, 7B2) requires patterning to form the above-mentioned complex shape, and an isotropic etching liquid is generally used for this patterning. Therefore, when the thickness T1 of the second lead frame (7B, 7B2) becomes large (thick), the required etching width (distance S) also becomes large, which reduces the packaging density. Therefore, when only the miniaturization of the semiconductor device 100 is considered in order to improve the packaging density, it is desirable that the thickness T1 of the second lead frame (7B, 7B2) be as small and thin as possible. Specifically, in consideration of various conditions in the manufacturing process, the thickness T1 of the second lead frame (7B, 7B2) is preferably about 0.1 to 0.2 mm.

[0030] <<First cross-sectional structure 21 in the vicinity of first lead frame 7>> Next, a first cross-sectional structure 21 shown in the right-hand region of the inner package 12 in FIG. 2 will be described. In a first cross-sectional structure 21 in the right region of the internal package 12 in Fig. 2, a first lead frame 7, a semiconductor chip 1, a chip upper electrode 4, and a chip bonding material 5 are arranged. The first lead frame 7 is formed in a plate shape, and the chip upper electrode 4 is formed in, for example, a block shape. The first lead frame 7 and the chip upper electrode 4 are made of metal.

[0031] As shown in the first cross-sectional structure 21, in the manufacturing process of the semiconductor device 100, in the bonding process of the semiconductor chip 1, a first lead frame (lower chip electrode) 7, a chip bonding material 5, the semiconductor chip 1, a chip bonding material 5, and a chip upper electrode 4 are stacked in this order from the bottom. After these are stacked, they are heated and cooled by reflow or the like to bond the above members together. In terms of planar shape, the chip upper electrode 4 is smaller than the semiconductor chip 1, and the first lead frame (chip lower electrode) 7 is larger than the semiconductor chip 1.

[0032] In the first cross-sectional structure 21 in the region on the right side of FIG. 2, the region of the chip bonding end 13, which is the region at the end of the chip (semiconductor chip 1), will be described. 2, the end of the bonding portion of the chip upper electrode 4 with the semiconductor chip 1 is located inside the end of the semiconductor chip 1. This inside area is referred to as a non-bonding area (semiconductor chip upper electrode non-bonding area) 16 as appropriate. The first lead frame 7 is plate-shaped, and the end of the first lead frame 7 is located outside the end of the semiconductor chip 1 . 2, the left end of the non-bonding region 16 in the region of the chip bonding end 13 is the "end of the bonding portion of the chip upper electrode with the semiconductor chip," and the right end of the non-bonding region 16 is the "end of the semiconductor chip." Also, in FIG. 2, the right end of the first lead frame 7 in the view of the page is the "end of the first lead frame."

[0033] The material of the chip bonding material 5 is a Pb-free material that does not contain Pb (lead), and a typical example is Sn-based solder (Sn-based solder) that contains Sn (tin) as its main component. The Sn-based solder may contain additive elements such as Ag (silver), Cu (copper), and Sb (antimony). Examples of Pb-free materials other than Sn-based solder include sinter bonding, which involves sintering a paste material containing fine particles of Cu, Ag, etc., and conductive adhesives.

[0034] The semiconductor chip 1 is configured to include, for example, rectifying elements such as diodes, and transistor elements such as MOSFETs and IGBTs (Insulated Gate Bipolar Transistors). When configured with transistor elements, the same semiconductor chip 1 may also include functions such as a control circuit and a capacitor in addition to the rectifying element. The main materials that make up the semiconductor chip 1 and the control circuit chip (3: FIG. 1) are Si (silicon), SiC (silicon carbide), GaN (gallium nitride), and the like.

[0035] When the semiconductor chip 1 is configured as a rectifying element, the positive and negative polarities are different on the top and bottom surfaces of the semiconductor chip 1, and a surface protection film is formed on the top surface side. Therefore, the top surface of the semiconductor chip 1 has a non-bonding region 16 (FIG. 2) where the chip upper electrode 4 is not connected.

[0036] Furthermore, when the semiconductor chip 1 is configured to include a transistor element, a surface protection film is formed on one side of a region called, for example, the source in a MOSFET or the emitter in an IGBT, and therefore, a non-bonded region 16 exists on the top surface of the semiconductor chip 1 where the chip upper electrode 4 is not connected.

[0037] In this way, since the non-bonding region 16 exists on the upper surface of the semiconductor chip 1, the planar outer dimensions of the chip upper electrode 4 are smaller than the planar outer dimensions of the semiconductor chip 1.

[0038] On the other hand, since it is usually not necessary to provide a non-bonding region on the underside of the semiconductor chip 1, the entire underside of the semiconductor chip 1 is bonded to the first lead frame (chip lower electrode) 7. Therefore, the planar external dimensions of the first lead frame 7 are larger than the planar external dimensions of the semiconductor chip 1. Furthermore, the plate thickness T of the first lead frame 7 is 0.5 mm or more at least in the region where the semiconductor chip is mounted on the first lead frame 7. For reasons that will be described later with reference to Figures 3 and 4, making the plate thickness T of the first lead frame 7 0.5 mm or more is a major feature of the configuration of the present invention.

[0039] When only the viewpoint of miniaturization (higher density) is taken into consideration, it is desirable that the thickness T of the plate of the first lead frame 7 be as thin as possible. In addition, general thermal stress occurs when components with different thermal deformations are constrained to each other, so in order to reduce the constraining force, the related components are often made thinner and less rigid. Therefore, conventionally, the thickness T of the first lead frame 7 has generally been set to a thin thickness of about 0.1 to 0.2 mm. However, the inventors of the present application have discovered that in small semiconductor devices, a unique effect when attempting to reduce stress in order to make the semiconductor device Pb-free is that it is effective to make the thickness T of the first lead frame (chip lower electrode) 7 0.5 mm or more. Next, the reasons and background for this will be explained with reference to FIGS.

[0040] <Deformation during cooling during the joining process> FIG. 3 is a diagram showing an example of deformation during cooling in the bonding process in chip bonding end portion 13 shown in FIG. 2 when first lead frame 7 is thin, with a plate thickness T of less than 0.5 mm. In Figure 3, a semiconductor chip 1 and a chip bonding material 5 are provided between the chip upper electrode 4 and the first lead frame (chip lower electrode) 7, and the semiconductor chip 1 and the first lead frame 7 are shown deformed due to cooling during the bonding process.

[0041] When the semiconductor chip 1 is made of, for example, Si (silicon), the linear expansion coefficient of Si is approximately 3 ppm / K. On the other hand, when the chip upper electrode 4 and the first lead frame (chip lower electrode) 7 are made of Cu, for example, the linear expansion coefficient is about 17 ppm / K, which is larger than that of Si. Therefore, in the bonding process described above, when the bonding material is heated to a high temperature above the melting point thereof, the chip upper electrode 4 and the first lead frame (chip lower electrode) 7, which have a larger linear expansion coefficient, thermally expand more than the semiconductor chip 1. Thereafter, as the chip bonding material 5 solidifies by cooling, the bonding material 5 thermally shrinks while the respective members are bonded together. During this thermal contraction, the amount of thermal contraction of the chip upper electrodes 4 and the first lead frame (chip lower electrodes) 7 is greater than the amount of thermal contraction of the semiconductor chip 1, so that thermal stress and warpage occur.

[0042] Regarding this deformation, we will consider the deformation and effects of each of two regions: region 14 (Figure 3) where both the top and bottom surfaces of semiconductor chip 1 are bonded to electrodes, and region 15 (Figure 3) where only the bottom surface of semiconductor chip 1 is bonded to electrodes.

[0043] About Area 14 In Figure 3, the region 14 where both the upper and lower surfaces of the semiconductor chip 1 are bonded to the electrodes (the electrode bonding region on both the upper and lower parts of the semiconductor chip) is susceptible to the thermal contraction of either the chip upper electrode 4 or the first lead frame (chip lower electrode) 7, whichever is thicker and more rigid. Therefore, for example, if the chip upper electrode 4 is thicker than the first lead frame (chip lower electrode) 7, a convex warpage deformation occurs on the lower surface side. However, in the region 14, since both the upper and lower surfaces of the semiconductor chip 1 are bonded to electrodes, the upper and lower asymmetry is smaller than in the region 15, and the warpage deformation is smaller.

[0044] About Area 15 On the other hand, in region 15 (semiconductor chip lower electrode bonding region) in Figure 3, since no electrodes are bonded to the upper surface side of the semiconductor chip 1, a relatively large convex warpage deformation occurs on the upper surface side due to the influence of thermal contraction of the first lead frame (chip lower electrode) 7. In the case of large electronic components with an external dimension exceeding 20 mm, each component is thicker depending on the product size, and has sufficient rigidity, so warpage deformation is less likely to become apparent. However, in small semiconductor devices with an external dimension of 20 mm or less, the first lead frame 7 is usually designed to be thin due to the above-mentioned circumstances, and a particular phenomenon occurs in which significant warpage occurs.

[0045] During this deformation, the stress acting on the semiconductor chip 1 is largely influenced by two stresses: shear force caused by the difference in the amount of lateral thermal contraction between the semiconductor chip 1 and the first lead frame 7, and bending stress caused by warpage deformation. In small semiconductor devices (for example, products with an outer diameter of 20 mm or less) where warpage is significant, increasing the thickness and rigidity of first lead frame 7 is an effective means for reducing stress.

[0046] <Stress analysis using the finite element method> An example of the results of a stress analysis performed by the finite element method to verify the effect of reducing stress on the semiconductor chip 1 due to thickening of the first lead frame 7 will be described with reference to FIG. The analytical model had the configuration shown in the first cross-sectional structure 21 in the vicinity of the first lead frame 7 in FIG. 2, and a temperature change simulating cooling during reflow was applied to the entire analytical model. The material of the chip bonding material 5 was set to two conditions: Pb-based solder and Sn-based solder. Further, under the condition that Sn-based solder, which is a Pb-free bonding material, was used, the stress σ, which is the maximum principal stress generated in the semiconductor chip 1, was evaluated when the thickness T of the first lead frame 7 was changed.

[0047] FIG. 4 is a diagram showing an example of the results of a stress analysis carried out by the finite element method in order to verify the stress reduction effect of the semiconductor chip 1. In FIG. 4, the horizontal axis represents the thickness T of the first lead frame 7 in units of [mm], and the vertical axis represents the stress σ of the semiconductor chip 1 in units of [pu]. Furthermore, Pb-based solder and Sn-based solder were selected as the materials for the chip bonding material 5 . 4, the point indicated by the symbol "A" uses Pb-based solder as the material for the chip bonding material 5, and the stress σ of the semiconductor chip 1 at this time is set to the reference value of 1 [pu] in the unit method to be the reference. Note that the point indicated by the symbol "A" corresponds to the case where the thickness T of the first lead frame 7 is 0.15 mm.

[0048] 4, the characteristic line consisting of multiple measurement points indicated by the symbol "B" shows the change in stress σ of the semiconductor chip 1 when the thickness T of the first lead frame 7 is used as a parameter. As mentioned above, the reference value of stress σ is 1 [pu], which is the reference value at "A." It was explained that "the vertical axis of Figure 4 represents the stress σ of the semiconductor chip 1, and the unit is [pu]." However, it can also be expressed as "the vertical axis of Figure 4 represents the thermal stress ratio (stress σ) of the semiconductor chip 1 relative to the reference value at "A." In the following description, the Pb-based solder designated "A" and the Sn-based solder designated "B" will be abbreviated simply as "A" and "B", respectively.

[0049] 4, "A" and "B" are compared under the condition of T=0.15 mm. The thickness T of the first lead frame 7, 0.15 mm, was selected as a typical dimension for current small semiconductor devices with an outer diameter of 20 mm or less. Comparing the stress σ of "A" and "B" under this condition of T = 0.15 mm, it can be seen that the stress of "B" is higher, more than 1.4 times. This result is due to the high rigidity of the Pb-free bonding material used in "B". Furthermore, as mentioned above, when the stress σ is high, deformation and cracks are more likely to occur. Therefore, even if the thickness T of "B" is increased under the condition of T<0.5 mm, the stress remains higher in "B" (T<0.5 mm) than in "A" (T=0.15 mm).

[0050] However, when the thickness T of the first lead frame 7 of "B" is increased in accordance with the characteristic line of "B", the stress σ of "B" becomes lower than the stress σ of "A" when T≧0.5 mm. Furthermore, when "B" is thickened to T=0.7 mm, the stress σ of "B" is lower than the stress σ of "A" (T=0.15 mm). In other words, the bending stress caused by warpage deformation is lower in "B". In other words, even in the case of "B" which uses Sn-based solder, a Pb-free bonding material, by setting the thickness T of "B" to "T≧0.5 mm" or even "T≧0.7 mm" as shown in Figure 4, the stress σ is reduced, deformation and cracks are alleviated, and the use of Pb-free bonding materials becomes practical.

[0051] <Relationship between thickness T of first lead frame and thickness T1 of second lead frame> As described above, it is desirable that the thickness T1 of the second lead frames 7B, 7B2 shown in FIG. 2 is thin (small) in order to improve the packaging density. On the other hand, it is desirable that the thickness T of the first lead frame 7 is thick (large), i.e., "T≧0.5 mm" or even "T≧0.7 mm," in order to reduce deformation and cracks when using Sn-based solder, which is a Pb-free bonding material. Therefore, it is desirable that T>T1 and T≧0.5 mm, and furthermore that T≧0.7 mm.

[0052] <Summary of the First Embodiment> When Sn-based solder is selected as a Pb-free joining material to reduce environmental impact, it has a higher elasticity than Pb-based solder. Therefore, the stress generated in the semiconductor chip is likely to increase due to temperature changes during the joining process. Therefore, it is necessary to reduce the stress generated in the semiconductor chip and suppress the occurrence of cracks. In the first embodiment of the present invention, in small semiconductor devices (for example, where the product outer dimensions are 20 mm or less) where warpage is a particular phenomenon that occurs in semiconductor devices that are becoming denser and smaller, thickening the first lead frame (chip lower electrode) 7 is an effective means of reducing stress.

[0053] Specifically, it was found that the use of a Pb-free bonding material becomes practical by setting the thickness T of the first lead frame 7 to "T≧0.5 mm", and further to "T≧0.7 mm". However, in order not to reduce the packaging density of the semiconductor device 100, the thickness T1 of the second lead frame (7B, 7B2) is kept thin (small) so that "T>T1". In this way, by making "T>T1" and "T≧0.5 mm" and even "T≧0.7 mm", the stress generated in the semiconductor chip is reduced, the occurrence of cracks is suppressed, and Pb-free manufacturing is achieved while ensuring the packaging density of the semiconductor device 100. Furthermore, as a specific and desirable condition for "T>T1", by setting the thickness T1 of the second lead frame (7B, 7B2) to 0.1 to 0.2 mm, the packaging density of the semiconductor device 100 can be further increased.

[0054] <Effects of the first embodiment> When mounting electronic components at high density in a small package, a relatively simple process is adopted in which the plate thickness T1 of the second lead frame (7B, 7B2) is made smaller than the plate thickness T of the first lead frame 7, and the plate thickness T of the first lead frame 7 is made larger than 0.5 mm, thereby providing a semiconductor device that is Pb-free and suppresses cracks in the semiconductor chip while ensuring the packaging density of the semiconductor device 100.

[0055] Second Embodiment The configuration of a semiconductor device according to a second embodiment of the present invention will be described with reference to FIGS. 5A and 5B. FIG. 5A is a diagram showing an example of the structural relationship between a semiconductor device 101 according to the second embodiment of the present invention and fins (heat dissipation fins) 91F. Although the semiconductor device 101 in FIG. 5A has a partial difference in shape from the semiconductor device 100 in FIG. 1, it basically has the same configuration. That is, in Figure 5A, the semiconductor device 101 includes a base electrode 9, a lead electrode 10, a semiconductor chip 1, a capacitor 2, a control circuit chip 3, a chip upper electrode 4, a first lead frame (chip lower electrode) 7, a second lead frame (lower electrode) 7B, 7B2, a chip bonding material 5, a wire (bonding wire) 6, resins 8A, 8B, and an inter-electrode bonding material 11.

[0056] Although these parts and members have different shapes, they generally correspond to the configuration of the semiconductor device 100 in FIG. 1, and therefore, overlapping descriptions will be omitted where appropriate.

[0057] In FIG. 5A, base electrode 9 of semiconductor device 101 is press-fitted and fitted between (into) holes of fins (heat dissipation fins) 91F, which are external members provided for heat dissipation and fixation. The base electrode 9 is press-fitted between the fins 91F (holes), and contact and electrical conduction occur due to the restoring force generated by the interference at this time. Furthermore, such a semiconductor device 101 having a package structure including a base electrode 9 suitable for being press-fitted or fitted (press-fit) between the fins 91F (holes) will be referred to as a press-fit type package and a press-fit type semiconductor device. As described above, a clamping force and a pressing force are applied to the base electrode 9. Therefore, the base electrode 9 is preferably made of a high-strength material such as an alloy of copper and zirconium.

[0058] Furthermore, with the above-described structure, no work such as soldering is required when fixing the base electrode 9 to the fins 91F, which contributes to reducing the environmental load and manufacturing costs. Furthermore, this structure fixes the semiconductor device 101, and also allows heat generated in the semiconductor device 101 to be transferred to the fins 91F and dissipated, thereby ensuring that the semiconductor device 101 operates within a temperature range that allows it to function normally.

[0059] FIG. 5B is a diagram showing an example of the structure of a horseshoe-shaped fin (heat dissipation fin) 91F as an external member used in, for example, an alternator (power generator), viewed from above (from lead electrode 10 to base electrode 9). In FIG. 5B, a horseshoe-shaped heat dissipation fin 91F is provided with holes (fin voids) 92H into which a plurality of semiconductor devices 101 are press-fitted. In Figure 5A, the base electrode 9 of the semiconductor device 101 is shown as being sandwiched between the fins 91F, but in reality, as shown in Figure 5B, one semiconductor device 101 is press-fitted into one hole 92H and fitted.

[0060] As shown in FIG. 5B, a plurality of holes (fin voids) 92H are provided in the fin 91F, and a plurality of semiconductor devices 101 are press-fitted into the respective holes 92H. The horseshoe-shaped heat dissipation fin 91F is provided on, for example, an alternator (not shown), which is a generator. The fin 91F is shown in a horseshoe shape because it is suitable for attachment to an alternator.

[0061] As shown in Figures 5A and 5B, semiconductor device 101 is press-fitted into hole 92H of fin 91F, which is an external member, so the shape and structure of semiconductor device 101 must be suitable for being press-fitted into a hole in an external member. As described above, the base electrode 9 of the semiconductor device 101 is fitted into the hole (fin cavity) 92H of the fin 91F, which is a member having a hole, and during the press-fitting, a tightening force and a pressing force act on the base electrode 9. Therefore, the base electrode 9 is preferably made of a high-strength material such as an alloy of copper and zirconium.

[0062] As mentioned above, the outer dimension D of the semiconductor device 101 (100) is designed according to the diameter of the hole into which it will be fitted. Since the mounting space is limited and miniaturization is required, the outer dimension D is usually 20 mm or less. Furthermore, since there are similar mounting space constraints in the height direction of the semiconductor device 101 (100), each component is designed to be as thin as possible while still ensuring its respective performance, reliability (including crack suppression), heat dissipation, etc.

[0063] <Effects of the second embodiment> 5A and 5B, the base electrode 9 of the semiconductor device 101 is press-fit between the fins 91F. This structure not only fixes the semiconductor device 101 but also transfers and dissipates heat generated in the semiconductor device 101 to the fins 91F, ensuring a temperature range in which the semiconductor device 101 operates normally.

[0064] Other embodiments and supplements The present invention is not limited to the above-described embodiments, and various modifications are also possible. For example, the above-described embodiments have been described in detail to clearly explain the present invention, and the present invention is not necessarily limited to those including all of the described configurations. Furthermore, it is possible to replace part of the configuration of one embodiment with part of the configuration of another embodiment, and it is also possible to add part or all of the configuration of another embodiment to the configuration of one embodiment. Other embodiments, modifications, and supplements will be further described below.

[0065] Semiconductor chips In the description of the first embodiment of the present invention, the semiconductor chip 1 is configured by a MOSFET, but is not limited to a MOSFET. For example, in addition to the above-mentioned MOSFET and IGBT, it may be configured with a superjunction MOSFET, a power bipolar transistor, a thyristor, or other semiconductor elements.

[0066] <Applications and uses of semiconductor devices> The applications and uses of the semiconductor device 100 and semiconductor chip 1 of the first embodiment described with reference to FIG. 1 have been exemplified as being used as a rectifier circuit element and a rectifying semiconductor chip, but the semiconductor device 100 and the semiconductor chip 1 are not limited to being a rectifier circuit or a rectifier element (rectifier circuit element). For example, the semiconductor device 100 or the semiconductor chip 1 may be applied to a switching circuit. The semiconductor device 100 may also be used in circuits other than rectifier circuits and switching circuits. A plurality of semiconductor devices 100 may be used to configure, for example, a power conversion circuit that converts three-phase AC to DC, or a power conversion circuit that converts DC to AC.

[0067] <<Structure of Semiconductor Device>> An embodiment of the semiconductor device of the present invention has been described with reference to Fig. 1. The essential features of the semiconductor device of the present invention are that the upper electrode (chip upper electrode) of the semiconductor chip 1 and the first lead frame (chip lower electrode) are joined with a Pb-free joining material, that the edge of the joint between the upper electrode (chip upper electrode) and the semiconductor chip is located inside the edge of the semiconductor chip, and that the edge of the first lead frame (chip lower electrode) is located outside the edge of the semiconductor chip, that the plate thickness T of the first lead frame (chip lower electrode) is 0.5 mm or more, and that the external dimensions of the semiconductor device are 20 mm or less. Furthermore, the relationship T > T1 between the plate thickness T1 of the second lead frame (lower electrode) of the control circuit chip 3 and the first lead frame satisfies the relationship T > T1.

[0068] In other words, even in semiconductor devices having structures other than that shown in FIG. 1, if the above conditions are met, various other semiconductor devices can achieve the effect of being Pb-free and suppressing cracks in the semiconductor chip while ensuring the packaging density of the semiconductor device. Although the example in which a control circuit chip and a capacitor are mounted on the second lead frame has been shown, the circuit elements to be mounted are not limited to these. For example, resistor elements and various sensors may be mounted.

[0069] <<Chip bonding material>> In the first embodiment, "Sn-based solder" is exemplified as a typical example of a Pb-free material that does not contain Pb as the chip bonding material 5. Examples of "Sn-based solder" include SnAgCu-based, SnZnBi-based, SnCu-based, SnAgInBi-based, and SnZnAl-based solders. However, this is not limited to Sn-based solders, and various metals other than Sn may also be applicable. Furthermore, although the bonding material is exemplified as being in the form of "solder," the bonding material is not limited to being in the form of "solder." For example, a bonding material made of a mixture of organic and inorganic materials may also be of interest.

[0070] <Fins, heat dissipation fins> Fins 91F shown in FIGS. 5A and 5B are external members and are not included in semiconductor device 101, but will be described below as they affect the operation of semiconductor device 101. 5B, the fins 91F are described as having a horseshoe shape, but the shape is not limited to a horseshoe. Although the horseshoe shape is used as an example suitable for attaching the fins 91F to, for example, an alternator, other shapes may be suitable for use in applications other than an alternator.

[0071] Furthermore, the number of holes (fin voids) 92H provided in the fin 91F is not limited to six as illustrated in FIG. 5B. Furthermore, if the external shape of the semiconductor device 101 is other than circular (for example, hexagonal or elliptical), the holes (fin voids) 92H provided in the fins 91F may take on other shapes depending on the situation. It is also possible to provide fins (heat dissipation fins) as part of the semiconductor device (101).

[0072] <Materials of the first and second lead frames> The first lead frame and the second lead frame in FIG. 1 have different thicknesses, and are therefore manufactured in separate processes. Therefore, the metal materials for the first lead frame and the second lead frame can be selected independently. For the first lead frame with thickness T1 suitable for high-density mounting and the second lead frame with thickness T suitable for stress reduction, it may be better to select different metal materials suited to each purpose. [Explanation of symbols]

[0073] 1. Semiconductor chips (rectifier circuit elements, rectifier semiconductor chips) 2 capacitors 3 Control circuit chip (control circuit element) 4. Chip upper electrode 5. Chip bonding materials (bonding materials, solder, solder) 6 Wire (bonding wire) 7 First lead frame (bottom electrode of chip) 7B Second lead frame (bottom electrode) 8A, 8B resin 9 Base Electrode 91F Fin (heat dissipation fin) 92H hole, fin cavity 10 Lead electrodes 11 Bonding material between electrodes 12 Internal Package 13 Tip joint end 14 area (electrode bonding area on both top and bottom of semiconductor chip) 15 area (semiconductor chip bottom electrode junction area) 16 Non-bonded area (non-bonded area of ​​upper electrode of semiconductor chip) 100,101 Semiconductor device

Claims

1. A semiconductor chip; a control circuit chip that drives the semiconductor chip; a capacitor for supplying power to the control circuit chip; a chip upper electrode disposed on the upper portion of the semiconductor chip; a first lead frame disposed below the semiconductor chip; a second lead frame disposed below the control circuit chip and the capacitor; a lead electrode connected to the chip upper electrode; a base electrode connected to the first lead frame; A semiconductor device comprising: the chip upper electrode is bonded to the upper surface of the semiconductor chip with a lead-free bonding material; the first lead frame is bonded to the underside of the semiconductor chip with a lead-free bonding material; an end of a joint between the chip upper electrode and the semiconductor chip is located inside an end of the semiconductor chip; the first lead frame is formed in a plate shape, and an end of the first lead frame is positioned outside an end of the semiconductor chip; the second lead frame is formed in a plate shape, and the control circuit chip and the capacitor are respectively joined to the second lead frame; the outer shape of the semiconductor device projected in a plane from the lead electrode toward the base electrode is 20 mm or less; The thickness of the first lead frame is greater than the thickness of the second lead frame. A semiconductor device characterized by:

2. In claim 1, The semiconductor chip is a rectifying semiconductor chip used as a rectifying circuit element. A semiconductor device characterized by:

3. In claim 1, the first lead frame has a thickness of 0.5 mm or more in a region where the semiconductor chip is mounted; A semiconductor device characterized by:

4. In claim 3, the first lead frame has a thickness of 0.7 mm or more in a region where the semiconductor chip is mounted; A semiconductor device characterized by:

5. In claim 3 or claim 4, The thickness of the second lead frame is 0.1 to 0.2 mm; A semiconductor device characterized by:

6. In claim 1, The bonding material is a solder mainly composed of Sn. A semiconductor device characterized by:

7. In claim 6, One or more of Ag, Cu, and Sb are added to the solder. A semiconductor device characterized by:

8. In claim 1, The semiconductor chip is configured to have a MOSFET or an IGBT. A semiconductor device characterized by:

9. In claim 5, the first lead frame and the second lead frame are formed of different materials; A semiconductor device characterized by:

10. In claim 1 or claim 2, The semiconductor device has a structure and strength that allows it to be press-fitted into a hole in an external member. A semiconductor device characterized by:

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