Method for manufacturing packaging substrate and packaging substrate using the same

JP7828402B2Active Publication Date: 2026-03-11ABSOLICS INC
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Patent Information

Authority / Receiving Office
JP · JP
Patent Type
Patents
Current Assignee / Owner
Filing Date
2024-08-27
Publication Date
2026-03-11

AI Technical Summary

Technical Problem

Existing packaging substrates using glass substrates face issues with undulation and gaps between cavity elements, leading to potential short circuits and leakage currents, which affect the electrical performance and reliability of semiconductor devices.

Method used

A packaging substrate design featuring a glass substrate with a core layer containing a cavity portion, where a cavity element is surrounded by a first insulating layer with a lower dielectric constant and a second insulating layer with a higher dielectric constant, preventing short circuits and undulation by ensuring proper insulation and electrical isolation.

Benefits of technology

The proposed design significantly reduces undulation and prevents short circuits, enhancing the quality and reliability of the packaging substrate by minimizing leakage currents and improving electrical performance.

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Patent Text Reader

Abstract

To provide a packaging substrate which prevents an undulation phenomenon due to a gap between elements and / or a gap between a cavity portion and an element, and a manufacturing method thereof.SOLUTION: A packaging substrate includes a core layer 22 including a glass substrate 21 having a first surface and a second surface facing each other and a cavity portion passing through the glass substrate, wherein a cavity module is disposed in the cavity portion, the cavity module comprises a cavity element 40 and a first insulating layer 61 enclosing the cavity element. The first insulation layer is formed on some surfaces other than one surface or on all the surface of the cavity element, and a second insulating layer 62 is further incorporated into the remaining portion of the cavity portion other than the cavity module, and the first insulating layer and the second insulating layer have different dielectric constants.SELECTED DRAWING: Figure 6
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Citation Information

Patent Citations

  • Packaging substrate and semiconductor device including same

    JP2022517061A

  • Packaging substrate and semiconductor device including same

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  • Partitioned Hybrid Substrate for Radio Frequency Applications

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