Planar silicon carbide MOS device and its manufacturing method

Abstract

The present invention provides a planar silicon carbide MOS device and its manufacturing method, which uses a metallization layer to fill the gaps inside the passivation layer instead of a PI layer, thereby increasing the effective area of ​​the cell region and preventing the PI layer from exerting a large stress on the passivation layer in the gaps, thereby reducing the stress on the passivation layer at the sidewalls of the gaps, protecting the passivation layer, and improving the cracking phenomenon of the passivation layer at the sidewalls of the gaps, thereby improving the reliability of the planar silicon carbide MOS device.

Description

[Technical Field]

[0001] The present invention relates to the field of semiconductor technology, and more particularly to planar silicon carbide MOS devices and methods for fabricating the same. [Background technology]

[0002] Silicon carbide is a typical representative of third-generation semiconductor materials and is currently one of the most mature and widely applied wide-bandgap semiconductor materials in terms of crystal growth and device fabrication technologies. Compared to silicon, silicon carbide has a larger bandgap, higher thermal conductivity, higher electron saturation drift velocity, and a critical breakdown field ten times that of silicon, making it an ideal semiconductor material for high-temperature, high-frequency, high-power, and radiation-resistant applications.

[0003] As shown in FIG. 1 , a conventional planar silicon carbide MOS device includes a gate structure 20 located on a silicon carbide substrate 10, a source region S located within the silicon carbide substrate 10, a dielectric layer 30 covering the gate structure 20 and the silicon carbide substrate 10, a gate metal layer 40 and a source metal layer 50 covering the dielectric layer 30, wherein the gate structure 20 exposes the source region S, the source metal layer 50 penetrates the dielectric layer 30 and contacts the source region S, and the gate metal layer 40 penetrates the dielectric layer 30 and contacts the gate structure 20. The gate metal layer 40 and the source metal layer 50 are spaced apart with an etched through-hole between them. The planar silicon carbide MOS device further includes a PA (passivation layer) layer 60 and a PI (polyimide paste) layer 70. The PA layer 60 covers a portion of the source metal layer 50, the gate metal layer 40, and the sidewall of the etched through-hole. The PI layer 70 is located on the PA layer 60 and fills the etched through-hole. This structure results in weak points at the interface between the PI layer 70 and the PA layer 60 on the sidewall of the etched through-hole, making the PA layer 60 prone to cracks 60a, which affect the reliability of the planar silicon carbide MOS device. Furthermore, due to the distribution of the source metal layer 50 and the gate metal layer 40, the source pads leading to the source metal layer 50 and the gate pads leading to the gate metal layer 40 are distributed. Summary of the Invention

[0004] An object of the present invention is to provide a planar silicon carbide MOS device capable of reducing cracking in the PA layer, and a method for manufacturing the same.

[0005] In order to solve the above problems, the present invention provides a gate structure located on a silicon carbide substrate; a source region located within a silicon carbide substrate between two adjacent gate structures; a dielectric layer overlying the gate structure and the silicon carbide substrate; a gate metal layer disposed on the dielectric layer, passing through the dielectric layer, and contacting the gate structure; a source metal layer provided on the dielectric layer, penetrating the dielectric layer, and contacting the source region, the source metal layer having a gap between it and the gate metal layer; a passivation layer covering the gate metal layer, the inner wall of the gap, and the source metal layer near the gap; a metallization layer covering the passivation layer and filling the gap; a PI layer covering the metal coating layer; The present invention provides a planar silicon carbide MOS device, comprising:

[0006] Optionally, the thickness of each of the source metal layer and the gate metal layer is 2 μm to 10 μm.

[0007] Optionally, the thickness of the metal coating layer is between 2 μm and 10 μm.

[0008] Optionally, the material of the metallization layer is at least one selected from Al, AlCu, AlSiCu.

[0009] Optionally, the gate structure includes a first gate structure and a second gate structure; the first gate structure includes a gate oxide layer overlying the silicon carbide substrate and a polysilicon gate overlying the gate oxide layer; The second gate structure includes a gate oxide layer, a field oxide layer, and a field plate, the gate oxide layer and the field oxide layer being adjacent to and in contact with each other on the silicon carbide substrate, and the field plate being located on the gate oxide layer and at least a portion of the field oxide layer.

[0010] further comprising: a gate metal layer positioned above the second gate structure, the gate metal layer passing through the dielectric layer and contacting the field plate; a source metal layer positioned above the first gate structure and a source region, the source metal layer passing through the dielectric layer and contacting a silicon carbide substrate of the source region; The gap is located above the second gate structure.

[0011] Furthermore, the metallization layer further covers the source metal layer near the second gate structure so as to communicate with the source metal layer outside the passivation layer.

[0012] In another aspect, the present invention provides a method for producing a pharmaceutical composition comprising: providing a silicon carbide substrate, wherein a source region is formed in the silicon carbide substrate, a gate structure and a dielectric layer covering the gate structure and the silicon carbide substrate are formed on the silicon carbide substrate, and a first through-hole and a second through-hole are formed in the dielectric layer, the first through-hole exposing the gate structure and the second through-hole exposing the silicon carbide substrate in the source region; simultaneously forming a gate metal layer and a source metal layer, wherein the gate metal layer and the source metal layer are both located on the dielectric layer, the gate metal layer fills the first via hole and contacts the gate structure, the source metal layer fills the second via hole and contacts the source region, and there is a gap between the gate metal layer and the source metal layer; forming a passivation layer and forming a third through-hole in the passivation layer, wherein the passivation layer covers the gate metal layer, an inner wall of the gap, and the source metal layer near the gap, and the third through-hole is located inside the gap; forming a metallization layer and a PI layer in this order, the metallization layer covering the passivation layer and filling the third through-hole, and the PI layer covering the metallization layer; There is further provided a method for fabricating a planar silicon carbide MOS device, comprising:

[0013] Optionally, the method for simultaneously forming the gate metal layer and the source metal layer comprises: forming a metal film layer on the dielectric layer, the metal film layer covering the dielectric layer and filling the first through hole and the second through hole; and etching the metal film layer by an etching process to form a gate metal layer in contact with the gate structure and a source metal layer in contact with the source region, and to form a gap separating the gate metal layer and the source metal layer.

[0014] Optionally, a first gap is formed between a side wall of the third through hole and a side wall of the gap, and a second gap is formed between a bottom wall of the third through hole and a bottom wall of the gap.

[0015] Optionally, the thickness of each of the source metal layer and the gate metal layer is 2 μm to 10 μm.

[0016] Optionally, the thickness of the metal coating layer is between 2 μm and 10 μm.

[0017] Optionally, the material of the metallization layer is at least one selected from Al, AlCu, AlSiCu.

[0018] Optionally, the metallization layer further covers the source metal layer adjacent the passivation layer so as to communicate with the source metal layer outside the passivation layer.

[0019] Compared with the prior art, the present invention has the following beneficial effects:

[0020] The present invention provides a planar silicon carbide MOS device and a method for fabricating the same. The planar silicon carbide MOS device includes a silicon carbide substrate, a source region, a gate structure, a dielectric layer, a gate metal layer, a source metal layer, a passivation layer, a metallization layer, and a PI layer, wherein the source region is located within the silicon carbide substrate, the gate structure is located on the silicon carbide substrate, and the source region is located between two adjacent gate structures, the dielectric layer covers the gate structure and the silicon carbide substrate, the gate metal layer and the source metal layer are simultaneously formed on the dielectric layer, and there is a gap between the gate metal layer and the source metal layer, the gate metal layer penetrates the dielectric layer to contact the gate structure, the source metal layer penetrates the dielectric layer to contact the source region, the passivation layer covers the gate metal layer, the inner wall (i.e., sidewall and bottom wall) of the gap, and the source metal layer near the gap, the metallization layer covers the passivation layer and fills the gap, and the PI layer covers the metallization layer. The present invention uses a structure in which the gap inside the passivation layer is filled with a metal coating layer instead of a PI layer, thereby increasing the effective area of ​​the cell region and preventing the PI layer from applying a large stress to the passivation layer in the gap. This reduces the stress on the passivation layer at the sidewall of the gap, protects the passivation layer, and improves the cracking phenomenon of the passivation layer at the sidewall of the gap, thereby improving the reliability of planar silicon carbide MOS devices. [Brief explanation of the drawings]

[0021] [Figure 1] FIG. 1 is a schematic cross-sectional view of a planar silicon carbide MOS device. [Figure 2] 1 is a cross-sectional structural schematic diagram of a planar silicon carbide MOS device provided by one embodiment of the present invention; [Figure 3] 1 is a flowchart of a method for fabricating a planar silicon carbide MOS device provided by one embodiment of the present invention. [Figure 4]1 is a cross-sectional structural schematic diagram of a silicon carbide substrate provided by an embodiment of the present invention; [Figure 5] 2 is a schematic cross-sectional view of a semiconductor device after forming a gate metal layer and a source metal layer according to an embodiment of the present invention; [Figure 6] FIG. 2 is a schematic cross-sectional view of a semiconductor device after forming a passivation layer according to an embodiment of the present invention. [Figure 7] FIG. 2 is a schematic cross-sectional view of a substrate after a metal coating layer and a PI layer are formed according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0022] The planar silicon carbide MOS device and its manufacturing method of the present invention will be described in more detail below. The present invention will be described in more detail below with reference to the drawings, in which preferred embodiments of the present invention are shown. It should be understood that those skilled in the art can achieve the advantageous effects of the present invention by modifying the invention described herein. Therefore, the following description should not be construed as limiting the present invention, but should be understood as being generally known to those skilled in the art.

[0023] For clarity, not all features of the actual embodiment will be described. In the following description, well-known functions and structures will not be described in detail so as not to obscure the present invention with unnecessary details. It should be understood that in the development of any actual embodiment, many implementation details will need to be considered to achieve the developer's specific goals, such as changing from one embodiment to another in accordance with the constraints of the related system or related business. Furthermore, such development work may be complex and time-consuming, but should be understood to be a routine task for those skilled in the art.

[0024] In order to make the objects and features of the present invention more comprehensible, the following detailed description of the present invention will be given with reference to the accompanying drawings, in which the drawings are all very simplified and not to scale, and are merely provided to facilitate the understanding of the objects of the embodiments of the present invention.

[0025] As shown in FIG. 2 , this embodiment provides a planar silicon carbide MOS device, which includes a silicon carbide substrate 100, a source region 110, a gate structure, a dielectric layer 300, a gate metal layer 420, a source metal layer 410, a passivation layer 500, a metallization layer 600, and a PI layer 700, wherein the source region 110 is located in the silicon carbide substrate 100, the gate structure is located on the silicon carbide substrate 100, and the source region 110 is located between two adjacent gate structures, the dielectric layer 300 covers the gate structure and the silicon carbide substrate 100, and the gate metal layer 420 and the source metal layer 410 are formed on the silicon carbide substrate 100. 0 is simultaneously disposed on the dielectric layer 300, and there is a gap 430 between the gate metal layer 420 and the source metal layer 410, the gate metal layer 420 penetrates the dielectric layer 300 to contact the gate structure, the source metal layer 410 penetrates the dielectric layer 300 to contact the source region 110, the passivation layer 500 covers the gate metal layer 420, the inner wall (i.e., the side wall and bottom wall) of the gap 430, and the source metal layer 410 near the gap 430, the metal covering layer 600 covers the passivation layer 500 and fills the gap 430, and the PI layer 700 covers the metal covering layer 600.

[0026] In the planar silicon carbide MOS device of this embodiment, the gap 430 inside the passivation layer 500 is filled with the metallization layer 600 instead of the PI layer 700, which increases the effective area of ​​the cell region and prevents the PI layer 700 from applying a large stress to the passivation layer 500 in the gap 430. This reduces the stress on the passivation layer 500 at the sidewall of the gap 430, protects the passivation layer 500, and improves the cracking phenomenon of the passivation layer 500 at the sidewall of the gap 430, thereby improving the reliability of the planar silicon carbide MOS device.

[0027] in particular, The silicon carbide substrate 100 includes a front surface and a back surface, and a plurality of source regions 110 are provided at intervals in the front surface of the silicon carbide substrate 100, and the source regions 110 may extend from the front surface of the silicon carbide substrate 100 toward the silicon carbide substrate 100. Here, the conductivity type of the source regions 110 is N-type.

[0028] A plurality of the gate structures are spaced apart on the surface, the gate structures are located on the silicon carbide substrate 100, and each of the source regions 110 is located between two adjacent gate structures. In this embodiment, the source regions 110 and the gate structures are elongated and arranged in parallel.

[0029] The gate structure may include a first gate structure and a second gate structure, where the first gate structure includes a gate oxide layer 220 located on the silicon carbide substrate 100 and a polysilicon gate 230 located on the gate oxide layer 220. The second gate structure includes a gate oxide layer 220, a field oxide layer 210, and a field plate 240, where the gate oxide layer 220 and the field oxide layer 210 are adjacent to and in contact with each other on the silicon carbide substrate 100, and the field plate 240 is located on the gate oxide layer 220 and at least a portion of the field oxide layer 210. The material of the field plate 240 is polysilicon. Here, the thickness of the field oxide layer 210 is greater than the thickness of the gate oxide layer 220.

[0030] The dielectric layer 300 covers the gate structure and the silicon carbide substrate 100 between the adjacent gate structures, where the material of the dielectric layer 300 is, for example, an oxide such as silica.

[0031] The gate metal layer 420 and the source metal layer 410 are provided in the same layer and are both located on the dielectric layer 300. Here, the gate metal layer 420 is located above the second gate structure and penetrates the dielectric layer 300 to contact the field plate 240, and the source metal layer 410 is located above the first gate structure and the source region 110 and penetrates the dielectric layer 300 to contact the silicon carbide substrate 100 of the source region 110.

[0032] The gate metal layer 420 and the source metal layer 410 may both be primarily made of metal, and the material may be at least one selected from Al, AlCu, and AlSiCu. The gate metal layer 420 and the source metal layer 410 located on the dielectric layer 300 each have a thickness of 2 μm to 10 μm. Compared to the thicknesses of the gate metal layer 40 and the source metal layer 50 in the prior art, the thinner gate metal layer 420 and the source metal layer 410 in this embodiment reduces the height of the gap 430, thereby reducing stress on the passivation layer 500 at the gap 430.

[0033] The width of the gap 430 between the gate metal layer 420 and the source metal layer 410 is 5 μm to 10 μm, and the gate metal layer 420 and the source metal layer 410 are not electrically connected by the gap 430. In this embodiment, the gap 430 is located above the second gate structure.

[0034] The passivation layer 500 covers the inner wall of the gap 430, and also covers the dielectric layer 300 near the gap 430, the gate metal layer 420, and a part of the source metal layer 410 near the gap 430. Here, the thickness of the passivation layer 500 on the sidewall of the gap 430 is 0.1 μm to 2 μm.

[0035] In this embodiment, the passivation layer 500 is located above the second gate structure and covers the sidewalls and bottom wall of the gap 430, and further covers the gate metal layer 420 and dielectric layer 300 on the gate structure, as well as the source metal layer 410 near the gap 430.

[0036] The metallization layer 600 covers the passivation layer 500 and also covers a portion of the source metal layer 410 near the second gate structure, so that the metallization layer 600 communicates with the source metal layer 410 outside the passivation layer 500, and the metallization layer 600 also fills and protects the gap 430. Compared with the prior art, the thicknesses of the gate metal layer 420 and the source metal layer 410 are thinner (i.e., the height of the gap 430 is reduced), which reduces the step height of the passivation layer 500 at the gap 430, thereby reducing stress on the passivation layer 500 at the gap 430 and further improving the cracking phenomenon of the passivation layer 500 at the sidewall of the gap 430.

[0037] Here, the thickness of the metal coating layer 600 located on the passivation layer 500 is 2 μm to 10 μm. The metal coating layer 600 may be mainly made of metal, and the material may be at least one selected from Al, AlCu, and AlSiCu. Because the hardness of the metal coating layer 600 is lower than the hardness of the PI layer 700, when the metal coating layer 600 fills the gap 430, it can further reduce the stress of the passivation layer 500 in the gap 430, thereby further improving the cracking phenomenon of the passivation layer 500 on the sidewall of the gap 430.

[0038] The planar silicon carbide MOS device of this embodiment further includes a gate pad and a source pad, the gate pad being connected to the gate metal layer 420 from above the gate metal layer 420, and the source pad being connected indirectly to the source metal layer 410 from above the metallization layer 600, so that the gate pad and the source pad are concentratedly distributed above the second gate structure, i.e., the distribution of the gate pad and the source pad is concentrated, thereby increasing the effective area of ​​the cell region.

[0039] The planar silicon carbide MOS device further includes a drain metal layer, the drain metal layer being located on the back surface.

[0040] 3, this embodiment further provides a method for manufacturing a planar silicon carbide MOS device, which includes the following steps S10, S20, S30, and S40.

[0041] In step S10, a silicon carbide substrate is provided, a source region is formed in the silicon carbide substrate, a gate structure and a dielectric layer covering the gate structure and the silicon carbide substrate are formed on the silicon carbide substrate, a first through-hole and a second through-hole are formed in the dielectric layer, the first through-hole exposes the gate structure and the second through-hole exposes the silicon carbide substrate in the source region.

[0042] In step S20, a gate metal layer and a source metal layer are simultaneously formed, the gate metal layer and the source metal layer are both located on the dielectric layer, the gate metal layer fills the first via hole and contacts the gate structure, the source metal layer fills the second via hole and contacts the source region, and there is a gap between the gate metal layer and the source metal layer.

[0043] In step S30, a passivation layer is formed, and a third through-hole is formed in the passivation layer, the passivation layer covers the gate metal layer, the inner wall of the gap, and the source metal layer near the gap, and the third through-hole is located inside the gap.

[0044] In step S40, a metallization layer and a PI layer are formed in this order, the metallization layer covering the passivation layer and filling the third through-hole, and the PI layer covering the metallization layer.

[0045] 4, in step S10, the first through-hole 310 exposes the field plate 240 of the second gate structure, and the second through-hole 320 exposes the silicon carbide substrate 100 of the source region 110 between two adjacent gate structures. In particular, the second through-hole 320 exposes the silicon carbide substrate 100 of the source region 110 between two adjacent first gate structures and the silicon carbide substrate 100 of the source region 110 between the first gate structure and the second gate structure.

[0046] As shown in FIG. 5, step S20 specifically includes:

[0047] First, a metal film layer is formed on the dielectric layer 300 to cover the dielectric layer 300 and fill the first through-hole 310 and the second through-hole 320, so that the metal film layer contacts the source region 110 and also contacts the field plate 240 of the second gate structure.

[0048] Next, the metal film layer is etched by an etching process to form a gate metal layer 420 and a source metal layer 410, where the gate metal layer 420 contacts the field plate 240 of the second gate structure and the source metal layer 410 contacts the source region 110, and at the same time, a gap 430 is formed on the second gate structure to separate the gate metal layer 420 and the source metal layer 410.

[0049] As shown in FIG. 6, step S30 includes:

[0050] First, a passivation layer 500 is formed, and the passivation layer 500 covers the gate metal layer 420, the inner wall of the gap 430, and the source metal layer 410 near the gap 430.

[0051] Next, a third through-hole 510 is formed in the passivation layer 500 by an etching process, the third through-hole 510 being located inside the gap 430, with a first distance between the sidewall of the third through-hole 510 and the sidewall of the gap 430, and a second distance between the bottom wall of the third through-hole 510 and the bottom wall of the gap 430, so that the passivation layer 500 on the sidewall and bottom wall of the bottom of the third through-hole 510 covers the inner wall and bottom wall of the gap 430. Here, the first distance may or may not be equal to the second distance, and preferably the first distance is equal to the second distance.

[0052] Step S40 includes:

[0053] As shown in FIG. 7, first, a metal covering layer 600 is formed, which fills the third through hole 510, covers the passivation layer 500, and further covers a portion of the source metal layer 410 near the second gate structure, so that the metal covering layer 600 communicates with the source metal layer 410 outside the passivation layer 500.

[0054] As shown in FIG. 2, a PI layer 700 is formed, and the PI layer 700 covers the metallization layer 600 .

[0055] As described above, the present invention provides a planar silicon carbide MOS device and a method for fabricating the same. The planar silicon carbide MOS device includes a silicon carbide substrate, a source region, a gate structure, a dielectric layer, a gate metal layer, a source metal layer, a passivation layer, a metallization layer, and a PI layer, wherein the source region is located within the silicon carbide substrate, the gate structure is located on the silicon carbide substrate, and the source region is located between two adjacent gate structures, the dielectric layer covers the gate structure and the silicon carbide substrate, the gate metal layer and the source metal layer are simultaneously formed on the dielectric layer, and there is a gap between the gate metal layer and the source metal layer, the gate metal layer penetrates the dielectric layer to contact the gate structure, the source metal layer penetrates the dielectric layer to contact the source region, the passivation layer covers the gate metal layer, the inner wall (i.e., sidewall and bottom wall) of the gap, and the source metal layer near the gap, the metallization layer covers the passivation layer and fills the gap, and the PI layer covers the metallization layer. The present invention uses a structure in which the gap inside the passivation layer is filled with a metal coating layer instead of a PI layer, thereby increasing the effective area of ​​the cell region and preventing the PI layer from applying a large stress to the passivation layer in the gap. This reduces the stress on the passivation layer at the sidewall of the gap, protects the passivation layer, and improves the cracking phenomenon of the passivation layer at the sidewall of the gap, thereby improving the reliability of planar silicon carbide MOS devices.

[0056] It should also be explained that the use of the terms "first" and "second" in this specification, unless otherwise specified or indicated, is not intended to represent a logical or sequential relationship between each component, element, or step, but is merely intended to distinguish each component, element, step, etc. in the specification.

[0057] Although the present invention has been disclosed above as a preferred embodiment, it is understood that the above embodiment is not intended to limit the present invention. Those skilled in the art can make many possible changes and modifications to the technical means of the present invention using the technical content disclosed above, or replace them with equivalently changed embodiments with equivalent effects, without departing from the scope of the technical means of the present invention. Therefore, as long as they do not deviate from the content of the technical means of the present invention, any simple substitutions, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention are also included in the scope of protection of the technical means of the present invention. [Explanation of symbols]

[0058] 10 Silicon carbide substrate 20 Gate Structure 30 dielectric layer 40 Gate Metal Layer 50 Source metal layer 60 PA layer 60a crack 70 PI layer 100 Silicon carbide substrate 110 Source Region 210 field oxide layer 220 Gate oxide layer 230 Polysilicon Gate 240 Field Plate 300 dielectric layer 310 First through hole 320 Second through hole 410 Source metal layer 420 gate metal layer 430 Gap 500 passivation layer 510 Third through hole 600 metal coating layer 700 PI layer

Claims

1. a gate structure located on a silicon carbide substrate; a source region located within the silicon carbide substrate between two adjacent gate structures; a dielectric layer overlying the gate structure and the silicon carbide substrate; a gate metal layer disposed on the dielectric layer, passing through the dielectric layer, and contacting the gate structure; a source metal layer provided on the dielectric layer, penetrating the dielectric layer, and contacting the source region, the source metal layer having a gap between it and the gate metal layer; a passivation layer covering the gate metal layer, the inner wall of the gap, and the source metal layer near the gap; a metallization layer covering the passivation layer and filling the gap; a PI layer covering the metal coating layer; 1. A planar silicon carbide MOS device comprising:

2. 2. The planar silicon carbide MOS device of claim 1, wherein the thickness of each of the source metal layer and the gate metal layer is 2 μm to 10 μm.

3. 2. The planar silicon carbide MOS device of claim 1, wherein the metallization layer has a thickness of 2 μm to 10 μm.

4. 2. The planar silicon carbide MOS device of claim 1, wherein the material of said metallization layer is at least one selected from the group consisting of Al, AlCu, and AlSiCu.

5. the gate structure includes a first gate structure and a second gate structure; the first gate structure includes a gate oxide layer overlying the silicon carbide substrate and a polysilicon gate overlying the gate oxide layer; 2. The planar silicon carbide MOS device of claim 1, wherein the second gate structure includes a gate oxide layer, a field oxide layer, and a field plate, the gate oxide layer and the field oxide layer being provided adjacent to and in contact with the silicon carbide substrate, and the field plate being located on at least a portion of the gate oxide layer and the field oxide layer.

6. the gate metal layer is located above the second gate structure, the gate metal layer penetrates the dielectric layer and contacts the field plate; the source metal layer is located above the first gate structure and a source region, the source metal layer penetrates the dielectric layer and contacts a silicon carbide substrate of the source region; 6. The planar silicon carbide MOS device of claim 5, wherein said gap is located above said second gate structure.

7. 6. The planar silicon carbide MOS device of claim 5, wherein the metallization layer further covers the source metal layer near the second gate structure so as to communicate with the source metal layer outside the passivation layer.

8. providing a silicon carbide substrate, wherein a source region is formed in the silicon carbide substrate, a gate structure is formed on the silicon carbide substrate, and a dielectric layer is formed covering the gate structure and the silicon carbide substrate, and a first through-hole and a second through-hole are formed in the dielectric layer, the first through-hole exposing the gate structure and the second through-hole exposing the silicon carbide substrate in the source region; simultaneously forming a gate metal layer and a source metal layer, wherein the gate metal layer and the source metal layer are both located on the dielectric layer, the gate metal layer fills the first via hole and contacts the gate structure, the source metal layer fills the second via hole and contacts the source region, and there is a gap between the gate metal layer and the source metal layer; forming a passivation layer and forming a third through-hole in the passivation layer, the passivation layer covering the gate metal layer, an inner wall of the gap, and the source metal layer near the gap, and the third through-hole being located inside the gap; forming a metallization layer and a PI layer in this order, the metallization layer covering the passivation layer and filling the third via hole, and the PI layer covering the metallization layer; 1. A method for fabricating a planar silicon carbide MOS device, comprising:

9. The method for simultaneously forming the gate metal layer and the source metal layer comprises: forming a metal film layer on the dielectric layer, the metal film layer covering the dielectric layer and filling the first through hole and the second through hole; 10. The method of claim 8, further comprising: etching the metal film layer by an etching process to form a gate metal layer in contact with the gate structure and a source metal layer in contact with the source region, and to form a gap separating the gate metal layer and the source metal layer.

10. 9. The method for manufacturing a planar silicon carbide MOS device according to claim 8, wherein a first distance is defined between a sidewall of the third through hole and a sidewall of the gap, and a second distance is defined between a bottom wall of the third through hole and a bottom wall of the gap.

11. 9. The method for fabricating a planar silicon carbide MOS device according to claim 8, wherein the thickness of each of the source metal layer and the gate metal layer is 2 μm to 10 μm.

12. 9. The method for fabricating a planar silicon carbide MOS device according to claim 8, wherein the thickness of the metallization layer is between 2 μm and 10 μm.

13. 9. The method for fabricating a planar silicon carbide MOS device according to claim 8, wherein the material of said metallization layer is at least one selected from the group consisting of Al, AlCu, and AlSiCu.

14. 9. The method for manufacturing a planar silicon carbide MOS device according to claim 8, wherein the metallization layer further covers the source metal layer near the passivation layer so as to communicate with the source metal layer outside the passivation layer.

15. The method of claim 10, wherein the first spacing is equal to the second spacing.

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