Semiconductor device, system board and calculation method

Abstract

To provide a semiconductor device that satisfactorily performs communication between chips and a data transfer method for the semiconductor device.SOLUTION: A semiconductor device SEM1 includes a first chip CP1 and a second chip CP2 arranged adjacent to the first chip, and the first chip transfers data to the second chip via a silicon interposer BRD. The data transferred from the first chip to the second chip via the silicon interposer is used for arithmetic operation by the internal circuit of the second chip, and the layout design of the first chip is the same as the layout design of the second chip.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device , system board and calculation method Regarding. [Background technology]

[0002] Multi-chip module type semiconductor devices are known, in which multiple chips are mounted on a substrate. For example, in a multi-chip module in which multiple chips are arranged on a substrate such as a silicon interposer, the chips are electrically connected to each other using wiring formed in the wiring layer of the substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-86820 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the embodiments of the present invention is to provide a semiconductor device that can perform good communication between chips. [Means for solving the problem]

[0005] In order to achieve the above object, a semiconductor device according to an embodiment of the present invention comprises: Has multiple arithmetic units a first chip and a second chip disposed adjacent to the first chip; , having multiple arithmetic units a second chip, wherein the first chip transfers data to the second chip via a silicon interposer; the second chip transfers data to the first chip via the silicon interposer; transferred from the first chip to the second chip via the silicon interposer The aforementioned The data is stored in the second chip. the plurality of computing units by About neural networks Used for arithmetic operations, the data transferred from the second chip to the first chip via the silicon interposer is used for arithmetic operations related to the neural network by the plurality of arithmetic units of the first chip; The layout design of the first chip is the same as the layout design of the second chip. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a block diagram illustrating an example of a semiconductor device according to an embodiment of the present invention. [Figure 2] 2 is a block diagram showing an example of the transfer circuit of FIG. 1 and its surrounding circuits. [Figure 3] 2 is an explanatory diagram schematically showing an example in which bumps provided on the chip of FIG. 1 are connected to each other by signal lines (wiring). FIG. [Figure 4] FIG. 2 is a block diagram showing, as a comparative example, an example in which the transfer circuit shown in FIG. 1 is not provided in each chip, and two chips located diagonally opposite each other are connected by a signal line. [Figure 5] FIG. 10 is a block diagram illustrating an example of a semiconductor device according to another embodiment of the present invention. [Figure 6] FIG. 10 is a block diagram illustrating an example of a semiconductor device according to another embodiment of the present invention. [Figure 7] 6 is a perspective view showing an example of a system board on which the semiconductor device of FIG. 5 is mounted. [Figure 8] FIG. 10 is a block diagram illustrating an example of a semiconductor device according to another embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Hereinafter, symbols indicating signal lines are also used as signal names (data names). Unless otherwise specified, the following description will be given in a planar view (for example, when viewed in a direction in which the substrate BRD and the chips CP (CP1-CP4) arranged and mounted on the substrate BRD shown in FIG. 1 overlap).

[0008] Fig. 1 is a block diagram showing an example of a semiconductor device according to one embodiment of the present invention. The semiconductor device SEM1 shown in Fig. 1 has four semiconductor chips CP (a first chip CP1, a second chip CP2, a third chip CP3, and a fourth chip CP4; hereinafter, these may be simply referred to as chip CP1, chip CP2, chip CP3, and chip CP4, respectively) each having a substantially square shape (a type of rectangular shape) with four sides, arranged in two rows and two columns in a plan view on a substrate BRD. In other words, each of the chips CP1-CP4 is provided at a different position on the substrate BRD in a plan view.

[0009] For example, each of the chips CP1-CP4 is connected to a terminal of the substrate BRD via a bump provided on the back surface, which is the surface facing the substrate BRD. Components (electronic components, mechanical components) other than the chips CP1-CP4 may be mounted on the substrate BRD. Furthermore, for example, each of the chips CP1-CP4 may have multiple arithmetic units, each including an arithmetic unit and a memory. The arithmetic unit may be a multiply-accumulate arithmetic unit, an inner product arithmetic unit, or the like.

[0010] The chips CP1 and CP3 are located on a first diagonal line D1, which is one diagonal line of the rectangular substrate BRD that is the placement area of ​​the chips CP1-CP4, and the chips CP2 and CP4 are located on a second diagonal line D2, which is the other diagonal line of the substrate BRD. Hereinafter, the first diagonal line D1 and the second diagonal line D2 may be simply referred to as diagonal lines D1 and D2, respectively. Furthermore, when the diagonal lines D1 and D2 are not distinguished from each other, they may be referred to as diagonal line D. In this embodiment, the outline shape of the substrate BRD in a plan view and the shape of the placement area of ​​the chips CP1-CP4 are the same. In other words, the diagonal lines of the substrate BRD and the diagonal lines D1 and D2 of the placement area of ​​the chips CP1-CP4 are the same. Furthermore, in this specification, when the chip CP is positioned on the diagonal D of the substrate BRD, it means that the chip CP arranged in a planar view overlaps with the diagonal D of the substrate BRD, and is not limited to the corners of the chip CP being on the diagonal D of the BRD.

[0011] Chip CP1 has an internal circuit INT1 and a transfer circuit TR1, chip CP2 has an internal circuit INT2 and a transfer circuit TR2, chip CP3 has an internal circuit INT3 and a transfer circuit TR3, and chip CP4 has an internal circuit INT4 and a transfer circuit TR4. Hereinafter, each of the internal circuits INT1-INT4 may be referred to as an internal circuit INT, and each of the transfer circuits TR1-TR4 may be referred to as a transfer circuit TR.

[0012] The internal circuit INT1 of the first chip CP1 and the internal circuit INT2 of the second chip CP2, which are adjacent and have opposing sides, are connected via signal lines S12 and S21 provided on the substrate BRD. The first chip CP1 has an input / output circuit IO12 that inputs and outputs signals such as data to and from the signal lines S12 and S21, and the second chip CP2 has an input / output circuit IO21 that inputs and outputs signals such as data to and from the signal lines S12 and S21.

[0013] The internal circuit INT2 of the second chip CP2 and the internal circuit INT3 of the third chip CP3, which are adjacent and have opposing sides, are connected via signal lines S23 and S32 provided on the substrate BRD. The second chip CP2 has an input / output circuit IO23 that inputs and outputs signals such as data to and from the signal lines S23 and S32, and the third chip CP3 has an input / output circuit IO32 that inputs and outputs signals such as data to and from the signal lines S23 and S32.

[0014] The internal circuit INT3 of the third chip CP3 and the internal circuit INT4 of the fourth chip CP4, which are adjacent and have opposing sides, are connected via signal lines S34 and S43 provided on the substrate BRD. The third chip CP3 has an input / output circuit IO34 that inputs and outputs signals such as data to and from the signal lines S34 and S43, and the fourth chip CP4 has an input / output circuit IO43 that inputs and outputs signals such as data to and from the signal lines S34 and S43.

[0015] The internal circuit INT4 of the fourth chip CP4 and the internal circuit INT1 of the first chip CP1, which are adjacent and have opposing sides, are connected via signal lines S41 and S14 provided on the substrate BRD. The fourth chip CP4 has an input / output circuit IO41 that inputs and outputs signals such as data to and from the signal lines S41 and S14, and the first chip CP1 has an input / output circuit IO14 that inputs and outputs signals such as data to and from the signal lines S41 and S14. Each of the signal lines S12, S21, S23, S32, S34, S43, S41, and S14 is connected to, for example, bumps BP (FIG. 3) provided on each chip CP. Hereinafter, various signal lines may be referred to as signal lines S when not distinguishing between them.

[0016] Meanwhile, the first chip CP1 and the third chip CP3, which are arranged with their corners facing each other and located on the first diagonal line D1 of the substrate BRD, are connected to each other via a signal line S13a provided on the substrate BRD, a first transfer circuit TR2 of the second chip CP2, and a signal line S13b provided on the substrate BRD. Also, the third chip CP3 and the first chip CP1 are connected to each other via a signal line S31a provided on the substrate BRD, a second transfer circuit TR4 of the fourth chip CP4, and a signal line S31b provided on the substrate BRD.

[0017] The second chip CP2 and the fourth chip CP4, which are arranged with their corners facing each other and located on the second diagonal line D2 of the substrate BRD, are connected via a signal line S24a provided on the substrate BRD, a third transfer circuit TR3 of the third chip CP3, and a signal line S24b provided on the substrate BRD. The fourth chip CP4 and the second chip CP2 are connected via a signal line S42a provided on the substrate BRD, a fourth transfer circuit TR1 of the first chip CP1, and a signal line S42b provided on the substrate BRD. Hereinafter, the first transfer circuit TR2, the second transfer circuit TR4, the third transfer circuit TR3, and the fourth transfer circuit TR1 may be simply referred to as the transfer circuits TR2, TR4, TR3, and TR1, respectively.

[0018] With the above configuration, the semiconductor device SEM1 can mutually communicate signals such as data among the four chips CP1-CP4. Therefore, for example, when performing calculations using multiple arithmetic units mounted on each of the chips CP1-CP4, data used in the arithmetic units and calculation results can be input and output to all other chips CP. Therefore, the semiconductor device SEM1 is suitable for, for example, machine learning, which performs data processing using a large amount of data and a large number of parameters, particularly deep learning using neural networks.

[0019] The arrows attached to each signal line S indicate the transfer direction of the signal transmitted on the signal line S, and the symbol " / " attached to each signal line S indicates that the signal line S is composed of multiple bits. The signal S transmitted on the signal line S includes data, clocks, etc. The number of data bits is not particularly limited, but may be from several tens of bits to around 100 bits.

[0020] The transfer circuit TR1 transfers the signal S42a transmitted from the internal circuit INT4 of the chip CP4 as a signal S42b to the internal circuit INT2 of the chip CP2. The transfer circuit TR2 transfers the signal S13a transmitted from the internal circuit INT1 of the chip CP1 as a signal S13b to the internal circuit INT3 of the chip CP3. The transfer circuit TR3 transfers the signal S24a transmitted from the internal circuit INT2 of the chip CP2 as a signal S24b to the internal circuit INT4 of the chip CP4. The transfer circuit TR4 transfers the signal S31a transmitted from the internal circuit INT3 of the chip CP3 as a signal S31b to the internal circuit INT1 of the chip CP1.

[0021] Then, in the placement area of ​​the four chips CP1-CP4, a data transfer method is realized in which data is transferred from one of the two chips CP located on one diagonal line D to the other via a transfer circuit TR provided in one of the two chips CP that are not located on one diagonal line D.

[0022] For example, signal line (wiring) S13a can be provided between the opposing sides of chips CP1 and CP2. Other signal lines S24a, S31a, S42a, S42b, S13b, S24b, and S31b can also be provided between the opposing sides of chip CP. Therefore, compared to connecting the corners between two chips CP located on diagonal line D with diagonal wiring, the number of signal lines S13a, S24a, S31a, S42a, S42b, S13b, S24b, and S31b that can be wired can be increased.

[0023] Furthermore, for example, the lengths of the multiple signal lines S13a wired between the opposing sides of the chips CP1 and CP2 can be made uniform. By suppressing the variation in the lengths of the signal lines S13a, the skew of the signals transmitted through the signal lines S13a can be reduced, facilitating timing design and contributing to improving the performance of the semiconductor device SEM1. The same applies to the other signal lines S24a, S31a, S42a, S42b, S13b, S24b, and S31b.

[0024] Furthermore, the signal lines S13a, S24a, S31a, S42a, S42b, S13b, S24b, and S31b can be wired using the same wiring rules as the signal lines S12 and S21 connecting the chips CP1 and CP2, for example, which makes it easier to design the layout of the signal lines S13a, S24a, S31a, S42a, S42b, S13b, S24b, and S31b.

[0025] As shown in FIG. 1, in this embodiment, the signal transmission path between two chips CP located on the diagonal line D is clockwise, and the input path and output path are different from each other. This allows one transfer circuit TR (any of TR1-TR4) to be placed on each chip CP, and the four chips CP can be designed using common layout data. As a result, chip costs can be reduced, and the cost of the semiconductor device SEM1 can be reduced. Note that the signal transmission path between two chips CP located on the diagonal line D may be counterclockwise.

[0026] For example, the transfer circuit TR2 outputs data contained in the signal S13a received from the chip CP1 only to the internal circuit INT3 of the chip CP3, and does not output it to the internal circuit INT2 of its own chip CP2. In other words, the internal circuit INT2 does not use the data contained in the signal S13a transferred between the chips CP1 and CP3 for data processing, etc., and the transfer circuit TR2 functions as a relay circuit for the data contained in the signals S13a and S13b between the chips CP1 and CP3. Note that the internal circuit INT2 may monitor the signal S13a transferred on the transfer circuit TR2.

[0027] In each chip CP, the transfer circuit TR is preferably arranged on the central side of the placement area (on the central side of the substrate BRD in the embodiment shown in FIGS. 1 to 3). This makes it possible to shorten the signal transmission path between the chips CP1 and CP3 and between the chips CP2 and CP4, and to reduce the signal transmission time, compared to when the transfer circuit TR is arranged on the outer periphery of the placement area (on the outer periphery of the substrate BRD).

[0028] The substrate BRD may be a silicon interposer. The semiconductor device SEM1 may be formed by packaging the substrate BRD on which the chips CP1-CP4 are mounted. The chips CP1-CP4 may be sealed with resin or the like and packaged. Furthermore, the semiconductor device SEM1 may be connected to a printed circuit board or the like on which other semiconductor components or the like are mounted via bumps provided on the back surface, which is the surface opposite to the front surface of the substrate BRD on which the chips CP1-CP4 are mounted.

[0029] When the signal transmission path between two chips CP located on the diagonal line D is bidirectional, for example, two transfer circuits TR1 and TR3 that transfer signals input / output between the chips CP2 and CP4 are provided on only one of the chips CP1 and CP3. Similarly, two transfer circuits TR2 and TR4 that transfer signals input / output between the chips CP1 and CP3 are provided on only one of the chips CP2 and CP4.

[0030] For example, if transfer circuits TR1 and TR3 are provided only on chip CP1 and transfer circuits TR2 and TR4 are provided only on chip CP2, layout designs for chips CP1 and CP2 and for chips CP3 and CP4 must be separately designed. Furthermore, since there are areas on the substrate BRD where the signal lines S are densely wired and areas where they are sparsely wired, the wiring layout design becomes difficult.

[0031] Furthermore, the internal circuits INT1 and INT2 of chips CP1 and CP2 have smaller areas than the internal circuits INT3 and INT4 of chips CP3 and CP4. Therefore, if chips CP1 to CP4 are made the same chip size, there may be wasted areas in the areas of the internal circuits INT3 and INT4 of chips CP3 and CP4 where no circuits are formed. Furthermore, if the chip size of chips CP3 and CP4 is made smaller than the chip size of chips CP1 and CP2 in order to eliminate the wasted area, it is necessary to design two types of chips.

[0032] Fig. 2 is a block diagram showing an example of the transfer circuit TR2 and its surrounding circuits in Fig. 1. The other transfer circuits TR1, TR3, TR4 and their surrounding circuits also have the same configuration as in Fig. 2.

[0033] The transfer circuit TR2 includes an input buffer 21, an input flip-flop (FF) 22, an error detection / correction circuit 23, a clock resynchronization circuit 24, staging FFs 25, FFs 26, an error detection / correction signal generation circuit 27, an output FF 28, and an output buffer 29. The number of staging FFs inserted in the transfer circuit TR2 may be determined depending on the length of the signal transmission path and the clock frequency, and is not limited to the number shown in FIG.

[0034] The input buffer 21 receives a multi-bit signal S13a from the chip CP1 via a signal line S13a and outputs the received signal S13a to the input FF 22. The input FF 22 accepts the signal S13a in synchronization with a clock (not shown) and outputs the accepted signal S13a to the error detection / correction circuit 23. The clock used by the input FF 22 is the clock used by the chip CP1 and is included in the signal S13a output from the chip CP1.

[0035] The error detection / correction circuit 23 uses the error detection / correction signal included in the multi-bit signal S13a to detect or correct an error in the data included in the signal S13a, and if a correction is made, outputs the error-corrected data to the clock transfer circuit 24. As a result, even if an error occurs in the data received from the chip CP1 via the signal line S13a, correct data with the error corrected can be transferred to the chip CP3.

[0036] When the error detection / correction circuit 23 detects an uncorrectable error, it may generate error information indicating the detection of the uncorrectable error. Furthermore, when the error detection / correction circuit 23 corrects a data error, it may generate correction information indicating that the error has been corrected. In this case, the error information or correction information may be output to the internal circuit INT2 of the chip CP2. Furthermore, when the error detection / correction circuit 23 generates error information or correction information, the internal circuit INT2 of the chip CP2 may store the error information or correction information and may use the stored error information or correction information to perform information processing such as calculating an error correction rate.

[0037] Alternatively, the error detection / correction circuit 23 may only perform data error detection, in which case the error detection / correction signal generation circuit 11 of the internal circuit INT1 may generate a signal that only performs error detection, such as a parity bit. Furthermore, when the error detection / correction circuit 23 detects a data error, it may generate detection information indicating that an error has been detected and output the generated detection information to the internal circuit INT2. When the error detection / correction circuit 23 generates detection information, the internal circuit INT2 may retain the detection information and may use the retained detection information to perform information processing, such as calculating an error detection rate.

[0038] The error information, correction information, or detection information generated by the error detection / correction circuit 23 and output to the internal circuit INT2, or information generated based on the error information, correction information, or detection information, may be output to the internal circuit INT3 of the chip CP3 via the internal circuit INT2. In this case, for example, the error information, correction information, or detection information, or information generated based on the error information, correction information, or detection information, may be transmitted to the internal circuit INT3 via the input / output circuit IO23 of the internal circuit INT2, the signal line S23, and the input / output circuit IO32 of the internal circuit INT3 shown in FIG. 1. This prevents signals other than data, error detection / correction signals, and clocks from being transmitted to the signal line S13b, thereby minimizing the number of signal lines S13b. In other words, the signal line S13b can be used only for transferring data from the chip CP1 to the chip CP3.

[0039] The clock resynchronizer circuit 24 converts data included in the signal S13a synchronized with the clock of the chip CP1 into data synchronized with the clock of the chip CP2, and outputs the converted data to the staging FF 25. For example, an input asynchronous FIFO (First-In First-Out) may be used as the clock resynchronizer circuit 24. Note that the order of connection of the error detection / correction circuit 23 and the clock resynchronizer circuit 24 may be reversed. That is, the data synchronized with the clock of the chip CP2 by the clock resynchronizer circuit 24 may be subjected to error detection by the error detection / correction circuit 23, and the error may be corrected as desired.

[0040] The staging FFs 25 and 26 are an example of a relay circuit that sequentially relays data. Note that if the signal transfer distance within the transfer circuit TR2 is short, the transfer circuit TR2 does not need to have the staging FFs 25 and 26. In this case, the data output from the clock resynchronizer circuit 24 may be output directly to the error detection / correction signal generation circuit 27.

[0041] The error detection / correction signal generation circuit 27 generates an error detection / correction signal for correcting errors in multiple bits of data, and outputs the generated error detection / correction signal together with the data to the output FF 28. For example, the error detection / correction signal is an ECC (Error Correction Code). The output FF 28 outputs the data, the error detection / correction signal, and a clock to the output buffer 29. The output buffer 29 outputs the data, the error detection / correction signal, and the clock as a signal S13b to the chip CP3.

[0042] The internal circuit INT1 of the chip CP1 that outputs the signal S13a includes an error detection / correction signal generation circuit 11, an output FF 12, and an output buffer 13. The error detection / correction signal generation circuit 11, the output FF 12, and the output buffer 13 have the same functions as the error detection / correction signal generation circuit 27, the output FF 28, and the output buffer 29 of the transfer circuit TR2, respectively.

[0043] The internal circuit INT3 of the chip CP3 has an input buffer 31, an input FF 32, an error detection / correction circuit 33, and a clock transfer circuit 34. The input buffer 31, the input FF 32, the error detection / correction circuit 33, and the clock transfer circuit 34 have the same functions as the input buffer 21, the input FF 22, the error detection / correction circuit 23, and the clock transfer circuit 24 of the transfer circuit TR2, respectively.

[0044] The input buffer 31 receives a multi-bit signal S13b transferred from the chip CP1 via the transfer circuit TR2 of the chip CP2, and outputs the received signal S13b to the input FF 32. The input FF 32 accepts the signal S13b in synchronization with the clock of the chip CP2 included in the signal S13b, and outputs the accepted signal S13b to the error detection / correction circuit 33.

[0045] The error detection / correction circuit 33 uses the error detection / correction signal included in the signal S13b to detect or correct errors in the data included in the signal S13b, and if the error is corrected, outputs the error-corrected data to the clock resynchronization circuit 34. The clock resynchronization circuit 34 converts the data included in the signal S13b, which is synchronized with the clock of the chip CP2, into data synchronized with the clock of the chip CP3. The internal circuit INT3 then performs data processing and the like using the signal S13b transferred from the chip CP1 via the transfer circuit TR2 of the chip CP2. If the processed data needs to be returned to the chip CP1, the internal circuit INT3 transfers the data to the chip CP1 via the transfer circuit TR4 of the chip CP4 shown in FIG. 1. Alternatively, the error detection / correction circuit 33 may perform only error detection. In this case, the error detection / correction signal generation circuit 27 of the transfer circuit TR2 may generate a signal that only performs error detection, such as a parity bit.

[0046] The order of connection of the error detection / correction circuit 33 and the clock resynchronizer circuit 34 may be reversed. That is, data synchronized with the clock of the chip CP3 by the clock resynchronizer circuit 34 may be subjected to error detection and arbitrary error correction by the error detection / correction circuit 33. Furthermore, the transfer circuit TR2 may not have the error detection / correction circuit 23 and the error detection / correction signal generation circuit 27, the transfer circuit TR1 may not have the error detection / correction signal generation circuit 11, and the transfer circuit TR3 may not have the error detection / correction circuit 33.

[0047] FIG. 3 is an explanatory diagram illustrating an example in which bumps BP provided on chips CP1-CP4 in FIG. 1 are interconnected by signal lines S (wiring). The signal lines S are formed, for example, using a wiring layer of a substrate BRD such as a silicon interposer. The signal lines S connected to the bumps BP shown in FIG. 3 are routed according to the same wiring rule, for example, regardless of the signal transfer destination. This reduces the variation in length of the multiple signal lines S and the skew of the signals S, as described in FIG. 1. Note that, for ease of explanation, FIG. 3 illustrates bumps BP on each chip CP, and only bumps BP facing each other are connected by signal lines S. However, in reality, the bumps BP are located between each chip CP and the substrate BRD. Furthermore, to align the lengths of the signal lines S, for example, bumps BP arranged on the right side of chip CP2 are connected via signal lines S to bumps BP located further back than bumps BP arranged on the left side of chip CP3.

[0048] Figure 4 is a block diagram showing, as a comparative example, an example in which the transfer circuit TR shown in Figure 1 is not provided on each chip CP, and two chips CP1 and CP3 (or CP2 and CP4) located on diagonal line D1 (or D2) are connected by signal lines S13 and S31 (or S24 and S42).

[0049] In this case, both input and output signal lines are connected by diagonal wiring using bumps (not shown) provided in the corner regions of chips CP1-CP4 near the intersections of diagonal lines D1 and D2. Furthermore, signal lines S13 and S31 must intersect with signal lines S24 and S42. Therefore, if there are a large number of signal lines S13, S31, S24, and S42, wiring may be difficult. Furthermore, increasing the number of wiring layers of a substrate BRD, such as a silicon interposer, to enable wiring may increase costs and signal delays. Furthermore, if the lengths of signal lines S13 and S31 (or S24 and S42) vary, signal skew may occur. In contrast, the embodiments shown in Figures 1 to 3 can mitigate the above problems.

[0050] As described above, in the embodiment shown in FIGS. 1 to 3, data can be transferred between two chips CP located on the diagonal line D via transfer circuits TR provided in two chips CP not located on the diagonal line D. The signal lines S connected to the transfer circuits TR are provided on opposing sides of the two chips CP located on the diagonal line D, so the number of signal lines S that can be wired can be increased compared to when the chips are connected by diagonal wiring substantially parallel to the diagonal line D. Furthermore, two chips CP adjacent to each other via opposing sides can input and output data to and from each other via the input / output circuit IO. As a result, data of an equal amount of information can be communicated between the four chips CP1 to CP4, and mutual communication between the chips CP1 to CP4 can be performed satisfactorily.

[0051] Because the four chips CP1-CP4 can communicate data of the same amount of information with each other, it is possible to divide the functions realized by one chip into four chips CP1-CP4 to create the semiconductor device SEM1. In this case, it is expected that the yield, which is the rate at which the chips CP are non-defective, will be improved compared to when the functions are realized by one chip. The improved yield will reduce chip costs, and therefore the cost of the semiconductor device SEM1.

[0052] It is possible to reduce the variation in the lengths of the multiple signal lines S that transmit data between the two chips CP located on the diagonal line D, thereby reducing the skew of data transmitted via the signal lines S. As a result, it is possible to facilitate timing design and contribute to improving the performance of the semiconductor device SEM1.

[0053] By arranging the transfer circuit TR on the central side of the substrate BRD of the chip CP (the central side of the placement area of ​​the chip CP), the signal transmission path between the chips CP can be shortened and the signal transmission time can be reduced compared to when the transfer circuit TR is arranged on the outer periphery of the substrate BRD (the outer periphery of the placement area of ​​the chip CP).By arranging one transfer circuit TR on each chip CP, the four chips CP can be designed using common layout data.As a result, the chip cost can be reduced, and the cost of the semiconductor device SEM1 can be reduced.

[0054] Even if an error occurs in data received from one chip CP via the signal line S, each transfer circuit TR can detect the error using the error detection / correction circuit 23 or transfer the correct data after correcting the error to the other chip CP. Furthermore, each transfer circuit TR generates an error detection / correction signal using the error detection / correction signal generation circuit 27 to detect or correct an error in the data to be transferred to the other chip CP. As a result, even if an error occurs in the data output from the transfer circuit TR, the error can be detected or corrected by the error detection / correction circuit 33 of the other chip CP that received the data. Therefore, even when data transmission between two chips CP located on the diagonal line D is performed via another chip CP, a decrease in data reliability can be reduced.

[0055] Fig. 5 is a block diagram showing an example of a semiconductor device according to another embodiment of the present invention. Elements similar to those in Fig. 1 are given the same reference numerals, and detailed description thereof will be omitted. The semiconductor device SEM2 shown in Fig. 5 has the same configuration as the semiconductor device SEM1 shown in Fig. 1, except that the transfer circuits TR (TR1-TR4) are provided on the outer periphery of the arrangement area of ​​each chip CP (CP1-CP4) (on the outer periphery of the substrate BRD).

[0056] In this embodiment, since the distance over which the signal S is transmitted within each transfer circuit TR is long, each transfer circuit TR has a greater number of staging FFs (not shown) than in FIG. 2. The configuration of each transfer circuit TR is the same as that of the transfer circuit TR2 shown in FIG. 2, except for the greater number of staging FFs. The position of the transfer circuit TR provided in each chip CP is not limited to the position shown in FIG. 5 and may include, for example, the central portion of each chip CP. The transfer circuits TR may also be provided in a distributed manner in multiple regions of each chip CP. The semiconductor device SEM2 shown in FIG. 5 can obtain the same effects as the semiconductor device SEM1 shown in FIG. 1.

[0057] Figure 6 is a block diagram showing an example of a semiconductor device according to another embodiment of the present invention. Elements similar to those in Figure 1 are given the same reference numerals, and detailed description thereof will be omitted. The semiconductor device SEM3 shown in Figure 6 has four rectangular chips CP (CP1-CP4) with long and short sides mounted on a substrate BRD. Each chip CP has a transfer circuit TR (TR1-TR4) similar to those in Figures 1 and 2, and relays signal transmission between two chips CP located on a diagonal line D1 (or D2).

[0058] Furthermore, a vacant area where the chips CP1-CP4 are not placed is provided in the central portion of the substrate BRD (the central portion of the placement area of ​​the chips CP) so that the peripheral shape of the placement area of ​​the chips CP1-CP4 does not have any protrusions, that is, so that the outer peripheral shape of the placement area is approximately rectangular. In other words, each side of the rectangular placement area where the chips CP1-CP4 are placed is formed by one of the long sides and one of the short sides of each chip CP. Furthermore, the other long side of each chip CP faces the other short side of the adjacent chip CP, and the other short side of each chip CP faces the other long side of the adjacent chip CP. The other long sides of two chips CP located on the diagonal line D1 (or D2) face each other across the vacant area. Furthermore, the vacant area is surrounded by the four chips CP1-CP4.

[0059] Other configurations of the semiconductor device SEM3 are the same as those of the semiconductor device SEM1 shown in Fig. 1. The position of the transfer circuit TR provided in each chip CP is not limited to the position shown in Fig. 6. The transfer circuit TR may be provided in a distributed manner in multiple regions of each chip CP.

[0060] 7 is a perspective view showing an example of a system board SBRD on which the semiconductor device SEM3 of FIG. 6 is mounted. In FIG. 7, the semiconductor device SEM3 is mounted on the system board SBRD together with other electronic components IC and a connector CN. For example, the system board SBRD is a printed circuit board. The system board SBRD may be connected to a back panel provided on a rack or the like (not shown) via the connector CN. Furthermore, a cluster may be formed by connecting multiple system boards SBRD to a rack or the like.

[0061] 1, the semiconductor device SEM2 in FIG. 5, and the semiconductor device SEM4 in FIG. 8, which will be described later, may also be mounted on the system board SBRD, similarly to FIG.

[0062] The semiconductor device SEM3 of this embodiment can also achieve the same effects as those of the semiconductor device SEM1 shown in FIG.

[0063] Figure 8 is a block diagram showing an example of a semiconductor device according to another embodiment of the present invention. Elements similar to those in Figures 1 and 6 are designated by the same reference numerals, and detailed description thereof will be omitted. The semiconductor device SEM4 shown in Figure 8 has four rectangular chips CP (CP1-CP4) mounted on a substrate BRD. Each chip CP has a transfer circuit TR (TR1-TR4) similar to those in Figures 1 and 2, and each transfer circuit TR relays signal transmission between two chips CP located on a diagonal line D1 (or D2).

[0064] In this embodiment, to minimize the size of the transfer circuit TR and the delay of the signal S transferred through the transfer circuit TR, the transfer circuit TR is provided near the center of the substrate BRD, which is the placement area for the chips CP1-CP4, as in FIG. 1. Therefore, each of the chips CP1-CP4 is mounted on the substrate BRD with one of its corners positioned close to the intersection of the diagonal lines D1 and D2. As a result, the outer edges of each of the chips CP1-CP4 are not aligned in a straight line, and the placement area for the chips CP1-CP4 has a protrusion. The size of the substrate BRD can be determined to accommodate the protrusion. Furthermore, by reducing the free space within the placement area, the area occupied by the chips CP1-CP4 on the substrate BRD can be reduced. Therefore, the area on the substrate BRD where other electronic components can be mounted can be increased. The other configurations of the semiconductor device SEM4 are similar to those of the semiconductor device SEM1 shown in FIGS. 1 and 6. The semiconductor device SEM4 of this embodiment can also achieve the same effects as the semiconductor device SEM1 shown in FIG. 1.

[0065] 1, 5, 6, and 8, an example has been described in which a transfer circuit TR is provided in each chip CP. However, if data transfer between chips CP2 and CP4 is necessary but data transfer between chips CP1 and CP3 is not necessary, the transfer circuit TR may be provided in chips CP1 and CP3 but not in chips CP2 and CP4. Also, if data transfer between chips CP1 and CP3 is necessary but data transfer between chips CP2 and CP4 is not necessary, the transfer circuit TR may be provided in chips CP2 and CP4 but not in chips CP1 and CP3.

[0066] The present invention is not limited to the specifically disclosed embodiments above, but various modifications and variations are possible without departing from the scope of the claims. [Explanation of symbols]

[0067] 11 Error detection / correction signal generation circuit 12 output flip-flops 13 Output Buffer 21 Input Buffer 22-input flip-flop 23 Error detection / correction circuit 24 Clock transfer circuit 25, 26 Staging 27 Error detection / correction signal generation circuit 28 output flip-flops 29 Output Buffer 31 Input Buffer 32-input flip-flop 33 Error detection / correction circuit 34 Clock transfer circuit BP Bump BRD substrate CP (CP1, CP2, CP3, CP4) chip D1, D2 diagonals INT (INT1, INT2, INT3, INT4) internal circuit S signal line SEM1, SEM2, SEM3, SEM4 semiconductor device TR (TR1, TR2, TR3, TR4) Transfer circuit IO Input / Output Circuit

Claims

1. A first chip having a plurality of arithmetic units; a second chip disposed adjacent to the first chip and having a plurality of arithmetic units; the first chip transfers data to the second chip via a silicon interposer; the second chip transfers data to the first chip via the silicon interposer; the data transferred from the first chip to the second chip via the silicon interposer is used for arithmetic operations related to a neural network by the plurality of arithmetic units of the second chip; the data transferred from the second chip to the first chip via the silicon interposer is used for arithmetic operations related to the neural network by the plurality of arithmetic units of the first chip; The layout design of the first chip is the same as the layout design of the second chip. Semiconductor device.

2. each of the first chip and the second chip has a rectangular shape having four sides in a plan view, and one side of the first chip faces one side of the second chip; The semiconductor device according to claim 1 .

3. The plurality of arithmetic units of the first chip include at least a multiply-accumulate arithmetic unit or an inner product arithmetic unit; the plurality of arithmetic units of the second chip include at least a multiply-accumulate unit or an inner product unit; 3. The semiconductor device according to claim 1.

4. the first chip and the second chip are sealed with a resin; The semiconductor device according to claim 1 .

5. A first signal line that transfers the data from the first chip to the second chip via the silicon interposer; a second signal line that transfers the data from the second chip to the first chip via the silicon interposer; the first signal line and the second signal line have the same length; 5. The semiconductor device according to claim 1.

6. a substrate on which the first chip and the second chip are mounted, The substrate is mounted on a system board.

6. The semiconductor device according to claim 1.

7. the first chip and the second chip are mounted on a substrate; the board is mounted on each of a plurality of system boards housed in a rack, each of the system boards having a connector connected to the rack; each of the plurality of system boards having at least two chips that transfer data to another chip within the same system board using a silicon interposer; 6. The semiconductor device according to claim 1.

8. the substrate is connected to a system board via a plurality of bumps provided on a back surface opposite to a front surface having the first chip and the second chip; 8. The semiconductor device according to claim 6.

9. A third chip adjacent to the second chip and having a plurality of arithmetic units; a fourth chip adjacent to the first chip and the third chip, the fourth chip having a plurality of arithmetic units; the first to fourth chips are rectangular in shape having four sides in a plan view, and the adjacent chips have sides facing each other; the first chip and the third chip have corners facing each other, the second chip and the fourth chip have corners facing each other, The layout designs of the first to fourth chips are the same.

9. The semiconductor device according to claim 1.

10. The second chip transfers data to the third chip via the silicon interposer; the third chip transfers data to the second chip via the silicon interposer; the third chip transfers data to the fourth chip via the silicon interposer; the fourth chip transfers data to the third chip via the silicon interposer; the fourth chip transfers data to the first chip via the silicon interposer; the first chip transfers data to the fourth chip via the silicon interposer; The semiconductor device according to claim 9 .

11. The data transferred from the second chip to the third chip via the silicon interposer is used for arithmetic operations related to the neural network by the plurality of arithmetic units of the third chip; the data transferred from the third chip to the second chip via the silicon interposer is used for arithmetic operations related to the neural network by the plurality of arithmetic units of the second chip; the data transferred from the third chip to the fourth chip via the silicon interposer is used for arithmetic operations related to the neural network by the plurality of arithmetic units of the fourth chip; the data transferred from the fourth chip to the third chip via the silicon interposer is used for arithmetic operations related to the neural network by the plurality of arithmetic units of the third chip; the data transferred from the fourth chip to the first chip via the silicon interposer is used for arithmetic operations related to the neural network by the plurality of arithmetic units of the first chip; the data transferred from the first chip to the fourth chip via the silicon interposer is used for arithmetic operations related to the neural network by the plurality of arithmetic units of the fourth chip; The semiconductor device according to claim 10.

12. A system substrate comprising a semiconductor device according to any one of claims 1 to 11.

13. A calculation method for performing arithmetic operations on the neural network using a semiconductor device described in any one of claims 1 to 11.

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