Bipolar Semiconductor Devices

Abstract

To provide a bipolar semiconductor device capable of suppressing an increase in on-resistance and reducing reverse recovery current.SOLUTION: A bipolar semiconductor device includes: a cathode region 10 composed of n-type SiC; a breakdown voltage sustention layer 20 formed on the cathode region 10; and an anode region 30 composed of p-type SiC formed on the breakdown voltage sustention layer 20. A trap layer 32 is provided in the anode region 30 to trap a carrier.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a bipolar semiconductor device such as a PiN diode using silicon carbide. [Background technology]

[0002] Silicon carbide (hereinafter referred to as SiC) has excellent physical properties compared to Si, such as a band gap approximately three times larger, a saturated drift velocity approximately twice larger, and a breakdown field strength approximately ten times larger. It is also a semiconductor with high thermal conductivity, and is therefore expected to be a material that will realize next-generation high-voltage, low-loss semiconductor elements that will far surpass the performance of currently used Si single-crystal semiconductors.

[0003] Known semiconductor devices using SiC include SiC bipolar semiconductor devices such as PiN diodes. Generally, a challenge for semiconductor devices is to reduce the on-resistance in order to reduce losses. However, it is known that these bipolar devices can reduce the on-resistance by lowering the resistance of the breakdown voltage maintaining layer through minority carrier injection (see, for example, Patent Document 1).

[0004] However, it is known that lowering the on-resistance generally increases the reverse recovery current that flows through the bipolar device during switching operation, and SiC bipolar semiconductor devices are also required to reduce this reverse recovery current. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 2019-067982 Summary of the Invention [Problem to be solved by the invention]

[0006] SUMMARY OF THE INVENTION In view of the above circumstances, an object of the present invention is to provide a bipolar semiconductor device that can suppress an increase in on-resistance and reduce reverse recovery current. [Means for solving the problem]

[0007] One aspect of the present invention for achieving the above object is a bipolar semiconductor device including a cathode region made of n-type SiC, a breakdown voltage sustaining layer formed on one side of the cathode region, and an anode region made of p-type SiC formed on the opposite side of the breakdown voltage sustaining layer from the cathode region, wherein a trap layer that traps carriers is provided in the anode region. [Effects of the Invention]

[0008] According to the present invention, a bipolar semiconductor device is provided that can suppress an increase in on-resistance and reduce reverse recovery current. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a schematic diagram of a PiN diode of the present invention. [Figure 2] FIG. 2 is a band diagram for explaining the state of carriers when a forward bias and a reverse bias are applied to the PiN diode of the present invention. [Figure 3] This is the configuration of a conventional PiN diode. [Figure 4] FIG. 1 is a circuit diagram including a PiN diode used in the simulation. [Figure 5] FIG. 10 is a diagram showing simulation results regarding on-resistance and reverse recovery current. [Figure 6] FIG. 10 is a diagram showing simulation results regarding on-resistance and reverse recovery current. [Figure 7] FIG. 10 is a diagram showing simulation results regarding on-resistance and reverse recovery current. [Figure 8] 10A and 10B are diagrams illustrating the trap density dependence of the on-resistance and reverse recovery characteristics of the PiN diode of the present invention. [Figure 9] FIG. 10 is a diagram showing the relationship between trap density and accumulated charge and the peak value of reverse recovery current. [Figure 10] 1 is a diagram illustrating the accumulated charge and reverse recovery characteristics of a PiN diode of the present invention and a conventional PiN diode. DETAILED DESCRIPTION OF THE INVENTION

[0010] As an example of a SiC bipolar semiconductor device, a PiN diode will be described. The n-type means that electrons are the majority carriers, and the p-type means that holes are the majority carriers. Also, + attached to n or p means that the impurity density is higher than n or p without + or n or p with a small number of +. Similarly, - attached to n or p means that the impurity density is lower than n or p without - or n or p with a small number of -. Note that n + type, n - The type is simply n-type, p ++ type, p + The type is sometimes simply referred to as p-type.

[0011] 1 is a schematic diagram of a PiN diode 1. The PiN diode 1 includes a cathode electrode 2, an anode electrode 3, a cathode region 10, a breakdown voltage maintaining layer 20, and an anode region 30.

[0012] A cathode electrode 2 is provided on one surface of the cathode region 10 (the surface opposite to the breakdown voltage maintaining layer 20), and an anode electrode 3 is provided on one surface of the contact layer 33 (the surface opposite to the trapping layer 32). The cathode electrode 2 and the anode electrode 3 are made of a conductive material such as a metal.

[0013] The cathode region 10 is made of n-type SiC. The breakdown voltage sustaining layer 20 is made of n-type SiC formed on one surface of the cathode region 10. The anode region 30 is made of p-type SiC formed on one surface of the breakdown voltage sustaining layer 20 (the surface opposite to the cathode region 10).

[0014] In detail, the anode region 30 is composed of a bonding layer 31, a trap layer 32, and a contact layer 33, which are stacked in this order from the side of the breakdown voltage sustaining layer 20. The bonding layer 31, the trap layer 32, and the contact layer 33 are all made of p-type SiC.

[0015] The trap layer 32 is formed on the junction layer 31 and is a layer that traps carriers. Specifically, the trap layer 32 contains traps (defects that serve as trapping centers for electrons or holes) that form energy levels that capture electrons or holes as carriers. In other words, the trap layer 32 is a region with a short carrier lifetime. Here, the carrier lifetime of the trap layer 32 is shorter than that of the junction layer 31.

[0016] Table 1 shows the film thickness, doping density, and trap density of each layer that constitutes the PiN diode 1. [Table 1]

[0017] As shown in Table 1, the trap density of the trap layer 32 is lower than the doping density of the anode region 30.

[0018] The traps in the trap layer 32 may be either donor type or acceptor type, but are preferably donor type traps that capture electrons in the conduction band.

[0019] The trap layer 32 has a larger electron capture cross section than a hole capture cross section. Specifically, when the electron capture cross section is σn and the hole capture cross section is σp, σn=5×10 -14 cm 2 and σp=1×10 -15 cm 2 is.

[0020] The trap layer 32 is spaced apart from the junction interface (pn junction surface) between the junction layer 31 and the breakdown voltage sustaining layer 20 by the film thickness of the junction layer 31 .

[0021] The PiN diode 1 having the above-described configuration can be manufactured, for example, as follows: First, a SiC substrate is prepared. There are no particular limitations on the polytype or off-angle of the SiC substrate.

[0022] Next, the cathode region 10 is formed on the SiC substrate with the film thickness and doping density shown in Table 1. Specifically, the cathode region 10 can be formed by epitaxially growing a SiC layer on the SiC substrate and mixing in an n-type dopant such as nitrogen.

[0023] Next, a breakdown voltage sustaining layer 20 and a bonding layer 31 are formed on the cathode region 10 with the film thickness and doping density shown in Table 1. Specifically, the breakdown voltage sustaining layer 20 can be formed by epitaxially growing SiC on the cathode region 10 and mixing in an n-type dopant such as nitrogen at that time. The bonding layer 31 can be formed by epitaxially growing SiC on the breakdown voltage sustaining layer 20 and mixing in a p-type dopant such as aluminum at that time.

[0024] Next, a trap layer 32 having the film thickness and trap density shown in Table 1 is formed on the bonding layer 31. The trap layer 32 can be formed by epitaxially growing a SiC layer on the bonding layer 31 and mixing in a p-type dopant and a trap dopant such as vanadium or boron during the growth. The trap density can be controlled by known methods such as adjusting the density of the dopant to be implanted, so a detailed explanation will be omitted. Alternatively, the trap layer 32 can be formed by irradiating the SiC layer formed on the bonding layer 31 with an electron beam or protons to form defects. In this case, the desired trap density can be achieved by adjusting the irradiation energy and dose of the electron beam.

[0025] Next, contact layer 33 having the film thickness and doping density shown in Table 1 is formed on trap layer 32. Contact layer 33 can be formed by epitaxially growing SiC on trap layer 32, mixing in a p-type dopant during the growth, and further injecting the p-type dopant at a higher density by ion implantation.

[0026] The doping densities of the cathode region 10, the breakdown voltage maintaining layer 20, the bonding layer 31, and the contact layer 33 can be controlled by a known method such as adjusting the density of the implanted impurities, and therefore detailed explanations thereof will be omitted.

[0027] The state of carriers when a forward bias and a reverse bias are applied to the PiN diode 1 configured as described above will be explained using Figure 2. Figure 2(a) shows a band diagram when a forward bias is applied to the PiN diode 1. When a forward bias is applied, some of the electrons injected into the conduction band are absorbed by the traps in the trap layer 32 of the anode region 30. The traps that have absorbed the electrons are now in a state where they can capture holes.

[0028] 2(b) shows the band diagram when a reverse bias is applied to the PiN diode 1. When switching from a forward bias to a reverse bias, holes accumulated in the breakdown voltage maintaining layer 20 flow out to the anode region 30 as a reverse recovery current, but some of the holes are captured by the traps that absorbed electrons during the forward bias. This makes it possible to reduce the reverse recovery current that flows out of the PiN diode 1 through the anode region 30 and anode electrode 3.

[0029] Simulations were performed to evaluate the on-resistance and reverse recovery current of the PiN diode 1 configured as described above and a conventional PiN diode without a trap layer. Figure 3 shows the configuration of the conventional PiN diode. Figure 4 is a circuit diagram including the PiN diode used in the simulation. Of the layers of the conventional PiN diode 100, the same layers as those in the PiN diode 1 of the present invention are designated by the same reference numerals, and duplicated explanations will be omitted.

[0030] 3, the PiN diode 100 has an anode region 30A that is composed of a bonding layer 31A and a contact layer 33. The bonding layer 31A is a layer made of p-type SiC, has a thickness of 4 μm, and a doping density of 1×10 18 cm -3The contact layer 33 is formed on the bonding layer 31A, and the total thickness of the anode region 30A is set to be the same as that of the anode region 30 of the present invention.

[0031] A double pulse measurement circuit including a PiN diode 1 or a PiN diode 100 was configured as shown in Figure 4, and the on-resistance and reverse recovery characteristics were simulated using the mixed mode of TCAD (manufactured by Silvaco). The simulation conditions were as follows: 3kV class PiN diode. (The substrate is simplified. Contact resistance is ignored. The operating area is S=0.01cm.) 2 (I decided to SRH recombination model only Carrier lifetime in each layer: 10ns (P ++ ; contact layer 33), 50 ns (P+; junction layer 31), 1 μs (i; breakdown voltage maintaining layer 20), 30 ns (N + ;Cathode region 10) Band gap narrowing was introduced. The band gap narrowing for each layer was 0.12 eV (P ++ ), 0.06 eV(P + ), 0.16 eV(N + ) The driving MOSFET is a Si nMOS (BSP89).

[0032] Figure 5 shows the simulation results for on-resistance and reverse recovery current. Figure 5(a) shows the forward characteristics (the relationship between the voltage applied to the anode electrode and the anode current), with the horizontal axis representing the forward bias voltage applied to the anode electrode and the vertical axis representing the anode current. "w / o Trap" refers to the forward characteristics of the PiN diode 100 without a trap layer (hereinafter referred to as the forward characteristics w / o), while "w / Trap" refers to the forward characteristics of the PiN diode 1 (hereinafter referred to as the forward characteristics w).

[0033] The forward characteristic w is shifted to the right more than the forward characteristic w / o. In other words, the forward characteristic w requires a higher voltage than the forward characteristic w / o even with the same current, and the PiN diode 1 has a higher on-resistance than the PiN diode 100.

[0034] Figure 5(b) shows the reverse recovery characteristics, which are changes in reverse recovery current over time, with the horizontal axis representing elapsed time and the vertical axis representing anode current. A positive value on the vertical axis indicates forward current, and a negative value indicates reverse current. "w / o Trap" refers to the reverse recovery characteristics of a PiN diode 100 without a trap layer (hereinafter referred to as "w / o reverse recovery characteristics"), while "w / Trap" refers to the reverse recovery characteristics of a PiN diode 1 (hereinafter referred to as "w reverse recovery characteristics").

[0035] In the section where reverse recovery current is generated by applying a reverse bias, the peak value of the reverse recovery characteristic w is smaller than that of the reverse recovery characteristic w / o. Also, the reverse recovery characteristic w has less accumulated charge than the reverse recovery characteristic w / o.

[0036] Thus, according to the simulation results shown in FIG. 5, the PiN diode 1 had a higher on-resistance but a lower reverse recovery current than the PiN diode 100.

[0037] The above simulation was performed on the PiN diode 100 by shortening the carrier lifetime in the breakdown voltage sustaining layer 20. The results are shown in Figure 6. Figure 6(a) is the same as Figure 5(a), Figure 6(b) is the same as Figure 5(b), and "LT" in the figures indicates the carrier lifetime in the breakdown voltage sustaining layer 20.

[0038] As shown in Figure 6(a), when the carrier lifetime was set to 1 μs, the forward characteristics w had a higher on-resistance than the forward characteristics w / o (LT = 1.0 μs). On the other hand, the forward characteristics w were almost the same as the forward characteristics w / o (LT = 0.3 μs).

[0039] As shown in Figure 6(b), the reverse recovery characteristic w has a smaller peak value than either of the two reverse recovery characteristics w / o (LT = 0.3, 1.0 μs). Also, the reverse recovery characteristic w has a smaller accumulated charge than either of the reverse recovery characteristics w / o (LT = 0.3, 1.0 μs).

[0040] As described above, according to the simulation results shown in FIG. 6, the PiN diode 1 of the present invention maintained an on-resistance equivalent to that of a PiN diode in which the carrier lifetime in the breakdown voltage maintaining layer 20 was shortened, and the reverse recovery current was reduced more than that of the PiN diode 100.

[0041] We simulated the proportion of holes that can be captured by the trap layer for the PiN diode 1 of the present invention. Figure 7(a) is a diagram similar to Figure 5(b), and only shows the reverse recovery characteristic w. Figure 7(b) is a diagram showing the distribution of carrier density as a function of distance from the anode region, with the horizontal axis representing the distance from the anode region 30 (the junction interface between the junction layer 31 and the breakdown voltage sustaining layer 20) and the vertical axis representing the carrier density (hole density).

[0042] The ratio R of traps captured by the trap layer 32 was calculated using the following formula.

number

[0043] Qcd was obtained by integrating the reverse recovery current in FIG. 7(a). Qh(@C) and Qh(@D) were obtained from FIG. 7(b). From the above formula, R=0.64. In other words, the percentage of traps that captured holes in the trap layer 32 was 64%. This percentage can be optimized by adjusting the capture cross-sectional area and the position at which the trap layer 32 is inserted into the anode region 30. Qh is obtained by integrating the hole density distribution in the breakdown voltage sustaining layer 20 shown in FIG. 7(b) as follows: Note that because these are holes emitted toward the anode region 30, integration was performed over a range from the boundary (approximately 1 μm) between the junction layer 31 and the breakdown voltage sustaining layer 20 in FIG. 7(b) to 25 μm.

number

[0044] The trap density dependence of the reverse recovery characteristics of the PiN diode 1 of the present invention will be explained using Figures 8 and 9. Figure 8(a) shows the forward characteristics w obtained by performing the above simulation while changing the trap density, and Figure 8(b) shows the reverse recovery characteristics w obtained by performing the above simulation while changing the trap density. Figure 9 shows the relationship between the trap density and the accumulated charge and the peak value of the reverse recovery current. In Figure 9, Qrr indicates the accumulated charge, and Irr indicates the peak value of the reverse recovery current.

[0045] As shown in Figure 8(a), the trap density is set to 1 × 10 16 cm -3 , 1×10 17 cm -3 , 3×10 17 cm -3 The forward characteristics w obtained by setting each of these parameters shifted to the right as the trap density increased, and the on-resistance increased. As shown in Figure 8(b), as the trap density increased, the peak value of the reverse recovery characteristics decreased and the stored charge also decreased. Furthermore, as shown in Figure 9, when the trap density was appropriately changed over a wider range than in Figure 8, a simulation was performed and the peak value of the reverse recovery current decreased and the stored charge decreased as the trap density increased.

[0046] As described above, the simulation results shown in FIGS. 8 and 9 confirm that the PiN diode 1 of the present invention can improve the reverse recovery characteristics by controlling the trap density.

[0047] The reverse recovery characteristics of the PiN diode 1 and the PiN diode 100 will be described using Figure 10. Figure 10(a) shows the relationship between the stored charge and the on-voltage in the reverse recovery characteristics, and Figure 10(b) shows the peak value of the current in the reverse recovery characteristics. In both figures, "carrier lifetime control" refers to the PiN diode 100 in which the carrier lifetime in the breakdown voltage maintaining layer 20 is appropriately set, and "trap density control" refers to the PiN diode 1 in which the trap density is appropriately set.

[0048] The accumulated charge in the PiN diode 1 does not absorb many electrons due to the low trap density in the trap layer. Therefore, as shown in Figure 10(a), the accumulated charge is not significantly improved compared to the PiN diode 100, which has a controlled carrier lifetime in the breakdown voltage sustaining layer. On the other hand, as shown in Figure 10(b), the peak value of the reverse recovery current of the PiN diode 1 is significantly reduced compared to the PiN diode 100 because the trap layer absorbs the charge that generates the large current at the beginning of reverse recovery.

[0049] Table 3 shows a comparison of the on-resistance, peak value of reverse recovery current, and stored charge of PiN diode 1 and PiN diode 100 (carrier lifetimes of 0.3 μs and 1.0 μs) based on the simulation results described above. [Table 3]

[0050] As shown in Figure 6(a), the PiN diode 100 with a carrier lifetime of 1.0 μs has the lowest on-resistance. The PiN diode 100 with a carrier lifetime of 0.3 μs and the PiN diode 1 with a carrier lifetime of 1.0 μs have almost the same on-resistance. As shown in Figure 6(b), the PiN diode 1 has the lowest peak value of reverse recovery current and the lowest stored charge.

[0051] The PiN diode of the present invention described above has a trap layer 32 in the anode region 30. With this configuration, it is possible to reduce the reverse recovery current that occurs when a reverse bias is applied, as shown in FIG. 2. Furthermore, as shown in Table 2, compared to the PiN diode 100, which has a shorter carrier lifetime, it is possible to suppress an increase in on-resistance and reduce the reverse recovery current. The reason why an increase in on-resistance can be suppressed is as follows. The injected carriers accumulated in the breakdown voltage maintaining layer 20 are sufficiently lower than the carrier density (hole density) present in the anode region 30 (see Table 1). Therefore, there is no need to increase the trap density. Because the trap density can be reduced in this way, the effect of the trap layer 32 on the on-resistance is small.

[0052] Furthermore, the trap density of the trap layer 32 is lower than the doping density of the anode region 30. By setting such a trap density, it is possible to suppress an increase in the on-resistance of the PiN diode 1 and reduce the reverse recovery current.

[0053] The traps in the trap layer 32 are donor type, which makes it difficult for the electrons trapped in the traps to be thermally released, thereby preventing a decrease in the number of holes that can be captured when a reverse bias is applied.

[0054] Furthermore, the trapping layer 32 has a larger electron capture cross section than the hole capture cross section. This allows electrons to be trapped when a forward bias is applied. However, if the hole capture cross section is made too small, it will not be possible to trap holes in the reverse recovery current, so it must be made larger to some extent. Specifically, σn is 1×10 -14 cm 2 Above, σp is 1×10 -15 cm 2 It is preferable that the above is set.

[0055] Furthermore, the trap layer 32 is formed at a position away from the junction interface between the anode region 30 and the breakdown voltage maintaining layer 20. If the trap layer 32 is provided at the junction interface, a significant decrease in injection efficiency may occur due to an increase in recombination current, but by providing the junction layer 31, the trap layer is less likely to affect the junction interface, thereby preventing a significant decrease in injection efficiency.

[0056] Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments. For example, the film thicknesses, doping densities, and trap densities of the cathode region 10, the breakdown voltage maintaining layer 20, the bonding layer 31, the trap layer 32, and the contact layer 33 are not limited to those shown in Table 1.

[0057] The cathode region 10 has a doping density of 1×10 18 cm -3 or more, and the film thickness is 10 μm or more. The breakdown voltage maintaining layer 20 has a doping density of 1×10 16 cm -3 The thickness is 10 μm or more. The junction layer 31 has a doping density of 1×10 17 cm -3 The film thickness is in the range of 0.5 to 1 μm. The trapping layer 32 has a doping density of 1×10 17 cm -3 The film thickness is in the range of 1 to 3 μm, and the trap density is 1×10 14 ~5×10 17 cm -3 The range is. The contact layer 33 has a doping density of 1×10 18 cm -3 The film thickness is in the range of 0.2 to 3 μm.

[0058] Furthermore, although the PiN diode in which the trap layer 32 is of the donor type has been described, it may be of the acceptor type.

[0059] Although the PiN diode has been described as an embodiment of the bipolar semiconductor device of the present invention, the present invention is not limited thereto. The present invention can also be applied to various bipolar semiconductor devices using SiC, such as npn bipolar transistors, IGBTs, GTOs, SIAFETs, SIJFETs, thyristors, MCTs (Mos Controlled Thyristors), SiCGTs (SiC Commutated Gate Thyristors), ESTs (Emitter Switched Thyristors), and BRTs (Base Resistance Controlled Thyristors). [Explanation of symbols]

[0060] 1... PiN diode (bipolar semiconductor device), 2... cathode electrode, 3... anode electrode, 10... cathode region, 20... breakdown voltage maintaining layer, 30, 30A... anode region, 31, 31A... junction layer, 32... trap layer, 33... contact layer

Claims

1. A cathode region made of n-type SiC; a voltage-resistant layer formed on one surface of the cathode region; an anode region made of p-type SiC formed on an opposite side of the breakdown voltage sustaining layer from the cathode region, a trap layer that traps carriers is provided in the anode region; The trap density of the trap layer is lower than the doping density of the anode region.

1. A bipolar semiconductor device comprising:

2. A cathode region made of n-type SiC; a voltage-resistant layer formed on one surface of the cathode region; an anode region made of p-type SiC formed on an opposite side of the breakdown voltage sustaining layer from the cathode region, a trap layer that traps carriers is provided in the anode region; The trapping layer is a donor type 1. A bipolar semiconductor device comprising:

3. A cathode region made of n-type SiC; a voltage-resistant layer formed on one surface of the cathode region; an anode region made of p-type SiC formed on an opposite side of the breakdown voltage sustaining layer from the cathode region, a trap layer that traps carriers is provided in the anode region; The trap layer has a larger electron capture cross section than a hole capture cross section.

1. A bipolar semiconductor device comprising:

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