Light-emitting diode element

Abstract

Provided is a light-emitting diode element (1) comprising: a semiconductor substrate (10) having a first surface (10a) and a second surface (10b) on the reverse side from the first surface (10a); a semiconductor lamination section (20) formed on the first surface (10a) of the semiconductor substrate (10); a first electrode (51) connected to part of the semiconductor lamination section (20) on the semiconductor substrate (10) side; and a second electrode (52) connected to a part of the semiconductor lamination section (20) on the opposite side from the semiconductor substrate (10). The semiconductor lamination section (20) includes an n-type semiconductor layer (20A), an active layer (25) having a p-type conductivity type and being laminated on the n-type semiconductor layer (20A), and a p-type semiconductor layer (20B) laminated on the active layer (25) on the reverse side from the n-type semiconductor layer (20A). The active layer (25) has a multiple quantum well structure in which a barrier layer containing AlInAs and a well layer containing InAsSb are laminated alternatingly. The grating constant of the barrier layer is smaller than the grating constant of the n-type semiconductor layer (20A), and the grating constant of the well layer is greater than the grating constant of the n-type semiconductor layer (20A).

Description

[Technical Field]

[0001] The present disclosure relates to a light emitting diode device. [Background technology]

[0002] Patent Document 1 describes a semiconductor laser device. In this semiconductor laser element, an n-type AlGaAs cladding layer, a GaAs lower optical waveguide layer, a GaInAs / GaNAs multiple quantum well active layer, a GaAs upper optical waveguide layer, a p-type AlGaAs cladding layer, and a p-type GaAs contact layer are sequentially stacked on an n-type GaAs substrate. The multiple quantum well active layer is configured with a GaInAs quantum well layer sandwiched between GaNas barrier layers on the top and bottom. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2004-172439 Summary of the Invention [Problem to be solved by the invention]

[0004] Incidentally, an AlInAs / InAsSb multiple quantum well active layer can be considered for use in infrared LEDs (Light Emitting Diodes) with an emission wavelength of 3 μm to 5 μm. According to the findings of the present inventors, in such infrared LEDs, even if the number of quantum wells is increased to a certain level (for example, 10 or more), the light emission output tends not to increase in proportion to the increase in the number of quantum wells.

[0005] Therefore, an object of the present disclosure is to provide a light-emitting diode element capable of improving light emission output. [Means for solving the problem]

[0006] As a result of intensive research to solve the above problems, the inventors have discovered that in an LED using an AlInAs / InAsSb multiple quantum well active layer, by doping the active layer with p-type impurities to make the active layer p-type (by making electrons the minority carriers in the active layer), the number of quantum wells can be increased, thereby improving the light emission output. The present disclosure has been made based on this discovery and through further research.

[0007] A light-emitting diode element according to the present disclosure comprises a semiconductor substrate having a first surface and a second surface opposite to the first surface, a semiconductor laminate formed on the first surface of the semiconductor substrate, a first electrode connected to a part of the semiconductor laminate on the semiconductor substrate side, and a second electrode connected to a part of the semiconductor laminate on the opposite side to the semiconductor substrate, wherein the semiconductor laminate includes an n-type semiconductor layer, an active layer having p-type conductivity and laminated on the n-type semiconductor layer, and a p-type semiconductor layer laminated on the active layer on the side opposite to the n-type semiconductor layer, and the active layer has a multiple quantum well structure formed by alternately laminating barrier layers containing AlInAs and well layers containing InAsSb, and the lattice constant of the barrier layers may be smaller than the lattice constant of the n-type semiconductor layers, and the lattice constant of the well layers may be larger than the lattice constant of the n-type semiconductor layers.

[0008] This light-emitting diode device includes an active layer having a multiple quantum well structure formed by alternately stacking barrier layers containing AlInAs and well layers containing InAsSb. The active layer has a p-type conductivity. Therefore, as shown by the above findings, increasing the number of quantum wells can improve the light-emitting output. As described above, in this light-emitting diode device, increasing the number of quantum wells can improve the light-emitting output. However, as the number of quantum wells increases, strain may accumulate during fabrication, increasing the number of crystal defects. In contrast, in this light-emitting diode device, the lattice constant of the barrier layers is smaller than that of the n-type semiconductor layer, and the lattice constant of the well layers is larger than that of the n-type semiconductor layer. As a result, this light-emitting diode device can improve the light-emitting output by suitably increasing the number of quantum wells while suppressing the increase in crystal defects due to strain accumulation.

[0009] In the light-emitting diode device according to the present disclosure, the active layer may include 10 or more pairs of barrier layers and well layers. Thus, with this light-emitting diode device, it is possible to increase the number of quantum wells to 10 or more and improve the light output.

[0010] In the light-emitting diode device according to the present disclosure, the p-type impurity concentration in the active layer is 1.0×10 16 / cm 3 Over 1.9 x 10 18 / cm 3 In this case, it is possible to more reliably improve the light emission output.

[0011] In the light-emitting diode device according to the present disclosure, the lattice mismatch between the average lattice constant of the barrier layer and the well layer and the lattice constant of the n-type semiconductor layer may be 0.9% or less, which can more reliably suppress strain accumulation even when the number of quantum wells in the active layer is increased.

[0012] The light-emitting diode device according to the present disclosure may include an n-type barrier layer containing AlInAs and disposed between the n-type semiconductor layer and the active layer, and a p-type barrier layer containing AlInAs and disposed between the active layer and the p-type semiconductor layer. In this case, providing the barrier layers on both sides of the active layer makes it possible to suitably confine carriers in the active layer.

[0013] In the light-emitting diode device according to the present disclosure, the semiconductor laminate may include a base having a third surface facing the side opposite the semiconductor substrate, and a mesa portion provided on the base so as to protrude from a partial area of ​​the third surface, having a top surface facing the side opposite the base, and including at least an active layer, wherein the first electrode is formed on the third surface so as to surround the mesa portion when viewed from a direction intersecting the third surface, and the second electrode is formed on the top surface so as to cover a central area of ​​the top surface, and the second surface of the semiconductor substrate serves as the light-emitting surface. In this case, the first electrode surrounding the mesa portion including the active layer and the second electrode on the top surface of the mesa portion form a current path over a wider area of ​​the mesa portion, and the second surface of the semiconductor substrate opposite the top surface of the mesa portion on which the second electrode is formed serves as the light-emitting surface, thereby more reliably improving the light-emitting output. [Effects of the Invention]

[0014] According to the present disclosure, it is possible to provide a light-emitting diode element capable of improving light emission output. [Brief explanation of the drawings]

[0015] [Figure 1] FIG. 1 is a plan view of a light-emitting diode element according to this embodiment. [Figure 2] FIG. 2 is a cross-sectional view taken along line II-II in FIG. [Figure 3] FIG. 3 is a graph showing the light output characteristics of the light emitting diode element. [Figure 4] FIG. 4 is a schematic diagram for explaining the principle of the expected improvement in light emission output. [Figure 5] FIG. 5 is a graph showing the light output characteristics of the light emitting diode element. [Figure 6] FIG. 6 is a cross-sectional view for explaining the action and effect of the light-emitting diode element shown in FIGS. [Figure 7] FIG. 7 is a cross-sectional view for explaining the action and effect of the light-emitting diode element shown in FIGS. [Figure 8] FIG. 8 is a cross-sectional view of a light-emitting diode element according to a modified example. DETAILED DESCRIPTION OF THE INVENTION

[0016] An embodiment will be described in detail below with reference to the drawings. In the description of the drawings, identical or overlapping elements are given the same reference numerals, and overlapping descriptions may be omitted. In addition, the drawings may show a Cartesian coordinate system defined by the X-axis, Y-axis, and Z-axis.

[0017] FIG. 1 is a plan view of a light-emitting diode device according to this embodiment. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1. The light-emitting diode device 1 shown in FIGS. 1 and 2 is, for example, an infrared LED emitting light at a wavelength of 3 μm to 5 μm. The light-emitting diode device 1 includes a semiconductor substrate 10, a semiconductor laminate portion 20, a first electrode 51, and a second electrode 52. The semiconductor substrate 10 has a main surface (first surface) 10a and a back surface (second surface) 10b opposite to the main surface 10a. The semiconductor substrate 10 is made of, for example, GaAs.

[0018] The semiconductor laminate 20 includes a base 30 and a mesa 40. The base 30 is formed on the principal surface 10a of the semiconductor substrate 10. The base 30 is in contact with the principal surface 10a. The base 30 includes a surface (third surface) 30a facing the side opposite the semiconductor substrate 10. The mesa 40 is provided on the base 30 so as to protrude from a partial area of ​​the surface 30a of the base 30. The mesa 40 includes a top surface 40a facing the side opposite the semiconductor substrate 10 and the base 30, and a side surface 40s extending from the top surface 40a to the surface 30a of the base 30.

[0019] The semiconductor laminate 20 includes at least an n-type semiconductor layer 20A, an active layer 25 laminated on the n-type semiconductor layer 20A, and a p-type semiconductor layer 20B laminated on the active layer 25 on the side opposite to the n-type semiconductor layer 20A. These are laminated in the order of the n-type semiconductor layer 20A, the active layer 25, and the p-type semiconductor layer 20B from the semiconductor substrate 10 side. Each layer of the semiconductor laminate 20 will be described in detail.

[0020] The semiconductor laminate 20 includes a buffer layer 21, a current spreading layer 22, a current blocking layer 23, a barrier layer 24, an active layer 25, a barrier layer 26, a semiconductor layer 27, and a contact layer 28, which are laminated in this order on the principal surface 10a of the semiconductor substrate 10. The buffer layer 21 is an undoped layer and includes, for example, InAs and GaAs. As an example, the buffer layer 21 can be formed by growing a GaAs layer to a thickness of about 0.2 μm on the semiconductor substrate 10, growing an InAs layer to a thickness of about 0.2 μm on the GaAs layer at a low temperature, and further growing an InAs layer to a thickness of about 0.2 μm on the InAs layer at a normal temperature.

[0021] The current spreading layer 22 has an n-type conductivity. The current spreading layer 22 includes, for example, InAs. For example, the current spreading layer 22 can be formed by growing an InAs layer with a thickness of about 4.0 μm on the buffer layer 21. For example, the n-type impurity concentration in the current spreading layer 22 is 3.0×10 18 / cm 3 The current spreading layer 22 makes contact with the first electrode 51 as described later, and also functions as a contact layer.

[0022] The current blocking layer 23 has n-type conductivity. The current blocking layer 23 includes, for example, InAs. For example, the current blocking layer 23 can be formed by growing an InAs layer with a thickness of about 0.65 μm on the current spreading layer 22. The n-type impurity concentration in the current blocking layer 23 is lower than the n-type impurity concentration in the current spreading layer 22, and for example, is 3.0×10 17 / cm 3The current spreading layer 22 and the current blocking layer 23 constitute the n-type semiconductor layer 20A. The material of the n-type semiconductor layer 20A may be, for example, AlInAs or InGaAs. The n-type semiconductor layer 20A may also include a layer different from the current spreading layer 22 and the current blocking layer 23.

[0023] The barrier layer (n-type barrier layer) 24 is disposed between the n-type semiconductor layer 20A and the active layer 25. Here, the barrier layer 24 is in contact with the n-type semiconductor layer 20A (current blocking layer 23) and the active layer 25. The barrier layer 24 has n-type conductivity. The barrier layer 24 contains Al. More specifically, the barrier layer 24 contains AlInAs. For example, the barrier layer 24 can be formed by growing an AlInAs layer on the current blocking layer 23 to a thickness that does not exceed the critical film thickness for the n-type semiconductor layer 20A (for example, about 0.02 μm). The n-type impurity concentration in the barrier layer 24 is, for example, 4.5×10 18 / cm 3 The Al composition in the barrier layer 24 is equal to or greater than the Al composition in the barrier layer of the active layer 25, which will be described later.

[0024] The active layer 25 has p-type conductivity. The active layer 25 has a multiple quantum well structure formed by alternately stacking barrier layers having p-type conductivity and containing AlInAs and well layers having p-type conductivity and containing InAsSb. The number of quantum wells in the active layer 25, i.e., the number of pairs of barrier layers and well layers, is 10 or more. There is no upper limit to the number of quantum wells in the active layer 25 (it may be several hundred, for example), but from the viewpoint of ease of manufacture, it may be set to 80 or less, or even 40 or less, for example.

[0025] In this case, the thickness of the active layer 25 can be, for example, 0.2 μm to 1.6 μm, or even 0.2 μm to 0.8 μm. The p-type impurity concentration in the active layer 25 is in a range in which electrons become minority carriers in each of the barrier layer and the well layer, and is, for example, 1.0×10 16 / cm 3 Over 1.9 x 10 18 / cm3 or less, and even 1.0 × 10 17 / cm 3 Over 1.9 x 10 18 / cm 3 The thickness of each of the barrier layer and the well layer can be set within a range not exceeding the critical film thickness for the n-type semiconductor layer 20A.

[0026] On the other hand, in the active layer 25, the lattice constant of the barrier layer is smaller than that of the n-type semiconductor layer 20A, and the lattice constant of the well layer is larger than that of the n-type semiconductor layer 20A. More specifically, in the active layer 25, the lattice mismatch between the average lattice constant of the barrier layer and the well layer and the lattice constant of the n-type semiconductor layer 20A is 0.9% or less.

[0027] The barrier layer (p-type barrier layer) 26 is disposed between the active layer 25 and the p-type semiconductor layer 20B. Here, the barrier layer 26 is in contact with the p-type semiconductor layer 20B (semiconductor layer 27) and the active layer 25. The barrier layer 26 has p-type conductivity. The barrier layer 26 contains Al. More specifically, the barrier layer 26 contains AlInAs. For example, the barrier layer 26 can be formed by growing an AlInAs layer on the active layer 25 to a thickness of, for example, about 0.02 μm. The p-type impurity concentration in the barrier layer 26 is, for example, 3.0×10 18 / cm 3 The Al composition in the barrier layer 26 is equal to or greater than the Al composition in the barrier layer of the active layer 25.

[0028] The semiconductor layer 27 includes, for example, InAs. As an example, the semiconductor layer 27 can be formed by growing an InAs layer on the barrier layer 26 to a thickness of about 0.5 μm. The semiconductor layer 27 has p-type conductivity. The p-type impurity concentration in the semiconductor layer 27 is higher than the p-type impurity concentration in the barrier layer 26 and lower than the p-type impurity concentration in the contact layer 28. The p-type impurity concentration in the semiconductor layer 27 is, for example, 5.0×10 18 / cm 3The semiconductor layer 27 has, for example, a function as a cladding layer and a function as a current spreading layer.

[0029] The contact layer 28 has a p-type conductivity. The contact layer 28 includes, for example, InAs. For example, the contact layer 28 can be formed by growing an InAs layer with a thickness of about 0.05 μm on the semiconductor layer 27. For example, the p-type impurity concentration in the contact layer 28 is 1.0×10 19 / cm 3 The contact layer 28 makes contact with the second electrode 52. The semiconductor layer 27 and the contact layer 28 form a p-type semiconductor layer 20B.

[0030] The base 30 includes the buffer layer 21 and a portion of the n-type semiconductor layer 20A facing the buffer layer 21 (here, a portion of the current spreading layer 22 facing the buffer layer 21). The mesa 40 includes at least the active layer 25, and here includes the remainder of the n-type semiconductor layer 20A, the barrier layers 24 and 26, the active layer 25, and the p-type semiconductor layer 20B. An insulating film 41 is provided on the surface 30a of the base 30, the side surfaces 40s of the mesa 40, and a portion of the top surface 40a of the mesa 40. The insulating film 41 is made of, for example, Al2O3.

[0031] An opening 41a is formed in the insulating film 41 on the surface 30a of the base 30. The opening 41a has a shape that follows the outline of the mesa portion 40 when viewed from the Z direction intersecting the surface 30a. Here, since the outline of the mesa portion 40 is rectangular when viewed from the Z direction, the opening 41a is formed in a rectangular ring shape so as to surround the mesa portion 40. As a result, a portion of the surface 30a that surrounds the mesa portion 40 when viewed from the Z direction is exposed from the insulating film 41 through the opening 41a.

[0032] An opening 41b is formed in the insulating film 41 on the top surface 40a. This exposes most of the top surface 40a, including a central area 40ar of the top surface 40a, from the insulating film 41. When viewed from the Z direction intersecting the top surface 40a, the central area 40ar is the area excluding the outer edge of the top surface 40a. The central area 40ar has an outer shape that follows the outer shape of the mesa portion 40, and is rectangular in this case.

[0033] The first electrode 51 and the second electrode 52 are connected to the semiconductor laminate 20 via openings 41a and 41b in the insulating film 41. More specifically, the first electrode 51 is an n-electrode and includes a first portion 51A and a second portion 51B. The first portion 51A is formed on the surface 30a of the base 30 via the insulating film 41 so as to surround the mesa 40 when viewed from the Z direction, and is in contact with the surface 30a of the base 30 via the opening 41a in the insulating film 41. The surface 30a of the base 30 is a portion of the surface of the semiconductor laminate 20 facing the semiconductor substrate 10. In this case, it is the surface of a portion of the current spreading layer 22 facing the side opposite to the semiconductor substrate 10. Therefore, the first electrode 51 is connected to a portion of the semiconductor laminate 20 facing the semiconductor substrate 10. The second portion 51B extends from the first portion 51A and is disposed on the surface 30a via the insulating film 41. The second portion 51B functions as an n-electrode pad.

[0034] The second electrode 52 is a p-electrode and includes a first portion 52A, a second portion 52B, and a third portion 52C. The first portion 52A is formed on the top surface 40a so as to cover at least the central area 40ar when viewed from the Z direction, and is in contact with the top surface 40a through an opening 41b in the insulating film 41. Therefore, the second electrode 52 is connected to a part of the semiconductor laminate 20 on the side opposite to the semiconductor substrate 10. The second portion 52B extends from the first portion 52A and is disposed on the side surface 40s of the mesa portion 40 via the insulating film 41. The third portion 52C extends from the second portion 52B and is disposed on the surface 30a of the base 30 via the insulating film 41. The third portion 52C functions as a p-type electrode pad.

[0035] In this way, most of the top surface 40a (central area 40ar) of the mesa portion 40 is covered with the second electrode 52. Therefore, in the light-emitting diode element 1, the back surface 10b of the semiconductor substrate 10 serves as a light-emitting surface. In other words, the light-emitting diode element 1 is configured as a back-side emission type.

[0036] Next, the operation and effect of the light-emitting diode element 1 will be described. FIG. 3 is a graph showing the light-emitting output characteristics of the light-emitting diode element. FIG. 3(a) shows the relationship between the number of quantum wells and the light-emitting output, and FIG. 3(b) shows the relationship between the injection current and the light-emitting output. The value of the "non-doped active layer" point among the points in FIG. 3(a) is normalized to 1.0 when the active layer is non-doped and the number of quantum wells is 20. Furthermore, the value of the "p-doped active layer" point among the points in FIG. 3(a) is normalized to 1.0 when the active layer is p-doped and the number of quantum wells is 20.

[0037] In addition, in (a) of FIG. 3, the value for the light-emitting diode element 1 according to this embodiment is shown as "p-doped active layer," and the value for the light-emitting diode element according to the comparative example is shown as "non-doped active layer." In both the light-emitting diode element 1 according to this embodiment and the light-emitting diode element according to the comparative example, the thickness of each of the barrier layer and well layer is 10 nm, and the injection current is 80 mA. In (b) of FIG. 3, the value for the light-emitting diode element 1 according to this embodiment is shown as "p-doped," and the value for the light-emitting diode element according to the comparative example is shown as "non-doped."

[0038] As shown in FIG. 3(a), the light-emitting diode device 1 according to this embodiment has improved light output compared to the light-emitting diode device according to the comparative example. Furthermore, in the light-emitting diode device according to the comparative example, the light output improves as the number of quantum wells increases until the number of quantum wells reaches 20. However, once the number of quantum wells exceeds 20, the light-emitting output does not improve as the number of quantum wells increases. Furthermore, as shown in FIG. 3(b), the light-emitting diode device 1 according to this embodiment has improved light output compared to the light-emitting diode device according to the comparative example across almost the entire range of injection current from 0 mA to 500 mA. Note that in FIG. 3(a), the light-emitting diode device 1 according to this embodiment and the light-emitting diode device according to the comparative example are normalized separately. Therefore, although the light-emitting output ratio is the same (1.0) when the number of quantum wells is 20, the actual light-emitting output value is higher for the light-emitting diode device 1 according to this embodiment than for the light-emitting diode device according to the comparative example, even when the number of quantum wells is 20 (see FIG. 3(b)).

[0039] According to the findings of the present inventors, the light emitting diode element 1 according to this embodiment has improved light output due to the following reasons. Fig. 4 is a schematic diagram for explaining the assumed principle of improved light output. Fig. 4(a) shows a light emitting diode element according to a comparative example (in which the active layer 25A is non-doped), and Fig. 4(b) shows the light emitting diode element 1 according to this embodiment.

[0040] As shown in FIG. 4(a), in the light-emitting diode device according to the comparative example, the non-doped active layer 25A has a - Therefore, when a current is injected using the first electrode 51 and the second electrode 52, + Holes Ch are injected as minority carriers from the p-type semiconductor layer 20B into the active layer 25A, causing light emission in a region R in the active layer 25A where the electrons Ce and holes Ch exist.

[0041] 4(b), in the light-emitting diode device 1 according to this embodiment, the minority carriers injected into the active layer 25 having the p-type conductivity are electrons Ce. The diffusion length L of the carriers is given by (diffusion coefficient D × carrier lifetime τ). 1 / 2 The diffusion coefficient D is proportional to the mobility μ. In compound semiconductors used in light-emitting diodes, electrons tend to have a higher mobility than holes, and this tendency is particularly strong in materials that emit infrared light. For example, in the case of InAs, the mobility μ is approximately 33,000 cm for electrons and approximately 33,000 cm for holes. 2 / V / sec, and for holes Ch, it is approximately 450cm 2 / V / sec. In the case of InSb, the mobility μ is approximately 77000 cm 2 / V / sec, and for holes Ch, it is approximately 1100cm 2 In the case of InAsSb, which is a mixed crystal of these, the mobility μ varies depending on the composition ratio of As and Sb, and the mobility μ is approximately 33,000 to 77,000 cm 2 / V / sec, and for holes Ch, it is approximately 450 to 1100 cm 2 / V / sec. In AlInAs, it changes depending on the composition ratio of Al and In. In the composition range of band gap 1.2 eV or less, the mobility μ is about 9000 to 33000 cm 2 / V / sec, and for holes Ch, it is approximately 280 to 450 cm 2 / V / sec. Therefore, the diffusion length L of the electrons Ce is longer than the diffusion length L of the holes Ch, and the electrons Ce, which are minority carriers, are widely diffused inside the active layer 25.

[0042] As a result, in the light-emitting diode device 1 according to this embodiment, the region R that contributes to light emission is enlarged compared to the light-emitting diode device according to the comparative example. This applies not only to the depth direction (Z direction) from the p-type semiconductor layer 20B toward the n-type semiconductor layer 20A, but also to the lateral directions (X direction and Y direction) that intersect with the depth direction, improving the minority carrier distribution inside the active layer 25. For at least the above reasons, it is believed that the light-emitting diode device 1 according to this embodiment has improved light output.

[0043] As shown in the dashed line graph in FIG. 5 and as described above with reference to FIG. 3, when the p-type impurity concentration in the active layer 25 is 1.0×10 18 / cm 3 When the p-type impurity concentration in the active layer 25 is about 1.9×10, the light emission output is improved over almost the entire range of the injection current from 0 mA to 500 mA, compared to the non-doped case. 18 / cm 3 If the injected current is about 100%, the light output will start to fall below that of the non-doped case in a certain range of the injected current.

[0044] This is thought to be due in part to an increase in crystal defects caused by the introduction of p-type impurities and a decrease in the diffusion length due to a decrease in the minority carrier lifetime. Therefore, taking this into consideration, the upper limit of the p-type impurity concentration in the active layer 25 is set to 1.9×10 18 / cm 3 It can be about.

[0045] As described above, the light-emitting diode device 1 according to this embodiment includes the active layer 25 having a multiple quantum well structure formed by alternately stacking barrier layers containing AlInAs and well layers containing InAsSb. The active layer 25 has p-type conductivity. Therefore, as shown by the above findings, it is possible to improve the light output by increasing the number of quantum wells.

[0046] As described above, in the light-emitting diode device 1 according to this embodiment, the light-emitting output can be improved by increasing the number of quantum wells. However, generally, as the number of quantum wells increases, strain may accumulate during fabrication, increasing the number of crystal defects. In contrast, in the light-emitting diode device 1, the lattice constant of the barrier layer is smaller than that of the n-type semiconductor layer 20A, and the lattice constant of the well layer is larger than that of the n-type semiconductor layer 20A. This makes it possible to improve the light-emitting output by suitably increasing the number of quantum wells while suppressing the increase in crystal defects due to strain accumulation.

[0047] In the light-emitting diode device 1 according to this embodiment, the active layer 25 includes 10 or more pairs of barrier layers and well layers. Thus, the light-emitting diode device 1 can increase the number of quantum wells to 10 or more, thereby improving the light output.

[0048] In the light-emitting diode device 1 according to this embodiment, the p-type impurity concentration in the active layer 25 is 1.0×10 16 / cm 3 Over 1.9 x 10 18 / cm 3 As a result, it is possible to more reliably improve the light emission output.

[0049] Furthermore, in the light-emitting diode device 1 according to this embodiment, the lattice mismatch between the average lattice constant of the barrier layer and well layer and the lattice constant of the n-type semiconductor layer is 0.9% or less. Therefore, even if the number of quantum wells in the active layer 25 is increased, strain accumulation can be more reliably suppressed.

[0050] The light-emitting diode element 1 according to this embodiment also includes an n-type barrier layer 24 containing AlInAs and disposed between the n-type semiconductor layer 20A and the active layer 25, and a p-type barrier layer 26 containing AlInAs and disposed between the active layer 25 and the p-type semiconductor layer 20B. By providing the barrier layers 24 and 26 on both sides of the active layer 25 in this manner, carriers can be suitably confined in the active layer 25.

[0051] Furthermore, in the light-emitting diode device 1 according to this embodiment, the semiconductor laminate 20 includes a base 30 having a surface 30a facing the side opposite the semiconductor substrate 10, and a mesa 40 provided on the base 30 so as to protrude from a partial area of ​​the surface 30a, having a top surface 40a facing the side opposite the base 30, and including at least an active layer 25. A first electrode 51 is formed on the surface 30a so as to surround the mesa 40 when viewed from the Z direction intersecting the surface 30a, and a second electrode 52 is formed on the top surface 40a so as to cover a central area 40ar of the top surface 40a. The back surface 10b of the semiconductor substrate 10 serves as a light-emitting surface.

[0052] Therefore, as shown in Figure 6, the first electrode 51 surrounding the mesa portion 40 including the active layer 25 and the second electrode 52 on the top surface 40a of the mesa portion 40 form a current path CR over a wider area of ​​the mesa portion 40, and by using the back surface 10b of the semiconductor substrate 10 opposite the top surface 40a of the mesa portion 40 on which the second electrode 52 is formed as the light emitting surface, it is possible to more reliably improve the light emitting output.

[0053] 7, this configuration does not include any intervening layer that blocks light LA ​​emitted from the active layer 25 toward the back surface 10b of the semiconductor substrate 10, and light LB emitted from the active layer 25 toward the opposite side of the semiconductor substrate 10 can be reflected by the second electrode 52 toward the semiconductor substrate 10 and emitted from the back surface 10b. Furthermore, the n-type semiconductor layer 20A, the buffer layer 21, and the semiconductor substrate 10 have relatively high transmittance, so there is little loss of light LA ​​and LB. As a result, the light emission output can be improved more reliably.

[0054] Examples of the light-emitting diode device 1 according to this embodiment will be given below. [First Example]

[0055] On a GaAs substrate as the semiconductor substrate 10, a GaAs buffer layer (0.2 μm), a low-temperature InAs buffer layer (0.2 μm), and an InAs buffer layer (0.2 μm) were sequentially grown as the buffer layer 21. On this InAs buffer layer, an n-type impurity was doped at 3.0×10 to form a current diffusion layer 22 serving as both an n-type contact layer and a current diffusion layer. 18 / cm 3 A doped InAs layer was grown to a thickness of 4.0 μm. On this InAs layer, an n-type impurity was doped at 3.0×10 17 / cm 3 A doped InAs layer was grown to a thickness of 0.6 μm. On this InAs layer, an n-type barrier layer 24 was formed by doping 3.0×10 18 / cm 3 Doped Al x An InAs layer (composition x=0.15) was grown to a thickness of 20 nm.

[0056] On this InAs layer, 10 layers of 10 nm thick AlInAs barrier layers and 10 nm thick InAsSb well layers were alternately formed as the active layer 25 to form a multiple quantum well structure. At this time, p-type impurities were doped in all layers at a concentration of 1.0 × 10 18 / cm 3 On this multi-quantum well structure, a p-type barrier layer 26 was formed by doping with 3.0×10 p-type impurities. 18 / cm 3 Doped Al x An InAs layer (composition x = 0.15) was grown to 20 nm. The Al composition x of the barrier layer was set higher than that of the barrier layer, but the thickness and Al composition were set so as not to exceed the critical thickness for the n-type semiconductor layer.

[0057] On this AlInAs layer, a semiconductor layer 27 is formed by doping 5.0×10 p-type impurities. 18 / cm 3 A doped InAs layer was grown to 0.5 μm. Furthermore, a p-type impurity of 1.0×10 19 / cm 3A doped InAs layer was grown to a thickness of 0.1 μm. The epitaxial wafer thus completed was cut into chips using a normal semiconductor process to obtain light-emitting diode elements. This light-emitting diode element also provided the same effects as the light-emitting diode element 1 described above. The light-emitting wavelength of the light-emitting diode element according to the first example is, for example, about 4.3 μm. [Second Example]

[0058] On a GaAs substrate as the semiconductor substrate 10, a GaAs buffer layer (0.2 μm), a low-temperature InAs buffer layer (0.2 μm), and an InAs buffer layer (0.2 μm) were sequentially grown as the buffer layer 21. On this InAs buffer layer, an n-type impurity was doped at 3.0×10 to form a current diffusion layer 22 serving as both an n-type contact layer and a current diffusion layer. 18 / cm 3 Doped Al x An InAs layer (composition x=0.05) was grown to a thickness of 4.0 μm. On this AlInAs layer, an n-type impurity of 3.0×10 17 / cm 3 Doped Al x An InAs layer (composition x=0.05) was grown to a thickness of 0.6 μm. On this InAs layer, an n-type barrier layer 24 was formed by doping 3.0×10 18 / cm 3 Doped Al x An InAs layer (composition x=0.2) was grown to a thickness of 20 nm.

[0059] On this InAs layer, 10 layers of 10 nm thick AlInAs barrier layers and 10 nm thick InAsSb well layers were alternately formed as the active layer 25 to form a multiple quantum well structure. At this time, p-type impurities were doped in all layers at a concentration of 1.0 × 10 18 / cm 3 On this multi-quantum well structure, a p-type barrier layer 26 was formed by doping with 3.0×10 p-type impurities. 18 / cm 3 Doped Al xAn InAs layer (composition x = 0.15) was grown to 20 nm. The Al composition x and y of the barrier layer were set higher than those of the barrier layer, but the thickness and Al composition were set so as not to exceed the critical thickness for the n-type semiconductor layer.

[0060] On this AlInAs layer, a semiconductor layer 27 is formed by doping 5.0×10 p-type impurities. 18 / cm 3 Doped Al x An InAs layer (composition x=0.05) was grown to a thickness of 0.5 μm. Furthermore, as a contact layer 28, a p-type impurity was added at 1.0×10 19 / cm 3 Doped Al x An InAs layer (composition x=0.05) was grown to a thickness of 0.1 μm. The epitaxial wafer thus completed was cut into chips by a normal semiconductor process to obtain light-emitting diode elements. This light-emitting diode element also provided the same effects as the light-emitting diode element 1 described above. The light-emitting wavelength of the light-emitting diode element according to the first example is, for example, about 3.3 μm. [Third Example]

[0061] A GaAs buffer layer (0.2 μm), a GaSb buffer layer (0.1 μm), and an InAs buffer layer (0.1 μm) were sequentially grown on a GaAs substrate as a semiconductor substrate 10 as a buffer layer 21. On this InAs buffer layer, an n-type impurity was doped at 3.0×10 to form a current diffusion layer 22 serving as both an n-type contact layer and a current diffusion layer. 18 / cm 3 Doped Al x An InAs layer (composition x=0.05) was grown to a thickness of 4.0 μm. On this AlInAs layer, an n-type impurity of 3.0×10 17 / cm 3 Doped Al x An InAs layer (composition x=0.05) was grown to a thickness of 0.6 μm. On this InAs layer, an n-type barrier layer 24 was formed by doping 3.0×10 18 / cm 3 Doped Al x An InAs layer (composition x=0.2) was grown to a thickness of 20 nm.

[0062] On this InAs layer, 10 layers of 10 nm thick AlInAs barrier layers and 10 nm thick InAsSb well layers were alternately formed as the active layer 25 to form a multiple quantum well structure. At this time, p-type impurities were doped in all layers at a concentration of 1.0 × 10 18 / cm 3 On this multi-quantum well structure, a p-type barrier layer 26 was formed by doping with 3.0×10 p-type impurities. 18 / cm 3 Doped Al x An InAs layer (composition x = 0.15) was grown to 20 nm. The Al composition x and y of the barrier layer were set higher than those of the barrier layer, but the thickness and Al composition were set so as not to exceed the critical thickness for the n-type semiconductor layer.

[0063] On this AlInAs layer, a semiconductor layer 27 is formed by doping 5.0×10 p-type impurities. 18 / cm 3 Doped Al x An InAs layer (composition x=0.05) was grown to a thickness of 0.5 μm. Furthermore, as a contact layer 28, a p-type impurity was added at 1.0×10 19 / cm 3 Doped Al x An InAs layer (composition x=0.05) was grown to a thickness of 0.1 μm. The epitaxial wafer thus completed was cut into chips by a normal semiconductor process to obtain light-emitting diode elements. This light-emitting diode element also provided the same effects as the light-emitting diode element 1 described above. The light-emitting wavelength of the light-emitting diode element according to the first example is, for example, about 3.3 μm. [Fourth Example]

[0064] On a GaAs substrate as the semiconductor substrate 10, a GaAs buffer layer (0.2 μm), a low-temperature InAs buffer layer (0.2 μm), and an InAs buffer layer (0.2 μm) were sequentially grown as the buffer layer 21. On this InAs buffer layer, an n-type impurity was doped at 3.0×10 to form a current diffusion layer 22 serving as both an n-type contact layer and a current diffusion layer. 18 / cm 3 Doped InGax An As layer (composition x=0.13) was grown to a thickness of 4.0 μm. On this InGaAs layer, an n-type impurity of 3.0×10 17 / cm 3 Doped InGa x An As layer (composition x=0.13) was grown to a thickness of 0.6 μm. On this InGaAs layer, an n-type barrier layer 24 was formed by doping 3.0×10 18 / cm 3 Doped Al x An InAs layer (composition x=0.2) was grown to a thickness of 20 nm.

[0065] On this InAs layer, 10 layers of 10 nm thick AlInAs barrier layers and 10 nm thick InAsSb well layers were alternately formed as the active layer 25 to form a multiple quantum well structure. At this time, p-type impurities were doped in all layers at a concentration of 1.0 × 10 18 / cm 3 On this multi-quantum well structure, a p-type barrier layer 26 was formed by doping with 3.0×10 p-type impurities. 18 / cm 3 Doped Al x An InAs layer (composition x = 0.15) was grown to 20 nm. The Al composition x and y of the barrier layer were set higher than those of the barrier layer, but the thickness and Al composition were set so as not to exceed the critical thickness for the n-type semiconductor layer.

[0066] On this AlInAs layer, a semiconductor layer 27 is formed by doping 5.0×10 p-type impurities. 18 / cm 3 Doped InGa x An As layer (composition x=0.13) was grown to a thickness of 0.5 μm. Furthermore, as a contact layer 28, a p-type impurity was added at 1.0×10 19 / cm 3 Doped InGa xAn InAs layer (composition x=0.13) was grown to a thickness of 0.1 μm. The epitaxial wafer thus completed was cut into chips using a normal semiconductor process to obtain light-emitting diode elements. This light-emitting diode element also provided the same effects as the light-emitting diode element 1 described above. The light-emitting wavelength of the light-emitting diode element according to the first example is, for example, about 3.3 μm.

[0067] The above-described embodiment and examples are merely illustrative of one aspect of the present disclosure, and therefore the present disclosure is not limited to the above-described light-emitting diode elements and may be modified as desired.

[0068] For example, in the above embodiment, a back-emission type light-emitting diode element 1 has been exemplified. However, as shown in Fig. 8, the light-emitting diode element 1 may be configured such that an opening 52h is formed in the first portion 52A of the second electrode 52 so that the central portion of the central area 40ar of the top surface 40a of the mesa portion 40 is exposed, and light is emitted through the opening 52h. In this case, the light-emitting diode element 1 is configured as a front-emission type.

[0069] In the above embodiment, the semiconductor substrate 10 is exemplified as the substrate. However, instead of the semiconductor substrate 10, a substrate such as a polymer film, a glass substrate, a plastic, or a metal plate may be used. Furthermore, in the above embodiment, the conductivity types of the semiconductor layers are n-type and p-type from the semiconductor substrate 10 side, but may be p-type and n-type from the semiconductor substrate 10 side. [Industrial Applicability]

[0070] A light emitting diode element capable of improving light output is provided. [Explanation of symbols]

[0071] 1...light-emitting diode element, 10...semiconductor substrate, 10a...main surface (first surface), 10b...back surface (second surface), 20...semiconductor laminate portion, 20A...n-type semiconductor layer, 20B...p-type semiconductor layer, 24...barrier layer (n-type barrier layer), 25...active layer, 26...barrier layer (p-type barrier layer), 30...base portion, 30a...surface (third surface), 40...mesa portion, 40a...top surface, 40ar...central area, 51...first electrode, 52...second electrode.

Claims

1. a semiconductor substrate having a first surface and a second surface opposite the first surface; a semiconductor laminate portion formed on the first surface of the semiconductor substrate; a first electrode connected to a part of the semiconductor laminate portion on the semiconductor substrate side; a second electrode connected to a part of the semiconductor laminate portion on the opposite side to the semiconductor substrate; Equipped with The semiconductor laminate portion is an n-type semiconductor layer; an active layer having p-type conductivity and stacked on the n-type semiconductor layer; a p-type semiconductor layer stacked on the active layer on the side opposite to the n-type semiconductor layer; Including, the active layer has a multiple quantum well structure formed by alternately stacking barrier layers containing AlInAs and well layers containing InAsSb; the lattice constant of the barrier layer is smaller than the lattice constant of the n-type semiconductor layer, the lattice constant of the well layer is larger than the lattice constant of the n-type semiconductor layer; Light-emitting diode element.

2. the active layer includes 10 or more pairs of the barrier layer and the well layer; The light-emitting diode device according to claim 1 .

3. a p-type impurity concentration in the active layer is 1.0×10 / cm or more and 1.9×10 / cm or less; The light-emitting diode element according to claim 1 or 2.

4. a lattice mismatch between the average lattice constant of the barrier layer and the well layer and the lattice constant of the n-type semiconductor layer is 0.9% or less; The light-emitting diode element according to any one of claims 1 to 3.

5. an n-type barrier layer including AlInAs, the n-type barrier layer being disposed between the n-type semiconductor layer and the active layer; a p-type barrier layer including AlInAs and disposed between the active layer and the p-type semiconductor layer; The light-emitting diode element according to any one of claims 1 to 4, comprising:

6. The semiconductor laminate portion is a base having a third surface facing the opposite side to the semiconductor substrate; a mesa portion provided on the base portion so as to protrude from a partial area of ​​the third surface, the mesa portion having a top surface facing the opposite side to the base portion, and including at least the active layer; and the first electrode is formed on the third surface so as to surround the mesa portion when viewed in a direction intersecting the third surface, the second electrode is formed on the top surface so as to cover a central area of ​​the top surface; the second surface of the semiconductor substrate is a light emitting surface; The light-emitting diode element according to any one of claims 1 to 5.

Images