Semiconductor Devices

Abstract

A semiconductor device according to the present invention includes: a semiconductor substrate; a first electroconductive member 25 that is formed on the semiconductor substrate and that has a first linear section 36 extending along a principal surface 11 of the semiconductor substrate; and an organic insulating layer 55 that is formed on the semiconductor substrate and that covers the first electroconductive member 25. The first linear section 36 includes a first lateral edge section 46 formed of a curve 47 that, in plan view, is bent alternately towards one side and the other side in a direction Y1 intersecting the longitudinal direction of the first linear section 36. The first linear section 36 includes: a base section 40; and a first lateral section 41 including protruding sections 44, 48 that protrude from the base section 40 in the direction Y1 intersecting the longitudinal direction of the first linear section 36 and recessed sections 45, 49 that are recessed with respect to the protruding sections 44, 48. The first lateral edge section 46 may be formed of the curve 47 that, in plan view, continuously connects the protruding sections 44, 48 and the recessed sections 45, 49 along the longitudinal direction of the first linear section 36.

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] For example, Patent Document 1 discloses a semiconductor package including a conductive member, a semiconductor device, a bonding layer, and a sealing resin. The semiconductor device is a flip-chip type LSI. The semiconductor device has an element body, multiple electrodes, and a surface protection film. The surface protection film is made of polyimide and covers the bases of the multiple electrodes. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-167330 Summary of the Invention [Problem to be solved by the invention]

[0004] When the ambient temperature of a structure in which conductive members such as wiring and electrodes are covered with an organic insulating layer fluctuates, high residual stress may occur in the straight sections of the conductive members. This stress is thought to be caused by external forces being applied to the organic insulating layer in contact with the conductive members when they expand and contract due to temperature changes.

[0005] An embodiment of the present disclosure provides a semiconductor device capable of reducing stress on the sides of the straight portion of a conductive member. [Means for solving the problem]

[0006] A semiconductor device according to one embodiment of the present disclosure includes a semiconductor substrate, a first conductive member formed on the semiconductor substrate and having a first linear portion extending along a main surface of the semiconductor substrate, and an organic insulating layer formed on the semiconductor substrate and covering the first conductive member, wherein the first linear portion includes a first side edge portion formed by a curve that alternately bends to one side and the other side in a direction intersecting the longitudinal direction of the first linear portion in a planar view. [Effects of the Invention]

[0007] According to the semiconductor device according to the embodiment of the present disclosure, the stress on the side of the first linear portion of the first conductive member can be reduced. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a schematic perspective view of a semiconductor device according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is an enlarged plan view of the semiconductor chip of FIG. [Figure 3] FIG. 3 is an enlarged view (first embodiment) of the part surrounded by the two-dot chain line III in FIG. [Figure 4] FIG. 4 is a cross-sectional view taken along line IV-IV shown in FIG. [Figure 5] FIG. 5 is an enlarged view (second embodiment) of the part surrounded by the two-dot chain line III in FIG. [Figure 6] FIG. 6 is a cross-sectional view taken along line VI-VI shown in FIG. [Figure 7] FIG. 7 is a flow chart showing a part of the manufacturing process of the semiconductor chip of FIG. 1 in the order of steps. [Figure 8] FIG. 8 is a diagram for explaining the stress relaxation effect of the semiconductor device. DETAILED DESCRIPTION OF THE INVENTION

[0009] <Embodiments of the present disclosure> First, embodiments of the present disclosure will be listed and described.

[0010] A semiconductor device (1) according to one embodiment of the present disclosure includes a semiconductor substrate (4, 15), a first conductive member (25) formed on the semiconductor substrate (4, 15) and having a first linear portion (36) extending along a main surface (11) of the semiconductor substrate (4, 15), and an organic insulating layer (55) formed on the semiconductor substrate (4, 15) and covering the first conductive member (25), wherein the first linear portion (36) includes a first side edge portion (46) formed by a curve (47) that alternately bends to one side and the other side in a direction intersecting the longitudinal direction of the first linear portion (36) in a planar view.

[0011] For example, if the first side edge of the first linear portion is straight, fluctuations in ambient temperature can cause high stress on the first side of the first linear portion due to differences in thermal expansion coefficients between the first conductive member and the organic insulating layer. If this stress applies an external force to the organic insulating layer during expansion and contraction due to temperature changes, strain may occur in the organic insulating layer, degrading its mechanical properties. Therefore, in the semiconductor device according to this embodiment, the first side edge is curved, which can disperse stress generated on the first side of the first linear portion. This can reduce overall stress on the first side of the first linear portion of the first conductive member. As a result, strain generated in the organic insulating layer during expansion and contraction due to temperature changes can be suppressed.

[0012] In a semiconductor device (1) according to one embodiment of the present disclosure, the first straight portion (36) includes a base portion (40) to which a joining member can be connected, and a first side portion (41) including convex portions (44, 48) protruding from the base portion (40) in a direction intersecting the longitudinal direction of the first straight portion (36) and concave portions (45, 49) recessed relative to the convex portions (44, 48), and the first side edge portion (46) may be formed by a curve (47) that continuously connects the convex portions (44, 48) and the concave portions (45, 49) along the longitudinal direction of the first straight portion (36) in a plan view.

[0013] According to this configuration, stress generated in the first side portion, including the convex portion and the concave portion, is dispersed, so that even if additional stress is applied to the first linear portion when connecting the bonding member to the base portion of the first linear portion, a deterioration in the mechanical properties of the organic insulating layer can be suppressed. Furthermore, the first conductive member does not meander to form an S-shape overall, but rather the stress dispersion structure is configured by selectively forming convex portions and concave portions on the first side portion of the first linear portion. Therefore, there is no need to increase the installation space for the first conductive member according to this embodiment, which can suppress an increase in the size of the semiconductor device.

[0014] In a semiconductor device (1) according to one embodiment of the present disclosure, the base portion (40) is formed in a strip shape having a first width (W2), and the first width (W2) of the base portion (40) may be 10 times or more the protrusion amount (P1) of the convex portions (44, 48) from the base portion (40).

[0015] According to this configuration, for example, by forming a protrusion with a protrusion amount of about 1 / 10 the width of an existing first conductive member (e.g., wiring, electrode, etc.), it is possible to achieve the effect of stress dispersion in the first conductive member. Conversely, even if a stress dispersion structure is formed by the protrusion and recess, the first width of the base portion can be maintained relatively wide. As a result, it is possible to maintain a wide range of options for bonding members that can be bonded to the base portion (e.g., the shape and thickness of the bonding member).

[0016] In a semiconductor device (1) according to one embodiment of the present disclosure, the first conductive member (25) includes a tip portion (39) including a part of the first straight portion (36) and a second straight portion (37) connected to the first straight portion (36) via a corner portion (38), and the first side edge portion (46) may be selectively formed on the first straight portion (36) out of the first straight portion (36) and the second straight portion (37).

[0017] According to this configuration, a curved first side edge portion is formed on the first linear portion including the tip portion where stress is likely to occur due to fluctuations in ambient temperature, so that stress can be effectively distributed in the first conductive member.

[0018] In a semiconductor device (1) according to one embodiment of the present disclosure, the tip portion (39) of the first conductive member (25) may have a first side surface (52) formed by a first arc (51) having a first radius of curvature (R1) in a planar view, and the first side edge portion (46) of the first conductive member (25) may have a second side surface (54) formed by a second arc (53) having a second radius of curvature (R2) smaller than the first radius of curvature (R1) in a planar view.

[0019] In a semiconductor device (1) according to one embodiment of the present disclosure, the first conductive member (25) includes, in a cross-sectional view, a first base layer (26) and a first covering layer (27) laminated on the first base layer (26) so as to protrude laterally beyond an end face (29) of the first base layer (26), and the first side edge portion (46) may be selectively formed on the first covering layer (27).

[0020] With this configuration, the curved first side edge is selectively formed on the first covering layer, and does not necessarily have to be formed on the first base layer, which reduces the number of steps required to form the first side edge.

[0021] In the semiconductor device (1) according to one embodiment of the present disclosure, the organic insulating layer (55) may have a pad opening (56) that exposes the base portion (40) of the first linear portion (36) as a pad (14).

[0022] According to this configuration, a bonding member such as a bonding wire can be connected to the base portion of the first linear portion through the pad opening.

[0023] The semiconductor device (1) according to one embodiment of the present disclosure may further include a second conductive member (59) connected to the base portion (40) of the first linear portion (36) within the organic insulating layer (55).

[0024] With this configuration, the stress dispersion structure prevents the deterioration of the mechanical properties of the organic insulating layer around the second conductive member, thereby improving the connection reliability between the first conductive member (first linear portion) and the second conductive member.

[0025] In a semiconductor device (1) according to one embodiment of the present disclosure, the second conductive member (59) has a third straight portion (72) extending along the main surface (11) of the semiconductor substrate (4, 15), and the third straight portion (72) may include a second side edge portion (79) formed by a curve (80) that alternately bends to one side and the other side in a direction intersecting the longitudinal direction of the third straight portion (72) in a plan view.

[0026] With this configuration, since the second side edge portion is formed in a curve, stress generated in the second side portion of the third linear portion can be dispersed. This reduces the overall stress in the second side portion of the third linear portion of the second conductive member. As a result, distortion generated in the organic insulating layer during expansion and contraction due to temperature changes can be suppressed.

[0027] In a semiconductor device (1) according to one embodiment of the present disclosure, the second conductive member (59) includes, in a cross-sectional view, a second base layer (60) and a second coating layer (61) laminated on the second base layer (60) so as to protrude laterally beyond an end face (63) of the second base layer (60), and the second side edge portion (79) may be selectively formed on the second coating layer (61).

[0028] According to this configuration, the curved second side edge is selectively formed on the second covering layer, and does not necessarily have to be formed on the second base layer, which reduces the number of steps required to form the second side edge.

[0029] A semiconductor device (1) according to one embodiment of the present disclosure may include an insulating layer stack structure (17) formed between the first conductive member (25) and the semiconductor substrate (4, 15), and including at least a first inorganic insulating layer (18, 57) and a second inorganic insulating layer (19, 58) stacked on the first inorganic insulating layer (18, 57).

[0030] The semiconductor device (1) according to one embodiment of the present disclosure may include an integrated circuit element (16) formed on the semiconductor substrate (4, 15) and electrically connected to the first conductive member (25).

[0031] With this configuration, as described above, the stress on the first side portion of the first linear portion of the first conductive member can be reduced, thereby providing a semiconductor device including an integrated circuit with high insulation reliability of the organic insulating layer.

[0032] In the above, the numbers in parentheses represent the reference symbols of the corresponding components in the detailed description that follows, but these reference symbols are not intended to limit the above components as equivalents to the components that will be described later. Detailed Description of Embodiments of the Present Disclosure Next, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following detailed description, there are a plurality of components with names each having an ordinal number, but the ordinal numbers do not necessarily match the ordinal numbers of the components described in the claims.

[0033] FIG. 1 is a schematic perspective view of a semiconductor device 1 according to an embodiment of the present disclosure.

[0034] In this embodiment, the semiconductor device 1 is a so-called SOP (Small Outline Package). The semiconductor device 1 includes a sealing resin 2, a die pad 3, a semiconductor chip 4, a conductive bonding material 5, a plurality of lead terminals 6, and a plurality of conductive wires .

[0035] The sealing resin 2 may contain, for example, an epoxy resin. The sealing resin 2 may also be referred to as a resin package. The sealing resin 2 is formed in a rectangular parallelepiped shape. The sealing resin 2 includes a first main surface 8 on one side, a second main surface 9 on the other side, and four side surfaces 10A, 10B, 10C, and 10D connecting the first main surface 8 and the second main surface 12. The four side surfaces 10A to 10D specifically include a first side surface 10A, a second side surface 10B, a third side surface 10C, and a fourth side surface 10D. The first side surface 10A and the second side surface 10B face each other. The third side surface 10C and the fourth side surface 10D face each other.

[0036] The die pad 3 is disposed within the sealing resin 2. The die pad 3 may be exposed from the second main surface 9. The die pad 3 includes a metal plate formed in a rectangular parallelepiped shape. The die pad 3 may include at least one of Fe, Au, Ag, Cu, and Al. The die pad 3 may have an outer surface on which at least one of a Ni plating layer, an Au plating layer, an Ag plating layer, and a Cu plating layer is formed.

[0037] The plurality of lead terminals 6 include a first lead terminal 6A, a second lead terminal 6B, a third lead terminal 6C, a fourth lead terminal 6D, a fifth lead terminal 6E, a sixth lead terminal 6F, a seventh lead terminal 6G, and an eighth lead terminal 6H. The number of lead terminals 6 is adjusted depending on the function of the semiconductor chip 4 and is not limited to the number shown in FIG. 1.

[0038] The four lead terminals 6A to 6D are arranged on the first side surface 10A side of the sealing resin 2. The four lead terminals 6A to 6D are arranged at intervals from the die pad 3. The four lead terminals 6A to 6D are arranged at intervals in the direction in which the first side surface 10A extends. The four lead terminals 6A to 6D are drawn out from inside the sealing resin 2 across the first side surface 10A to the outside of the sealing resin 2.

[0039] The four lead terminals 6E to 6H are arranged on the second side surface 10B side of the sealing resin 2. The four lead terminals 6E to 6H are arranged at intervals from the die pad 3. The four lead terminals 6E to 6H are arranged at intervals in the direction in which the second side surface 10B extends. The four lead terminals 6E to 6H are drawn from inside the sealing resin 2 across the second side surface 10B to the outside of the sealing resin 2.

[0040] The lead terminals 6 may contain at least one of Fe, Au, Ag, Cu, and Al. The lead terminals 6 may have outer surfaces on which at least one of a Ni plating layer, an Au plating layer, an Ag plating layer, and a Cu plating layer is formed.

[0041] The semiconductor chip 4 includes, for example, an LSI (Large Scale Integration) chip. The semiconductor chip 4 is disposed on a die pad 3. The semiconductor chip 4 has a first main surface 11 on one side and a second main surface 12 on the other side. A plurality of element regions 13 are formed on the first main surface 11 of the semiconductor chip 4, in which elements constituting an LSI circuit are fabricated. The plurality of element regions 13 may include, for example, a diode region 13A, a transistor region 13B, a resistor region 13C, etc. A plurality of pads 14 are formed on the first main surface 11 of the semiconductor chip 4. The plurality of pads 14 are arranged on the first main surface 11 of the semiconductor chip 4 on the side of the four lead terminals 6A to 6D and the four lead terminals 6E to 6H. The plurality of pads 14 are electrically connected to a functional element 16 (a circuit element constituting the LSI), which will be described later.

[0042] The conductive bonding material 5 is interposed between the semiconductor chip 4 and the die pad 3 and bonds the semiconductor chip 4 to the die pad 3. The conductive bonding material 5 includes solder or a conductive paste. The solder may be lead-free solder. The solder may include at least one of SnAgCu, SnZnBi, SnCu, SnCuNi, and SnSbNi. The metal paste may include at least one of Au, Ag, and Cu. The conductive bonding material 5 is preferably made of silver paste. The silver paste particularly preferably includes sintered silver paste. The sintered silver paste may include a paste in which nano-sized or micro-sized Ag particles are dispersed in an organic solvent.

[0043] The number of conductive wires 7 is adjusted depending on the function of the semiconductor chip 4 and is not limited to the number shown in FIG. 1. The conductive wires 7 electrically connect the lead terminals 6 and the pads 14. In this embodiment, the conductive wires 7 include aluminum wires as an example of bonding wires. Instead of aluminum wires, the conductive wires 7 may be gold wires or copper wires.

[0044] The semiconductor device 1 may be packaged in a form other than SOP. For example, the semiconductor device 1 may have a TO (Transistor Outline), a QFN (Quad For Non-Lead Package), a DFP (Dual Flat Package), a DIP (Dual Inline Package), a QFP (Quad Flat Package), a SIP (Single Inline Package), or an SOJ (Small Outline J-leaded Package), or various other similar package forms.

[0045] Fig. 2 is an enlarged plan view of the semiconductor chip 4 in Fig. 1, showing the periphery of the pad 14. Fig. 3 is an enlarged view (first form) of the portion surrounded by the two-dot chain line III in Fig. 2. Fig. 4 is a cross-sectional view taken along line IV-IV in Fig. 3.

[0046] Next, a first embodiment of the semiconductor chip 4 will be described with reference to FIGS.

[0047] First, regarding the cross-sectional structure of the semiconductor chip 4, referring to FIG. 4, the semiconductor chip 4 includes a semiconductor substrate 15. The semiconductor substrate 15 may be an epitaxial substrate including, for example, a base substrate containing Si and an epitaxial layer grown on the base substrate. Furthermore, since the semiconductor chip 4 is formed in layers, it may also be referred to as a semiconductor layer.

[0048] The first main surface 11 and the second main surface 12 of the semiconductor chip 4 may be the first main surface 11 and the second main surface 12 of the semiconductor substrate 15. A plurality of functional elements 16 are formed on the first main surface 11 of the semiconductor substrate 15. The plurality of functional elements 16 may include circuit elements that constitute an LSI, such as diodes, transistors, and resistors.

[0049] An insulating layer stack structure 17 is formed on the first main surface 11 of the semiconductor substrate 15. The insulating layer stack structure 17 includes a stack structure of multiple inorganic insulating layers. In this embodiment, the insulating layer stack structure 17 includes a first insulating layer 18, a second insulating layer 19, a third insulating layer 20, a fourth insulating layer 21, and a fifth insulating layer 22, which are stacked in this order from the first main surface 11 of the semiconductor substrate 15. Each of the insulating layers 18 to 22 of the insulating layer stack structure 17 includes an inorganic insulating material, such as silicon oxide (SiO2) or silicon nitride (SiN).

[0050] Each of the insulating layers 18-22 has a plurality of wirings 23 and a plurality of vias 24 that connect the wirings 23 located above and below each other. The wirings 23 are electrically connected to the functional element 16 through the vias 24. As a result, the insulating layer stack structure 17 is configured as a multilayer wiring structure in which the wirings 23 electrically connected to the functional element 16 are provided across the insulating layers 18-22. The plurality of wirings 23 may include, for example, a known wiring material such as Cu or Al. The plurality of vias 24 may include, for example, a known via material such as W.

[0051] A first conductive member 25 is formed on the insulating layer stack structure 17. In this embodiment, the first conductive member 25 is the uppermost wiring layer that forms the pads 14 of the semiconductor chip 4, and may also be referred to as the first wiring layer. The first conductive member 25 is formed by a plurality of conductive layers, and may also be referred to as the first conductive layer.

[0052] 4, the first conductive member 25 includes a first base layer 26 and a first coating layer 27 laminated on the first base layer 26. The first base layer 26 contains, for example, Cu and may include a Cu plating layer in this embodiment. The first base layer 26 is connected to, for example, the via 24. As a result, the first conductive member 25 is electrically connected to the functional element 16 via the via 24 and the wiring 23.

[0053] The first covering layer 27 covers the first base layer 26. The first covering layer 27 integrally includes a first covering portion 28 that contacts the upper surface of the first base layer 26 and covers the first base layer 26, and a first protruding portion 30 that protrudes laterally beyond an end face 29 of the first base layer 26. As a result, a first step 32 corresponding to the protrusion amount of the first protruding portion 30 is formed between the end face 29 of the first base layer 26 and an end face 31 of the first covering layer 27. The first protruding portion 30 may hang down below the first covering portion 28 (toward the first main surface 11 of the semiconductor substrate 15). Therefore, both portions of the upper surface 33 of the first covering layer 27 may be inclined downward relative to the portion on the first base layer 26. The first covering layer 27 may be formed thinner than the first base layer 26. For example, the first base layer 26 may have a thickness of 2 μm or more and 3 μm or less, and the first coating layer 27 may have a thickness of 1 μm or more and 2 μm or less.

[0054] In this embodiment, the first coating layer 27 includes multiple coating layers. The first coating layer 27 may include, for example, a first layer 34 in contact with the first base layer 26 and a second layer 35 laminated on the first layer 34. The first layer 34 may contain, for example, Ni and may include a Ni-plated layer in this embodiment. The second layer 35 may contain, for example, Pd and may include a Pd-plated layer in this embodiment. Although not shown, the first coating layer 27 may further include an Au-plated layer on its outermost surface. The first layer 34 and the second layer 35 are laminated over both the first coating portion 28 and the first protruding portion 30. As a result, the boundary between the first layer 34 and the second layer 35 may be exposed at the end surface 31 of the first coating layer 27.

[0055] Next, the planar structure of the first conductive member 25 will be described. With reference to FIG. 2, the first conductive member 25 extends over a wide area on the first main surface 11 of the semiconductor substrate 15. In this embodiment, the first conductive member 25 includes a first linear portion 36 and a second linear portion 37. The first linear portion 36 and the second linear portion 37 are each formed in a strip shape in a plan view and are integrally connected via corner portions 38. Note that the first linear portion 36 and the second linear portion 37 are defined as strip-shaped because they are shown in FIG. 2 as being relatively wide compared to their length. In contrast, the first linear portion 36 and the second linear portion 37 may be defined as line-shaped or the like if their widths are very small compared to their lengths.

[0056] The first linear portion 36 includes a tip portion 39 that is an end portion of the first conductive member 25. An end portion (not shown) of the first conductive member 25 opposite the tip portion 39 may be connected to the above-described via 24. The first linear portion 36 and the second linear portion 37 may intersect with each other at an obtuse angle at a corner portion 38, as in the two first conductive members 25 on the left side of FIG. 2 . The first linear portion 36 and the second linear portion 37 may intersect with each other at a right angle at the corner portion 38, as in the two first conductive members 25 on the right side of FIG. 2 . In other words, the angle of the corner portion 38 may be an obtuse angle, a right angle, or, of course, an acute angle.

[0057] A more detailed description of the shape of the first straight portion 36 will be provided with reference to Fig. 3. In Fig. 3, the longitudinal direction (extension direction) of the first straight portion 36 is defined as a first direction X1, and the direction perpendicular to the first direction X1 is defined as a second direction Y1.

[0058] The first linear portion 36 includes a strip-shaped first base portion 40 extending in the first direction X1, and first side portions 41 integrally formed on both sides of the first base portion 40 in the second direction Y1. The first base portion 40 is a conveniently set strip-shaped region that can be extracted from the first linear portion 36 while maintaining substantially the same outer shape as the first linear portion 36, such as the inner region of a first boundary portion 42 indicated by a dashed line in FIG. 3 or the inner region of a first boundary portion 43 indicated by a dashed line in FIG. 3.

[0059] The first base portion 40 may have a width that allows connection of a joining member such as the aforementioned conductive wire 7. The first base portion 40 may also have a first width W2 that is 80% or more, preferably 90% or more, of the width W1 of the first linear portion 36. For example, the width W1 of the first linear portion 36 may be 12 μm or more and 25 μm or less, and the first width W2 of the first base portion 40 may be 10 μm or more and 20 μm or less. The width W1 of the first linear portion 36 may be the distance between the apex of the first protrusion 44 on one side and the apex of the first protrusion 44 on the other side in the second direction Y1.

[0060] In this embodiment, the first side portion 41 is an outer region of the first boundary portion 42 or an outer region of the first boundary portion 43, and has an uneven structure that does not affect the outer shape of the first linear portion 36. More specifically, the first side portion 41 includes a first protrusion 44 that protrudes from the first base portion 40 in the second direction Y1 and a first recess 45 that is recessed relative to the first protrusion 44. In this embodiment, the first linear portion 36 has a first side edge portion 46 formed by a curve that alternately curves to one side (the left side of the drawing) and the other side (the right side of the drawing) in the second direction Y1. The first side edge portion 46 is an outer line of the first linear portion 36 that extends in the first direction X1 of the first linear portion 36 in a plan view, and forms a side surface of the first linear portion 36. Therefore, the first side portion 41 of the first straight portion 36 is the area between the first base portion 40 and the first side edge portion 46, and the first convex portion 44 and the first concave portion 45 that constitute the first side portion 41 are formed by the curved first side edge portion 46 that is continuously connected along the first direction X1.

[0061] The protrusion amount P1 of the first convex portion 44 of the first side portion 41 may be any amount that does not significantly change the outer shape of the first linear portion 36. For example, compared to the first width W2 of the first base portion 40, the protrusion amount P1 may be 1 / 10 or less of the first width W2 (i.e., the first width W2 may be 10 times or more the protrusion amount P1). In other words, even if a stress dispersion structure is formed by the first convex portion 44 and the first concave portion 45, the first width W2 of the first base portion 40 can be maintained relatively wide. As a result, many options for bonding members that can be bonded to the first base portion 40 remain (for example, the shape and thickness of wires or wiring).

[0062] In this embodiment, the curved first side edge 46 may be a sine curve 47 extending along the first direction X1. As a result, the first side portion 41 includes a plurality of first curved protrusions 48 and a plurality of first curved recesses 49 formed alternately along the first direction X1. In this case, the first width W2 of the first base portion 40 may be five times or more the amplitude A1 of the sine curve 47 from the first reference line 50 shown by the two-dot chain line in FIG. 3 .

[0063] The first boundaries 42, 43 between the first side portion 41 and the first base portion 40 may be defined, for example, by a line (dotted line in Figure 3) formed by connecting the tops of the multiple first recesses 45 along the first direction X1, or by a line (dashed line in Figure 3) parallel to the line, formed at a position slightly inward from the tops of the multiple first recesses 45.

[0064] The tip portion 39 of the first conductive member 25 has a first side surface 52 formed by a first circular arc 51 having a first radius of curvature R1 in a plan view. In comparison to this first side surface 52, the first side edge portion 46 may have a second side surface 54 formed by a second circular arc 53 having a second radius of curvature R2 smaller than the first radius of curvature R1 in a plan view. When the first side edge portion 46 includes a sinusoidal curve 47, the curved surfaces of the first curved convex portion 48 and the first curved concave portion 49 may each be formed by the second circular arc 53.

[0065] In this embodiment, a pair of first side edges 46 including the sine curves 47 are formed along the first direction X1. That is, both side edges of the first linear portion 36 may be first side edges 46 including the sine curves 47. The pair of sine curves 47 may include one sine curve 47A and the other sine curve 47B. When comparing the one sine curve 47A and the other sine curve 47B, the positions of the first curved convex portions 48 in the first direction X1 may be different from each other. For example, in the second direction Y1, the first curved convex portion 48 of the one sine curve 47A may be offset from the first curved convex portion 48 of the other sine curve 47B.

[0066] In this embodiment, in the second direction Y1, the first curved convex portion 48 of one sine curve 47A faces the first curved concave portion 49 of the other sine curve 47B. Also, the first curved convex portion 48 of the other sine curve 47B faces the first curved concave portion 49 of the one sine curve 47A. As a result, in the first direction X1, the first curved convex portions 48 (first curved concave portions 49) are alternately formed on the first side portion 41 including one sine curve 47A and the first side portion 41 including the other sine curve 47B.

[0067] As such, the first straight portion 36 has a first side portion 41 including a first curved convex portion 48 and a first curved concave portion 49. On the other hand, for example, when the magnification when observing the first straight portion 36 is low, the curved portions of the first curved convex portion 48 and the first curved concave portion 49 of the sine curve 47 may appear sharp. In this case, the first side portion 41 may be defined as being formed in a zigzag shape in a planar view. The shape of the apex of the first convex portion 44 protruding outward from the zigzag shape may correspond to the shape of the curved surface of the first curved convex portion 48.

[0068] Furthermore, the first convex portion 44 and the first concave portion 45 may be selectively formed in the first covering layer 27 of the first base layer 26 and the first covering layer 27 that constitute the first conductive member 25. Of course, they may be formed in both the first base layer 26 and the first covering layer 27. Furthermore, the first convex portion 44 and the first concave portion 45 may be selectively formed in the first linear portion 36, or selectively formed in the second linear portion 37, or may be formed in both the first linear portion 36 and the second linear portion 37, as shown in FIG.

[0069] Referring to FIG. 4, a protective layer 55 is formed on the insulating layer stack structure 17 so as to cover the first conductive member 25. The protective layer 55 contains an organic insulating resin. The organic insulating resin may contain, for example, an epoxy resin, a phenolic resin, or a polyimide. The protective layer 55 may be a resin layer having a higher thermal expansion coefficient than the first conductive member 25. For example, if the first thermal expansion coefficient of Cu constituting the base layer of the first conductive member 25 is 16×10 -6 / ℃ or more 18×10 -6 / °C or less, whereas the second thermal expansion coefficient of the resin (e.g., epoxy resin) constituting the protective layer 55 is 45×10 -6 / ℃ or more 65×10 -6 / °C or less. Pad openings 56 are formed in the protective layer 55 to expose the first base portions 40 of the first linear portions 36 as pads 14. The aforementioned conductive wires 7 are connected to the first conductive members 25 via the pads 14.

[0070] Fig. 5 is an enlarged view (second embodiment) of a portion surrounded by a two-dot chain line III in Fig. 2. Fig. 6 is a cross-sectional view taken along line VI-VI shown in Fig. 3.

[0071] Next, a description will be given of a second embodiment of the semiconductor chip 4. In the following, structures corresponding to those described with reference to Figures 2 to 4 will be given the same reference numerals and descriptions thereof will be omitted.

[0072] 6, in the second embodiment, the wiring 23 and the via 24 are not formed in the portion of the insulating layer stack structure 17 directly below the first conductive member 25 in the thickness direction of the semiconductor substrate 15. In other words, the first conductive member 25 may face the semiconductor substrate 15 via only the insulating layer of the insulating layer stack structure 17, without via conductive members such as the wiring 23 and the via 24. The insulating layer stack structure 17 in the second embodiment includes a stack structure of multiple inorganic insulating layers, and includes, for example, a first insulating layer 57 and a second insulating layer 58. Each insulating layer of the insulating layer stack structure 17 includes, for example, an inorganic insulating material such as silicon oxide (SiO2) or silicon nitride (SiN).

[0073] First insulating layer 57 and second insulating layer 58 may be made of the same insulating material but formed by different processes. For example, first insulating layer 57 may be a thermal silicon oxide film, and second insulating layer 58 may be a CVD (Chemical Vapor Deposition) silicon oxide film. In this case, first insulating layer 57 may have a denser film quality than second insulating layer 58.

[0074] Since the wiring 23 and the via 24 are not formed directly below the first conductive member 25, the first conductive member 25 does not need to be electrically connected to the functional element 16 formed on the semiconductor substrate 15. Instead of this connection, the first conductive member 25 may be electrically connected to a functional element 16 mounted on a semiconductor device 1 different from the semiconductor device 1, for example, via a conductive wire 7 connected to the pad 14.

[0075] A second conductive member 59 is formed on the first conductive member 25. The second conductive member 59 is a second layer of wiring stacked on the first conductive member 25, and may also be referred to as a second wiring layer. The second conductive member 59 is formed of a plurality of conductive layers, and may also be referred to as a second conductive layer.

[0076] The second conductive member 59 includes a second base layer 60 and a second coating layer 61 laminated on the second base layer 60. The second base layer 60 contains, for example, Cu, and may include a Cu plating layer in this embodiment. The second base layer 60 is connected to the first coating layer 27 of the first conductive member 25. In this way, the second conductive member 59 is physically connected to the first conductive member 25.

[0077] The second covering layer 61 covers the second base layer 60. The second covering layer 61 integrally includes a second covering portion 62 that contacts the upper surface of the second base layer 60 and covers the second base layer 60, and a second protruding portion 64 that protrudes laterally beyond an end face 63 of the second base layer 60. As a result, a second step 66 corresponding to the protrusion amount of the second protruding portion 64 is formed between the end face 63 of the second base layer 60 and the end face 65 of the second covering layer 61. The second protruding portion 64 may face the first base layer 26 of the first conductive member 25, with a part of the protective layer 55 sandwiched therebetween.

[0078] The second protruding portion 64 may hang down below the second covering portion 62 (toward the first main surface 11 of the semiconductor substrate 15). Therefore, the upper surface 67 of the second covering layer 61 may have both sides inclined downward relative to the portion on the second base layer 60. The second covering layer 61 may be formed thinner than the second base layer 60. For example, the second base layer 60 may have a thickness of 2 μm or more and 3 μm or less, and the second covering layer 61 may have a thickness of 1 μm or more and 2 μm or less.

[0079] In this embodiment, the second coating layer 61 includes multiple coating layers. The second coating layer 61 may include, for example, a first layer 68 in contact with the second base layer 60 and a second layer 69 laminated on the first layer 68. The first layer 68 may include, for example, Ni and, in this embodiment, a Ni-plated layer. The second layer 69 may include, for example, Pd and, in this embodiment, a Pd-plated layer. Although not shown, the second coating layer 61 may further include an Au-plated layer on its outermost surface. The first layer 68 and the second layer 69 are laminated over both the second coating portion 62 and the second protruding portion 64. As a result, the boundary between the first layer 68 and the second layer 69 may be exposed at the end surface 65 of the second coating layer 61.

[0080] 5, the second conductive member 59 is formed in a portion of the protective layer 55 above the first conductive member 25, and extends so as to overlap the first conductive member 25 in a plan view. The second conductive member 59 has a connection portion 70 connected to the tip end 39 of the first conductive member 25. In FIG. 5, the connection portion 70 of the second conductive member 59 is indicated by dashed hatching. For clarity, the hatching is applied to only one second conductive member 59.

[0081] The second conductive member 59 is bent upward at the connection portion 70 and extends diagonally upward away from the first conductive member 25. In FIG. 5, the straight line shown at the end of the connection portion 70 is the bent portion 71 of the second conductive member 59. In this embodiment, in a plan view, the first conductive member 25 extends toward one side in the first direction X1, and the second conductive member 59 extends toward the other side in the first direction X1, with the connection portion 70 between the first conductive member 25 and the second conductive member 59 as the boundary. As a result, the first conductive member 25 and the second conductive member 59 are aligned linearly along the first direction X1.

[0082] In this embodiment, the second conductive member 59 includes a third linear portion 72. The third linear portion 72 is formed in a band shape in a plan view. Note that the third linear portion 72 is defined as being band-shaped because it is shown in FIG. 5 as being relatively wide compared to its length. In contrast, if the width of the third linear portion 72 is very small compared to its length, it may be defined as being line-shaped or the like. The third linear portion 72 includes a tip portion 73, which is an end portion of the second conductive member 59. The tip portion 73 of the second conductive member 59 is the portion that is physically connected to the first conductive member 25.

[0083] Hereinafter, the longitudinal direction (extension direction) of the third linear portion 72 is referred to as the third direction X2, and the direction perpendicular to the third direction X2 is referred to as the fourth direction Y2. In this embodiment, the third direction X2 and the fourth direction Y2 coincide with the first direction X1 and the second direction Y1, respectively.

[0084] The third straight portion 72 includes a band-shaped second base portion 74 extending in the third direction X2, and second side portions 75 integrally formed on both sides of the second base portion 74 in the fourth direction Y2. The second base portion 74 is a conveniently set band-shaped region that can be extracted from the third straight portion 72 while maintaining substantially the same outer shape as the third straight portion 72, such as the inner region of a second boundary portion 76 indicated by a dashed line in FIG. 5 .

[0085] The second base portion 74 may have a second width W4 that is 80% or more, preferably 90% or more, of the width W3 of the third linear portion 72. For example, the width W3 of the third linear portion 72 may be 8 μm or more and 20 μm or less, and the second width W4 of the second base portion 74 may be 7 μm or more and 16 μm or less. The width W3 of the third linear portion 72 may be the distance between the apex of the second convex portion 77 on one side and the apex of the second convex portion 77 on the other side in the fourth direction Y2. Furthermore, the width W3 of the third linear portion 72 may be smaller than the width W1 of the first linear portion 36 of the first conductive member 25. This allows a connection margin to be provided on the sides of the second conductive member 59 when connecting the second conductive member 59 to the first conductive member 25.

[0086] In this embodiment, the second side portion 75 is an outer region of the second boundary portion 76 and has an uneven structure that does not affect the outer shape of the third linear portion 72. More specifically, the second side portion 75 includes a second protrusion 77 that protrudes from the second base portion 74 in the fourth direction Y2 and a second recess 78 that is recessed relative to the second protrusion 77. In this embodiment, the third linear portion 72 has a second side edge portion 79 formed by a curve that alternately curves to one side (the left side of the drawing) and the other side (the right side of the drawing) in the fourth direction Y2. The second side edge portion 79 is an outer line of the third linear portion 72 that extends in the third direction X2 of the third linear portion 72 in a plan view and forms a side surface of the third linear portion 72. Therefore, the second side portion 75 of the third straight portion 72 is the area between the second base portion 74 and the second side edge portion 79, and the second convex portion 77 and second concave portion 78 that constitute the second side portion 75 are formed by the curved second side edge portion 79 that is continuously connected along the third direction X2.

[0087] The protrusion amount P2 of the second convex portion 77 of the second side portion 75 may be any amount that does not significantly change the outer shape of the third linear portion 72. For example, the protrusion amount P2 may be 1 / 10 or less of the second width W4 of the second base portion 74 (i.e., the second width W4 may be 10 times or more the protrusion amount P2). In this embodiment, the curved second side edge 79 may be a sine curve 80 extending along the third direction X2. This allows the second side portion 75 to include a plurality of second curved convex portions 81 and a plurality of second curved concave portions 82 alternately formed along the third direction X2. In this case, the second width W4 of the second base portion 74 may be 5 times or more the amplitude A2 of the sine curve 80 from a second reference line 83, which is indicated by a two-dot chain line in FIG. 5 .

[0088] The tip portion 73 of the second conductive member 59 has a third side surface 85 formed by a third arc 84 having a third radius of curvature R3 in a plan view. In comparison to this third side surface 85, the second side edge portion 79 may have a fourth side surface 87 formed by a fourth arc 86 having a fourth radius of curvature R4 smaller than the third radius of curvature R3 in a plan view. When the second side edge portion 79 includes a sinusoidal curve 47, the curved surfaces of the second curved convex portion 81 and the second curved concave portion 82 may each be formed by the fourth arc 86.

[0089] In this embodiment, a pair of second side edges 79 including the sine curves 80 are formed along the third direction X2. That is, both side edges of the third linear portion 72 may be second side edges 79 including the sine curves 80. The pair of sine curves 80 may include one sine curve 80A and the other sine curve 80B. When comparing one sine curve 80A and the other sine curve 80B, the positions of the second curved convex portions 81 in the third direction X2 may be different from each other. For example, in the fourth direction Y2, the second curved convex portion 81 of one sine curve 80A may be offset from the second curved convex portion 81 of the other sine curve 80B.

[0090] In this embodiment, in the fourth direction Y2, the second curved convex portion 81 of one sinusoidal curve 80A faces the second curved concave portion 82 of the other sinusoidal curve 80B. Also, the second curved convex portion 81 of the other sinusoidal curve 80B faces the second curved concave portion 82 of the one sinusoidal curve 80A. As a result, in the third direction X2, the second curved convex portions 81 (second curved concave portions 82) are formed alternately on the second side portion 75 including one sinusoidal curve 80A and the second side portion 75 including the other sinusoidal curve 80B.

[0091] 5, the third straight portion 72 has a second side portion 75 including a second curved convex portion 81 and a second curved concave portion 82. On the other hand, for example, when the magnification when observing the third straight portion 72 is low, the curved portions of the second curved convex portion 81 and the second curved concave portion 82 of the sine curve 80 may appear sharp. In this case, the second side portion 75 may be defined as being formed in a zigzag shape in a planar view. The shape of the apex of the second convex portion 77 protruding outward from the zigzag shape may correspond to the shape of the curved surface of the second curved convex portion 81.

[0092] Furthermore, the second convex portion 77 and the second concave portion 78 may be selectively formed in the second covering layer 61 of the second base layer 60 and the second covering layer 61 that constitute the second conductive member 59. Of course, they may be formed in both the second base layer 60 and the second covering layer 61.

[0093] FIG. 7 is a flow chart showing some of the manufacturing steps of the semiconductor chip 4 in order of steps.

[0094] To manufacture the semiconductor chip 4, for example, a semiconductor wafer is prepared (step S1). The semiconductor wafer serves as the base of the semiconductor substrate 15. Next, a functional element 16 is formed on the main surface of the semiconductor wafer (step S2). The functional element 16 may be formed by a known method, such as implanting impurities into the semiconductor substrate 15 or depositing a resistive conductive material. Next, an insulating layer stack structure 17 is formed on the semiconductor substrate 15 (step S3). The insulating layer stack structure 17 may be formed, for example, by utilizing a known technique for forming a multilayer wiring structure.

[0095] Next, a first conductive member 25 is formed on the insulating layer stack structure 17 (step S4). The first conductive member 25 is formed, for example, by plating the materials of the first base layer 26 and the first covering layer 27 on the insulating layer stack structure 17. Next, the first conductive member 25 is patterned (step S5). As a result, a first side portion 41 including a first convex portion 44 and a first concave portion 45 is formed on the first linear portion 36 of the first conductive member 25. Specifically, a mask having a pattern of the first side edge portion 46 (sine curve 47) is placed on the stack structure of the first base layer 26 and the first covering layer 27, and the first covering layer 27 and the first base layer 26 are selectively etched through this mask to form the first convex portion 44 and the first concave portion 45. Note that if the semiconductor chip 4 includes a second conductive member 59, the second conductive member 59 can be formed by repeating steps S4 and S5 after patterning the first conductive member 25.

[0096] Next, a protective layer 55 is formed on the insulating layer stack structure 17 so as to cover the first conductive member 25 (step S6). For example, the protective layer 55 may be formed by setting the semiconductor wafer in a mold and filling the mold with a resin material. Thereafter, the protective layer 55 is cured by heat treatment.

[0097] Next, pad openings 56 are formed in the protective layer 55, thereby exposing portions of the first conductive members 25 as pads 14. Thereafter, the semiconductor wafer is cut into a plurality of semiconductor chips 4. Through the steps including those described above, the aforementioned semiconductor chips 4 are obtained.

[0098] FIG. 8 is a diagram illustrating the stress relaxation effect achieved by introducing a concave-convex structure. More specifically, FIG. 8 shows the results of a simulation of stress applied to samples 1 and 2. Sample 1 is a wiring 89 whose side edge 88 is formed by the aforementioned sine curve 47. Sample 2 is a wiring 91 whose side edge 90 is formed in a straight line. In FIG. 8, the area hatched with dashed lines is an area where the stress is 0.1% to 10% when the stress in the other white areas is taken as 100%. Referring to FIG. 8, it can be seen that in sample 1, which employs a concave-convex structure, the stress applied to the side of wiring 89 is dispersed and reduced overall compared to sample 2, which does not employ a concave-convex structure.

[0099] Furthermore, a temperature cycle test was carried out on Sample 1. The test conditions were -65°C to 150°C, and the number of cycles was 500 (30 minutes each at high and low temperatures). After the test, a cross-sectional SEM image of Sample 1 was observed, and no cracks originating from side edge 88 of wiring 89 were found in protective layer 55 made of organic insulating resin. From this result, it is considered that in Sample 1, the uneven structure of side edge 88 of wiring 89 dispersed the stress applied to the side of wiring 89.

[0100] 8, in the semiconductor chip 4 according to this embodiment, the first side edge 46 is formed in the shape of a sine curve 47, which allows the stress generated in the first side portion 41 of the first linear portion 36 to be dispersed. This reduces the overall stress in the first side portion 41 of the first linear portion 36 of the first conductive member 25. As a result, it is possible to suppress distortion generated in the protective layer 55 when the protective layer 55 expands or contracts due to changes in the ambient temperature (for example, changes in temperature during curing of the protective layer 55).

[0101] Furthermore, rather than first conductive member 25 being entirely meandering to form an S-shape, a stress dispersion structure is configured by selectively forming first convex portions 44 and first concave portions 45 on first side portions 41 of first linear portions 36. Therefore, there is no need to increase the installation space for first conductive member 25, which prevents semiconductor chip 4 from becoming larger.

[0102] Furthermore, if the semiconductor chip 4 includes the second conductive member 59 and the second side edge 79 of this second conductive member 59 is also formed in the shape of a sinusoidal curve 80, the stress generated in the second side portion 75 of the third linear portion 72 can be dispersed. This reduces the overall stress in the second side portion 75 of the third linear portion 72 of the second conductive member 59. As a result, distortion generated in the protective layer 55 during expansion and contraction due to temperature changes can be suppressed.

[0103] Although the embodiments of the present disclosure have been described above, the present disclosure can be embodied in other forms.

[0104] For example, in the above-described embodiment, the wiring layer of an LSI chip was taken as an example of the first conductive member 25 and the second conductive member 59, but the characteristic structures of the first conductive member 25 and the second conductive member 59 can also be employed in the structures of the wiring, electrodes, and coils of other semiconductor elements. More specifically, they can be employed in the surface wiring of a wafer-level CSP (Wafer Level Chip Size Package), the coil junction of an isolation transformer element, and the like.

[0105] The embodiments of the present disclosure are to be considered in all respects as illustrative and not restrictive, and are intended to include modifications in all respects.

[0106] The following additional features can be extracted from the description of this specification and the drawings. Note that in the following, numbers in parentheses represent reference symbols of corresponding components in the above detailed description. However, these reference symbols are not intended to limit the following components as equivalents of the above components. [Appendix 1-1] A semiconductor chip (4, 15); a first conductive layer (25) formed on the semiconductor chip (4, 15) and having a first linear portion (36) extending along a main surface (11) of the semiconductor chip (4, 15); an organic insulating layer (55) formed on the semiconductor chip (4, 15) and covering the first conductive layer (25); The first straight portion (36) includes a base portion (40) having a bonding area to which a bonding member can be connected, and a first side portion (41) including protrusions (44, 48) protruding from the base portion (40) in a direction intersecting the longitudinal direction of the first straight portion (36) and recesses (45, 49) recessed relative to the protrusions (44, 48), in the semiconductor device (1).

[0107] For example, if the first side of the first linear portion is straight, fluctuations in ambient temperature can cause high stress on the first side of the first linear portion due to differences in thermal expansion coefficients between the first conductive layer and the organic insulating layer. If this stress applies an external force to the organic insulating layer during expansion and contraction due to temperature changes, distortion of the organic insulating layer may occur, resulting in deterioration of the mechanical properties of the organic insulating layer. Therefore, in the semiconductor device according to this embodiment, the first side of the first linear portion includes a convex portion and a concave portion, thereby dispersing the stress generated on the first side of the first linear portion. This reduces the overall stress on the first side of the first linear portion of the first conductive layer. As a result, distortion generated in the organic insulating layer during expansion and contraction due to temperature changes can be suppressed. [Appendix 1-2] The semiconductor device (1) described in Appendix 1-1, wherein the convex portions (44, 48) and the concave portions (45, 49) include a plurality of curved convex portions (48) and a plurality of curved concave portions (49) formed alternately by sinusoidal curves (47) extending along the longitudinal direction of the first linear portion (36).

[0108] According to this configuration, since the convex portion and the concave portion are curved convex portions and curved concave portions, respectively, it is possible to prevent stress from concentrating at specific points of the convex portion and the concave portion. [Appendix 1-3] The semiconductor device (1) described in Appendix 1-2, wherein the first side portion (41) of the first straight portion (36) is formed by a pair of sinusoidal curves (47A, 47B) extending along the longitudinal direction of the first straight portion (36).

[0109] With this configuration, stress can be dispersed to each of the pair of first side portions of the first linear portion. [Appendix 1-4] The semiconductor device (1) according to Appendix 1-3, wherein, in a direction intersecting the longitudinal direction of the first straight portion (36), the curved convex portion (48) of one of the sine curves (47A) faces the curved concave portion (49) of the other sine curve (47B), and the curved convex portion (48) of the other sine curve (47B) faces the curved concave portion (49) of one of the sine curves (47A).

[0110] According to this configuration, curved convex portions (curved concave portions) are alternately formed on one first side portion and the other first side portion along the longitudinal direction of the first straight portion. For example, consider a case where the stress in at least one of the curved convex portions and the curved concave portions (e.g., the curved convex portion) is reduced more than the other (e.g., the curved concave portion). In this case, the stress relief portions in the first straight portion do not appear intermittently along the longitudinal direction of the first straight portion, but instead appear alternately and continuously on one first side portion and the other first side portion. This reduces the unevenness of the stress relief portions in the first straight portion. [Appendix 1-5] The base portion (40) is formed in a strip shape having a first width (W2). The semiconductor device (1) according to any one of Supplementary Notes 1-2 to 1-4, wherein the first width (W2) of the base portion (40) is five times or more the amplitude (A1) of the sine curve (47).

[0111] According to this configuration, the effect of stress dispersion in the first conductive layer can be achieved by forming the curved convex portions and curved concave portions in a sinusoidal shape having an amplitude approximately 1 / 5 of the width of an existing first conductive layer (e.g., wiring, electrode, etc.). Conversely, even if a stress dispersion structure is formed using the curved convex portions and curved concave portions, the first width of the base portion can be maintained relatively wide. As a result, many options (shapes, thicknesses, etc.) for bonding members that can be bonded to the base portion remain available. [Appendix 1-6] the first conductive layer (25) includes a tip portion (39) including a part of the first linear portion (36) and a second linear portion (37) connected to the first linear portion (36) via a corner portion (38); The semiconductor device (1) according to any one of Supplementary Notes 1-2 to 1-5, wherein the sine curve (47) is selectively formed on the first straight line portion (36) out of the first straight line portion (36) and the second straight line portion (37).

[0112] According to this configuration, the first linear portion, which includes the tip portion where stress is likely to occur due to fluctuations in ambient temperature, has curved convex portions and curved concave portions formed by sinusoidal curves, thereby enabling stress to be effectively distributed in the first conductive layer. [Appendix 1-7] The tip portion (39) of the first conductive layer (25) has a first side surface (52) formed by a first arc (51) having a first radius of curvature (R1) in a plan view, The semiconductor device (1) described in Appendix 1-6, wherein at least one of the curved convex portion (48) and the curved concave portion (49) of the sinusoidal curve (47) has a second side surface (54) formed by a second arc (53) having a second radius of curvature (R2) smaller than the first radius of curvature (R1) in a planar view. [Appendix 1-8] The first conductive layer (25) includes, in a cross-sectional view, a first base layer (26) and a first coating layer (27) laminated on the first base layer (26) so as to protrude laterally beyond an end face (29) of the first base layer (26); The semiconductor device (1) according to any one of Supplementary Notes 1-1 to 1-7, wherein the first side portion (41) including the convex portions (44, 48) and the concave portions (45, 49) is selectively formed in the first covering layer (27).

[0113] According to this configuration, the first side portion including the protrusions and recesses is selectively formed on the first coating layer, and does not necessarily have to be formed on the first base layer, which reduces the number of steps required to form the protrusions and recesses. [Appendix 1-9] The semiconductor device (1) according to any one of Supplementary Notes 1-1 to 1-8, wherein the organic insulating layer (55) has a pad opening (56) that exposes the base portion (40) of the first linear portion (36) as a pad (14).

[0114] According to this configuration, a bonding member such as a bonding wire can be connected to the base portion of the first linear portion through the pad opening. [Appendix 1-10] The semiconductor device (1) according to any one of Supplementary Notes 1-1 to 1-8, further comprising a second conductive layer (59) connected to the base portion (40) of the first linear portion (36) within the organic insulating layer (55).

[0115] According to this configuration, the aforementioned stress dispersion structure prevents the deterioration of the mechanical properties of the organic insulating layer around the second conductive layer, thereby improving the connection reliability between the first conductive layer (first linear portion) and the second conductive layer. [Appendix 1-11] the second conductive layer (59) has a third linear portion (72) extending along the main surface (11) of the semiconductor chip (4, 15); The semiconductor device (1) described in Appendix 1-10, wherein the third straight portion (72) includes, in a plan view, a second side portion (75) including a second convex portion (77, 81) protruding in a direction intersecting the longitudinal direction of the third straight portion (72) and a second concave portion (78, 82) recessed relative to the second convex portion (77, 81).

[0116] According to this configuration, since the second side portion of the third linear portion includes the second convex portion and the second concave portion, stress generated in the second side portion of the third linear portion can be dispersed. This reduces the overall stress in the second side portion of the third linear portion of the second conductive layer. As a result, distortion generated in the organic insulating layer during expansion and contraction due to temperature changes can be suppressed. [Appendix 1-12] The second conductive layer (59) includes, in a cross-sectional view, a second base layer (60) and a second coating layer (61) laminated on the second base layer (60) so as to protrude laterally beyond an end face (63) of the second base layer (60); The semiconductor device (1) described in Appendix 1-11, wherein the second side portion (75) including the second convex portion (77, 81) and the second concave portion (78, 82) is selectively formed in the second coating layer (61).

[0117] According to this configuration, the second side portion including the second convex portion and the second concave portion is selectively formed on the second coating layer, and does not necessarily have to be formed on the second base layer, which reduces the number of steps required to form the second convex portion and the second concave portion. [Appendix 1-13] The semiconductor device (1) according to any one of Appendices 1-1 to 1-12, comprising an insulating layer stack structure (17) formed between the first conductive layer (25) and the semiconductor chip (4, 15), the insulating layer stack structure (17) including at least a first inorganic insulating layer (18, 57) and a second inorganic insulating layer (19, 58) stacked on the first inorganic insulating layer (18, 57). [Appendix 1-14] The semiconductor device (1) according to any one of Supplementary Notes 1-1 to 1-13, including an integrated circuit element (16) formed on the semiconductor chip (4, 15) and electrically connected to the first conductive layer (25).

[0118] According to this configuration, as described above, the stress on the first side portion of the first linear portion of the first conductive layer can be reduced, thereby providing a semiconductor device including an integrated circuit with high insulation reliability of the organic insulating layer. [Appendix 2-1] A semiconductor chip (4, 15); a first wiring layer (25) formed on the semiconductor chip (4, 15) and extending along a main surface (11) of the semiconductor chip (4, 15); an organic insulating layer (55) formed on the semiconductor chip (4, 15) and covering the first wiring layer (25); The semiconductor device (1) has a first side (41) including a zigzag shape (47) formed along the extension direction of the first wiring layer (25) in a plan view.

[0119] For example, if the first side of the first wiring layer is straight, fluctuations in the ambient temperature may cause high stress on the first side of the first wiring layer due to differences in the thermal expansion coefficients between the first wiring layer and the organic insulating layer. If this stress applies an external force to the organic insulating layer during expansion and contraction due to temperature changes, distortion may occur in the organic insulating layer, degrading the mechanical properties of the organic insulating layer. Therefore, in the semiconductor device according to this embodiment, the first side of the first wiring layer includes a zigzag shape, which can disperse the stress generated on the first side of the first wiring layer. This can reduce the overall stress on the first side of the first wiring layer. As a result, distortion generated in the organic insulating layer during expansion and contraction due to temperature changes can be suppressed. [Appendix 2-2] The semiconductor device (1) according to Appendix 2-1, wherein the top of the zigzag shape (47) is formed by a first arc (53) having a first radius of curvature (R2) in a plan view.

[0120] According to this configuration, since the top of the zigzag shape is curved, it is possible to prevent stress from concentrating on the top. [Appendix 2-3] The semiconductor device (1) described in Appendix 2-2, wherein the first side portion (41) of the first wiring layer (25) is formed by a pair of zigzag shapes (47A, 47B) extending along the extension direction of the first wiring layer (25).

[0121] According to this configuration, stress can be distributed to each of the pair of first side portions of the first wiring layer. [Appendix 2-4] The semiconductor device (1) according to Appendix 2-3, wherein, in a direction intersecting the extension direction of the first wiring layer (25), the convex portions (44, 48) of one of the zigzag shapes (47A) face the concave portions (45, 49) of the other of the zigzag shapes (47B), and the convex portions (44, 48) of the other of the zigzag shapes (47B) face the concave portions (45, 49) of one of the zigzag shapes (47A).

[0122] According to this configuration, convex portions (concave portions) are alternately formed on one first side portion and the other first side portion along the longitudinal direction of the first wiring layer. For example, consider a case where the stress in at least one of the convex portions and the concave portions (e.g., the convex portion) is reduced more than the other (e.g., the concave portion). In this case, the stress relief portions in the first wiring layer do not appear intermittently along the longitudinal direction of the first wiring layer, but instead appear alternately and continuously on one first side portion and the other first side portion. This reduces the unevenness of the stress relief portions in the first wiring layer. [Appendix 2-5] the first wiring layer (25) includes a first linear portion (36) including a tip portion (39) and a second linear portion (37) connected to the first linear portion (36) via a corner portion (38); The semiconductor device (1) according to any one of Supplementary Notes 2-2 to 2-4, wherein the zigzag shape (47) is selectively formed on the first straight portion (36) out of the first straight portion (36) and the second straight portion (37).

[0123] According to this configuration, the zigzag shape is formed in the first linear portion including the tip portion where stress is likely to occur due to fluctuations in the ambient temperature, so that stress can be effectively dispersed in the first wiring layer. [Appendix 2-6] The semiconductor device (1) described in Appendix 2-5, wherein the tip portion of the first wiring layer (25) is formed by a second arc (51) having a second radius of curvature (R1) larger than the first radius of curvature (R2) in a planar view. [Appendix 2-7] The first wiring layer (25) includes, in a cross-sectional view, a first base layer (26) and a first covering layer (27) laminated on the first base layer (26) so as to protrude laterally beyond an end face (29) of the first base layer (26); The semiconductor device (1) according to any one of Supplementary Notes 2-1 to 2-6, wherein the first side portion (41) including the zigzag shape (47) is selectively formed on the first covering layer (27).

[0124] According to this configuration, the first side portion including the zigzag shape is selectively formed on the first coating layer, and does not necessarily have to be formed on the first base layer, which reduces the number of steps required to form the zigzag shape. [Appendix 2-8] The semiconductor device (1) according to any one of Supplementary Notes 2-1 to 2-7, wherein the organic insulating layer (55) has a pad opening (56) that exposes the first wiring layer (25) as a pad (14).

[0125] According to this configuration, a bonding member such as a bonding wire can be connected to the first wiring layer through the pad opening. [Appendix 2-9] The semiconductor device (1) according to any one of Supplementary Notes 2-1 to 2-7, further comprising a second wiring layer (59) connected to the first wiring layer (25) in the organic insulating layer (55).

[0126] According to this configuration, the aforementioned stress dispersion structure prevents the deterioration of the mechanical properties of the organic insulating layer around the second wiring layer, thereby improving the connection reliability between the first wiring layer and the second wiring layer. [Appendix 2-10] The semiconductor device (1) described in Appendix 2-9, wherein the second wiring layer (59) has a second side portion (75) including a second zigzag shape (80) formed along the extension direction of the second wiring layer (59) in a planar view.

[0127] According to this configuration, since the second side portion of the second wiring layer includes a second zigzag shape, stress generated in the second side portion of the second wiring layer can be dispersed. This reduces the overall stress in the second side portion of the second wiring layer. As a result, distortion generated in the organic insulating layer during expansion and contraction due to temperature changes can be suppressed. [Appendix 2-11] the second wiring layer (59) includes, in a cross-sectional view, a second base layer (60) and a second covering layer (61) laminated on the second base layer (60) so as to protrude laterally beyond an end face (63) of the second base layer (60); The semiconductor device (1) according to appendix 2-10, wherein the second side portion (75) including the second zigzag shape (80) is selectively formed on the second covering layer (61).

[0128] According to this configuration, the second side portion including the second zigzag shape is selectively formed in the second coating layer, and does not necessarily have to be formed in the second base layer, which reduces the number of steps in the process of forming the second zigzag shape. [Appendix 2-12] The semiconductor device (1) according to any one of Appendices 2-1 to 2-11, comprising an insulating layer stack structure (17) formed between the first wiring layer (25) and the semiconductor chip (4, 15), the insulating layer stack structure (17) including at least a first inorganic insulating layer (18, 57) and a second inorganic insulating layer (19, 58) stacked on the first inorganic insulating layer (18, 57). [Appendix 2-13] The semiconductor device (1) according to any one of Supplementary Notes 2-1 to 2-12, including an integrated circuit element (16) formed on the semiconductor chip (4, 15) and electrically connected to the first wiring layer (25).

[0129] According to this configuration, as described above, the stress on the first side portion of the first wiring layer can be reduced, and therefore a semiconductor device including an integrated circuit in which the organic insulating layer has high insulation reliability can be provided. [Appendix 3-1] A semiconductor substrate (4, 15); a first conductive member (25) formed on the semiconductor substrate (4, 15), having a first linear portion (36) extending along a main surface (11) of the semiconductor substrate (4, 15), and having a first thermal expansion coefficient; a resin layer (55) formed on the semiconductor substrate (4, 15), covering the first conductive member (25), and having a second thermal expansion coefficient higher than the first thermal expansion coefficient; The semiconductor device (1) includes a first side edge portion (46) formed by a curve (47) that alternately bends to one side and the other side in a direction intersecting the longitudinal direction of the first straight portion (36) when viewed in a plane.

[0130] For example, if the first side edge of the first linear portion is straight, fluctuations in ambient temperature cause the resin layer to expand more than the first conductive member. This difference in thermal expansion coefficients can result in high stress on the first side of the first linear portion. If this stress applies an external force to the resin layer during expansion and contraction due to temperature changes, strain may occur in the resin layer, degrading its mechanical properties. Therefore, in the semiconductor device according to this embodiment, the first side edge is curved, which can disperse the stress generated on the first side of the first linear portion. This can reduce the overall stress on the first side of the first linear portion of the first conductive member. As a result, strain generated in the resin layer during expansion and contraction due to temperature changes can be suppressed. [Appendix 3-2] The first linear portion (36) includes a base portion (40) to which a joining member can be connected, and a first side portion (41) including protrusions (44, 48) protruding from the base portion (40) in a direction intersecting the longitudinal direction of the first linear portion (36) and recesses (45, 49) recessed relative to the protrusions (44, 48), The semiconductor device (1) described in Appendix 3-1, wherein the first side edge portion (46) is formed by a curve (47) that continuously connects the convex portions (44, 48) and the concave portions (45, 49) along the longitudinal direction of the first linear portion (36) in a plan view.

[0131] According to this configuration, stress generated in the first side portion, including the convex portion and the concave portion, is dispersed, so that even if additional stress is applied to the first linear portion when connecting the bonding member to the base portion of the first linear portion, the mechanical properties of the resin layer can be prevented from deteriorating. Furthermore, the first conductive member does not meander to form an S-shape overall, but rather the stress dispersion structure is achieved by selectively forming convex portions and concave portions on the first side portion of the first linear portion. Therefore, there is no need to increase the installation space for the first conductive member according to this embodiment, which prevents the semiconductor device from becoming larger. [Appendix 3-3] The base portion (40) is formed in a strip shape having a first width (W2), The semiconductor device (1) described in Appendix 3-2, wherein the first width (W2) of the base portion (40) is 10 times or more the protrusion amount (P1) of the convex portion (44, 48) from the base portion (40).

[0132] According to this configuration, for example, by forming a protrusion with a protrusion amount of about 1 / 10 the width of an existing first conductive member (e.g., wiring, electrode, etc.), it is possible to achieve the effect of stress dispersion in the first conductive member. Conversely, even if a stress dispersion structure is formed by the protrusion and recess, the first width of the base portion can be maintained relatively wide. As a result, it is possible to maintain a wide range of options for bonding members that can be bonded to the base portion (e.g., the shape and thickness of the bonding member). [Appendix 3-4] the first conductive member (25) includes a tip portion (39) including a part of the first linear portion (36), and a second linear portion (37) connected to the first linear portion (36) via a corner portion (38); The semiconductor device (1) according to any one of Supplementary Notes 3-1 to 3-3, wherein the first side edge portion (46) is selectively formed on the first straight portion (36) out of the first straight portion (36) and the second straight portion (37).

[0133] According to this configuration, a curved first side edge portion is formed on the first linear portion including the tip portion where stress is likely to occur due to fluctuations in ambient temperature, so that stress can be effectively distributed in the first conductive member. [Appendix 3-5] The tip portion (39) of the first conductive member (25) has a first side surface (52) formed by a first arc (51) having a first radius of curvature (R1) in a plan view, The semiconductor device described in Appendix 3-4, wherein the first side edge portion (46) of the first conductive member (25) has a second side surface (54) formed by a second arc (53) having a second radius of curvature (R2) smaller than the first radius of curvature (R1) in a planar view. [Appendix 3-6] The first conductive member (25) includes, in a cross-sectional view, a first base layer (26) and a first covering layer (27) laminated on the first base layer (26) so as to protrude laterally beyond an end face (29) of the first base layer (26), The semiconductor device (1) according to any one of Supplementary Notes 3-1 to 3-5, wherein the first side edge portion (46) is selectively formed on the first covering layer (27).

[0134] With this configuration, the curved first side edge is selectively formed on the first covering layer, and does not necessarily have to be formed on the first base layer, which reduces the number of steps required to form the first side edge. [Appendix 3-7] The semiconductor device (1) described in Appendix 3-2, wherein the resin layer (55) has a pad opening (56) that exposes the base portion (40) of the first linear portion (36) as a pad (14).

[0135] According to this configuration, a bonding member such as a bonding wire can be connected to the base portion of the first linear portion through the pad opening. [Appendix 3-8] The semiconductor device (1) according to Appendix 3-2, further comprising a second conductive member (59) connected to the base portion (40) of the first linear portion (36) within the resin layer (55).

[0136] With this configuration, the stress dispersion structure prevents the deterioration of the mechanical properties of the resin layer around the second conductive member, thereby improving the connection reliability between the first conductive member (first linear portion) and the second conductive member. [Appendix 3-9] the second conductive member (59) has a third linear portion (72) extending along the main surface (11) of the semiconductor substrate (4, 15); The semiconductor device (1) described in Appendix 3-8, wherein the third straight portion (72) includes a second side edge portion (79) formed by a curve (80) that alternately bends to one side and the other side in a direction intersecting the longitudinal direction of the third straight portion (72) in a planar view.

[0137] With this configuration, because the second side edge portion is curved, stress generated in the second side portion of the third linear portion can be dispersed. This reduces the overall stress in the second side portion of the third linear portion of the second conductive member. As a result, distortion generated in the resin layer during expansion and contraction due to temperature changes can be suppressed. [Appendix 3-10] The second conductive member (59) includes, in a cross-sectional view, a second base layer (60) and a second covering layer (61) laminated on the second base layer (60) so as to protrude laterally beyond an end face (63) of the second base layer (60); The semiconductor device (1) according to Appendix 3-8 or Appendix 3-9, wherein the second side edge portion (79) is selectively formed on the second covering layer (61).

[0138] According to this configuration, the curved second side edge is selectively formed on the second covering layer, and does not necessarily have to be formed on the second base layer, which reduces the number of steps required to form the second side edge. [Appendix 3-11] The semiconductor device (1) according to any one of Supplementary Notes 3-1 to 3-10, comprising an insulating layer stack structure (17) formed between the first conductive member (25) and the semiconductor substrate (4, 15), the insulating layer stack structure (17) including at least a first inorganic insulating layer (18, 57) and a second inorganic insulating layer (19, 58) stacked on the first inorganic insulating layer (18, 57). [Appendix 3-12] The semiconductor device (1) according to any one of Supplementary Notes 3-1 to 3-11, including an integrated circuit element (16) formed on the semiconductor substrate (4, 15) and electrically connected to the first conductive member (25).

[0139] With this configuration, as described above, the stress on the first side portion of the first linear portion of the first conductive member can be reduced, thereby providing a semiconductor device including an integrated circuit in which the insulating reliability of the resin layer is high.

[0140] This application corresponds to Patent Application No. 2021-43633 filed with the Japan Patent Office on March 17, 2021, the entire disclosure of which is incorporated herein by reference. [Explanation of symbols]

[0141] 1: Semiconductor device 2: Sealing resin 3: Die pad 4: Semiconductor chip 5: Conductive adhesive 6: Lead terminal 7: Conductor 8: First main surface 9: Second main surface 10A: First side 10B: 2nd side 10C: 3rd side 10D: 4th side 11: First main surface 12: Second main surface 13: Element area 13A: Diode area 13B: Transistor area 13C: Resistor element area 14: Pad 15: Semiconductor substrate 16: Functional element 17: Insulating layer laminated structure 18: First insulating layer 19: Second insulating layer 20: Third insulating layer 21: Fourth insulating layer 22: Fifth insulating layer 23: Wiring 24: Beer 25: First conductive member 26: First base layer 27: 1st coating layer 28: First covering part 29: End face 30: 1st protrusion 31: End face 32: First step 33:Top surface 34: 1st layer 35: 2nd layer 36: 1st straight section 37: 2nd straight section 38: Corner 39:Tip 40: First base part 41: First side 42: First boundary 43: First boundary 44: First convex part 45: First recess 46:First side edge 47: Sine curve 47A: Sine curve 47B: Sine curve 48: First curved convex part 49: First curved recess 50: First reference line 51: First arc 52 :1st side 53: Second arc 54:Second side 55 :Protective layer 56: Pad opening 57: First insulating layer 58: Second insulating layer 59: Second conductive member 60: Second base layer 61:Second coating layer 62: Second coating part 63: End face 64:Second protrusion 65: End face 66: Second step 67:Top surface 68: 1st layer 69: 2nd layer 70: Connection part 71: Bend 72: 3rd straight section 73:Tip 74: Second base part 75: Second side 76: Second boundary 77: Second convex part 78: Second recess 79:Second side edge 80: Sine curve 80A: Sine curve 80B: Sine curve 81: Second curved convex part 82: Second curved recess 83: Second reference line 84: Third arc 85:Third side 86: 4th arc 87: 4th side 88: Side edge 89: Wiring 90: Side edge 91: Wiring A1: Amplitude A2: Amplitude P1:Protrusion amount P2:Protrusion amount R1: 1st radius of curvature R2: Second radius of curvature R3: Third radius of curvature R4: 4th radius of curvature W1: Width W2: First width W3: Width W4: 2nd width X1: 1st direction X2: 3rd direction Y1: Second direction Y2: 4th direction

Claims

1. a semiconductor substrate; a first conductive member formed on the semiconductor substrate and having a first linear portion extending along a main surface of the semiconductor substrate; a protective layer formed on the semiconductor substrate and covering the first conductive member; the first linear portion includes a first side edge portion formed by a curve that alternately curves to one side and the other side in a direction intersecting the longitudinal direction of the first linear portion in a plan view, the first conductive member includes, in a cross-sectional view, a first base layer and a first coating layer laminated on the first base layer so as to protrude laterally beyond an end surface of the first base layer; The first side edge portion is selectively formed on the first covering layer.

2. the first linear portion includes a base portion to which a joining member can be connected, and a first side portion including a convex portion protruding from the base portion in a direction intersecting with a longitudinal direction of the first linear portion and a concave portion recessed relative to the convex portion; 2 . The semiconductor device according to claim 1 , wherein the first side edge portion is formed by a curve that continuously connects the convex portion and the concave portion along the longitudinal direction of the first linear portion in a plan view.

3. The base portion is formed in a strip shape having a first width, The semiconductor device according to claim 2 , wherein the first width of the base portion is at least 10 times the amount of protrusion of the convex portion from the base portion.

4. the first conductive member includes a tip portion including a part of the first linear portion and a second linear portion connected to the first linear portion via a corner portion; 4. The semiconductor device according to claim 1, wherein the first side edge portion is selectively formed on the first linear portion out of the first linear portion and the second linear portion.

5. the tip end of the first conductive member has a first side surface formed by a first arc having a first radius of curvature in a plan view; 5. The semiconductor device according to claim 4, wherein the first side edge of the first conductive member has a second side surface formed by a second arc having a second radius of curvature smaller than the first radius of curvature in a plan view.

6. 3. The semiconductor device according to claim 2, wherein said protective layer has a pad opening that exposes said base portion of said first linear portion as a pad.

7. The semiconductor device according to claim 2 , further comprising a second conductive member in said protective layer, said second conductive member being connected to said base portion of said first linear portion.

8. the second conductive member has a third linear portion extending along the main surface of the semiconductor substrate, 8. The semiconductor device according to claim 7, wherein the third linear portion includes a second side edge portion formed by a curve that alternately curves to one side and the other side in a direction intersecting the longitudinal direction of the third linear portion in a plan view.

9. the second conductive member includes, in a cross-sectional view, a second base layer and a second coating layer laminated on the second base layer so as to protrude laterally beyond an end surface of the second base layer; The semiconductor device according to claim 8 , wherein the second side edge portion is selectively formed on the second covering layer.

10. 10. The semiconductor device according to claim 1, further comprising an insulating layer stack structure formed between the first conductive member and the semiconductor substrate, the insulating layer stack structure including at least a first inorganic insulating layer and a second inorganic insulating layer stacked on the first inorganic insulating layer.

11. 11. The semiconductor device according to claim 1, further comprising an integrated circuit element formed on said semiconductor substrate and electrically connected to said first conductive member.

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