Light receiving element array and manufacturing method thereof

Abstract

A light receiving element array of the present invention comprises a substrate and a semiconductor stack structure formed on the substrate. The semiconductor stack structure comprises a light absorbing layer arranged above the substrate, and a plurality of window layers of a first conductivity type formed on the light absorbing layer that are separated from each other. Each window layer in the semiconductor stack structure is formed with a first second-conductivity-type region that extends into the light absorbing layer from the surface of the respective window layer on the side opposite to the light absorbing layer. Inside the light absorbing layer, a second second-conductivity-type region is formed that is arranged so as to surround each of the plurality of window layers in the plan view. The second second-conductivity-type region extends toward the substrate-side surface of the light absorbing layer from the surface of the light absorbing layer on the side opposite to the substrate.

Description

[Technical Field]

[0001] The present disclosure relates to a photodetector array and a method for manufacturing the same. [Background technology]

[0002] Patent Document 1 discloses a light-receiving element array including an n-type substrate and a semiconductor layer formed on the n-type substrate, and including a plurality of light-receiving elements. The semiconductor layer consists of a light-receiving layer formed on the n-type substrate and an n-type semiconductor layer formed on the light-receiving layer. The semiconductor layer has a plurality of p-type semiconductor regions for each element-divided area. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-225359 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present disclosure is to provide a light-receiving element array capable of reducing crosstalk and a method for manufacturing the same. [Means for solving the problem]

[0005] One embodiment of the present disclosure provides a photodetector array including a substrate and a semiconductor laminate structure formed on the substrate, the semiconductor laminate structure including a light absorbing layer disposed above the substrate and a plurality of window layers of a first conductivity type formed and spaced apart on the light absorbing layer, wherein a first second conductivity type region is formed in the semiconductor laminate structure for each of the window layers, the first second conductivity type region extending from a surface of the window layer opposite to the light absorbing layer into the light absorbing layer, and a second second conductivity type region is formed in the light absorbing layer so as to surround each of the plurality of window layers in a planar view, the second second conductivity type region extending from a surface of the light absorbing layer opposite to the substrate toward a surface of the light absorbing layer facing the substrate.

[0006] This configuration can reduce crosstalk.

[0007] One embodiment of the present disclosure provides a photodetector array including a substrate and a semiconductor laminate structure formed on the substrate, the semiconductor laminate structure including a light absorbing layer disposed above the substrate, and a plurality of first conductivity type window layers formed and spaced apart on the light absorbing layer, wherein a second conductivity type region is formed in each of the window layers within the semiconductor laminate structure, extending from a surface of the window layer opposite to the light absorbing layer into the light absorbing layer, and the light absorbing layer is formed with separation grooves that are disposed so as to surround each of the plurality of window layers in a planar view, and extend from the surface of the light absorbing layer opposite to the substrate toward the surface of the light absorbing layer facing the substrate.

[0008] This configuration can reduce crosstalk.

[0009] One embodiment of the present disclosure provides a method for manufacturing a light-receiving element array, including the steps of: forming a semiconductor laminate structure on a substrate, the semiconductor laminate structure including a light absorption layer and a plurality of window layers of a first conductivity type formed on the light absorption layer and spaced apart from one another; forming, within the semiconductor laminate structure, for each of the window layers, a first region of a second conductivity type extending from a surface of the window layer opposite to the light absorption layer into the light absorption layer; and forming second regions of a second conductivity type arranged to surround each of the plurality of window layers in a planar view, the second region extending from a surface of the light absorption layer opposite to the substrate toward a surface of the light absorption layer facing the substrate.

[0010] This manufacturing method makes it possible to obtain a light-receiving element array that can reduce crosstalk.

[0011] The above and other objects, features, and advantages of the present disclosure will become apparent from the following description of the embodiments with reference to the accompanying drawings. [Brief explanation of the drawings]

[0012] [Figure 1A]FIG. 1A is a plan view illustrating the configuration of a light-receiving element array according to a first embodiment of the present disclosure. [Figure 1B] FIG. 1B is a partially enlarged plan view showing the portion IB in FIG. 1A. [Figure 2] FIG. 2 is a schematic cross-sectional view taken along line II-II in FIG. 1B. [Figure 3] FIG. 3 is a schematic cross-sectional view taken along line III-III in FIG. 1B. [Figure 4] Figure 4 is a cross-sectional view showing a photodiode array in which, compared to the photodiode arrays shown in Figures 1 to 3, a window layer is integrally formed over almost the entire surface of the light absorption layer, and no second p-type region is formed in the light absorption layer. [Figure 5] FIG. 5 is a graph showing the measurement results of the first sample, which is a sample of the light-receiving element array shown in FIG. [Figure 6] FIG. 6 is a graph showing the measurement results of a second sample, which is a sample of the light-receiving element array shown in FIGS. 1A to 3. In FIG. [Figure 7A] FIG. 7A is a cross-sectional view showing an example of a manufacturing process for the light-receiving element array shown in FIGS. 1A to 3, and is a cross-sectional view corresponding to the cross section of FIG. [Figure 7B] FIG. 7B is a cross-sectional view showing the next step of FIG. 7A. [Figure 7C] FIG. 7C is a cross-sectional view showing the step subsequent to FIG. 7B. [Figure 7D] FIG. 7D is a cross-sectional view showing the step subsequent to FIG. 7C. [Figure 7E] FIG. 7E is a cross-sectional view showing the step subsequent to FIG. 7D. [Figure 7F] FIG. 7F is a cross-sectional view showing the step following FIG. 7E. [Figure 7G] FIG. 7G is a cross-sectional view showing the step subsequent to FIG. 7F. [Figure 7H] FIG. 7H is a cross-sectional view showing the step subsequent to FIG. 7G. [Figure 7I] FIG. 7I is a cross-sectional view showing the step subsequent to FIG. 7H. [Figure 7J]FIG. 7J is a cross-sectional view showing the step subsequent to FIG. 7I. [Figure 7K] FIG. 7K is a cross-sectional view showing the step subsequent to FIG. 7J. [Figure 8A] FIG. 8A is a cross-sectional view showing an example of a manufacturing process for the light-receiving element array shown in FIGS. 1A to 3, and is a cross-sectional view corresponding to the cross section of FIG. [Figure 8B] FIG. 8B is a cross-sectional view showing the next step of FIG. 8A. [Figure 8C] FIG. 8C is a cross-sectional view showing the step subsequent to FIG. 8B. [Figure 8D] FIG. 8D is a cross-sectional view showing the step subsequent to FIG. 8C. [Figure 8E] FIG. 8E is a cross-sectional view showing the step subsequent to FIG. 8D. [Figure 8F] FIG. 8F is a cross-sectional view showing the step subsequent to FIG. 8E. [Figure 8G] FIG. 8G is a cross-sectional view showing the step subsequent to FIG. 8F. [Figure 8H] FIG. 8H is a cross-sectional view showing the step subsequent to FIG. 8G. [Figure 8I] FIG. 8I is a cross-sectional view showing the step subsequent to FIG. 8H. [Figure 8J] FIG. 8J is a cross-sectional view showing the step subsequent to FIG. 8I. [Figure 8K] FIG. 8K is a cross-sectional view showing the step following FIG. 8J. [Figure 9] FIG. 9 is a cross-sectional view illustrating the configuration of a light-receiving element array according to the second embodiment of the present disclosure. [Figure 10] FIG. 10 is a graph showing the measurement results of the third sample, which is the sample of the light-receiving element array shown in FIG. [Figure 11A] FIG. 11A is a cross-sectional view showing an example of a manufacturing process for the light-receiving element array shown in FIG. [Figure 11B] FIG. 11B is a cross-sectional view showing the next step of FIG. 11A. [Figure 11C] FIG. 11C is a cross-sectional view showing the step subsequent to that of FIG. 11B. [Figure 11D]FIG. 11D is a cross-sectional view showing the step subsequent to that of FIG. 11C. [Figure 11E] FIG. 11E is a cross-sectional view showing the step subsequent to that of FIG. 11D. [Figure 11F] FIG. 11F is a cross-sectional view showing the step subsequent to FIG. 11E. [Figure 11G] FIG. 11G is a cross-sectional view showing the step subsequent to FIG. 11F. [Figure 11H] FIG. 11H is a cross-sectional view showing the step subsequent to FIG. 11G. DETAILED DESCRIPTION OF THE INVENTION

[0013] [Description of the embodiments of the present disclosure] One embodiment of the present disclosure provides a photodetector array including a substrate and a semiconductor laminate structure formed on the substrate, the semiconductor laminate structure including a light absorbing layer disposed above the substrate and a plurality of window layers of a first conductivity type formed and spaced apart on the light absorbing layer, wherein a first second conductivity type region is formed in the semiconductor laminate structure for each of the window layers, the first second conductivity type region extending from a surface of the window layer opposite to the light absorbing layer into the light absorbing layer, and a second second conductivity type region is formed in the light absorbing layer so as to surround each of the plurality of window layers in a planar view, the second second conductivity type region extending from a surface of the light absorbing layer opposite to the substrate toward a surface of the light absorbing layer facing the substrate.

[0014] This configuration can reduce crosstalk.

[0015] In one embodiment of the present disclosure, the second second-conductivity type region extends from the surface of the light absorbing layer opposite to the substrate to partway through the thickness of the light absorbing layer.

[0016] In one embodiment of the present disclosure, the second second conductivity type region penetrates the light absorbing layer.

[0017] One embodiment of the present disclosure provides a photodetector array including a substrate and a semiconductor laminate structure formed on the substrate, the semiconductor laminate structure including a light absorbing layer disposed above the substrate, and a plurality of first conductivity type window layers formed and spaced apart on the light absorbing layer, wherein a second conductivity type region is formed in each of the window layers within the semiconductor laminate structure, extending from a surface of the window layer opposite to the light absorbing layer into the light absorbing layer, and the light absorbing layer is formed with separation grooves that are disposed so as to surround each of the plurality of window layers in a planar view, and extend from the surface of the light absorbing layer opposite to the substrate toward the surface of the light absorbing layer facing the substrate.

[0018] This configuration can reduce crosstalk.

[0019] In an embodiment of the present disclosure, the separation groove penetrates the light absorbing layer in the thickness direction.

[0020] In one embodiment of the present disclosure, the light absorbing layer includes an insulating film formed to cover the plurality of window layers, and a plurality of first electrodes provided for each of the window layers and arranged on the insulating film, and each of the first electrodes is electrically connected to a corresponding one of the first second-conductivity type regions.

[0021] In one embodiment of the present disclosure, the light absorbing layer includes an insulating film formed on the light absorbing layer so as to cover the plurality of window layers, and a plurality of first electrodes provided for each of the window layers and arranged on the insulating film, and each of the first electrodes is electrically connected to a corresponding one of the second conductivity type regions.

[0022] In one embodiment of the present disclosure, the insulating film is an anti-reflection film that prevents reflection of light of a preset wavelength.

[0023] In one embodiment of the present disclosure, the first electrode is endless in plan view.

[0024] In one embodiment of the present disclosure, the device further includes a second electrode formed on the second major surface of the substrate.

[0025] In one embodiment of the present disclosure, the plurality of window layers are arranged in a matrix in a plan view.

[0026] In one embodiment of the present disclosure, the semiconductor stacked structure includes a buffer layer of a first conductivity type formed between the substrate and the light absorbing layer.

[0027] In one embodiment of the present disclosure, the buffer layer has an exposed surface on a part of the surface opposite to the substrate, and a third electrode is formed on the exposed surface.

[0028] In one embodiment of the present disclosure, the substrate is an n-type InP substrate, the light absorption layer is an undoped InGaAs layer, and the window layer is an n-type InP layer.

[0029] In one embodiment of the present disclosure, the substrate is an n-type InP substrate, the buffer layer is an n-type InP layer, the light absorption layer is an undoped InGaAs layer, and the window layer is an n-type InP layer.

[0030] One embodiment of the present disclosure provides a method for manufacturing a light-receiving element array, including the steps of: forming a semiconductor laminate structure on a substrate, the semiconductor laminate structure including a light absorption layer and a plurality of window layers of a first conductivity type formed on the light absorption layer and spaced apart from one another; forming, within the semiconductor laminate structure, for each of the window layers, a first region of a second conductivity type extending from a surface of the window layer opposite to the light absorption layer into the light absorption layer; and forming second regions of a second conductivity type arranged to surround each of the plurality of window layers in a planar view, the second region extending from a surface of the light absorption layer opposite to the substrate toward a surface of the light absorption layer facing the substrate.

[0031] This manufacturing method makes it possible to obtain a light-receiving element array that can reduce crosstalk.

[0032] In one embodiment of the present disclosure, the step of forming the first second-conductivity type region and the step of forming the second second-conductivity type region are performed in the same step.

[0033] In one embodiment of the present disclosure, the method further includes the steps of forming an insulating film on the light absorption layer so as to cover the plurality of window layers, forming a first electrode on the insulating film for each of the window layers, the first electrode being electrically connected to the first second-conductivity-type region, and forming a second electrode on a surface of the substrate opposite to the semiconductor stack structure.

[0034] Detailed Description of Embodiments of the Present Disclosure Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0035] Fig. 1A is a plan view illustrating the configuration of a light-receiving element array according to a first embodiment of the present disclosure. Fig. 1B is a partially enlarged plan view showing part IB in Fig. 1A. Fig. 2 is a schematic cross-sectional view taken along line II-II in Fig. 1B. Fig. 3 is a schematic cross-sectional view taken along line III-III in Fig. 1B.

[0036] Hereinafter, the left-right direction of the paper surface of FIG. 1A may be referred to as the horizontal direction, and the up-down direction of the paper surface of FIG. 1A may be referred to as the vertical direction.

[0037] The light receiving element array 1 has a rectangular parallelepiped shape. In this embodiment, the shape of the light receiving element array 1 in a plan view is a square having two sides parallel to the horizontal direction and two sides parallel to the vertical direction.

[0038] The photodiode array 1 includes a substrate 2 having a first main surface (front surface) 2a and an opposite second main surface (back surface) 2b, and a semiconductor laminate structure 20 formed on the first main surface 2a of the substrate 2. The semiconductor laminate structure 20 includes an n-type buffer layer 3 formed on the first main surface 2a of the substrate 2, and an undoped light-absorbing layer 4 formed on the surface of the buffer layer 3 excluding four corner portions. The semiconductor laminate structure 20 further includes a plurality of n-type window layers 5 formed spaced apart in a central region of the surface of the light-absorbing layer 4, and an n-type layer 6 formed on the peripheral portion of the surface of the light-absorbing layer 4 so as to surround the window layers. The semiconductor laminate structure 20 also includes p-type contact layers 7 formed on each window layer 5 and in contact with a first p-type region 8 (described later).

[0039] In the semiconductor stacked structure 20, a first p-type region 8 is formed for each window layer 5, extending from the surface of the window layer 5 opposite to the light absorbing layer 4 into the light absorbing layer 4. In the light absorbing layer 4, a second p-type region 9 is formed so as to surround each of the plurality of window layers 5 in plan view, and extending from the surface of the light absorbing layer 4 opposite to the substrate 2 toward the surface of the light absorbing layer 4 on the substrate 2 side. In FIG. 1B, for clarity, the second p-type regions 9 are indicated by dots.

[0040] The photodiode array 1 includes an insulating film 10 that covers a part of the exposed surface of the buffer layer 3, the exposed surface of the light absorption layer 4, the exposed surface of the window layer 5, the exposed surface of the n-type layer 6, and the contact layer 7. The photodiode array 1 also includes a plurality of first electrodes (p-side electrodes) 12 that are provided for each window layer 5 and arranged on the insulating film 10.

[0041] The photodiode array 1 also includes a second electrode (main n-side electrode) 13 formed on the second main surface 2b of the substrate 2 and a plurality of third electrodes (sub n-side electrodes) 14 formed at four corners of the surface of the buffer layer 3. The photodiode array 1 further includes a plurality of bonding pads 15, wiring 16, and marks 17 and 18 formed on the insulating film 10.

[0042] In the photodetector array 1, a photodetector 30 made of a PIN-type photodiode is formed in each region where the window layer 5 is present in a plan view. In other words, in the photodetector array 1, a photodetector 30 is formed in each first p-type region 8. In this embodiment, the photodetector array 1 includes 16 photodetectors 30 arranged in 4 rows and 4 columns. Each photodetector 30 includes a substrate 2, a buffer layer 3, a light absorption layer 4, a window layer 5, a contact layer 7, an insulating film 10, a first electrode 12, and a second electrode 13.

[0043] In the orientation of the light receiving element array 1 shown in Fig. 1A, the four rows will be referred to as the first, second, third, and fourth rows from the top of the page in Fig. 1A, and the four columns will be referred to as the first, second, third, and fourth columns from the left of the page in Fig. 1A. The light receiving elements 30 are assigned identification numbers such as 1 to 4 from the first column to the fourth column of the first row, 5 to 8 from the first column to the fourth column of the second row, 9 to 12 from the first column to the fourth column of the third row, and 13 to 16 from the first column to the fourth column of the fourth row.

[0044] In this embodiment, the substrate 2 is an n-type InP substrate. The n-type impurity is, for example, S (sulfur), and the impurity concentration is 1×10 18 cm -3 ~5×10 18 cm -3 In this embodiment, the thickness of the substrate 2 is about 180 μm. The substrate 2 may be a semi-insulating substrate.

[0045] The buffer layer 3 is a buffer layer for alleviating strain caused by the difference between the lattice constant of the light absorption layer 4 formed on the buffer layer 3 and the lattice constant of the substrate 2. In this embodiment, the buffer layer 3 is made of an n-type InP layer. The n-type impurity is, for example, Si (silicon), and the impurity concentration is 1×10 18 cm -3 ~5×10 18 cm -3 The thickness of the buffer layer 3 is about 100 nm to 200 nm.

[0046] The light absorbing layer 4 has chamfered portions 4a at four corners. The outer surfaces of the chamfered portions 4a are formed in an arc shape that protrudes inward in a plan view. In this embodiment, the light absorbing layer 4 is made of an undoped InGaAs layer. The thickness of the light absorbing layer 4 is approximately 2 μm to 5 μm.

[0047] In this embodiment, the window layer 5 has a square shape in a plan view. In this embodiment, the multiple window layers 5 are arranged in a matrix in a plan view. More specifically, the multiple window layers 5 are arranged side by side at equal intervals in the horizontal and vertical directions. In this embodiment, the multiple window layers 5 include 16 window layers 5 arranged in 4 rows and 4 columns.

[0048] The n-type layer 6 has chamfered portions 6a at four corners corresponding to the four corners of the light absorption layer 4. The outer surfaces of the chamfered portions 6a are formed in an arc shape that protrudes inward in a plan view. In this embodiment, the window layer 5 and the n-type layer 6 are made of an n-type InP layer. The n-type impurity is, for example, Si (silicon), and the impurity concentration is 1×10 16 cm -3 ~5×10 17 cm -3 The thickness of the window layer 5 and the n-type layer 6 is about 0.5 μm to 1.5 μm.

[0049] The first p-type region 8 is formed by diffusing Zn (zinc) into the window layer 5 and the light absorption layer 4 from the surface of the window layer 5 opposite to the light absorption layer 4. The concentration of Zn in the surface portion of the window layer 5 is 2×10 18 cm -3 In this embodiment, the first p-type region 8 has a circular shape in plan view. The first p-type region 8 extends from the surface of the window layer 5 to partway through the thickness of the light absorption layer 4.

[0050] The second p-type region 9 is formed by diffusing Zn (zinc) into the light absorbing layer 4 from the surface of the light absorbing layer 4 opposite to the substrate 2. The concentration of Zn in the surface portion of the light absorbing layer 4 is 2×10 18 cm -3The second p-type region 9 is formed in a lattice pattern in a plan view in the central region of the light absorption layer 4. That is, the second p-type region 9 is made up of a plurality of first portions 91 extending in the horizontal direction at equal intervals in the vertical direction in a plan view, and a plurality of second portions 92 extending in the vertical direction at equal intervals in the horizontal direction and intersecting with the plurality of first portions. The plurality of first portions 91 and the plurality of second portions 92 form a plurality of endless (rectangular ring-shaped in this example) second p-type regions 9 surrounding each of the window layers 5 in a plan view.

[0051] In this embodiment, the second p-type region 9 extends from the surface of the light absorbing layer 4 to partway through the thickness of the light absorbing layer 4. Note that the second p-type region 9 may extend from the surface of the light absorbing layer 4, penetrating the light absorbing layer 4 and reaching the buffer layer 3, as indicated by the two-dot chain line 9A in FIG.

[0052] In this embodiment, the contact layer 7 is made of a p-type InGaAs layer. The p-type impurity is, for example, Zn (zinc), and the impurity concentration is 1×10 19 cm -3 ~2×10 19 cm -3 The thickness of the contact layer 7 is about 100 nm. The contact layer 7 has an endless shape (annular in this example) in a plan view, and is formed on the peripheral edge of the surface of the first p-type region 8. In other words, the lower surface of the contact layer 7 is in contact with the surface of the first p-type region 8.

[0053] The insulating film 10 covers the exposed surface of the light absorption layer 4, the exposed surface of the window layer 5, the exposed surface of the n-type layer 6, and the contact layer 7. The insulating film 10 also covers the exposed surface of each corner of the buffer layer 3, in the vicinity of the chamfered portion 4a of the light absorption layer 4. The insulating film 10 has a contact hole 11 that is annular in plan view, exposing the entire periphery of the intermediate portion in the width direction of the surface of the contact layer 7, which is annular in plan view. Chamfered portions 10a are formed at the four corners of the insulating film 10. The outer surface of the chamfered portion 10a is formed in an arc shape that protrudes inward in plan view.

[0054] In this embodiment, the insulating film 10 is made of a SiN film. In this embodiment, the thickness of the insulating film 10 is set to about 200 nm so as to prevent reflection of light with a wavelength of 1500 nm. In other words, in this embodiment, the insulating film 10 is an anti-reflection film that prevents reflection of light of a predetermined wavelength. The thickness of the insulating film 10 is set according to the wavelength of light whose reflection is to be prevented. The wavelength of light whose reflection is to be prevented is set in advance.

[0055] The first electrode 12 has an endless shape (annular in this example) in a plan view, and is formed on the insulating film 10 so as to cover the contact hole 11. A portion of the first electrode 12 enters the contact hole 11 and is in contact with the surface of the contact layer 7 within the contact hole 11. This allows the first electrode 12 to be electrically connected to the first p-type region 8 via the contact layer 7. In this embodiment, the first electrode 12 is made of a Ti / Pt / Au stacked film in which a Ti film, a Pd film, and an Au film are stacked in that order from the bottom up.

[0056] The second electrode 13 is electrically connected to the buffer layer 3 via the substrate 2. In this embodiment, the second electrode 13 is composed of a Ti / Pt / Au laminated film in which a Ti film, a Pd film, and an Au film are laminated in that order on the second main surface 2b of the substrate 2.

[0057] The third electrodes 14 are formed on the exposed surfaces of the four corners of the buffer layer 3. That is, the third electrodes 14 are electrically connected to the buffer layer 3. The third electrodes 14 may be used to examine the characteristics of the light-receiving elements 30 during the manufacturing process of the light-receiving element array 1. In this embodiment, the third electrodes 14 are made of a Ti / Pt / Au laminated film in which a Ti film, a Pd film, and an Au film are laminated in that order from the bottom up.

[0058] A plurality of bonding pads 15 are formed on the peripheral portion of the surface of the insulating film 10. Specifically, four bonding pads 15 are formed on each edge portion corresponding to each side of the insulating film 10. Also, a plurality of wirings 16 are formed on the surface of the insulating film 10 to connect the first electrodes 12 of the plurality of light receiving elements 30 to different bonding pads 15, respectively.

[0059] Furthermore, one first mark 17 shaped like a + (plus sign) in plan view and three second marks 18 shaped like an L in plan view are formed on the surface of the insulating film 10 so that the identification numbers of each light receiving element 30 can be recognized. In this embodiment, the first mark 17 is formed near the upper left corner of the surface of the insulating film 10, and second marks are formed near the other three corners of the surface of the insulating film 10, respectively. These marks 17 and 18 make it possible to recognize the identification numbers assigned to the multiple light receiving elements 30.

[0060] In this embodiment, the bonding pad 15, the wiring 16, and the marks 17 and 18 are made of the same material as the electrodes 12 and 14. As will be described later, the bonding pad 15, the wiring 16, the marks 17 and 18, the first electrode 12, and the third electrode 14 are formed in the same process.

[0061] The light-receiving element array 1 is used with external wiring connected between each bonding pad 15 and the second electrode 13. A power supply is connected to the external wiring to generate an internal electric field in the light-absorbing layer 4. When light is incident on the light-absorbing layer 4 from the upper surface of the light-receiving element 30, electrons and holes are generated in the light-absorbing layer 4. The electrons generated in the light-absorbing layer 4 move toward the second electrode 13 due to the internal electric field, and the holes generated in the light-absorbing layer 4 move toward the first electrode 12 due to the internal electric field. This causes a current to flow in an external circuit.

[0062] In the first embodiment, the light absorption layer 4 has a second p-type region 9 formed therein so as to surround each of the plurality of window layers 5 (light receiving elements 30) in plan view. This makes it possible to prevent electrons and holes generated in the light absorption layer 4 of a light receiving element 30 from migrating to an adjacent light receiving element 30 when light is incident on that light receiving element 30. This makes it possible to reduce crosstalk. Crosstalk is a phenomenon in which light incident on a light receiving element causes current to leak to an adjacent light receiving element.

[0063] 1 to 3, Fig. 4 shows a photodetector array 101 in which a window layer 5 is integrally formed over almost the entire surface of the light absorbing layer 4 and no second p-type region 9 is formed in the light absorbing layer 4. In the photodetector array 101, a photodetector 30 is also formed for each first p-type region 8. In Fig. 4, parts corresponding to those in Fig. 2 are denoted by the same reference numerals as in Fig. 2.

[0064] In the following, the sample of the light receiving element array 101 shown in Fig. 4 may be referred to as a first sample, and the sample of the light receiving element array 1 shown in Figs. 1 to 3 may be referred to as a second sample.

[0065] For each of the first and second samples, the current flowing through a light-receiving element 30 when 1 mW of light is incident on that element (hereinafter referred to as the "first current I1"), the current flowing through a light-receiving element adjacent to that light-receiving element when 1 mW of light is incident on that light-receiving element (hereinafter referred to as the "second current I2"), and the dark current were measured. The dark current is the current that flows through a light-receiving element when no light is incident on that light-receiving element.

[0066] Fig. 5 is a graph showing the measurement results for the first sample, and Fig. 6 is a graph showing the measurement results for the second sample. In Fig. 5 and Fig. 6, the line a is a graph showing the first current I1, the line b is a graph showing the second current I2, and the group of circular dots c is a graph showing the dark current.

[0067] 5 and 6, it can be seen that the second current is significantly lower in the second sample than in the first sample. Furthermore, if {(I2 / I1) × 100} is taken as the crosstalk characteristic [%], the crosstalk characteristic in the first sample is 2.32%, while the crosstalk characteristic in the second sample is 0.13%. This means that the crosstalk is significantly reduced in the second sample compared to the first sample. It can also be seen that the dark current in the second sample is reduced compared to the first sample.

[0068] 7A to 7K are cross-sectional views illustrating an example of a manufacturing process for the light-receiving element array 1, and are cross-sectional views corresponding to the cross section of Fig. 2. Figs. 8A to 8K are cross-sectional views illustrating an example of a manufacturing process for the light-receiving element array 1, and are cross-sectional views corresponding to the cross section of Fig. 3.

[0069] 7A and 8A, a buffer layer (e.g., an n-type InP layer) 3 and a light absorbing layer (e.g., an InGaAs layer) 4 are epitaxially grown in this order on a first main surface 2a of a substrate (e.g., an n-type InP substrate) 2, for example, by MOCVD (Metal Organic Chemical Vapor Deposition). Furthermore, a window material layer (e.g., an n-type InP layer) 41, which is a material layer for the window layer 5 and the n-type layer 6, and a contact material layer (e.g., a p-type InGaAs layer) 42, which is a material layer for the contact layer, are epitaxially grown in this order on the light absorbing layer 4 by MOCVD. The substrate 2 used is thicker than the final thickness of the substrate 2.

[0070] 7B and 8B, photolithography and etching are used to remove regions of contact material layer 42 other than the regions where first p-type regions 8 are to be formed. As a result, contact material layer 42 remains only in the regions on the surface of window material layer 41 where first p-type regions 8 are to be formed.

[0071] Next, as shown in Figures 7C and 8C, the window material layer 41 is patterned by photolithography and etching. As a result, a plurality of window layers 5 and an n-type layer 6 are formed on the light-absorbing layer 4. The plurality of window layers 5 are formed so as to be arranged in a matrix in the central region of the surface of the light-absorbing layer 4. The n-type layer 6 is formed on the peripheral portion of the surface of the light-absorbing layer 4 excluding the four corners so as to surround the window layer group. As a result, the n-type layer 6 has chamfered portions 6a at the corners corresponding to the four corners of the light-absorbing layer 4.

[0072] Next, as shown in FIGS. 7D and 8D, a mask insulating film 43 is formed on the entire exposed surface by plasma CVD, LPCVD (Low Pressure CVD), MOCVD, sputtering, or the like.

[0073] 7E and 8E, photolithography and etching are used to remove the portion of the insulating film 43 that covers the surface (upper surface) of the contact material layer 42 and the portion that covers the region in the surface of the light absorption layer 4 where the second p-type region 9 is to be formed. This forms in the insulating film 43 a first opening 43a for forming the first p-type region 8 and a second opening 43b for forming the second p-type region 9.

[0074] 7F and 8F, using the insulating film 43 as a mask, Zn is diffused into the contact material layer 42, the window layer 5, and the light absorbing layer 4 through the first opening 43a, and Zn is diffused into the light absorbing layer 4 through the second opening 43b. As a result, a first p-type region 8 is formed in the window layer 5 and the light absorbing layer 4, and a second p-type region 9 is formed in the light absorbing layer 4. Thereafter, the insulating film 43 is removed.

[0075] 7G and 8G, the contact material layer 42 is patterned by photolithography and etching. As a result, a contact layer 7 having a circular ring shape in plan view is formed on each first window layer 5A, in contact with the peripheral portion of the surface of the first p-type region 8. As a result, a semiconductor stacked structure 20 including the buffer layer 3, the light absorption layer 4, the window layer 5, the n-type layer 6, and the contact layer 7 is obtained.

[0076] 7H and 8H, the four corners of the light absorbing layer 4 are removed by photolithography and etching, thereby forming chamfered portions 4a at the four corners of the light absorbing layer 4.

[0077] Next, as shown in FIGS. 7I and 8I, an insulating material film 44, which is a material film for the insulating film 10, is formed over the entire exposed surface by plasma CVD, LPCVD, MOCVD, sputtering, or the like.

[0078] Next, as shown in FIGS. 7J and 8J, contact holes 11 that expose portions of the contact layer 7 are formed in the insulating material film 44 for each window layer 5 by photolithography and etching. Furthermore, portions of the insulating material film 44 on the four corners of the surface of the buffer layer 3 are removed except for the portions near the chamfered portions 4a of the light absorption layer 4. This results in an insulating film 10 having chamfered portions 10a at the four corners. This exposes the four corners of the surface of the buffer layer 3.

[0079] Next, an electrode film, which is a material film for the first electrodes 12, third electrodes 14, bonding pads 15, wiring 16, and marks 17 and 18, is formed by electron beam evaporation, sputtering, or the like, so as to cover the exposed surfaces of the corners of the buffer layer 3 and the insulating film 10. The electrode film is then patterned by photolithography and etching. As a result, as shown in FIGS. 7K and 8K, a plurality of first electrodes 12, a plurality of bonding pads 15, a plurality of wiring 16, and a plurality of marks 17 and 18 are formed on the insulating film 10, and third electrodes 14 are formed at each of the four corners of the buffer layer 3.

[0080] Finally, the substrate 2 is ground from the second main surface 2b side to thin the substrate 2. Then, the second electrode 13 is formed on the second main surface 2b of the thinned substrate 2. This results in the light-receiving element array 1 as shown in FIGS. 1A to 3.

[0081] Fig. 9 is a cross-sectional view illustrating the configuration of a light-receiving element array according to a second embodiment of the present disclosure. Fig. 9 is a cross-sectional view corresponding to the cross section of Fig. 2. In Fig. 9, parts corresponding to those in Fig. 2 are denoted by the same reference numerals as in Fig. 2.

[0082] 9 differs from the photodetector array 1 shown in FIGS. 1A to 3 in that the second p-type region 9 is not formed in the light absorption layer 4, that a separation groove 50 is formed in the light absorption layer 4 so as to surround the window layer 5 in a plan view, and that the inner surface (bottom surface and side surface) of the separation groove 50 is covered with an insulating film 10. The remaining structure is the same as that of the photodetector array 1 shown in FIGS. 1A to 3. Since the photodetector array 1A according to the second embodiment does not have a second p-type region 9, a region corresponding to the first p-type region 8 of the photodetector array 1 according to the first embodiment will be referred to as a p-type region 8.

[0083] 1 and 1B, which are plan views of the photodetector array 1 according to the second embodiment. However, since the photodetector array 1A according to the second embodiment does not have the second p-type region 9, the dashed line representing the second p-type region 9 in FIG. 1B can be regarded as the dashed line representing the separation groove 50. In other words, the region with dots in FIG. 1B can be regarded as the region where the separation groove 50 is formed.

[0084] The separation grooves 50 are formed in a lattice pattern in plan view in the central region of the light absorption layer 4. That is, the separation grooves 50 have a plurality of first portions (portions indicated by reference numeral 50 in FIG. 9) extending in the horizontal direction and spaced equally apart in the vertical direction in plan view, and a plurality of second portions (portions not shown in FIG. 9) extending in the vertical direction and spaced equally apart in the horizontal direction and intersecting with the plurality of first portions. The plurality of first portions and the plurality of second portions form a plurality of rectangular annular separation grooves 50 surrounding each of the window layers 5 in plan view.

[0085] In this embodiment, the separation groove 50 extends from the surface of the light absorbing layer 4, penetrating the light absorbing layer 4 and reaching the buffer layer 3. The separation groove 50 may extend from the surface of the light absorbing layer 4 to partway through the thickness of the light absorbing layer 4.

[0086] In the second embodiment, the light absorbing layer 4 has separation grooves 50 formed therein so as to surround each of the plurality of window layers 5 (light receiving elements 30) in plan view. This makes it possible to prevent electrons and holes generated in the light absorbing layer 4 of a light receiving element 30 from migrating to an adjacent light receiving element 30 when light is incident on that light receiving element 30. This makes it possible to reduce crosstalk.

[0087] 9 may be referred to as the third sample. For the third sample, the current (first current I1) flowing through a certain light receiving element 30 when 1 mW of light is incident on the light receiving element, the current (second current I2) flowing through a light receiving element adjacent to the certain light receiving element when 1 mW of light is incident on the light receiving element, and the dark current were measured.

[0088] Fig. 10 is a graph showing the measurement results for Sample 3. In Fig. 10, line a is a graph showing the first current I1, line b is a graph showing the second current I2, and group of circular dots c is a graph showing the dark current.

[0089] 5 and 10, it can be seen that the second current is significantly lower in the third sample than in the first sample. Furthermore, if {(I2 / I1) × 100} is taken as the crosstalk characteristic [%], the crosstalk characteristic in the first sample is 2.32%, while the crosstalk characteristic in the third sample is 0.12%. In other words, it can be seen that the crosstalk is significantly reduced in the third sample compared to the first sample. It can also be seen that the dark current in the third sample is reduced compared to the first sample.

[0090] 11A to 11H are cross-sectional views illustrating an example of a manufacturing process for the light-receiving element array 1A, and correspond to the cross section of FIG.

[0091] 7A to 7C are also performed when manufacturing the light-receiving element array 1A. After the step of Fig. 7C is completed, separation grooves 50 are formed in the light-absorbing layer 4 by photolithography and etching, as shown in Fig. 11A, so as to surround each of the window layers 5 in plan view.

[0092] Next, as shown in FIG. 11B, a mask insulating film 43 is formed on the entire exposed surface by plasma CVD, LPCVD, MOCVD, sputtering or the like.

[0093] 11C, the portion of insulating film 43 covering the surface (upper surface) of contact material layer 42 is removed by photolithography and etching. As a result, opening 43a for forming p-type region 8 is formed in insulating film 43.

[0094] Next, as shown in 11D, Zn is diffused into the contact material layer 42, the first window layer 5A, and the light absorption layer 4 through the first opening 43a, using the insulating film 43 as a mask. This forms a p-type region 8 in the window layer 5 and the light absorption layer 4. Thereafter, the insulating film 43 is removed.

[0095] 11E, the contact material layer 42 is patterned by photolithography and etching. As a result, a contact layer 7 having a circular ring shape in plan view is formed on each first window layer 5A in contact with the peripheral portion of the surface of the p-type region 8. As a result, a semiconductor stacked structure 20 including the buffer layer 3, the light absorption layer 4, the window layer 5, the n-type layer 6, and the contact layer 7 is obtained.

[0096] Next, the four corners of the light absorbing layer 4 are removed by photolithography and etching, thereby forming chamfered portions 4a at the four corners of the light absorbing layer 4.

[0097] Next, as shown in FIG. 11F, an insulating material film 44, which is a material film for the insulating film 10, is formed over the entire exposed surface by plasma CVD, LPCVD, MOCVD, sputtering, or the like.

[0098] Next, as shown in FIG. 11G, contact holes 11 that expose portions of the contact layer 7 are formed in the insulating material film 44 for each window layer 5 by photolithography and etching. Furthermore, portions of the insulating material film 44 on the four corners of the surface of the buffer layer 3 are removed except for the portions near the chamfered portions 4a of the light absorption layer 4. This results in an insulating film 10 having chamfered portions 10a at the four corners. This exposes the four corners of the surface of the buffer layer 3.

[0099] Next, an electrode film, which is a material film for the first electrodes 12, third electrodes 14, bonding pads 15, wiring 16, and marks 17 and 18, is formed by electron beam evaporation, sputtering, or the like, so as to cover the exposed surface portions of the four corners of the buffer layer 3 and the insulating film 10. The electrode film is then patterned by photolithography and etching. As a result, as shown in FIG. 11H, a plurality of first electrodes 12, a plurality of bonding pads 15, a plurality of wiring 16, and a plurality of marks 17 and 18 are formed on the insulating film 10, and third electrodes 14 are formed at each of the four corners of the buffer layer 3.

[0100] Finally, the substrate 2 is thinned by grinding from the second main surface 2b side. Then, the second electrode 13 is formed on the second main surface 2b of the thinned substrate 2. This results in a light-receiving element array 1A as shown in FIG.

[0101] In the first and second embodiments described above, the light receiving element arrays 1, 1A include 16 light receiving elements 30, but the light receiving element arrays 1, 1A may include any number of light receiving elements as long as they include a plurality of light receiving elements, and the number of light receiving elements can be set arbitrarily.

[0102] Furthermore, although the plurality of light receiving elements 30 are arranged two-dimensionally, they may also be arranged one-dimensionally.

[0103] The first p-type region 8 has a circular shape in plan view, but may have a polygonal shape such as a quadrilateral (square, rectangle, etc.) or a regular hexagon in plan view.

[0104] In the first and second embodiments described above, the conductivity types of the n-type substrate 2, the n-type buffer layer 3, the n-type window layer 5, and the n-type layer 6 may be reversed to the conductivity types of the p-type contact layer 7, the p-type first p-type region 8, and the p-type second p-type region 9. In other words, the n-type portion may be made p-type, and the p-type portion may be made n-type.

[0105] Although the embodiments of the present disclosure have been described in detail, these are merely specific examples used to clarify the technical content of the present disclosure, and the present disclosure should not be construed as being limited to these specific examples, and the scope of the present disclosure is limited only by the appended claims.

[0106] This application corresponds to Patent Application No. 2021-047583 filed with the Japan Patent Office on March 22, 2021, the entire disclosures of which are incorporated herein by reference. [Explanation of symbols]

[0107] 1,1A Photodetector Array 2 boards 3. Buffer layer 4. Light absorption layer 4a Chamfered part 5 Window layer 6 n-type layer 6a Chamfered part 7 Contact layer 8 1st p-type region (p-type region) 9 2nd p-type region 10. Insulating film 10a Chamfered part 11 Contact hole 12 1st electrode 13 Second electrode 14 3rd electrode 15 Bonding Pads 16 Wiring 17,18 marks 20 Semiconductor stacked structure 30 Photodetector 41 Window material layer 42 Contact material layer 43 Insulating film 43 Insulating material film 50 Separation groove 91 Part 1 92 Part 2

Claims

1. A substrate; a semiconductor laminate structure formed on the substrate, The semiconductor laminated structure is a light absorbing layer disposed above the substrate; a plurality of window layers of a first conductivity type formed on the light absorption layer and spaced apart from each other; a first second-conductivity-type region is formed in each of the window layers in the semiconductor laminate structure, the first second-conductivity-type region extending from a surface of the window layer opposite to the light absorption layer into the light absorption layer; a second second-conductivity type region is formed in the light absorbing layer, the second second-conductivity type region being arranged to surround each of the plurality of window layers in a plan view and extending from a surface of the light absorbing layer opposite to the substrate toward a surface of the light absorbing layer facing the substrate; the second second-conductivity-type region extends from the surface of the light absorbing layer opposite the substrate to partway through the thickness of the light absorbing layer.

2. A substrate; a semiconductor laminate structure formed on the substrate, The semiconductor laminated structure is a light absorbing layer disposed above the substrate; a plurality of first conductivity type window layers formed on the light absorption layer and spaced apart from each other; an insulating film formed on the light absorption layer so as to cover the plurality of window layers; a plurality of first electrodes provided for each of the window layers and disposed on the insulating film; a first second-conductivity-type region is formed in each of the window layers in the semiconductor laminate structure, the first second-conductivity-type region extending from a surface of the window layer opposite to the light absorption layer into the light absorption layer; a second second-conductivity type region is formed in the light absorbing layer, the second second-conductivity type region being arranged to surround each of the plurality of window layers in a plan view and extending from a surface of the light absorbing layer opposite to the substrate toward a surface of the light absorbing layer facing the substrate; each of the first electrodes is electrically connected to a corresponding one of the first second conductivity type regions; The light-receiving element array, wherein the first electrode is endless in plan view.

3. 3. The light-receiving element array according to claim 2, wherein the second second-conductivity type region extends from a surface of the light-absorbing layer opposite to the substrate to partway through the thickness of the light-absorbing layer.

4. 3. The light-receiving element array according to claim 2, wherein the second second-conductivity type region penetrates the light-absorbing layer.

5. A substrate; a semiconductor laminate structure formed on the substrate, The semiconductor laminated structure is a light absorbing layer disposed above the substrate; a plurality of first conductivity type window layers formed on the light absorption layer and spaced apart from each other; an insulating film formed on the light absorption layer so as to cover the plurality of window layers; a plurality of first electrodes provided for each of the window layers and disposed on the insulating film; a second conductivity type region is formed in each of the window layers in the semiconductor laminate structure, the second conductivity type region extending from a surface of the window layer opposite to the light absorption layer into the light absorption layer, the light absorbing layer is disposed so as to surround each of the plurality of window layers in a plan view, a separation groove is formed extending from a surface of the light absorbing layer opposite to the substrate toward a surface of the light absorbing layer facing the substrate, each of the first electrodes is electrically connected to a corresponding one of the first second conductivity type regions; The light-receiving element array, wherein the first electrode is endless in plan view.

6. The light-receiving element array according to claim 5 , wherein the separation groove penetrates the light absorption layer in the thickness direction.

7. 7. The light-receiving element array according to claim 2, wherein the insulating film is an anti-reflection film that prevents reflection of light having a preset wavelength.

8. 8. The light-receiving element array according to claim 1, further comprising a second electrode formed on a second main surface of the substrate.

9. 9. The light-receiving element array according to claim 1, wherein the plurality of window layers are arranged in a matrix in plan view.

10. 10. The light-receiving element array according to claim 1, wherein the semiconductor laminated structure includes a buffer layer of a first conductivity type formed between the substrate and the light absorbing layer.

11. the buffer layer has an exposed surface on a part of the surface opposite to the substrate, The light-receiving element array according to claim 10 , further comprising a third electrode formed on the exposed surface.

12. the substrate is an n-type InP substrate, the light absorption layer is an undoped InGaAs layer, 11. The photodiode array according to claim 1, wherein the window layer is an n-type InP layer.

13. the substrate is an n-type InP substrate, the buffer layer is an n-type InP layer, the light absorption layer is an undoped InGaAs layer, 12. The photodiode array according to claim 10, wherein the window layer is an n-type InP layer.

14. forming a semiconductor laminated structure on a substrate, the semiconductor laminated structure including a light absorbing layer and a plurality of window layers of a first conductivity type formed on the light absorbing layer and spaced apart from each other; forming a first second-conductivity-type region for each window layer in the semiconductor stack structure, the first second-conductivity-type region extending from a surface of the window layer opposite to the light absorption layer into the light absorption layer; forming second second-conductivity-type regions that are arranged to surround each of the plurality of window layers in a plan view and that extend from a surface of the light absorbing layer opposite to the substrate toward a surface of the light absorbing layer facing the substrate, A method for manufacturing a light-receiving element array, wherein the step of forming the first second-conductivity type region and the step of forming the second second-conductivity type region are carried out in the same process.

15. forming an insulating film on the light absorbing layer so as to cover the plurality of window layers; forming a first electrode on the insulating film for each of the window layers, the first electrode being electrically connected to the first second-conductivity-type region; The method for manufacturing a light-receiving element array according to claim 14 , further comprising the step of forming a second electrode on a surface of the substrate opposite to the semiconductor laminated structure.

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