Semiconductor Devices

Abstract

This semiconductor device comprises a peripheral region surrounding a cell region, a gate electrode disposed in the peripheral region, and an emitter electrode. The emitter electrode includes a cell electrode portion, a peripheral electrode portion formed at a distance from the cell electrode portion in the peripheral region, and a connecting portion connecting the cell electrode portion and the peripheral electrode portion. The peripheral region includes a well region formed to surround the cell region, an insulating film and an intermediate insulating film that cover the well region, and a gate finger embedded in the insulating films. The connecting portion is formed across the gate finger on the intermediate insulating film. The peripheral electrode portion is electrically connected to the well region.

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] For example, in semiconductor devices such as IGBTs (Insulated Gate Bipolar Transistors) used in vehicle inverter devices, an emitter routing portion is formed integrally with the emitter electrode so as to surround the gate fingers in order to suppress heat generation (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2018-120990 Summary of the Invention [Problem to be solved by the invention]

[0004] However, because the emitter routing portion, gate fingers, and emitter electrode are spaced apart from one another, there is a limit to how much of the area of ​​the semiconductor device that can be formed with the emitter electrode can be occupied by the emitter electrode. Note that this problem is not limited to IGBTs, but can also occur in other transistors such as MOSFETs (metal-oxide-semiconductor field-effect transistors). [Means for solving the problem]

[0005] A semiconductor device that solves the above problem comprises a cell region in which a cell is provided, a peripheral region surrounding the cell region, a gate electrode arranged in the peripheral region, an electrode portion provided in the cell region, a peripheral electrode portion formed in the peripheral region at a distance from the electrode portion, and a drive electrode having a connection portion that connects the electrode portion and the peripheral electrode portion, wherein the peripheral region is provided with a well region which is a semiconductor region provided to surround the cell region, an insulating film that covers the well region and is provided to surround the cell region in a planar view, and a gate finger that is embedded in the insulating film, is connected to the gate electrode, and is formed to surround the cell region, and the connection portion is formed on the insulating film across the gate finger, and the peripheral electrode portion is electrically connected to the well region. [Effects of the Invention]

[0006] According to the semiconductor device, the area of ​​the drive electrode can be increased. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a plan view of a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is an enlarged view of the gate electrode and its periphery in the semiconductor device of FIG. [Figure 3] FIG. 3 is a cross-sectional view showing the cross-sectional structure of the cell region of the semiconductor device of FIG. [Figure 4] FIG. 4 is a cross-sectional view showing the cross-sectional structure of the peripheral region of the semiconductor device of FIG. [Figure 5] 5 is a cross-sectional view showing the cross-sectional structure of the semiconductor device taken along line 5-5 of FIG. [Figure 6] 6 is a cross-sectional view showing the cross-sectional structure of the semiconductor device of FIG. 1 taken along line 6-6. [Figure 7] FIG. 7 is a plan view of a semiconductor device of a comparative example. [Figure 8] FIG. 8 is a cross-sectional view showing the cross-sectional structure of the semiconductor device of the comparative example taken along line 8-8 of FIG. [Figure 9]FIG. 9 is a cross-sectional view showing the cross-sectional structure of the semiconductor device of the comparative example taken along line 9-9 of FIG. [Figure 10] FIG. 10 is a plan view of the semiconductor device according to the second embodiment. [Figure 11] FIG. 11 is an enlarged view of the gate electrode and its periphery in the semiconductor device of FIG. [Figure 12] 12 is a cross-sectional view showing the cross-sectional structure of the semiconductor device of FIG. 10 taken along line 12-12. [Figure 13] 13 is a cross-sectional view showing the cross-sectional structure of the semiconductor device of FIG. 10 taken along line 13-13. [Figure 14] FIG. 14 is an enlarged plan view of a gate electrode and its periphery in a semiconductor device according to a modified example. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments of a semiconductor device will be described with reference to the drawings. The embodiments shown below are intended to exemplify configurations and methods for embodying the technical ideas, and are not intended to limit the materials, shapes, structures, arrangements, dimensions, etc. of the components described below.

[0009] [First embodiment] (Configuration of semiconductor device) The configuration of one embodiment of a semiconductor device 10 will be described with reference to FIGS.

[0010] 1, a semiconductor device 10 according to this embodiment is a trench-gate IGBT (Insulated Gate Bipolar Transistor). The semiconductor device 10 is used as a switching element in, for example, an in-vehicle inverter. In this case, a current of, for example, 5 A or more and 1000 A or less flows through the semiconductor device 10.

[0011] As shown in FIG. 1, the semiconductor device 10 is formed, for example, in the shape of a rectangular plate. In this embodiment, the device main surface 10s of the semiconductor device 10 is formed, for example, in the shape of a square. In this embodiment, the length of one side of the device main surface 10s is approximately 11 mm. In other words, the chip size of the semiconductor device 10 of this embodiment is 11 mm square. The semiconductor device 10 has a device back surface 10r (see FIG. 3) facing the opposite side to the device main surface 10s, and four device side surfaces 10a to 10d formed between the device main surface 10s and the device back surface 10r. The device side surfaces 10a to 10d are, for example, surfaces connecting the device main surface 10s and the device back surface 10r, and are perpendicular to both the device main surface 10s and the device back surface 10r.

[0012] In the following description, the direction in which the device principal surface 10s and the device rear surface 10r face is referred to as the "z direction." The z direction can also be said to be the height direction of the semiconductor device 10. Two mutually orthogonal directions perpendicular to the z direction are referred to as the "x direction" and the "y direction." In this embodiment, the device side surfaces 10a and 10b form both end faces of the semiconductor device 10 in the x direction, and the device side surfaces 10c and 10d form both end faces of the semiconductor device 10 in the y direction. For convenience, the direction from the device rear surface 10r toward the device principal surface 10s is referred to as the "upward direction," and the direction from the device principal surface 10s toward the device rear surface 10r is referred to as the "downward direction." Viewing the semiconductor device 10 from the z direction is referred to as a "planar view."

[0013] As shown in FIG. 2, the semiconductor device 10 includes an emitter electrode 21, a gate electrode 22, and a collector electrode 27 (see FIG. 3) as external electrodes for connecting the semiconductor device 10 to the outside.

[0014] The emitter electrode 21 is an electrode that constitutes the emitter of the IGBT and is an electrode through which the main current of the semiconductor device 10 flows. The emitter electrode 21 is formed on the device main surface 10s. An opening 21a is formed in the emitter electrode 21 at a position closer to the device side surface 10c than the center in the y direction and at the center in the x direction.

[0015] The gate electrode 22 is an electrode that constitutes the gate of the IGBT, and is an electrode to which a drive voltage signal for driving the semiconductor device 10 is supplied from outside the semiconductor device 10. The gate electrode 22 is formed on the device main surface 10s. The gate electrode 22 is formed in the opening 21a of the emitter electrode 21.

[0016] The collector electrode 27 is an electrode that constitutes the collector of the IGBT, and is an electrode through which the main current of the semiconductor device 10 flows. That is, in the semiconductor device 10, the main current flows from the collector electrode 27 to the emitter electrode 21. The collector electrode 27 is formed on the device rear surface 10r. More specifically, the collector electrode 27 is formed over the entire device rear surface 10r.

[0017] As indicated by dashed lines in Figures 1 and 2, the semiconductor device 10 includes a cell region 11 in which a plurality of cells 11A (see Figure 3) are formed, and an outer peripheral region 12 provided outside the cell region 11 so as to surround the cell region 11. Here, the cell 11A refers to a main cell in which a transistor is formed. In other words, the cell region 11 is a region in which a transistor is formed. In this embodiment, the shape of the cell region 11 in a plan view is rectangular.

[0018] An emitter electrode 21 is provided in the cell region 11. The emitter electrode 21 is formed over most of the cell region 11. In a plan view, the emitter electrode 21 has a shape that follows the shape of the cell region 11. No cells 11A are formed in the cell region 11 at positions that overlap with the gate electrodes 22. In other words, the cell region 11 has recesses 11a that are recessed to avoid the gate electrodes 22.

[0019] The peripheral region 12 is a region where a termination structure that improves the dielectric strength of the semiconductor device 10 is provided. In plan view, the peripheral region 12 is an annular region formed on the outer periphery of the device main surface 10s. In other words, in plan view, the peripheral region 12 is the region of the device main surface 10s other than the cell region 11.

[0020] A part of the emitter electrode 21 and the gate electrode 22 are arranged in the peripheral region 12. The peripheral region 12 also includes a gate finger 23, a field limiting ring (FLR) portion 24, and an equipotential ring 25. The emitter electrode 21, the gate electrode 22, a plurality of field plates 24b (described later, eight in this embodiment) of the FLR portion 24, and the equipotential ring 25 include a common metal film. This metal film is formed of a material containing AlCu (an alloy of aluminum and copper), for example.

[0021] The gate finger 23 is configured to quickly supply the current supplied to the gate electrode 22 to the cells 11A in the portion of the emitter electrode 21 that is distant from the gate electrode 22. The gate finger 23 is connected to the gate electrode 22.

[0022] The gate fingers 23 are provided on the outer periphery of the emitter electrode 21. The gate fingers 23 are formed so as to surround the cell region 11. The gate fingers 23 are formed of metal wiring. In a plan view, the gate fingers 23 are arranged at positions overlapping the outer periphery of the emitter electrode 21. In this embodiment, the gate fingers 23 are formed of a material containing tungsten (W).

[0023] The gate finger 23 includes gate fingers 23A, 23B, and 23C. Gate finger 23A extends from the gate electrode 22 toward the device side surface 10a and is formed to surround the cell region 11 from the device side surfaces 10c, 10a, and 10d. Gate finger 23B extends from the gate electrode 22 toward the device side surface 10b and is formed to surround the cell region 11 from the device side surfaces 10c, 10b, and 10d. The tip of gate finger 23A and the tip of gate finger 23B face each other with a gap in the x-direction at a portion closer to the device side surface 10d than the emitter electrode 21. Gate finger 23C is formed at a position overlapping with the gate electrode 22 in a plan view. Gate finger 23C connects gate finger 23A and gate finger 23B. Note that a plurality of gate fingers 23 may be provided.

[0024] The FLR section 24 is a termination structure for improving the breakdown voltage of the semiconductor device 10, and is provided outside the emitter electrode 21. The FLR section 24 is formed in a ring shape surrounding the emitter electrode 21 and the gate electrode 22. In this embodiment, the FLR section 24 is formed in a closed ring shape. The FLR section 24 has the function of improving the breakdown voltage of the semiconductor device 10 by alleviating the electric field in the peripheral region 12 and suppressing the influence of external ions.

[0025] The equipotential ring 25 is a termination structure for improving the breakdown voltage of the semiconductor device 10, and is formed in a ring shape to surround the FLR portion 24. In this embodiment, the equipotential ring 25 is formed in a closed ring shape. The equipotential ring 25 has the function of improving the breakdown voltage of the semiconductor device 10.

[0026] The semiconductor device 10 includes a passivation film 13 (see FIG. 4) that covers both the cell region 11 and the peripheral region 12. The passivation film 13 covers the emitter electrode 21, the gate electrode 22, the FLR portion 24, and the equipotential ring 25. The passivation film 13 is a protective film that protects the semiconductor device 10 from the outside of the semiconductor device 10. The passivation film 13 is an organic insulating film formed of a material containing, for example, polyimide (PI). Note that the passivation film 13 is omitted from FIGS. 1 and 2 to make the drawings easier to understand.

[0027] The passivation film 13 is provided with a first opening (not shown) that exposes a portion of the emitter electrode 21 and a second opening (not shown) that exposes a majority of the gate electrode 22. The portion of the emitter electrode 21 exposed by the first opening constitutes an emitter electrode pad. The portion of the gate electrode 22 exposed by the second opening constitutes a gate electrode pad.

[0028] Fig. 3 shows an example of a cross-sectional structure of a part of the cell region 11. For convenience, hatching of some of the components of the semiconductor device 10 in the cell region 11 is omitted in Fig. 3.

[0029] 3, the semiconductor device 10 includes a semiconductor substrate 30. The semiconductor substrate 30 is, for example, an n - The semiconductor substrate 30 is made of a material containing silicon (Si) and has a thickness of, for example, 50 μm or more and 200 μm or less.

[0030] The semiconductor substrate 30 has a substrate front surface 30s and a substrate back surface 30r that face opposite each other in the z direction. In other words, the z direction can also be said to be the thickness direction of the semiconductor substrate 30. The semiconductor substrate 30 is formed by sequentially stacking p + a n-type collector layer 31, an n-type buffer layer 32, and an n -The semiconductor device 10 has a structure in which a collector electrode 27 is formed on a rear surface 30r of the substrate. The collector electrode 27 is formed over substantially the entire surface of the rear surface 30r of the substrate. The surface of the collector electrode 27 opposite to the rear surface 30r of the substrate forms the rear surface 10r of the semiconductor device 10.

[0031] As a p-type dopant for collector layer 31, for example, B (boron), Al (aluminum), etc. are used. The impurity concentration of collector layer 31 is, for example, 1×10 15 cm -3 Over 2×10 19 cm -3 The following is the result.

[0032] For example, N (nitrogen), P (phosphorus), As (arsenic), etc. are used as n-type dopants for buffer layer 32 and drift layer 33. The impurity concentration of buffer layer 32 is, for example, 1×10 15 cm -3 5x10 or more 17 cm -3 The impurity concentration of the drift layer 33 is lower than that of the buffer layer 32, for example, 1×10 13 cm -3 5x10 or more 14 cm -3 The following is the result.

[0033] A p-type base region 34 is formed on the surface of the drift layer 33, i.e., on the substrate surface 30s. The base region 34 is formed over substantially the entire surface of the substrate surface 30s. The impurity concentration of the base region 34 is, for example, 1×10 16 cm -3 More than 1×10 18 cm -3 The depth of the base region 34 from the substrate surface 30s is, for example, not less than 1.0 μm and not more than 4.0 μm.

[0034] A plurality of trenches 35 are arranged side by side on the surface (substrate surface 30s) of the base region 34 in the cell region 11. The trenches 35 extend, for example, along the y direction and are spaced apart from one another in the x direction, thereby dividing the cell region 11A into striped cells 11A. The spacing between adjacent trenches 35 in the x direction (the center-to-center distance between the trenches 35) is, for example, 1.5 μm or more and 7.0 μm or less. The width of each trench 35 (the dimension of the trench 35 in the x direction) is, for example, 0.5 μm or more and 3.0 μm or less. Each trench 35 penetrates the base region 34 in the z direction and extends partway through the drift layer 33. Note that the trenches 35 may be formed in a lattice pattern to divide the matrix-shaped cells 11A.

[0035] The surface of the base region 34 in the cell region 11 (substrate surface 30s) has n + The emitter regions 36 are formed in the base region 34. The emitter regions 36 are arranged on both sides of the trench 35 in the x direction. In other words, the emitter regions 36 can be said to be provided on both sides of the trench 35 in the arrangement direction of the trenches 35 in the base region 34. Therefore, two emitter regions 36 are arranged with a gap between them in the x direction between adjacent trenches 35 in the x direction. The depth of each emitter region 36 is, for example, 0.2 μm or more and 0.6 μm or less. The impurity concentration of each emitter region 36 is higher than that of the base region 34, for example, 1×10 19 cm -3 5x10 or more 20 cm -3 The following is the result.

[0036] The surface of the base region 34 in the cell region 11 (substrate surface 30s) contains p +A base contact region 37 of the type is formed. The base contact region 37 is provided at a position adjacent to the emitter region 36 in the x direction. In other words, the base contact region 37 is provided in the x direction between two emitter regions 36 provided between the x directions of the trenches 35 adjacent to each other in the x direction. Each base contact region 37 may be formed deeper than the emitter region 36. The depth of each base contact region 37 is, for example, 0.2 μm or more and 0.8 μm or less. The impurity concentration of each base contact region 37 is higher than that of the base region 34, for example, 5×10 18 cm -3 More than 1×10 20 cm -3 The following is the result.

[0037] An insulating film 38 is integrally formed on both the inner surface of each trench 35 and the substrate surface 30s. Therefore, it can be said that the insulating film 38 is formed on the surface of the drift layer 33. The insulating film 38 includes, for example, silicon oxide (SiO2). The thickness of the insulating film 38 is, for example, 1100 Å or more and 1300 Å or less. It can also be said that the insulating film 38 in the cell region 11 constitutes a gate insulating film. The insulating film 38 formed on the substrate surface 30s has a back surface 38r facing the same side as the substrate back surface 30r. In this embodiment, the back surface 38r of the insulating film 38 is in contact with the substrate surface 30s.

[0038] An electrode material made of, for example, polysilicon is buried in each trench 35 via an insulating film 38. The electrode material buried in each trench 35 is electrically connected to either the gate electrode 22 (gate finger 23) or the emitter electrode 21. That is, the electrode material buried in each trench 35 forms a gate trench 22A and an emitter trench 21TE. In this embodiment, the gate trenches 22A and the emitter trenches 21TE are alternately provided in the arrangement direction of the multiple trenches 35. In this embodiment, both the gate trenches 22A and the emitter trenches 21TE are buried up to the opening end of each trench 35.

[0039] An intermediate insulating film 39 is formed on a surface 38s of the insulating film 38 provided on the substrate surface 30s. The intermediate insulating film 39 includes, for example, SiO2. The thickness of the intermediate insulating film 39 is thicker than that of the insulating film 38, and is, for example, not less than 3000 Å and not more than 15000 Å.

[0040] The emitter electrode 21 is formed on a surface 39s of the intermediate insulating film 39. The intermediate insulating film 39 is an interlayer insulating film that fills both the space between the emitter electrode 21 and the gate trench 22A and the space between the emitter electrode 21 and the emitter trench 21TE.

[0041] A contact hole 40a exposing the base contact region 37 is formed in both the intermediate insulating film 39 and the insulating film 38 in the cell region 11. A part of the emitter electrode 21 is embedded in the contact hole 40a and is in contact with the base contact region 37.

[0042] FIG. 4 shows an example of the cross-sectional structure of the outer peripheral region 12. As shown in FIG. As shown in FIG. 4, a well region 34A, which is a semiconductor region of the second conductivity type (p-type in this embodiment), is formed in the peripheral region 12. The well region 34A is formed on the surface of the drift layer 33 (substrate surface 30s of the semiconductor substrate 30). The depth of the well region 34A is deeper than the depth of the base region 34. In this embodiment, the depth of the well region 34A is deeper than the depth of the trench 35. The impurity concentration of the well region 34A is higher than the impurity concentration of the drift layer 33 and lower than the impurity concentration of the base region 34. In one example, the impurity concentration of the well region 34A is 1×10 16 cm -3 More than 1×10 18 cm -3 The following is the result.

[0043] The FLR portion 24 is formed at a position outside the well region 34 A. The FLR portion 24 is composed of a plurality of (four in this embodiment) annular conductors and semiconductor regions that are arranged at a distance from each other.

[0044] A plurality of (eight in this embodiment) annular guard rings 24a are formed on the substrate surface 30s of the semiconductor substrate 30. In this embodiment, each guard ring 24a is formed in a closed ring shape. Each guard ring 24a is partially formed in the drift layer 33. Each guard ring 24a is a semiconductor region of a second conductivity type (p-type in this embodiment) and is arranged spaced apart from each other in a direction perpendicular to the z direction. In this embodiment, the depth of each guard ring 24a is the same as the depth of the well region 34A. For example, B, Al, or the like is used as the p-type dopant for each guard ring 24a. The impurity concentration of each guard ring 24a is the same as the impurity concentration of the well region 34A, for example, 1×10 16 cm -3 More than 1×10 18 cm -3 In this case, the guard rings 24a and the well region 34A may be formed in the same process.

[0045] The FLR section 24 has a plurality of field plates 24b provided corresponding to the plurality of guard rings 24a. Each field plate 24b is provided on an intermediate insulating film 39. In plan view, the field plates 24b are provided at positions overlapping the corresponding guard rings 24a.

[0046] The field plates 24b are in contact with the corresponding guard rings 24a. More specifically, openings 40b (see FIG. 5) exposing each guard ring 24a are individually formed in the intermediate insulating film 39 and the insulating film 38 at positions corresponding to each guard ring 24a. Each field plate 24b is in contact with each guard ring 24a via the openings 40b corresponding to each guard ring 24a. In this embodiment, each guard ring 24a and each field plate 24b is in an electrically floating state.

[0047] The equipotential ring 25 is a first conductivity type (n +The semiconductor device has a channel stop region (not shown) of the insulating film 38 and the intermediate insulating film 39, internal wiring (not shown) provided in the insulating film 38 and the intermediate insulating film 39, and a surface-side wiring 25a provided on the intermediate insulating film 39.

[0048] The channel stop region is formed from the position overlapping with the surface-side wiring 25a to the device side surface 10c when viewed from the z direction. The channel stop region is disposed outward (closer to the device side surface 10c) with respect to the internal wiring. The impurity concentration of the channel stop region is, for example, the same as the impurity concentration of the emitter region 36 (see FIG. 3), and is 1×10 19 cm -3 5x10 or more 20 cm -3 In this case, for example, the channel stop region is formed in the same process as the emitter region 36.

[0049] The internal wiring is provided on an insulating film 38 and is covered with an intermediate insulating film 39. The internal wiring is made of an electrode material such as polysilicon. An oxide film is formed on the surface of the internal wiring.

[0050] The surface-side wiring 25a is provided at a position overlapping both the channel stop region and the internal wiring in a plan view. The surface-side wiring 25a is formed of a material containing, for example, AlCu. The surface-side wiring 25a is electrically connected to both the channel stop region and the internal wiring. More specifically, first openings are provided in the intermediate insulating film 39 and the insulating film 38 at positions corresponding to the channel stop region. The surface-side wiring 25a has a first contact that contacts the channel stop region through the first opening. A second opening is provided in the intermediate insulating film 39 at a position corresponding to the internal wiring. The surface-side wiring 25a has a second contact that contacts the internal wiring through the second opening.

[0051] 5 and 6 show an example of the cross-sectional structure of a portion of the cell region 11 and the peripheral region 12. For convenience, hatching of some of the components of the semiconductor device 10 in the portion of the cell region 11 and the peripheral region 12 is omitted in FIGS. 5 and 6. For convenience, passivation film 13 is also omitted in FIGS. 5 and 6.

[0052] As shown in FIGS. 2, 5, and 6, in this embodiment, the well region 34A is provided adjacent to the cell region 11. In plan view, the well region 34A is provided so as to surround the cell region 11. In plan view, the well region 34A is formed in an annular shape having a width in a direction (e.g., the x direction or the y direction) perpendicular to the z direction. As shown in FIG. 5, the well region 34A is formed at a position overlapping the gate electrode 22. In plan view, it can be said that the gate electrode 22 is disposed within the well region 34A.

[0053] The well region 34A has a first well region 34AA having a first width around the cell region 11 and a second well region 34AB having a second width greater than the first width. The second well region 34AB is formed so as to enter the recess 11a of the cell region 11. The second well region 34AB has a rectangular shape in plan view. In plan view, the second well region 34AB is formed at a position overlapping the gate electrode 22.

[0054] The first well region 34AA is connected to both x-direction end portions of the second well region 34AB and is formed in a ring shape surrounding the cell region 11. The first well region 34AA is connected to one of both y-direction end portions of the second well region 34AB that is farther from a cell electrode portion 21A (described later) of the emitter electrode 21. In other words, the second well region 34AB is formed inward from the FLR portion 24 and adjacent to the FLR portion 24.

[0055] The well region 34A has an inner peripheral portion 34B, which is closer to the cell electrode portion 21A than the center in the width direction, and an outer peripheral portion 34C, which is farther from the cell electrode portion 21A than the center in the width direction. The outer peripheral portion 34C can also be said to be closer to the outer peripheral region 12 than the center in the width direction.

[0056] An insulating film 38 is formed on the substrate surface 30s in the peripheral region 12. An intermediate insulating film 39 is formed on the insulating film 38 formed on the substrate surface 30s. That is, both the insulating film 38 and the intermediate insulating film 39 are formed across both the cell region 11 and the peripheral region 12.

[0057] The gate electrode 22 is formed on a surface 39s of the intermediate insulating film 39. The intermediate insulating film 39 can be considered an interlayer insulating film that fills the gap between the gate electrode 22 and the well region 34A. The intermediate insulating film 39 can also be considered an interlayer insulating film that fills the gap between the multiple field plates 24b and the multiple guard rings 24a of the FLR portion 24 (see FIG. 4 for both).

[0058] In this embodiment, the intermediate insulating film 39 and the insulating film 38 correspond to the "insulating film." The surface 39s of the intermediate insulating film 39 corresponds to the "surface of the insulating film," and the back surface 38r of the insulating film 38 corresponds to the "back surface of the insulating film."

[0059] (Configuration of emitter electrode, gate electrode, and gate finger) The configurations of the emitter electrode 21, the gate electrode 22, and the gate finger 23A (23B) will be described with reference to Figures 2, 5, and 6. Note that the configuration of the gate finger 23B is the same as the configuration of the gate finger 23A, and therefore a description thereof will be omitted.

[0060] The emitter electrode 21 is provided at a position overlapping both the cell region 11 and the outer peripheral region 12 in plan view. It can also be said that the emitter electrode 21 is provided inward of the annular FLR portion 24.

[0061] The emitter electrode 21 has a cell electrode portion 21A provided in the cell region 11, a peripheral electrode portion 21B provided in the peripheral region 12 at a distance from the cell electrode portion 21A, and a connection portion 21G connecting the cell electrode portion 21A and the peripheral electrode portion 21B. In this embodiment, the cell electrode portion 21A, the peripheral electrode portion 21B, and the connection portion 21G are integrally formed.

[0062] In a plan view, the cell electrode portion 21A covers the entire cell region 11. Therefore, the shape of the cell electrode portion 21A in a plan view is rectangular. Here, in this embodiment, the cell electrode portion 21A corresponds to an "electrode portion."

[0063] In a plan view, the peripheral electrode portion 21B covers the inner circumferential region of the peripheral region 12. The inner circumferential region of the peripheral region 12 is a region of the peripheral region 12 that is located more inward than the FLR portion 24. The peripheral electrode portion 21B is located more outward than the gate fingers 23. In other words, the peripheral electrode portion 21B covers a region of the inner circumferential region of the peripheral region 12 that is close to the FLR portion 24. The peripheral electrode portion 21B is also formed to avoid the gate electrode 22. In this way, the peripheral electrode portion 21B can also be said to be a portion that is provided in the peripheral region 12 at a distance from the cell region 11 in a plan view.

[0064] In plan view, the peripheral electrode portion 21B covers a region outside the gate finger 23 in the well region 34A other than the region overlapping with the gate electrode 22. More specifically, the peripheral electrode portion 21B covers a portion of the peripheral portion 34C of the second well region 34AB outside the gate electrode 22. The peripheral electrode portion 21B also covers a region outside the gate fingers 23A and 23B in the peripheral portion 34C of the first well region 34AA.

[0065] In this embodiment, the peripheral electrode portion 21B is provided in a ring shape surrounding the cell electrode portion 21A in a plan view. The peripheral electrode portion 21B is provided as a peripheral portion of the emitter electrode 21.

[0066] As described above, the emitter electrode 21 has the opening 21a in which the gate electrode 22 is disposed. Both the peripheral electrode portion 21B and the connection portion 21G include a portion of the emitter electrode 21 adjacent to the opening 21a in the x-direction, in other words, a portion of the emitter electrode 21 adjacent to the gate electrode 22 in the x-direction. In this embodiment, as shown in FIG. 2, the opening 21a can be said to be formed across the peripheral electrode portion 21B and the connection portion 21G in the x-direction.

[0067] 5 and 6, the peripheral electrode portion 21B has a peripheral end portion 21C located outward in the y direction from the gate electrode 22. Here, the peripheral end portion 21C of the peripheral electrode portion 21B refers to the end portion of the peripheral electrode portion 21B formed in a ring shape with a certain width that is closer to the FLR portion 24 in the width direction. The peripheral end portion 21C has a portion that is located between the gate electrode 22 and the FLR portion 24 in the y direction.

[0068] The connection portion 21G is provided between the cell electrode portion 21A and the outer peripheral electrode portion 21B. In plan view, the connection portion 21G is disposed in the outer peripheral region 12 and covers the gate fingers 23A and 23B. Therefore, the connection portion 21G covers the inner peripheral region of the outer peripheral region 12. In plan view, the connection portion 21G is formed so as to surround the entire periphery of the cell electrode portion 21A. In other words, the connection portion 21G is formed in a ring shape having a certain width.

[0069] In plan view, the connection portion 21G covers a region of the well region 34A that is inward of the gate finger 23, except for the region that overlaps with the gate electrode 22. More specifically, the connection portion 21G covers a portion of the inner periphery 34B of the second well region 34AB that is inward of the gate electrode 22. The connection portion 21G also covers the inner periphery 34B and part of the outer periphery 34C of the first well region 34AA. The connection portion 21G covers a region of the outer periphery 34C of the first well region 34AA that overlaps with the gate fingers 23A, 23B in plan view. In this way, the emitter electrode 21 covers the entire well region 34A by the outer electrode portion 21B and the connection portion 21G. The outer electrode portion 21B has the connection portion 21G. In plan view, the gate fingers 23A, 23B are provided at positions that overlap with the outer electrode portion 21B.

[0070] The insulating film 38 and the intermediate insulating film 39 are provided over both the cell region 11 and the peripheral region 12. Therefore, the insulating film 38 and the intermediate insulating film 39 are formed so as to cover the well region 34A.

[0071] A first opening 41 and a second opening 42 are formed in both the insulating film 38 and the intermediate insulating film 39 so as to penetrate the insulating film 38 and the intermediate insulating film 39. These openings 41, 42 expose the well region 34A from the insulating film 38 and the intermediate insulating film 39. In other words, both the first opening 41 and the second opening 42 are provided at positions that overlap the well region 34A in a plan view.

[0072] The first opening 41 is formed on the opposite side of the gate finger 23 from the cell electrode portion 21A. In other words, the first opening 41 is formed at a position farther from the cell electrode portion 21A than the gate finger 23. The first opening 41 extends in the x direction at a position overlapping with the outer circumferential end portion 21C. In other words, the first opening 41 is formed on the opposite side of the gate electrode 22 in the y direction from the cell electrode portion 21A.

[0073] The first opening 41 is formed at a position overlapping the outer periphery 34C of the well region 34A in plan view. In the present embodiment, the first opening 41 is formed at a position overlapping the outer periphery edge of the well region 34A. The outer periphery edge of the well region 34A is the end closer to the FLR portion 24 of both ends of the well region 34A in the width direction of the well region 34A.

[0074] The second opening 42 is formed closer to the cell electrode portion 21A than the gate finger 23. As shown in Fig. 2, in plan view, the second opening 42 has a recess 42a that is recessed along the shape of the opening 21a in the emitter electrode 21. In other words, the second opening 42 extending in the y direction is provided at a position that overlaps with the gate electrode 22 when viewed from the x direction, and has a bent shape in plan view so as to avoid the gate electrode 22.

[0075] The second opening 42 is formed at a position overlapping the inner periphery 34B of the well region 34A in plan view. In the present embodiment, the second opening 42 is formed at a position overlapping the inner periphery edge of the well region 34A. The inner periphery edge of the well region 34A is the end closer to the emitter electrode 21 of both ends of the well region 34A in the width direction of the well region 34A.

[0076] In plan view, peripheral electrode portion 21B is formed so as to cover first opening 41. Peripheral electrode portion 21B has first contact 21D embedded in first opening 41. Therefore, the shape of first contact 21D in plan view is the same as the shape of first opening 41 in plan view.

[0077] In a plan view, the connection portion 21G is formed so as to cover the second opening 42. The connection portion 21G has a second contact 21E embedded in the second opening 42. Therefore, the shape of the second contact 21E in a plan view is the same as the shape of the second opening 42 in a plan view.

[0078] The first contact 21D is in contact with the outer periphery 34C of the well region 34A. As a result, the peripheral electrode portion 21B is electrically connected to the well region 34A. In this embodiment, the first contact 21D is in contact with the outer periphery edge of the well region 34A. That is, the peripheral electrode portion 21B is electrically connected to the well region 34A at the outer periphery edge of the well region 34A. The first contact 21D is formed in a ring shape at the outer periphery edge 21C of the peripheral electrode portion 21B in a plan view. Therefore, the first contact 21D has a portion that is arranged on the opposite side of the gate electrode 22 from the cell electrode portion 21A.

[0079] The second contact 21E is in contact with the inner peripheral portion 34B of the well region 34A. As a result, the connection portion 21G is electrically connected to the well region 34A. The second contact 21E is formed in an annular shape at the inner end portion of the connection portion 21G in a plan view. Here, the inner end portion of the connection portion 21G refers to a portion of the annular connection portion 21G that is closer to the cell electrode portion 21A in the width direction. Therefore, it can be said that the second contact 21E has a portion that is arranged closer to the cell electrode portion 21A than the gate electrode 22. In this embodiment, the second contact 21E is in contact with the inner peripheral end portion of the well region 34A. In other words, the connection portion 21G is electrically connected to the well region 34A at the inner peripheral end portion of the well region 34A.

[0080] The gate finger 23 is embedded in an insulating film including an insulating film 38 and an intermediate insulating film 39. In this embodiment, the gate finger 23 is formed on a surface 38s of the insulating film 38 and is covered with the intermediate insulating film 39.

[0081] 2 and 6, the gate fingers 23A and 23B (not shown in FIG. 6) are provided at positions overlapping the connection portion 21G in a plan view. The gate fingers 23A and 23B are arranged at positions overlapping the well region 34A in a plan view. The gate fingers 23A and 23B can also be said to be arranged between the first contact 21D and the second contact 21E in a plan view. In this embodiment, the gate fingers 23A and 23B are arranged near the center of the first well region 34AA in the width direction of the well region 34A. In one example, as shown in FIG. 6, one of the multiple gate fingers 23A is arranged at a position overlapping the outer periphery 34C of the first well region 34AA in a plan view, and another is arranged at a position overlapping the inner periphery 34B of the first well region 34AA in a plan view. The remaining one of the plurality of gate fingers 23A is arranged at a position overlapping the boundary between the inner periphery 34B and the outer periphery 34C of the first well region 34AA in a plan view. The arrangement positions of the plurality of gate fingers 23B with respect to the first well region 34AA are the same as those of gate finger 23A.

[0082] 5, the gate finger 23C is provided at a position overlapping with the outer peripheral end (the end closer to the FLR portion 24) of both ends of the gate electrode 22 in the y direction in a plan view. In other words, the gate finger 23C is disposed between the first contact 21D and the second contact 21E, closer to the first contact 21D. In addition, it can be said that the gate finger 23C is disposed at a position overlapping with the outer peripheral portion 34C of the second well region 34AB in a plan view. In this embodiment, the gate finger 23C extends along the x direction.

[0083] An opening 39a exposing the gate finger 23A is formed in the intermediate insulating film 39 corresponding to the gate finger 23C. That is, the opening 39a is not formed in the intermediate insulating film 39 corresponding to the gate fingers 23A and 23B. The gate electrode 22 has a buried electrode portion 22c buried in the opening 39a. The buried electrode portion 22c is in contact with the gate finger 23C. This electrically connects the gate electrode 22 and the gate finger 23C.

[0084] (Method of manufacturing the semiconductor device 10) Next, an outline of a method for manufacturing the semiconductor device 10 of this embodiment will be described. The method for manufacturing the semiconductor device 10 includes the steps of: - The method includes the steps of preparing a semiconductor substrate 30 having a p-type drift layer 33, forming a p-type well region 34A and a plurality of guard rings 24a in the semiconductor substrate 30, forming a plurality of trenches 35, forming an insulating film 38, and filling each trench with polysilicon as an electrode material to form an emitter trench 21TE and a gate trench 22A. These steps are performed by a known method.

[0085] The method for manufacturing the semiconductor device 10 includes a step of forming the gate fingers 23. The gate fingers 23 are formed by forming metal wiring made of a material containing, for example, tungsten (W) on the surface 38s of the insulating film 38.

[0086] The method for manufacturing the semiconductor device 10 includes the steps of forming an intermediate insulating film 39, forming openings 41 and 42 in both the intermediate insulating film 39 and the insulating film 38, and forming an opening 39a in the intermediate insulating film 39. First, the intermediate insulating film 39 is formed on the exposed surface 38s of the insulating film 38. In this case, the intermediate insulating film 39 is formed so as to cover the gate finger 23. Next, the opening 39a, the first opening 41, and the second opening 42 are formed in both the intermediate insulating film 39 and the insulating film 38. Next, the opening 39a is formed in a region of the intermediate insulating film 39 where the gate electrode 22 is to be formed. As a result, the gate finger 23C is exposed through the opening 39a.

[0087] The method for manufacturing the semiconductor device 10 includes a step of forming the emitter electrode 21, the gate electrode 22, the plurality of field plates 24b of the FLR portion 24, and the equipotential ring 25. This step is performed by a known method. In this case, the first contact 21D, the second contact 21E, and the buried electrode portion 22c are formed.

[0088] The method for manufacturing the semiconductor device 10 includes the steps of forming the buffer layer 32, the collector layer 31, and the collector electrode 27. Specifically, the buffer layer 32 and the collector layer 31 are formed in this order by selectively ion-implanting and diffusing n-type and p-type dopants into the rear surface 30r of the semiconductor substrate 30. Then, the collector electrode 27 is formed on the surface of the collector layer 31 opposite to the buffer layer 32. Through these steps, the semiconductor device 10 is manufactured.

[0089] (Operation of the first embodiment) The operation of the semiconductor device 10 of this embodiment will be described. Fig. 7 is a plan view of the semiconductor device 10X of the comparative example, Fig. 8 is a cross-sectional view of the semiconductor device 10X of the comparative example taken along line 8-8 in Fig. 7, and Fig. 9 is a cross-sectional view of the semiconductor device 10X of the comparative example taken along line 9-9 in Fig. 7.

[0090] As shown in FIGS. 7 to 9, the emitter electrode 21X of the semiconductor device 10X of the comparative example has an emitter routing portion 21Y. The emitter routing portion 21Y is a ring-shaped wiring that extends from one of both ends of the emitter electrode 21X in the y direction that is closer to the device side surface 10d, so as to surround the emitter electrode 21X. The emitter routing portion 21Y is integrated with the emitter electrode 21X. The emitter routing portion 21Y is arranged outward of the gate electrode 22 and the gate fingers 23X. In other words, both the gate electrode 22 and the gate fingers 23X are arranged between the emitter electrode 21X and the emitter routing portion 21Y.

[0091] 9, the gate finger 23X has an internal wiring 23XA embedded in the intermediate insulating film 39, an external wiring 23XB formed on the intermediate insulating film 39, and a connecting wiring 23XC connecting the internal wiring 23XA and the external wiring 23XB. Therefore, in a plan view, the external wiring 23XB cannot be positioned so as to overlap with the emitter electrode 21X, and is therefore positioned outward of the emitter electrode 21X. The external wiring 23XB of the gate finger 23X is integrated with the gate electrode 22. Meanwhile, as shown in FIG. 8, the internal wiring 23XA and the connecting wiring 23XC are provided in the intermediate insulating film 39, and therefore extend into the intermediate insulating film 39 at a position so as to overlap with the gate electrode 22.

[0092] 9, the external wiring 23XB of the gate finger 23X is disposed between the emitter routing portion 21Y and the emitter electrode 21X, so the emitter electrode 21X requires space for arranging the external wiring 23XB. In other words, the emitter electrode 21X is formed so as to avoid the external wiring 23XB. Therefore, the emitter electrode 21X cannot be made larger by the amount of the external wiring 23XB of the gate finger 23X.

[0093] 5 and 6, in this embodiment, a first contact 21D provided on the peripheral electrode portion 21B of the emitter electrode 21 contacts the peripheral portion 34C of the well region 34A. That is, the first contact 21D corresponds to the emitter routing portion 21Y. The gate fingers 23 are buried in the intermediate insulating film 39 and the insulating film 38, and the connection portion 21G is formed so as to cover the gate fingers 23. That is, the emitter electrode 21 is formed at a position overlapping the gate fingers 23 in a plan view. This eliminates the need to form the emitter electrode 21 while avoiding the gate fingers 23, and the size of the emitter electrode 21 can be made larger than the emitter electrode 21X.

[0094] (Effects of the first embodiment) According to the semiconductor device 10 of this embodiment, the following effects can be obtained. (1-1) The semiconductor device 10 includes a cell region 11, a gate electrode 22 disposed in a region different from the cell region 11, a peripheral region 12 surrounding the cell region 11 and the region in which the gate electrode 22 is disposed, a peripheral electrode portion 21B formed in the peripheral region 12 at a distance from the cell electrode portion 21A, and an emitter electrode 21 having a connection portion 21G connecting the cell electrode portion 21A and the peripheral electrode portion 21B. The peripheral region 12 includes a well region 34A disposed to surround the cell region 11, an insulating film 38 and an intermediate insulating film 39 covering the well region 34A, and gate fingers 23 embedded in the insulating film made of the insulating film 38 and the intermediate insulating film 39, connected to the gate electrode 22, and surrounding the cell region 11. The peripheral electrode portion 21B of the emitter electrode 21 is electrically connected to the well region 34A through a first opening 41 formed in the intermediate insulating film 39 and the insulating film 38 on the opposite side of the gate finger 23 from the cell electrode portion 21A.

[0095] According to this configuration, the connecting portion 21G is formed so as to cover the gate finger 23, which makes it possible to increase the size of the emitter electrode 21. That is, the area of ​​the emitter electrode 21 can be increased in a plan view. Therefore, the heat dissipation performance from the emitter electrode 21 can be improved.

[0096] (1-2) The well region 34A is formed in a ring shape having a certain width, and has an outer peripheral portion 34C that is a portion that is farther from the cell electrode portion 21A than the center of the well region 34A in the width direction. The outer peripheral electrode portion 21B has a first contact 21D that contacts the well region 34A. In a plan view, the first contact 21D contacts the outer peripheral portion 34C of the well region 34A.

[0097] With this configuration, the current flowing from the collector electrode 27 to the emitter electrode 21 flows to the cell electrode portion 21A via the outer peripheral portion 34C of the well region 34A and the first contact 21D. As a result, the amount of current flowing from the collector electrode 27 to the emitter electrode 21 to the cell electrode portion 21A via the outer peripheral portion 34C and inner peripheral portion 34B of the well region 34A is reduced. In other words, the path through the well region 34A for the current flowing from the collector electrode 27 to the emitter electrode 21 is shortened. This reduces heat generation caused by the current flowing through the well region 34A.

[0098] (1-3) The first contact 21D has a portion that is disposed on the opposite side of the gate electrode 22 from the cell electrode portion 21A. According to this configuration, the peripheral electrode portion 21B has a portion disposed on the opposite side of the gate electrode 22 from the cell electrode portion 21A, so that the area of ​​the emitter electrode 21 can be made larger in a plan view.

[0099] (1-4) In plan view, second openings 42 are formed in the insulating film 38 and the intermediate insulating film 39 at positions closer to the cell electrode portion 21A than the gate finger 23. The peripheral electrode portion 21B has a second contact 21E that contacts the well region 34A through the second openings 42.

[0100] According to this configuration, the first contact 21D and the second contact 21E increase the path of the current flowing from the collector electrode 27 to the emitter electrode 21, so that the amount of current flowing from the collector electrode 27 to the emitter electrode 21 can be increased.

[0101] (1-5) The gate finger 23 is formed by metal wiring. This configuration reduces the resistance of the gate fingers 23 compared to when the gate fingers 23 are made of polysilicon, for example. Therefore, current can be supplied to the cell 11A via the gate fingers 23 more quickly.

[0102] (1-6) The gate finger 23 is disposed so as to be spaced apart from both the rear surface 38r of the insulating film 38 and the surface 39s of the intermediate insulating film 39. This configuration can prevent the gate finger 23 from being electrically connected to either the semiconductor substrate 30 or the emitter electrode 21.

[0103] (1-7) The gate finger 23 is formed on the surface 38 s of the insulating film 38 and is covered with the intermediate insulating film 39 . According to this configuration, the gate fingers 23 are embedded in the insulating film consisting of the insulating film 38 and the intermediate insulating film 39, so there is no need to form openings in the intermediate insulating film 39. This simplifies the process of embedding the gate fingers 23 in the insulating film consisting of the insulating film 38 and the intermediate insulating film 39.

[0104] [Second embodiment] 10 to 13, a semiconductor device 10 of the second embodiment will be described. The semiconductor device 10 of the present embodiment differs from the semiconductor device 10 of the first embodiment in the configuration of the emitter electrode 21. In the following description, configurations that differ from the semiconductor device 10 of the first embodiment will be described in detail, and components that are common to the semiconductor device 10 of the first embodiment will be assigned the same reference numerals and descriptions thereof will be omitted.

[0105] 10, the emitter electrode 21 has a recess 21b instead of the opening 21a. The recess 21b is provided at one of the two ends of the emitter electrode 21 in the y direction that is closer to the side surface 10c of the device and at the center in the x direction. The recess 21b opens toward the side surface 10c of the device. The gate electrode 22 is disposed in the recess 21b. As described above, in this embodiment, no part of the emitter electrode 21 is disposed between the gate electrode 22 and the FLR portion 24 in the y direction.

[0106] 11 , the gate electrode 22 is disposed at a position overlapping with one of the y-direction end portions of the emitter electrode 21 that is closer to the device side surface 10c. More specifically, the one of the y-direction end portions of the gate electrode 22 that is closer to the device side surface 10c and the one of the y-direction end portions of the emitter electrode 21 that is closer to the device side surface 10c are disposed so as to be aligned with each other in the y direction but spaced apart from each other in the x direction. For this reason, it can also be said that the gate electrode 22 is disposed at a position overlapping with the outer peripheral end portion 21C of the outer peripheral electrode portion 21B of the emitter electrode 21.

[0107] 11 and 12, first contact 21D of peripheral electrode portion 21B is not formed in the portion where gate electrode 22 is disposed. Both end portions 21DE of first contact 21D in the direction in which first contact 21D extends are provided at positions adjacent to gate electrode 22 in the x direction. For this reason, first contact 21D can also be said to be an open ring formed along outer peripheral end portion 21C of peripheral electrode portion 21B, excluding the portion where gate electrode 22 is disposed.

[0108] Thus, the contact portion 21DA, which is a portion of the first contact 21D that is disposed closer to the device side surface 10c and extends in the x direction, is disposed closer to the cell electrode portion 21A in the y direction than the first contact 21D of the first embodiment. Therefore, as shown in FIG. 13, the distance between the first contact 21D and the second contact 21E is smaller than the distance between the first contact 21D and the second contact 21E of the first embodiment. Accordingly, as shown in FIGS. 12 and 13, the widths of both the first well region 34AA and the second well region 34AB of the well region 34A are smaller.

[0109] (Operation of the second embodiment) In the semiconductor device 10 of the comparative example shown in FIGS. 7 to 9, the emitter routing portion 21Y is disposed between the gate electrode 22 and the FLR portion 24, making it difficult to reduce the chip size of the semiconductor device 10X of the comparative example.

[0110] 8 and 9, because the emitter routing portion 21Y is in contact with the well region 34A, the width of the well region 34A increases by the amount of the emitter routing portion 21Y. As a result, when a current flows from the collector electrode 27 to the second contact 21E of the emitter electrode 21X via the well region 34A, the length of the path along which the current flows through the well region 34A increases. Because the well region 34A has a higher resistance than the emitter electrode 21X, heat is easily generated by the current flowing through the well region 34A.

[0111] 11 , of both ends of the emitter electrode 21 in the y direction, the end closer to the device side surface 10c and the end closer to the device side surface 10c of both ends of the gate electrode 22 in the y direction are aligned with each other. In other words, no part of the emitter electrode 21 is formed between the gate electrode 22 and the FLR portion 24 in the y direction. Therefore, the chip size of the semiconductor device 10 can be made smaller than that of the semiconductor device 10X of the comparative example.

[0112] 12 and 13, in this embodiment, as the distance between the first contact 21D and the second contact 21E in the y direction decreases, the width of the well region 34A decreases. Therefore, when a current flows from the collector electrode 27 (see FIG. 2) to the second contact 21E of the emitter electrode 21 via the well region 34A, the length of the path along which the current flows through the well region 34A becomes shorter. This reduces the amount of heat generated by the current flowing through the well region 34A.

[0113] (Effects of the second embodiment) According to the semiconductor device 10 of this embodiment, in addition to the effects (1-1), (1-2), and (1-4) to (1-7) of the first embodiment, the following effects can be obtained.

[0114] (2-1) The gate electrode 22 is disposed at a position overlapping with the outer peripheral end 21C of the outer peripheral electrode portion 21B of the emitter electrode 21. The first contact 21D is an open ring-shaped portion formed along the outer peripheral end 21C of the outer peripheral electrode portion 21B, except for the portion where the gate electrode 22 is disposed.

[0115] According to this configuration, the peripheral electrode portion 21B is not located outward from the gate electrode 22, that is, the first contact 21D is not disposed outward from the gate electrode 22, so the area of ​​the peripheral region 12 can be reduced in plan view, thereby enabling the semiconductor device 10 to be miniaturized.

[0116] [Example of change] The above-described embodiments are merely examples of possible forms of the semiconductor device according to the present disclosure, and are not intended to limit the forms. The semiconductor device according to the present disclosure may take forms different from those exemplified in the above-described embodiments. Examples include forms in which part of the configuration of the above-described embodiments is replaced, modified, or omitted, or forms in which new configurations are added to the above-described embodiments. Furthermore, the following modified examples can be combined with each other as long as there is no technical contradiction. In the following modified examples, parts common to the above-described embodiments are assigned the same reference numerals as the above-described embodiments, and their description will be omitted.

[0117] In the first embodiment, the shapes of the first contact 21D and the second contact 21E can be changed as desired. For example, the first contact 21D may be formed in an open ring shape with a portion cut out. The second contact 21E may be formed in an open ring shape with a portion cut out.

[0118] In each embodiment, the shape of the outer peripheral electrode portion 21B of the emitter electrode 21 can be changed as desired. In one example, the outer peripheral electrode portion 21B may be formed in an open ring shape with a portion cut out around the cell electrode portion 21A.

[0119] In each embodiment, the shape of the connection portion 21G of the emitter electrode 21 can be changed as desired. In one example, the connection portion 21G may be formed in an open ring shape with a portion cut out around the cell electrode portion 21A.

[0120] In each embodiment, the position of the gate finger 23C relative to the gate electrode 22 can be changed as desired in a plan view. In one example, the gate finger 23C may be located at the center of the gate electrode 22 in the y direction in a plan view.

[0121] In each embodiment, the shape of the gate finger 23C in a plan view can be changed as desired. For example, as shown in Fig. 14, the gate finger 23C may be formed to avoid a region RB of the gate electrode 22 to which a conductive member such as a wire is bonded.

[0122] In each embodiment, another insulating film may be formed on the surface 39s of the intermediate insulating film 39. In this case, the surface of the other insulating film corresponds to the "surface of the insulating film." An example of the other insulating film is a barrier layer formed of a material containing silicon nitride. The barrier layer prevents external ions from penetrating the intermediate insulating film 39 and the insulating film 38, and prevents the intermediate insulating film 39 and the insulating film 38 from being charged by external ions. In this case, the emitter electrode 21, the gate electrode 22, and the multiple field plates 24b of the FLR section 24 are formed on the surface of the barrier layer.

[0123] In each embodiment, the first contact 21D may be provided separately from the peripheral electrode portion 21B. The second contact 21E may be provided separately from the connection portion 21G. In this case, the first contact 21D and the second contact 21E may be formed of a material containing, for example, tungsten (W).

[0124] In each embodiment, the number of first contacts 21D and second contacts 21E can be changed as desired. In one example, a plurality of first contacts 21D may be provided. In this case, the first contacts 21D may be arranged spaced apart from each other in the width direction of the peripheral electrode portion 21B.

[0125] In each embodiment, the second contact 21E may be omitted from the connection portion 21G. In each embodiment, the position of the gate electrode 22 relative to the emitter electrode 21 can be changed arbitrarily. In one example, the gate electrode 22 may be disposed at one of the four corners of the emitter electrode 21.

[0126] In each embodiment, the number of gate fingers 23 can be changed as desired. The number of gate fingers 23 may be one, two, or four or more. In each embodiment, the configuration in which the gate fingers 23 are embedded in the insulating film 38 and the intermediate insulating film 39 can be changed as desired. In one example, the gate fingers 23 may be embedded in the intermediate insulating film 39. That is, the gate fingers 23 may be disposed apart from the surface 38s of the insulating film 38.

[0127] In each embodiment, the shape of the gate finger 23 in plan view can be changed as desired. In one example, the gate finger 23 may be formed in a ring shape surrounding the cell region 11 in plan view.

[0128] In each embodiment, at least one of the FLR portion 24 and the equipotential ring 25 may be omitted. In each embodiment, the emitter trenches 21TE and the gate trenches 22A are arranged alternately, but this is not limitative, and the arrangement of the emitter trenches 21TE and the gate trenches 22A can be changed as desired.

[0129] In each embodiment, the semiconductor device 10 may be a planar gate IGBT instead of a trench gate IGBT. In each embodiment, the semiconductor device 10 is embodied as an IGBT, but is not limited to this. The semiconductor device 10 may be a trench-type SiCMOSFET (metal-oxide-semiconductor field-effect transistor) or a SiMOSFET. In this case, the source electrode of the MOSFET corresponds to the "drive electrode."

[0130] The term "on" used in this disclosure includes the meanings of "on" and "above," unless the context clearly indicates otherwise. Therefore, the expression "A is formed on B" is intended to mean that, in this embodiment, A may be in contact with B and disposed directly on B, but as a variant, A may be disposed above B without contacting B. In other words, the term "on" does not exclude a structure in which another member is formed between A and B.

[0131] The z-direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure are not limited to the "up" and "down" of the z-direction described herein being "up" and "down" of the vertical direction. For example, the x-direction may be the vertical direction, or the y-direction may be the vertical direction.

[0132] [Note] The technical ideas that can be understood from the above-described embodiments and modified examples are described below. Note that the reference numerals of the components of the embodiments corresponding to the components described in each appendix are shown in parentheses. The reference numerals are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.

[0133] (Appendix 1) a cell region (11) in which a cell (11A) is provided; an outer peripheral region (12) surrounding the cell region (11); a gate electrode (22) disposed in the peripheral region (12); a driving electrode (21) having an electrode portion (21A) provided in the cell region (11), a peripheral electrode portion (21B) formed in the peripheral region (12) at a distance from the electrode portion (21A), and a connection portion (21G) connecting the electrode portion (21A) and the peripheral electrode portion (21B), The outer peripheral region (12) has a well region (34A) which is a semiconductor region provided so as to surround the cell region (11); insulating films (38, 39) provided to cover the well region (34A) and surround the cell region (11) in a plan view; a gate finger (23) embedded in the insulating film (38, 39), connected to the gate electrode (22), and formed so as to surround the cell region (11); the connection portion (21G) is formed on the insulating film (38, 39) so as to straddle the gate finger (23), The peripheral electrode portion (21B) is electrically connected to the well region (34A). A semiconductor device (10).

[0134] (Appendix 2) the well region (34A) is formed in a ring shape having a certain width, and has an outer peripheral portion (34C) that is a portion that is farther from the electrode portion (21A) than the center of the well region (34A) in the width direction, When viewed in the thickness direction (z direction) of the insulating films (38, 39), the contact (21D) is in contact with the outer periphery (34C) of the well region (34A). 2. The semiconductor device according to claim 1.

[0135] (Appendix 3) The contact (21D) has a portion disposed on the opposite side of the gate electrode (22) from the electrode portion (21A). 3. The semiconductor device according to claim 1 or 2.

[0136] (Appendix 4) The contact (21D) is formed in a ring shape at the outer peripheral end (21C) of the outer peripheral electrode portion (21B) when viewed in the thickness direction (z direction) of the insulating films (38, 39). 4. The semiconductor device according to claim 3.

[0137] (Appendix 5) the gate electrode (22) is disposed at a position overlapping with an outer peripheral end portion (21C) of the outer peripheral electrode portion (21B); The contact (21D) is an open ring-shaped contact formed along the outer peripheral end (21C) of the outer peripheral electrode portion (21B) except for the portion where the gate electrode (22) is disposed. 3. The semiconductor device according to claim 1 or 2.

[0138] (Appendix 6) The opening is a first opening (41), a second opening (42) is formed in the insulating film (38, 39) at a position closer to the electrode portion (21A) than the gate finger (23) when viewed in a thickness direction (z direction) of the insulating film (38, 39); the contact is a first contact (21D), The connection portion (21G) has a second contact (21E) that contacts the well region (34A) through the second opening (42). 6. The semiconductor device according to any one of claims 1 to 5.

[0139] (Appendix 7) The gate finger (23) is formed by metal wiring. 7. The semiconductor device according to any one of claims 1 to 6.

[0140] (Appendix 8) The gate finger (23) is made of a material containing tungsten. 8. The semiconductor device according to claim 7.

[0141] (Appendix 9) The gate fingers (23) are provided in plurality in the insulating films (38, 39), and are spaced apart from one another in a direction perpendicular to the thickness direction (z direction) of the insulating films (38, 39). 9. The semiconductor device according to any one of appendices 1 to 8.

[0142] (Appendix 10) the insulating films (38, 39) have a front surface (39s) and a back surface (38r) facing opposite to each other in a thickness direction (z direction) of the insulating films (38, 39), The gate finger (23) is disposed apart from both the front surface (39s) and the back surface (38r) in the thickness direction (z direction) of the insulating films (38, 39). 10. The semiconductor device according to any one of appendices 1 to 9.

[0143] (Appendix 11) The insulating films (38, 39) are a first insulating film (38) covering the well region (34A) and including the back surface (38r); a second insulating film (39) laminated on the first insulating film (38) and including the surface (39s); and The gate finger (23) is formed on the first insulating film (38) and is covered with the second insulating film (39). 11. The semiconductor device according to claim 10.

[0144] (Appendix 12) When viewed in the thickness direction (z direction) of the insulating films (38, 39), the gate finger (23) is provided at a position overlapping the peripheral electrode portion (21B). 12. The semiconductor device according to claim 10 or 11.

[0145] (Appendix 13) The semiconductor device (10) is an IGBT, The driving electrode (21) is an emitter electrode. 13. The semiconductor device according to any one of claims 1 to 12.

[0146] (Appendix 14) The semiconductor device (10) is a trench gate type MOSFET, The driving electrode (21) is a source electrode. 13. The semiconductor device according to any one of claims 1 to 12. [Explanation of symbols]

[0147] 10...Semiconductor device 11...Cell area 11A…cell 12...Outer area 21...Emitter electrode (drive electrode) 21A...Cell electrode part (electrode part) 21B…Outer electrode part 21C...Outer edge 21D...First contact (contact) 21E…Second Contact 21G…Connection 22...Gate electrode 23...Gate Finger 34A...Well area 34C…Outer periphery 38...insulating film (first insulating film) 38r...Back surface (back surface of insulating film) 39...Intermediate insulating film (second insulating film) 39s...Surface (surface of insulating film) 41...First opening 42...Second opening

Claims

1. a cell region in which cells are provided; a peripheral region surrounding the cell region; a gate electrode disposed in the peripheral region; a driving electrode including an electrode portion provided in the cell region, a peripheral electrode portion formed in the peripheral region at a distance from the electrode portion, and a connection portion connecting the electrode portion and the peripheral electrode portion; Equipped with The outer peripheral region includes: a well region which is a semiconductor region provided so as to surround the cell region; an insulating film provided to cover the well region and surround the cell region in a plan view; a gate finger embedded in the insulating film, connected to the gate electrode, and formed so as to surround the cell region; is established, the connection portion is formed on the insulating film so as to straddle the gate finger, The peripheral electrode portion is electrically connected to the well region. Semiconductor device.

2. the well region is formed in a ring shape having a certain width, and has an outer periphery that is a portion that is farther from the electrode portion than the center of the well region in the width direction, the peripheral electrode portion has a contact in contact with the well region, When viewed in the thickness direction of the insulating film, the contact is in contact with the outer periphery of the well region. The semiconductor device according to claim 1 .

3. The contact has a portion disposed on the opposite side of the electrode portion with respect to the gate electrode. The semiconductor device according to claim 2 .

4. The contact is formed in a ring shape at the outer peripheral end of the outer electrode portion when viewed in the thickness direction of the insulating film. The semiconductor device according to claim 3 .

5. the gate electrode is disposed at a position overlapping an outer peripheral end of the outer electrode portion, The contact is an open ring formed along the outer peripheral edge of the outer electrode portion except for the portion where the gate electrode is disposed. The semiconductor device according to claim 2 .

6. the contact is a first contact, The connection portion has a second contact that contacts the well region at a position closer to the electrode portion than the gate finger. The semiconductor device according to any one of claims 2 to 5.

7. The gate finger is formed by a metal wiring. The semiconductor device according to any one of claims 1 to 6.

8. The gate finger is formed of a material including tungsten. The semiconductor device according to claim 7 .

9. The gate fingers are provided in plurality in the insulating film and are spaced apart from one another in a direction perpendicular to the thickness direction of the insulating film. The semiconductor device according to any one of claims 1 to 8.

10. the insulating film has a front surface and a back surface facing opposite to each other in a thickness direction of the insulating film, The gate finger is disposed apart from both the front surface and the back surface in the thickness direction of the insulating film. The semiconductor device according to any one of claims 1 to 9.

11. The insulating film is a first insulating film covering the well region and including the rear surface; a second insulating film stacked on the first insulating film and including the surface; and The gate finger is formed on the first insulating film and is covered with the second insulating film. The semiconductor device according to claim 10.

12. When viewed in the thickness direction of the insulating film, the gate finger is provided at a position overlapping the peripheral electrode portion. The semiconductor device according to claim 10 or 11.

13. the semiconductor device is an IGBT, The drive electrode is an emitter electrode. The semiconductor device according to any one of claims 1 to 12.

14. the semiconductor device is a trench gate MOSFET, The drive electrode is a source electrode. The semiconductor device according to any one of claims 1 to 12.

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