Solid-state imaging device and imaging device

Abstract

A solid-state imaging device (100) comprises a plurality of pixel circuits (1) arranged in a matrix, and a remedial unit composed of N (N is an integer of 3 or more) signal lines, wherein each of n (n is an integer of N or less) pixel circuits (1) is connected to a set of at least two signal lines of the N signal lines and outputs a pixel signal selectively to one of the signal lines included in the set, and n sets corresponding to the n pixel circuits (1) have mutually different combinations of signal lines.

Description

[Technical Field]

[0001] The present disclosure relates to a solid-state imaging device and an imaging apparatus. [Background technology]

[0002] As image sensors become increasingly pixel-rich and faster, the number of wiring lines in the pixel array is also increasing. As wiring density increases, the probability of open and short-circuit defects in the wiring lines increases. In the case of a unit pixel cell failure, the impact is a scratch failure of only one pixel. If the number of scratches on a chip is small, the image quality degradation caused by correction processing is minimal, so correction can be performed and the product can often be shipped as a good product. On the other hand, in the case of line defects, the area requiring correction is adjacent and wide, so the image quality degradation caused by correction is significant. Therefore, even if even a single line occurs on a chip, the solid-state image sensor itself is often treated as defective. Line defects pose a problem, as they can lead to an increase in the defect rate of image sensor chips.

[0003] Therefore, a technology has been devised to reduce the defect rate by using a redundant circuit to repair a failure when one occurs. Patent Document 1 discloses a technology that has two output circuits and two signal lines for one pixel and uses the output path that is not faulty.

[0004] Patent Document 2 discloses a technique for avoiding wiring defects by providing one redundant signal line for every n signal lines and connecting each of the n signal lines to the one redundant signal line with a switch. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-184075 [Patent Document 2] Japanese Patent Publication No. 2020-123795 Summary of the Invention [Problem to be solved by the invention]

[0006] However, according to the prior art document 1, each pixel circuit has a redundant repair circuit and a redundant signal line, which means that twice as many output circuits and signal lines are required, and a larger area must be reserved for the redundant repair. In addition, the large number of redundant repair lines further increases the wiring density, which in turn increases the probability of a failure occurring.

[0007] On the other hand, according to the prior art in Patent Document 2, one redundant repair signal line is sufficient for n signal lines, enabling redundant repair in a small area. However, the technique involves connecting all switches connected to the remaining n signal lines to a specific redundant repair line. In the event of a failure, the technique avoids open defects by connecting the failed signal line to the redundant signal line via a switch. Therefore, the wiring load of the failed signal line remains connected, and the wiring load of the redundant repair signal line is added. In other words, the wiring load of the redundantly repaired signal line is significantly greater than that of a signal line not subjected to redundant repair. As a result, the pixel signal readout time is slower than that of a signal line not subjected to redundant repair, leading to a decrease in frame rate. Furthermore, because the failed signal line is repaired while remaining connected, it is not possible to repair short-circuit defects in the signal line.

[0008] Therefore, the present disclosure provides a solid-state imaging device and an imaging device that can repair both open defects and short defects with little redundancy while preventing a decrease in readout speed. [Means for solving the problem]

[0009] In order to solve the above problem, the solid-state imaging device of the present disclosure comprises a plurality of pixel circuits arranged in a matrix and a relief unit, the relief unit having N (N is an integer equal to or greater than 3) signal lines and n (n is an integer equal to or less than N) pixel circuits among the plurality of pixel circuits, each of the n pixel circuits being connected to a set of at least two signal lines among the N signal lines and selectively outputting a pixel signal to one of the signal lines included in the set, and the n sets corresponding to the n pixel circuits having different combinations of signal lines. [Effects of the Invention]

[0010] According to the solid-state imaging device and imaging device of the present disclosure, it is possible to repair both open defects and short defects with little redundancy while preventing a decrease in readout speed. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a diagram illustrating an example of the configuration of a solid-state imaging device according to the first embodiment. [Figure 2] FIG. 2 is a diagram showing an example of the configuration of a pixel array unit and column circuits in the solid-state imaging device according to the first embodiment. [Figure 3] FIG. 3 is a diagram showing an example of a pixel circuit and an example of signal line connections according to the first embodiment. [Figure 4] FIG. 4 is an explanatory diagram illustrating an example of a repair operation for a wiring defect in the solid-state imaging device according to the first embodiment. [Figure 5] FIG. 5 is a diagram illustrating an example of the configuration of a column circuit according to the first embodiment. [Figure 6] FIG. 6 is a diagram showing a main part of a pixel array unit having a first example of a load element according to the first embodiment. [Figure 7] FIG. 7 is a diagram showing a main part of a pixel array unit having a second example of a load element according to the first embodiment. [Figure 8] FIG. 8 is a diagram showing a main part of a pixel array unit having a third example of a load element according to the first embodiment. [Figure 9]FIG. 9 is an explanatory diagram illustrating an example of a repair operation for a wiring defect in the solid-state imaging device according to the first embodiment. [Figure 10A] FIG. 10A is a diagram showing an example of connections between n pixel circuits and n+α (α=1) signal lines in the solid-state imaging device according to the first embodiment. [Figure 10B] FIG. 10B is a diagram showing an example of connections between n pixel circuits and n+α (α=2) signal lines in the solid-state imaging device according to Embodiment 1. In FIG. [Figure 11] FIG. 11 is a diagram showing another example of connections between n pixel circuits and n+α (α=1) signal lines in the solid-state imaging device according to the first embodiment. [Figure 12] FIG. 12 is a diagram showing an example of connections between n pixel circuits and n+α (α=0) signal lines in the solid-state imaging device according to the first embodiment. [Figure 13] FIG. 13 is a diagram illustrating a configuration example of a pixel array unit and column circuits in a solid-state imaging device according to the second embodiment. [Figure 14] FIG. 14 is an explanatory diagram illustrating an example of a repair operation for a wiring defect in the solid-state imaging device according to the second embodiment. [Figure 15] FIG. 15 is a diagram showing a modification of the pixel array section and column circuits in the solid-state imaging device according to the second embodiment. [Figure 16] FIG. 16 is a diagram illustrating another example of the configuration of the solid-state imaging device according to the first and second embodiments. [Figure 17] FIG. 17 is a flowchart illustrating a process of writing recovery information into the solid-state imaging device according to the second embodiment. [Figure 18] FIG. 18 is a flowchart showing an imaging process for imaging using recovery information in the solid-state imaging device according to the second embodiment. [Figure 19] FIG. 19 is a diagram illustrating an example of the configuration of an imaging device according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, embodiments for carrying out the present technology will be described. Note that the following embodiments each show a specific example of the present disclosure, and the numerical values, shapes, materials, components, arrangement and connection of the components, steps, order of steps, etc. are merely examples and do not limit the present disclosure.

[0013] (Embodiment 1) First, the configuration of a solid-state imaging device 100 according to this embodiment will be described.

[0014] Fig. 1 is a diagram showing a configuration example of a solid-state imaging device 100 according to embodiment 1. Fig. 2 is a diagram showing a configuration example of a pixel array unit and column circuits in the solid-state imaging device according to embodiment 1.

[0015] The solid-state imaging device 100 in FIG. 1 includes a pixel array section 10, a vertical scanning circuit 2, a current source 3, a reference signal generating section 5, a column circuit 30, a timing control section 6, and a signal processing section 7.

[0016] The pixel array section 10 has a plurality of pixel circuits 1 arranged in a matrix. N (N is an integer equal to or greater than 3) signal lines VL are arranged for each pixel circuit column in the pixel array section 10. Of the N signal lines, n (n is an integer equal to or less than N) signal lines are non-redundant signal lines for parallel readout of n pixel signals from n pixel circuits. The remaining Nn signal lines are redundant signal lines for replacing defective signal lines. The number Nn of redundant signal lines is denoted as α in FIG. 2. Note that the signal lines for replacing defective signal lines can replace not only the α signal lines but also n other signal lines. α (=Nn) is an integer equal to or greater than 1 when parallel readout of the n pixel signals is performed, and is an integer equal to or greater than 0 when parallel readout is not performed. In the following, pixel circuit columns may be simply referred to as columns.

[0017] Each of the plurality of pixel circuits 1 is connected to a set of at least two signal lines out of the N signal lines, and is configured to selectively output a pixel signal to one of the signal lines included in the set.

[0018] The vertical scanning circuit 2 controls the exposure and readout operations of the pixel array section 10. To control the readout operation, the vertical scanning circuit 2 scans in units of n rows. Specifically, the vertical scanning circuit 2 scans in units of n rows so that n pixel circuits 1 arranged in the column direction simultaneously output n pixel signals in parallel to n signal lines VL. In other words, the vertical scanning circuit 2 performs control to simultaneously read out n rows of pixel signals in parallel.

[0019] Here, the following description focuses on n pixel circuits 1 arranged in the column direction among n rows of pixel circuits 1 in a scanning unit. As shown in FIG. 2, each of the n pixel circuits 1 arranged in the column direction is connected to a set of at least two signal lines VL out of N signal lines VL, and selectively outputs a pixel signal to one of the signal lines VL included in that set. As shown in FIG. 2, a circuit portion including a pixel circuit 1 belonging to one column and a column circuit 30 is called a repair unit 11. The solid-state imaging device 100 includes repair units 11 in the same number as the number of columns of pixel circuits 1. In a broad sense, the repair unit 11 refers to a circuit portion including at least (n+α) signal lines.

[0020] The current source 3 is provided for each of the n signal lines. Each current source 3 forms a source follower together with an amplifier transistor in a pixel circuit that outputs a pixel signal, and supplies a load current to the amplifier transistor.

[0021] The reference signal generator 5 outputs a ramp signal for AD conversion to the column circuit 30.

[0022] A column circuit 30 is provided for each column and internally includes n column AD circuits 4. The column circuit 30 is connected to N signal lines VL corresponding to the same column and converts n analog pixel signals output from n of the N signal lines VL into digital pixel signals. The column AD circuit 4 is a single-slope AD conversion circuit that compares a ramp signal from a reference signal generation unit 5 with the analog pixel signals and converts them into digital values.

[0023] The timing control section 6 generates various timing signals for operating the solid-state imaging device 100 as a whole.

[0024] The signal processing unit 7 acquires n digital pixel signals output from each column circuit 30, and performs signal processing such as offset correction and gain correction.

[0025] 3 is a diagram showing an example of a pixel circuit and an example of signal line connections according to embodiment 1. In the diagram, n pixel circuits 1 arranged in the column direction across n rows are shown. The n pixel circuits 1 are designated pixel circuit 1_1 to pixel circuit 1_n.

[0026] A pixel circuit 1_i (i is an integer from 1 to n) is connected to the i-th to (i+α)-th signal lines among N (i.e., n+α) signal lines in the arrangement order in the column direction, and outputs a pixel signal to one of the signal lines. Note that in FIG. 3, α is 1. In other words, n of the N signal lines are signal lines for parallel readout. α of the N signal lines are redundant signal lines for relieving faulty wiring. Each pixel circuit 1 in the figure is connected to two signal lines VL.

[0027] The pixel circuit 1 includes a light receiving section (pixel, photodiode, photoelectric conversion element) 110, an amplifying transistor 111 that outputs an amplified signal according to the amount of signal charge, a transfer transistor 112 that transfers the signal charge photoelectrically converted by the light receiving section 110, a reset transistor 113, a first selection transistor 116, a second selection transistor 117, and a floating diffusion section (FD section) 114.

[0028] The first selection transistor 116 and the second selection transistor 117 are connected to two of the N signal lines.

[0029] The first selection transistor 116 brings one of the two signal lines VL and the amplifier transistor 111 into conduction in response to a drive pulse signal SEL0.

[0030] The second selection transistor 117 brings the other of the two signal lines VL and the amplifier transistor 111 into conduction in response to a drive pulse signal SEL1.

[0031] The reset transistor 113 resets the FD section 114 to an initial voltage in response to a drive pulse signal RS. The transfer transistor 112 transfers the signal accumulated in the light receiving section 110 to the FD section 114 in response to a drive pulse signal TG. The pixel signal transferred to the FD section 114 is output as a voltage to a signal line VL via a selection transistor 115 by an amplification transistor 111, the drain of which is connected to a power supply, and a current source 3, and is input to a column AD circuit 4. The drive pulse signals SEL, TG, and RS shown in FIG. 3 are details of the signal line indicated by the horizontal control line HL in FIG. 1.

[0032] Here, the pixel circuit 1 has been described as having one light receiving section 110, but may have a plurality of light receiving sections 110.

[0033] Each signal line transmits a pixel signal, but it is necessary to wait for time to drive the load capacitance of the signal line. If the load capacitance varies, it is necessary to wait for time to drive the largest load capacitance, which results in a longer pixel signal readout time. It is preferable that the load capacitances of multiple signal lines VL1 to VLn+1 be equal. The load capacitance of the signal line is determined by the wiring parasitic capacitance between the signal line and the peripheral structure and the load capacitance of the pixel circuits connected to the signal line. If the number of pixel circuits in the vertical direction of the pixel array is a multiple of n, the number of pixel circuits connected to the signal lines VL1 to VLn will be the same. If the number of pixel circuits in the vertical direction of the pixel array is not a multiple of n, the remaining fractional pixel circuits are connected one by one to one of the signal lines VL1 to VLn+1. The number of pixel circuits connected to the signal lines VL1 to VLn+1 differs by up to one pixel circuit, but if the number of pixel circuits in the vertical direction of the pixel array is sufficiently greater than n, the load capacitances of the pixel circuits connected to the signal lines VL1 to VLn will be approximately equal. The readout speed is maximized by making the load capacitances of the multiple signal lines VL1 to VLn+1 approximately equal. Having n+α signal lines VL per pixel circuit column enables n pixel signals in the row direction to be simultaneously read out, resulting in a readout speed n times faster and a higher frame rate than a solid-state imaging device having one signal line VL per pixel circuit column. Furthermore, since the load capacitance of each signal line does not change significantly between when a defective wiring is repaired using redundant signal lines and when it is not repaired, it is possible to suppress a decrease in readout speed and a decrease in frame rate even when a defective wiring is repaired.

[0034] The circuit example of Fig. 3 will now be described in detail. In the circuit example of Fig. 3, n pixel circuits 1_1 to 1_n are arranged in the same pixel circuit column, constituting n rows of pixels. Each of the pixel circuits 1_1 to 1_n includes a plurality of selection transistors. The gates of the first selection transistor 116 and the second selection transistor 117 are connected to drive pulse signals SEL0 and SEL1, respectively. The first selection transistor 116 and the second selection transistor 117 are connected to the source side of an amplification transistor 111, the drain side of which is connected to a power supply.

[0035] The first selection transistor 116 of the pixel circuit 1_1 is connected to connect the amplifier transistor 111 to the signal line VL1. The second selection transistor 117 is connected to connect the amplifier transistor 111 to the signal line VL2. Next, the first selection transistor 116 of the pixel circuit 1_2 is connected to connect the amplifier transistor 111 to the signal line VL2. The second selection transistor 117 is connected to connect the amplifier transistor 111 to the signal line VL3. The first selection transistor 116 of the pixel circuit 1_n is connected to connect the amplifier transistor 111 to the signal line VLn. The second selection transistor 117 is connected to connect the amplifier transistor 111 to the signal line VLn+1. In this way, each pixel circuit is connected to two adjacent signal lines among the signal lines VL1 to VLn via the two selection transistors, and the next pixel circuit is connected to a signal line whose number is shifted by one from the previous pixel circuit. This is repeated every n rows of pixel circuits, and they are connected to the signal lines VL1 to VLn+1.

[0036] If the number of pixel circuits in the vertical direction of the pixel array is a multiple of n, the number of pixel circuits connected to the signal lines VL2 to VLn will be the same. The number of pixel circuits connected to the signal lines VL1 and VLn+1 will be half of the signal lines VL2 to VLn. If the number of pixel circuits in the vertical direction of the pixel array is not a multiple of n, the remaining fractional pixel circuits are connected one by one to one of the signal lines VL1 to VLn. The number of pixel circuits connected to the signal lines VL2 to VLn+1 differs by up to one pixel circuit, but if the number of pixel circuits in the vertical direction of the pixel array is sufficiently greater than n, the load capacitances of the pixel circuits connected to the signal lines VL2 to VLn will be approximately equal. The load capacitances of the pixel circuits connected to the signal lines VL1 and VLn+1 will be smaller than the difference in the number of pixel circuits compared to the signal lines VL2 to VLn, but they are still approximately twice as large, so the signal line load will not change significantly. Since the load capacitance of the pixel circuits of the signal lines VL2 to VLn is larger, it is sufficient to ensure the pixel readout time of the signal lines VL2 to VLn.

[0037] Here, the method of switching signal lines by disposing two selection transistors in each pixel circuit 1 has been described, but it is also possible to realize this with a plurality of selection transistors, three or more.

[0038] FIG. 4 is an explanatory diagram showing an example of a repair operation for a wiring defect in the solid-state imaging device according to the first embodiment. The figure shows a repair method when a failure occurs in a pixel signal line VL. FIG. 4 illustrates a pixel circuit of n rows and 2 columns in the pixel array section 10. Take the example of a case where a failure occurs at a fault location 8 in signal line VL2_2. In this example, the failed signal line is the second signal line out of n+1 signal lines.

[0039] Each pixel circuit has two selection transistors, each connected to two adjacently numbered signal lines. When it is the row's turn to read out pixel signals, if the smaller-numbered signal line of the two signal lines connected to each pixel circuit is smaller than the faulty signal line, the smaller-numbered signal line is selected and connected. If the smaller-numbered signal line connected to each pixel circuit is the same number as or larger than the faulty signal line, the larger-numbered signal line of the two signal lines is selected and connected. Signal line selection is performed using a control pulse SEL, a control signal for the vertical scanning circuit 2. In the example of Figure 4, the smaller-numbered signal line for pixel circuit 1_1 is signal line VL1, so SEL0_1 becomes Hi and SEL1_1 becomes Lo to select and connect the smaller-numbered signal line. For pixel circuits 1_2 to 1_n, the signal lines with smaller numbers are signal lines VL2 to VLn, which are equal to or greater than the faulty line VL2. Therefore, the signal lines with larger numbers are selected and connected, so SEL0_2 to SEL1_2 to SEL1_n become Low and SEL1_2 to SEL1_n become Hi. At this time, the pixel circuits in row n are connected to signal lines VL1 and VL3 to VLn+1, and the faulty signal line VL2 is not connected to any pixel circuit. Therefore, pixel signals can be transmitted using signal lines that are not faulty, so no line defect occurs even if there is a wiring fault. Furthermore, because the faulty signal line VL2 is isolated by the selection transistor, the load capacitance of the signal line does not increase, and the frame rate does not decrease due to the redundancy repair operation. This also enables the system to handle short-circuit failure modes.

[0040] The signal line is selected using a control pulse SEL of the control signal of the vertical scanning circuit 2, and therefore pixel circuit columns other than the faulty location 8 that are connected to the same control line will also select the same signal line as the pixel circuit column where the faulty location 8 exists. Therefore, in the example of Figure 4, pixel circuit columns that do not have the faulty location 8 will also be connected to signal lines VL1 and VL3 to VLn+1.

[0041] FIG. 5 is a diagram showing an example of the configuration of a column circuit according to the first embodiment. As explained in FIGS. 3 and 4, n pixel circuits are connected simultaneously using n of the n+1 signal lines. In order to propagate pixel signals as explained in FIG. 3, a current source 3 needs to be connected to the pixel circuit 1. A method is required to connect n current sources to the n signal lines to be used from the n+1 signal lines.

[0042] The column circuit 30 in FIG. 5 is composed of signal lines VL1 to VLn for one pixel circuit column, n current sources 3, n column AD circuits 4, and 2n-2 switches 120 that connect the signal lines to the current sources and column AD circuits. Each current source 3 and column AD circuit is connected individually, so these two are collectively referred to as the column circuit 30. To connect the n signal lines and n column circuits, the first column circuit is connected to signal lines VL1 and VL2 via SW120. The second column circuit is connected to signal lines VL2 and VL3 via SW120. This process is repeated until the nth column circuit is connected to signal lines VLn and VLn+1 via SW120.

[0043] The column circuits 30 with numbers smaller than the faulty signal line are connected to the signal line with the smaller number using SW120, and the signal line with the larger number is disconnected using SW120. The column circuits 30 with numbers the same as or larger than the faulty signal line are connected to the signal line with the larger number using SW120, and the signal line with the smaller number is disconnected using SW120.

[0044] 4, if a failure occurs in the second signal line, the first column circuit is connected to VL1, and the second and subsequent column circuits are connected to the signal lines with larger numbers, so the second to nth column circuits are connected to VL3 to VLn+1. This operation disconnects the faulty signal line VL2, and the non-faulty signal lines VL1 and VL3 to VLn+1 are used.

[0045] 4 and 5 are merely examples, and similar effects can be achieved by a method that prioritizes the selection of larger numbers, etc. In this way, by adding one redundant signal line to n signal lines, it is possible to have the function of disconnecting a signal line in which a failure has occurred and connecting it to a signal line that is not faulty. Furthermore, with the configuration of embodiment 1, it is possible to minimize the number of signal lines connected to one pixel circuit, and the number of pixel circuits connected to each signal line is at most twice as many, so there is no significant imbalance, and therefore the load capacitance does not change significantly between each signal line, and the difference in pixel readout time is minor.

[0046] In the examples of the present disclosure, the explanation has been given based on the case where one pixel circuit column is configured with a repair unit including n+α (n>α≧1) signal lines, which are n signal lines VL plus a redundant signal line. However, the present disclosure can also be applied to cases where the repair unit is configured in units of multiple pixel columns or where one pixel column has multiple repair units.

[0047] (Example 1: Matching the load on signal lines) FIG. 6 is a diagram showing a main part of a pixel array unit having a first example of a load element according to the first embodiment. This diagram shows an example in which the loads of redundant signal lines are made uniform by using load elements. In the redundant repair circuit of FIG. 3, the number of pixel circuits 1 connected to signal lines VL1 and VLn+1 is small. Therefore, the load capacitance of the signal lines is smaller than that of the other signal lines VL2 to VLn. Therefore, one dummy selection transistor 118 is connected to each of signal lines VL1 and VLn+1, which have fewer pixel circuits, in each of the n rows. This makes the loads of all signal lines uniform, resulting in equal pixel readout times. The redundant repair method can be implemented in the same way as described with reference to FIG. 4.

[0048] (Example 2: Matching the load on signal lines) FIG. 7 is a diagram showing a main part of a pixel array unit having a second example of a load element according to the first embodiment. This diagram shows an example in which redundant signal line loads are made uniform using load elements. In the redundant repair circuit of FIG. 3, the number of pixel circuits 1 connected to signal lines VL1 and VLn+1 is small. Therefore, the load capacitance of the signal lines is smaller than that of the other signal lines VL2 to VLn. Therefore, by adding capacitance 119 so that the wiring parasitic capacitance of signal lines VL1 and VLn+1, which have fewer pixel circuits, is larger than that of the other signal lines VL2 to VLn, the loads of all signal lines are made equal, and the pixel readout times are made equal. The redundant repair method can be implemented in the same way as described with reference to FIG. 4.

[0049] (Example 3: Matching the load on signal lines) FIG. 8 is a diagram showing a main part of a pixel array unit having a third example of a load element according to the first embodiment. This diagram shows an example of aligning redundant signal line loads using load elements. In the redundant repair circuit of FIG. 5, the number of SW120 connected to signal lines VL1 and VLn+1 is small. Therefore, the load capacitance of the signal lines is smaller than that of the other signal lines VL2 to VLn. Therefore, dummy SW121 is connected to signal lines VL1 and VLn+1, which have fewer pixel circuits. This equalizes the loads on all signal lines, resulting in equal pixel readout times. The redundant repair method can be implemented in the same way as described with reference to FIG. 5.

[0050] (Redundancy repair is performed for each pixel array area) In the first embodiment, signal line selection is performed using a control pulse SEL of a control signal from the vertical scanning circuit 2, and therefore the same signal line is selected for pixel circuit columns connected to the same control line. Therefore, there is only one fault wiring to be redundantly repaired, among the signal lines VL1 to VLn, in the solid-state imaging device 100. If signal line failures occur at multiple locations in the imaging device 100, they cannot be repaired.

[0051] 9 is an explanatory diagram showing an example of a repair operation for a wiring defect in the solid-state imaging device according to Embodiment 1. The diagram shows connections for redundancy repair for each divided region of the pixel array.

[0052] The horizontal control signal HL is divided for each region of the pixel array 10, and a vertical scanning circuit 2 is arranged for each divided horizontal control signal HL. The redundancy repair method is implemented in the same way as described in FIG. 4. The n+1 signal lines can be selected using the vertical scanning circuit 2 for each region. Therefore, a fault signal line can be set for each region, and different signal lines can be repaired for different regions, improving the repair rate for wiring faults.

[0053] 9 shows an example in which the pixel array section 10 is divided into two regions and provided with two vertical scanning circuits 2, but the number of divisions may be three or more. For example, if the solid-state imaging device 100 is configured with two or more stacked semiconductor chips, the pixel circuit 1 and the vertical scanning circuit 2 may be mounted on different semiconductor chips. In such a configuration, the pixel array section 10 may be divided into k regions by boundary lines along the column direction, and k vertical scanning circuits 2 may be mounted. k may be, for example, 2, 4, 8, etc.

[0054] (Variation) 10A is a diagram showing an example of connections between n pixel circuits and n+α (α=1) signal lines in the solid-state imaging device according to Embodiment 1. The diagram shows an example where n=4 and α=1.

[0055] In the figure, pixel circuit 1_i (i is an integer from 1 to n) is connected to signal lines i-th to (i+α)-th in the column direction out of N=5 (=n+α) signal lines, and outputs a pixel signal to one of the signal lines. In this respect, Figure 10A is similar to Figure 3, but differs in that the order of pixel circuits in the column direction is reversed. This example also achieves the same effect as Figure 3.

[0056] Next, an example in which there are two redundant signal lines (α=2) will be described.

[0057] FIG. 10B is a diagram showing an example of connections between n pixel circuits and n+α (α=2) signal lines in the solid-state imaging device according to Embodiment 1. In FIG.

[0058] In the figure, pixel circuit 1_i (i is an integer from 1 to n) is connected to signal lines i-th to (i+α)-th in the arrangement order of the columns out of N=5 (=n+α) signal lines, and outputs a pixel signal to one of the signal lines. This is also the case in FIG. 10B. In FIG. 10B, there are two redundant signal lines, so each pixel circuit 1 is connected to three signal lines.

[0059] Next, another example of connection will be described.

[0060] 11 is a diagram showing another example of connections between n pixel circuits and n+α (α=1) signal lines in the solid-state imaging device according to Embodiment 1. In FIG. 11, n=4.

[0061] Each of n pixel circuits 1 (n is an integer equal to or less than N) arranged in the column direction is connected to a set of at least two of the N signal lines, and selectively outputs a pixel signal to one of the signal lines included in the set. The n sets corresponding to the n pixel circuits 1 have different combinations of signal lines. Figure 11 does not have the simple regularity of Figures 3, 10A, and 10B. This configuration and example also achieve the same effects as Figure 3, etc.

[0062] Next, an example where α=0, that is, no redundant signal lines are provided, will be described.

[0063] 12 is a diagram showing an example of connections between n pixel circuits and n+α (α=0) signal lines in the solid-state imaging device according to Embodiment 1. In the example of FIG. 12, N=n=4.

[0064] 12 also satisfies the following requirements, as in FIG. 11. Each of n pixel circuits 1 (n is an integer equal to or less than N) arranged in the column direction is connected to a set of at least two of N signal lines and selectively outputs a pixel signal to one of the signal lines included in the set. The n sets corresponding to the n pixel circuits 1 have different combinations of signal lines. However, since there are no redundant wirings in FIG. 12, one of the signal lines must substitute for the defective wiring to read out the pixel signal, and the pixel signal of the corresponding pixel circuit must also be read out. In other words, the defective signal line can be repaired by performing two readout operations in a time-division manner. For example, if signal line VL1 becomes a defective wiring, the pixel signals of pixel circuits 1_2 to 1_4 are read out via signal lines VL2 to VL3 in the first readout operation, and the pixel signal of pixel circuit 1_1 is read out via signal line VL2 in the second readout operation. In the second readout operation, signal line VL2 substitutes for signal line VL1. In FIG. 12, it is difficult to prevent a decrease in frame rate when repairing a defective signal line, but the defective signal line can be repaired.

[0065] As described above, the solid-state imaging device 100 according to the first embodiment comprises a plurality of pixel circuits 1 arranged in a matrix, and a relief unit, wherein the relief unit has N (N is an integer equal to or greater than 3) signal lines and n (n is an integer equal to or less than N) pixel circuits among the plurality of pixel circuits, each of the n pixel circuits being connected to a set of at least two signal lines among the N signal lines and selectively outputting a pixel signal to one of the signal lines included in the set, and the n sets corresponding to the n pixel circuits 1 having different combinations of signal lines.

[0066] This method adds (Nn) redundant signal lines for every n signal lines, allowing for both open and short circuit defects in (Nn) of the n signal lines. Furthermore, the wiring capacitance of the signal lines, i.e., the load capacitance on the pixel circuit, does not change significantly between repair and non-repair, eliminating the need to reduce the readout speed and minimizing frame rate degradation during repair. For example, by disconnecting a faulty signal line and connecting it to a non-faulty signal line, the wiring load on the faulty signal line is isolated. This prevents an increase in the wiring load on the signal line during redundant repair, eliminating a decrease in readout speed and maintaining the frame rate. Furthermore, because the faulty signal line is disconnected, this method can also be used to repair short circuit defects. Furthermore, because the redundant circuit provides α (α≧0) redundant signal lines for n signal lines, the area impact is minimal, and the increase in failure rate due to the added redundant signal lines is minimal.

[0067] Here, the pixel circuit 1 includes an amplifying transistor that outputs a pixel signal and a number of selecting transistors equal to the number of signal lines included in the corresponding set, and the selecting transistor may connect the output terminal of the amplifying transistor to one of the signal lines included in the corresponding set.

[0068] This makes it easy to selectively make the select transistors conductive.

[0069] Here, the N signal lines may include n signal lines, the same number as the n pixel signals, and α (α is an integer greater than or equal to 1) redundant signal lines, and each of the plurality of pixel circuits may be connected to the at least (1 + α) signal lines.

[0070] According to this, for example, if the number of redundant signal lines α (= Nn) is 1, one defect among n signal lines can be repaired, and if α (= Nn) is 2, two defects among n signal lines can be repaired.

[0071] Here, the i-th group (i is an integer from 1 to n) included in the n groups may include the i-th to (i+α)-th signal lines among the N signal lines in arrangement order in the column direction.

[0072] According to this, n sets of n pixel circuits connected to each other are arranged such that the signal lines are shifted one by one in the column direction. The n pixel circuits and (n+α) signal lines are regularly and periodically connected for every n pixel circuits in the column direction, which facilitates layout and repair control in the event of a defect.

[0073] Here, the n pixel circuits 1 (n is an integer smaller than N) may output pixel signals in parallel.

[0074] According to this, n pixel signals (that is, n rows) are output in parallel, which is suitable for increasing the number of pixels and speeding up the frame rate.

[0075] Here, the N signal lines may not include redundant signal lines, and at least one pixel circuit among the n pixel circuits may output in a time-division manner from the same signal line as the other pixel circuits.

[0076] According to this, it is difficult to suppress a decrease in frame rate when repairing a defective signal line, but it is possible to repair the defective signal line without providing a redundant signal line.

[0077] Here, a plurality of scanning circuits may be provided corresponding to a plurality of divided regions of the plurality of pixel circuits, and the plurality of scanning circuits may independently control the selection of signal lines to which pixel signals should be output.

[0078] This makes it possible to increase the number of unnecessary signal lines that can be repaired, thereby further improving the yield.

[0079] Here, at least two of the N signal lines may be provided with load elements for adjusting the magnitude of the load.

[0080] According to this, the readout speeds of the N signal lines are made uniform, so that a decrease in the frame rate can be suppressed.

[0081] where: The imaging device The image pickup apparatus includes the above-described solid-state imaging device for capturing an image of a subject, an imaging optical system for guiding incident light from the subject to the solid-state imaging device, and a signal processing unit for processing an output signal from the solid-state imaging device.

[0082] This adds (Nn) redundant signal lines for every n signal lines, making it possible to repair either an open defect or a short defect in (Nn) of the n signal lines. Moreover, because the wiring capacitance of the signal lines, i.e., the load capacitance on the pixel circuit, does not change significantly between repair and non-repair, there is no need to reduce the readout speed, and it is possible to suppress a decrease in frame rate when repair is performed.

[0083] (Second embodiment) In this embodiment, a configuration example in which N signal lines VL and column circuits 30 are divided into groups that can operate independently will be described.

[0084] 13 is a diagram illustrating a configuration example of a pixel array unit and column circuits in a solid-state imaging device according to Embodiment 2. In the circuit of FIG. 13, α=1, and one redundant signal line is provided.

[0085] solid In the imaging device 100, a layout may be adopted in which the column circuits 30 (current sources 3 and column AD circuits 4) are arranged not only on one side of the pixel array 10 but also on a separate side. This is because it is an arrangement that makes it easy to arrange the layout without degrading characteristics when increasing the number of column circuits that can be mounted on one pixel circuit column. Since the frame rate can be improved by increasing the number of column circuits, the basic configuration of the present disclosure, which has multiple signal lines in one pixel circuit column as described in FIG. solid It is compatible with the technology of the imaging device 100.

[0086] In the second embodiment, one pixel circuit column has n+1 signal lines VL and n column circuits 30. The column circuits 30 are laid out in two regions, each with n / 2 columns. Each divided column circuit 30 has n / 2 signal lines VL that are connected to only one column circuit among the n+1 signal lines. Lines and , and one signal line connected to both column circuits. In the initial state, pixel signals are transmitted from pixel circuit 1 to the column circuits using n / 2 signal lines connected to only one column circuit. The one signal line connected to both column circuits is a redundant line.

[0087] 14 is an explanatory diagram showing an example of a repair operation for a wiring defect in a solid-state imaging device according to embodiment 2. FIG. 14 illustrates pixel circuits in one pixel circuit column in the pixel array 10. Take the example of a case where a failure occurs at a failure point 8 in signal line VL2U. In this example, the failed signal line is the second signal line among the n+1 signal lines connected to the upper column circuit 30.

[0088] In the second embodiment, redundancy repair is performed by shifting the signal lines only within the group including the column circuit to which the faulty signal line is connected among the n+1 signal lines. Specifically, each pixel circuit has two selection transistors, each connected to two adjacent signal lines. When it is the row's turn to read pixel signals, in the group including the column circuit to which the faulty signal line is connected, if the smaller-numbered signal line is smaller than the faulty signal line, the smaller-numbered signal line is selected and connected. If the smaller-numbered signal line connected to the pixel circuit has the same or a larger number than the faulty signal line, the larger-numbered signal line is selected and connected. The signal line selection is performed using a control pulse SEL, which is a control signal for the vertical scanning circuit 2. In the example of FIG. 14, the signal lines VL1U, VL3U to VLn / 2U, and VLn+1 are connected, and the faulty signal line VL2U is not connected to any pixel circuit. Therefore, pixel signals can be propagated using signal lines that are not faulty, so even if a wiring failure occurs, no line defect occurs. Furthermore, because the signal line VL2U where the failure occurred is isolated by the selection transistor, the load capacitance of the signal line does not increase due to the redundancy repair operation, and the frame rate does not decrease due to the redundancy repair. In a group including a column circuit to which the faulty signal line is not connected, the signal line is not shifted. In the example of Figure 14, it is connected to signal lines VL1D to VLn / 2D. Since there are no failures in these signal lines, pixel signals can be propagated.

[0089] The above is just one example, and even if the column circuit 30 is divided into three or more regions and laid out, the signal lines connecting to the column circuit 30 can be divided into groups and connected to the column circuit in a similar manner, and if a signal line fails, redundancy repair can be performed by shifting only the signal line of the failed group.This makes it possible to reduce the number of signal lines for redundancy repair connected to multiple column circuits, and has the advantage of high layout efficiency.

[0090] (Example of matching redundant signal line loads in embodiment 2) 15 is a diagram showing a modification of the pixel array section and column circuits in the solid-state imaging device according to Embodiment 2. The diagram shows an example in which redundant signal line loads are made uniform.

[0091] 13, the signal lines connected to the two divided column circuits are divided into two groups and connected to each column circuit, but the redundancy repair signal line VLn+1 needs to be connected to both column circuits, which increases the wiring length by one line.As a result, the signal line load of only this signal line VLn+1 becomes large.

[0092] 15, SW120 is provided to selectively connect this redundancy repair signal line VLn+1 to the column circuit. For redundancy repair operation, only SW120 on the side connected to the column circuit 30 is turned on, and SW120 on the side not connected is turned off, thereby reducing the wiring capacitance of the signal line VLn+1 for connecting to both column circuits 30 and bringing it closer to the load capacitance with the other signal lines. This makes the loads on all signal lines equal, resulting in equal pixel readout times.

[0093] (Overall redundant relief configuration) FIG. 16 is a diagram illustrating another example of the configuration of the solid-state imaging device according to the first and second embodiments.

[0094] In contrast to the basic configuration example of the solid-state imaging device in FIG. 1, a memory 9 is provided in the signal processing section.

[0095] The memory 9 stores information about wiring defects detected in a pre-shipment inspection of the solid-state imaging device 100 and recovery information for repairing the wiring defects. Specifically, the recovery information stores information about which current source 3 and column AD circuit 4 the signal line VL should be connected to due to the wiring defect, and information about which signal line VL should be selected by the vertical scanning circuit 2. Based on the information in the memory 9, the timing control unit 6 controls the vertical scanning circuit 2, the current source 3, and the column AD circuit 4.

[0096] The memory 9 is a non-volatile memory, and by writing data at the time of shipping inspection, the data in the memory 9 is read when the image sensor is powered on, and the sensor is started in a state where redundancy in the wiring is relieved.

[0097] FIG. 17 is a flowchart illustrating a process of writing recovery information into the solid-state imaging device according to the second embodiment.

[0098] 10 is a flowchart for recording recovery information in the memory 9. This process is performed only once, for example, when the solid-state imaging device 100 is inspected before shipping.

[0099] In step 11, an imaging test is performed in an initial state where there is no recovery information.

[0100] The image data is processed, and the presence or absence of a line defect and, if there is a defect, the location of the defect are detected in step 12. If there is no line defect, the process proceeds to step 15.

[0101] If a line defect is present, in step 13, the system is set to a recovery state in which the signal line in which the line defect has occurred is not used, and then imaging is performed.

[0102] In step 14, the imaging data is processed to detect whether or not there is a line defect. If there is a line defect, the solid-state imaging device 100 is determined to be defective in step 16. If there is no line defect, the process proceeds to step 15.

[0103] In step 15, information on the signal line where the line defect occurs is written into memory 9.

[0104] In step 17, the product is judged to be non-defective.

[0105] FIG. 18 is a flowchart showing an imaging process for imaging using recovery information in the solid-state imaging device according to the second embodiment.

[0106] 10 is a flowchart of an imaging process for capturing an image using recovery information stored in the memory 9. This process is executed when the solid-state imaging device 100 is powered on, for example.

[0107] In step 21, the power supply to the solid-state imaging device 100 is turned on.

[0108] In step 22, the initial state of the signal line VL immediately after power-on is set to the vertical scanning circuit 2 so that the select transistors of all rows are of The horizontal control line is fixed to Lo. Also, all SW120 connecting the signal line VL, the current source 3, and the column AD circuit 4 are turned OFF. This is because if the signal line VL is faulty, there is a possibility that an abnormal current will flow, so all current paths must be cut off.

[0109] In step 23, the memory 9 is accessed, the recovery information is read, and the signal line VL to be used is determined.

[0110] In step 24, the timing control section 6 outputs a signal for selecting the signal line VL to be used.

[0111] In step 25, the timing control unit 6 uses the signal line VL connected to the current source 3 via SW of Turn it ON.

[0112] In step 26, the timing control unit 6 starts scanning and an image is output. By starting up in this step, the faulty signal line VL is connected to the peripheral circuit after power is turned on, preventing an abnormal current from flowing.

[0113] (camera system) 19 is a diagram showing an example of the configuration of an imaging device 200 to which the solid-state imaging device 100 according to the embodiment is applied. The imaging device in the figure is a camera system, and includes the solid-state imaging device 100, an imaging optical system 202 including a lens, a signal processing unit 203, a drive circuit 204, and a system control unit 205.

[0114] In the imaging device 200, the solid-state imaging device 100 according to the first to fourth embodiments is used.

[0115] Furthermore, the drive circuit 204 receives a control signal corresponding to the drive mode from the system control unit 205 and supplies a drive mode signal to the solid-state imaging device 100. Upon receiving the drive mode signal, the solid-state imaging device 100 generates drive pulses corresponding to the drive mode signal and supplies them to each block within the solid-state imaging device 100.

[0116] Furthermore, the signal processing unit 203 receives the image signal output from the solid-state imaging device 100 and performs various signal processing on the image signal.

[0117] As such, the imaging device in this embodiment comprises the above-mentioned solid-state imaging device 100, an imaging optical system 202 that guides incident light from a subject to the solid-state imaging device 100, and a signal processing unit 203 that processes output signals from the solid-state imaging device 100.

[0118] As described above, in the solid-state imaging device 100 according to the second embodiment, the N signal lines include a first group and a second group, the first group includes n / 2 of the N signal lines and α signal lines, the second group includes n / 2 signal lines other than the n / 2 signal lines of the first group and α signal lines that are the same as the α signal lines of the first group, the solid-state imaging device has a first column circuit and a second column circuit for each column, the first column circuit is connected to the signal lines belonging to the first group, and the second column circuit is connected to the signal lines belonging to the second group, and the n / 2 pixel circuits corresponding to the first group may select signal lines to which pixel signals are output independently of the n / 2 pixel circuits corresponding to the second group.

[0119] According to this, the signal line to which the pixel signal is to be output is selected independently for each group, so that a faulty signal line can be repaired for each group, and faults in the signal line can be repaired more flexibly.

[0120] Here, it is preferable to provide first and second switches provided on each of the α signal lines, the first switch switching between connection and disconnection between one end of the corresponding signal line and the first column circuit, the second switch switching between connection and disconnection between the other end of the corresponding signal line and the second column circuit, and the first switch and the second switch not being connected at the same time.

[0121] This allows the wiring loads on the signal lines to be equalized for the first and second column circuits, whether they are performing the relief operation or not, thereby equalizing the readout times of pixel signals and suppressing a decrease in frame rate due to the relief operation.

[0122] Here, a scanning circuit that scans the plurality of pixel circuits may be provided, and the scanning circuit may control selection of a signal line to which a pixel signal is to be output for the n pixel circuits.

[0123] Connection control of N signal lines can be easily achieved in units of one row or n rows. [Industrial Applicability]

[0124] The present disclosure relates to a solid-state imaging device, and a photographing device or a distance measuring imaging device that uses the solid-state imaging device as an imaging device, and is suitable for, for example, a video camera, a digital camera, a distance measuring system, and the like. [Explanation of symbols]

[0125] 100 Solid-state imaging device 1. Pixel circuit 10 Pixel array section 2 Vertical scanning circuit 30 column circuit 3 Current source 4 Column AD circuit 5 Reference signal generation section 6 Timing control section 7 Signal Processing Section 8 Failure location 9. Memory VL signal line HL Horizontal control line 110 Light receiving section 111 Amplifying transistor 112 Transfer transistor 113 Reset Transistor 114 Floating Diffusion 115 Select transistor 116 first selection transistor 117 Second select transistor 120 Signal line and column circuit connection SW 118 Dummy select transistor 119 Wiring parasitic capacitance 121 Dummy SW 200 Imaging device 202 Imaging Optical System 203 Signal Processing Unit 204 Drive circuit 205 System Control Unit

Claims

1. a plurality of pixel circuits arranged in a matrix; a relief unit; the repair unit has N (N is an integer equal to or greater than 3) signal lines and n (n is an integer equal to or less than N) pixel circuits among the plurality of pixel circuits, each of the n pixel circuits is connected to a set of at least two signal lines among the N signal lines, and selectively outputs a pixel signal to one of the signal lines included in the set; The n sets corresponding to the n pixel circuits have different combinations of signal lines. Solid-state imaging device.

2. The pixel circuit an amplifying transistor that outputs a pixel signal; a number of selection transistors equal to the number of signal lines included in the corresponding set; The selection transistor connects the output terminal of the amplification transistor to one of the signal lines included in the corresponding set. The solid-state imaging device according to claim 1 .

3. the N signal lines include n signal lines, the same number as the n pixel circuits, and α (α is an integer equal to or greater than 1) redundant signal lines, 3. The solid-state imaging device according to claim 1, wherein each of the plurality of pixel circuits is connected to at least (1+α) signal lines.

4. The i-th group (i is an integer from 1 to n) included in the n groups includes the i-th to (i+α)-th signal lines in the arrangement order of the N signal lines in the column direction. The solid-state imaging device according to claim 3 .

5. The n is an integer smaller than N, and the n pixel circuits output pixel signals in parallel.

3. The solid-state imaging device according to claim 1.

6. 3. The solid-state imaging device according to claim 1, wherein the N signal lines do not include redundant signal lines, and at least one pixel circuit among the n pixel circuits outputs a pixel signal in a time-division manner from a signal line that is also connected to other pixel circuits.

7. the N signal lines include a first group and a second group; the first group includes n / 2 signal lines out of N signal lines and α signal lines, the second group includes n / 2 signal lines other than the n / 2 signal lines of the first group and α signal lines that are the same as the α signal lines of the first group, the solid-state imaging device has a first column circuit and a second column circuit for each column; the first column circuit is connected to a signal line belonging to the first group; the second column circuit is connected to a signal line belonging to the second group; The n / 2 pixel circuits corresponding to the first group select signal lines to which pixel signals are output independently of the n / 2 pixel circuits corresponding to the second group. The solid-state imaging device according to claim 5 .

8. a first switch and a second switch provided on each of the α signal lines; the first switch switches between a connection state in which one end of a corresponding signal line is connected to the first column circuit and a separation state in which one end of the corresponding signal line is separated from the first column circuit; the second switch switches between a connection state in which the other end of the corresponding signal line is connected to the second column circuit and a separation state in which the other end of the corresponding signal line is separated from the second column circuit; The first switch and the second switch are not in a connected state at the same time. The solid-state imaging device according to claim 7 .

9. a scanning circuit that scans the plurality of pixel circuits; The scanning circuit controls the selection of a signal line to which a pixel signal is to be output for the n pixel circuits.

3. The solid-state imaging device according to claim 1.

10. a plurality of scanning circuits corresponding to a plurality of divided regions of the plurality of pixel circuits, the plurality of scanning circuits independently controlling selection of signal lines to which pixel signals are to be output; 3. The solid-state imaging device according to claim 1.

11. Load elements for adjusting the magnitude of the load are provided on at least two of the N signal lines.

3. The solid-state imaging device according to claim 1.

12. a solid-state imaging device according to claim 1 or 2 for imaging a subject; an imaging optical system that guides incident light from the subject to the solid-state imaging device; a signal processing unit that processes an output signal from the solid-state imaging device; Imaging device.

Images