Semiconductor structure and method for forming same
The semiconductor structure with a vertical channel hole and compensation layer addresses the limitations of traditional two-dimensional memories by enhancing insulation and reducing leakage current, improving integration density and operational performance.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- Filing Date
- 2025-07-17
- Publication Date
- 2026-03-12
AI Technical Summary
Traditional semiconductor memories are two-dimensional and limited by the need for expensive equipment to miniaturize patterns, hindering integration density and increasing production costs.
A semiconductor structure with a vertical channel hole, sidewalls, and a compensation layer filling gaps between the channel hole and gate structure to enhance insulation and reduce leakage current, ensuring the threshold voltage and operational performance.
The structure improves integration density and reduces leakage current, ensuring the semiconductor meets the required threshold voltage and enhances operational performance.
Smart Images
Figure 0007829091000001_ABST
Abstract
Description
[Technical Field]
[0001] FIELD OF THE INVENTION Embodiments of the present invention relate to the field of semiconductor manufacturing, and more particularly to semiconductor structures and methods of forming the same. [Background technology]
[0002] Semiconductor devices incorporate integrated circuit (IC) chips on a package to meet the requirements of various electronic products. In recent years, the demand for integrated systems for specialized processing applications has continued to grow in complex scenarios such as the Internet of Things and edge computing. Functionally integrated systems require the integration of underlying materials. However, traditional semiconductor memories are two-dimensional or planar, and their integration level is a key factor in determining product price.
[0003] Furthermore, the integration density is primarily determined by the area occupied by a unit memory cell, which is heavily influenced by the level of fine pattern formation technology. Although the integration density of two-dimensional semiconductor memory has improved, it is still limited due to the need for extremely expensive equipment to miniaturize the patterns. Therefore, the integration density of semiconductor memory must be improved to meet consumer demands for superior performance and low cost. Summary of the Invention [Problem to be solved by the invention]
[0004] The problem solved by embodiments of the present invention is to provide semiconductor structures and methods for forming the same that are advantageous in improving the operational performance of semiconductor structures. [Means for solving the problem]
[0005] In order to solve the above problems, an embodiment of the present invention provides a semiconductor structure including: a substrate; a gate structure located on the substrate; a channel hole located on the substrate and penetrating the gate structure along a vertical direction; a sidewall extending between a sidewall of the channel hole and the gate structure along the vertical direction; and a compensation layer filling a gap between the channel hole and the gate structure at a bottom of the sidewall.
[0006] Optionally, the semiconductor structure further includes a partition layer located between the sidewall and a sidewall of the channel hole, and the compensation layer also fills a gap between the channel hole and the gate structure at a bottom of the partition layer.
[0007] Optionally, the barrier layer is a protective layer, the protective layer covers the sidewall of the sidewall, or the barrier layer is an air gap.
[0008] Optionally, the barrier layer is a protective layer, and the material of the protective layer includes amorphous silicon, polycrystalline silicon, a combination of polycrystalline silicon with silicon oxide and tungsten, or a combination of polycrystalline silicon with silicon oxide and titanium nitride.
[0009] Optionally, the compensation layer also fills the gap surrounded by the top of the sidewall and the barrier layer.
[0010] Optionally, the sidewalls include a first sidewall covering the gate structure sidewall and a second sidewall covering the first sidewall sidewall, and at the sidewall bottom, the gap filled with the compensation layer is surrounded by the second sidewall bottom, the barrier layer bottom, the first sidewall, and the channel hole sidewall, and at the sidewall top, the gap filled with the compensation layer is surrounded by the second sidewall top, the barrier layer sidewall, and the first sidewall sidewall.
[0011] Optionally, the material of the first sidewall includes silicon nitride and the material of the second sidewall includes silicon oxide.
[0012] Optionally, the material of the compensation layer includes silicon nitride.
[0013] Optionally, the semiconductor structure further includes a top dielectric layer covering a top surface of the gate structure and a bottom dielectric layer located between the gate structure and the substrate, the channel hole further extending through the top dielectric layer and the bottom dielectric layer, the sidewall also extending between the sidewall of the channel hole and the top dielectric layer, and the compensation layer also filling the gap between the channel hole and the bottom dielectric layer.
[0014] Optionally, the semiconductor structure further includes a source / drain doped layer located in the substrate, the source / drain doped layer being exposed on the top surface of the substrate, and the channel hole being located on the source / drain doped layer and in contact with the source / drain doped layer.
[0015] Optionally, a groove is formed on the top side of the channel hole, the groove being positioned at a part of the height of the channel hole, and the semiconductor structure further includes an insulating layer filled in the groove.
[0016] Correspondingly, an embodiment of the present invention further provides a method for forming a semiconductor structure, including: providing a substrate having a gate structure formed thereon; forming an opening penetrating the gate structure; forming a sidewall covering a sidewall of the opening; performing a gap compensation process at a bottom corner of the opening to form a compensation layer filling a gap at the bottom of the sidewall; and forming a channel hole in the opening, the channel hole being located on the substrate and penetrating the gate structure.
[0017] Optionally, the method further includes forming a protective layer covering the sidewalls before performing the gap compensation process at the bottom corner portion of the opening, and in the step of performing the gap compensation process at the bottom corner portion of the opening, the compensation layer also fills the gap at the bottom of the protective layer at the bottom corner portion of the opening, and in the step of forming a channel hole in the opening, located on the substrate and penetrating the gate structure, the channel hole and the protective layer are in contact with each other.
[0018] Optionally, after forming a channel hole in the opening, the channel hole being located on the substrate and penetrating the gate structure, the method further includes removing the protective layer and forming an air gap located between the sidewall and a sidewall of the channel hole.
[0019] Optionally, in the step of performing gap compensation at the bottom corners of the opening, the compensation layer also fills the gap surrounded by the top of the sidewall and the protective layer.
[0020] Optionally, the step of forming a sidewall covering the opening sidewall includes forming a sidewall material layer covering the sidewall and bottom of the opening and the top of the gate structure, and removing the sidewall material layer from the opening bottom and the top of the gate structure, leaving the sidewall material layer covering the opening sidewall as the sidewall.
[0021] Optionally, in the step of providing a substrate, a top dielectric layer is further formed on the top of the gate structure, and a bottom dielectric layer is further formed between the gate structure and the substrate; in the step of forming an opening through the gate structure, the opening further penetrates the top dielectric layer and extends through a portion of the thickness of the bottom dielectric layer; the step of removing the sidewall material layer at the bottom of the opening and on top of the gate structure further includes removing the bottom dielectric layer by the thickness of the remaining portion to expose the top surface of the substrate; and in the step of performing gap compensation treatment at the bottom corner portion of the opening, the compensation layer also fills a gap surrounded by the bottom dielectric layer and the substrate at the bottom corner portion of the opening.
[0022] Optionally, the step of forming a sidewall material layer covering the sidewalls and bottom of the opening and the top of the gate structure includes forming a first sidewall material layer covering the sidewalls and bottom of the opening and the top of the gate structure, and forming a second sidewall material layer covering the first sidewall material layer; the step of removing the sidewall material layer from the bottom of the opening and the top of the gate structure includes removing the first sidewall material layer and the second sidewall material layer from the bottom of the opening and the top of the gate structure, leaving the first sidewall material layer covering the sidewalls of the opening as the first sidewalls, and leaving the second sidewall material layer covering the sidewalls of the opening as the second sidewalls; and the step of performing gap compensation processing at the corner portions of the opening bottom includes filling the gap surrounded by the bottom of the second sidewall, the bottom of the protective layer, and the first sidewall, and further filling the gap surrounded by the top of the second sidewall, the sidewall of the protective layer, and the sidewall of the first sidewall.
[0023] Optionally, before removing the sidewall material layer from the bottom of the opening and the top of the gate structure, the step of removing the sidewall material layer from the bottom of the opening and the top of the gate structure further includes removing the protective material layer from the bottom of the opening and the top of the gate structure and leaving the protective material layer covering the sidewalls as a protective layer.
[0024] Optionally, the method further includes removing the sidewall material layer at the bottom of the opening and the top of the gate structure using a dry etching process, and performing a cleaning process on the sidewalls after removing the sidewall material layer at the bottom of the opening and the top of the gate structure and before performing the gap compensation process at the corners of the opening bottom.
[0025] Optionally, the step of performing gap compensation processing at the opening bottom corner portion and forming a compensation layer to fill the gap at the sidewall bottom includes forming a compensation material layer to cover the opening bottom, the sidewall sidewalls of the opening sidewalls, the top of the gate structure, and the gap filled at the sidewall bottom, and removing the compensation material layer covering the opening bottom, the sidewall sidewalls of the opening sidewalls, and the top of the gate structure, and leaving the compensation material layer filled in the gap at the sidewall bottom as the compensation layer.
[0026] Optionally, an atomic layer deposition process or a low pressure chemical vapor deposition process is employed to form a compensation material layer that fills the gaps at the bottom of the opening, the sidewalls of the opening sidewalls, the top of the gate structure, and the bottom of the sidewalls.
[0027] Optionally, a wet etching process is used to remove the compensation material layer covering the bottom of the opening, the sidewalls covering the opening sidewalls, and the top of the gate structure.
[0028] Optionally, the etching solution of the wet etching process includes a phosphoric acid solution, and the mass percentage of phosphoric acid in the phosphoric acid solution is 40 wt% to 86 wt%, and the process temperature of the wet etching process is 100°C to 160°C.
[0029] Optionally, in the step of providing a substrate, a source / drain doped layer is further formed in the substrate, and the source / drain doped layer is exposed on a top surface of the substrate; in the step of forming an opening penetrating the gate structure, an opening is formed above the source / drain doped layer; and in the step of forming a channel hole located on the substrate and penetrating the gate structure in the opening, the channel hole is formed on the source / drain doped layer and is in contact with the source / drain doped layer.
[0030] Optionally, in the step of forming a channel hole in the opening, the channel hole being located on the substrate and penetrating the gate structure, the channel hole is filled in the opening, or in the step of forming a channel hole in the opening, the channel hole being located on the substrate and penetrating the gate structure, a groove is formed on the top side of the channel hole, the groove being located at a part of the height of the channel hole, and an insulating layer is formed to fill the groove.
[0031] Compared with the prior art, the technical approach of the embodiment of the present invention has the following advantages:
[0032] In the semiconductor structure provided in the embodiment of the present invention, the channel hole is located on the substrate and penetrates the gate structure in the vertical direction, the sidewalls extend vertically between the sidewalls of the channel hole and the gate structure, and the compensation layer is filled in the gap between the channel hole and the gate structure at the bottom of the sidewall. In the embodiment of the present invention, the compensation layer is filled in the gap between the channel hole and the gate structure at the bottom of the sidewall, so that the compensation layer can be used to compensate for the blocking performance of the gate structure and the channel hole at the bottom of the sidewall, which helps to ensure the insulating effect between the gate structure and the channel hole, thereby reducing the probability of leakage current occurring between the gate structure and the channel hole, ensuring that the semiconductor structure meets the threshold voltage required for the process, and helping to reduce the probability of drain-induced barrier lowering of the semiconductor structure, which helps to ensure the operating performance of the semiconductor structure.
[0033] In the method provided in the embodiment of the present invention, an opening is formed through the gate structure, a sidewall is formed to cover the sidewall of the opening, a gap compensation process is performed at the bottom corner of the opening to form a compensation layer to fill the gap at the bottom of the sidewall, and a channel hole is formed in the opening, located on the substrate and penetrating the gate structure. In the embodiment of the present invention, by performing the gap compensation process at the bottom corner of the opening, the compensation layer can be used to compensate for the blocking performance of the gate structure and the channel hole at the bottom of the sidewall, which helps to ensure the insulating effect between the gate structure and the channel hole, thereby reducing the probability of leakage current occurring between the gate structure and the channel hole, ensuring that the semiconductor structure meets the threshold voltage required for the process, and helping to reduce the probability of drain-induced barrier lowering of the semiconductor structure, which helps to ensure the operating performance of the semiconductor structure. [Brief explanation of the drawings]
[0034] [Figure 1] FIG. 1 is a structural schematic diagram corresponding to a semiconductor structure.
[0035] [Figure 2] FIG. 2 is a structural schematic diagram corresponding to one embodiment of a semiconductor structure in the present invention.
[0036] [Figure 3] FIG. 3 is a structural schematic diagram corresponding to another embodiment of the semiconductor structure of the present invention.
[0037] [Figure 4] FIG. 4 is a structural schematic diagram corresponding to yet another embodiment of the semiconductor structure of the present invention.
[0038] [Figure 5] FIG. 5 is a structural diagram corresponding to each step in one embodiment of a method for forming a semiconductor structure in the present invention. [Figure 6] FIG. 6 is a structural diagram corresponding to each step in one embodiment of a method for forming a semiconductor structure in the present invention. [Figure 7] FIG. 7 is a structural diagram corresponding to each step in one embodiment of a method for forming a semiconductor structure in the present invention. [Figure 8] FIG. 8 is a structural diagram corresponding to each step in one embodiment of a method for forming a semiconductor structure in the present invention. [Figure 9] FIG. 9 is a structural diagram corresponding to each step in one embodiment of a method for forming a semiconductor structure in the present invention. [Figure 10] FIG. 10 is a structural diagram corresponding to each step in one embodiment of a method for forming a semiconductor structure in the present invention. [Figure 11] FIG. 11 is a structural diagram corresponding to each step in one embodiment of a method for forming a semiconductor structure in the present invention. [Figure 12] FIG. 12 is a structural diagram corresponding to each step in one embodiment of a method for forming a semiconductor structure in the present invention.
[0039] [Figure 13] FIG. 13 is a structural diagram corresponding to each step in another embodiment of the method for forming a semiconductor structure in the present invention. [Figure 14] FIG. 14 is a structural diagram corresponding to each step in another embodiment of the method for forming a semiconductor structure in the present invention. [Figure 15] FIG. 15 is a structural diagram corresponding to each step in another embodiment of the method for forming a semiconductor structure in the present invention.
[0040] [Figure 16] FIG. 16 is a structural diagram corresponding to each step in yet another embodiment of a method for forming a semiconductor structure according to the present invention. DETAILED DESCRIPTION OF THE INVENTION
[0041] From the background art, it can be seen that it is currently difficult to guarantee the operational performance of semiconductor structures. Here, we will analyze the reasons why the operational performance of semiconductor structures has not yet improved by combining them with a certain semiconductor structure.
[0042] FIG. 1 shows a structural schematic diagram corresponding to a semiconductor structure.
[0043] Referring to FIG. 1, the semiconductor structure includes a substrate 10 having a source-drain doped layer 11 formed thereon, a gate structure 20 located on the substrate 10, a channel hole 61 located on the source-drain doped layer 11 in the substrate 10 and penetrating the gate structure 20 along the vertical direction, and a sidewall 46 extending along the vertical direction between the sidewall of the channel hole 61 and the gate structure 20.
[0044] In the semiconductor manufacturing process, in the process of forming the sidewall 46, damage is likely to occur at the bottom of the sidewall 46, resulting in a defect (shown by a dotted circle in FIG. 1) in the sidewall 46 at the bottom of the channel hole 61. This deteriorates the blocking performance between the channel hole 61 and the gate structure 20 at the bottom of the sidewall 46, resulting in a leakage current (off-state leakage current, I off ) is likely to occur, so the threshold voltage (V t ), causing drain induced barrier low (DIBI) in the semiconductor structure, which affects the operational performance of the semiconductor structure.
[0045] To solve the technical problem, an embodiment of the present invention provides a semiconductor structure including: a substrate; a gate structure located on the substrate; a channel hole located on the substrate and penetrating the gate structure along a vertical direction; a sidewall extending between a sidewall of the channel hole and the gate structure along the vertical direction; and a compensation layer filling a gap between the channel hole and the gate structure at a bottom of the sidewall.
[0046] In the embodiment of the present invention, the gap between the channel hole and the gate structure at the bottom of the sidewall is filled with a compensation layer. Therefore, the compensation layer can be used to supplement the blocking performance of the gate structure and the channel hole at the bottom of the sidewall, which helps to ensure the insulating effect between the gate structure and the channel hole, thereby reducing the probability of leakage current occurring between the gate structure and the channel hole, ensuring that the semiconductor structure meets the threshold voltage required for the process, and reducing the probability of drain-induced barrier lowering of the semiconductor structure, which helps to ensure the operating performance of the semiconductor structure.
[0047] In order to make the above objects, features and advantages of the present invention more clearly comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the drawings.
[0048] FIG. 2 is a structural schematic diagram corresponding to one embodiment of a semiconductor structure in the present invention.
[0049] Referring to FIG. 2 , the semiconductor structure includes a substrate 100, a gate structure 200 located on the substrate 100, a channel hole 610 located on the substrate 100 and penetrating the gate structure 200 along the vertical direction, a sidewall 460 extending between the sidewall of the channel hole 610 and the gate structure 200 along the vertical direction, and a compensation layer 510 filling a gap between the channel hole 610 and the gate structure 200 at the bottom of the sidewall 460.
[0050] The substrate 100 provides a base for processing operations for the formation of semiconductor structures.
[0051] In this embodiment, the substrate 100 is a dielectric material, and specifically, the material of the substrate 100 includes silicon oxide or silicon nitride. As an example, in this embodiment, the material of the substrate 100 is silicon oxide.
[0052] The gate structure 200 is used to control the opening and closing of the channel of the transistor.
[0053] In this embodiment, the gate structure 200 is a metal gate structure, and specifically, the material of the gate structure 200 includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC. As an example, in this embodiment, the material of the gate structure 200 is W.
[0054] The channel hole 610 is used as the channel of the transistor.
[0055] Specifically, in this embodiment, the channel hole 610 extends vertically and penetrates the gate structure 200 to form a vertical channel transistor (VCT). The vertical channel design improves the integration density of transistors, allowing more transistors to be integrated on the same wafer area, thereby improving chip performance and efficiency.
[0056] In this embodiment, the material of the channel hole 610 includes silicon, germanium, silicon germanide, or III-V semiconductor materials. As an example, in this embodiment, the material of the channel hole 610 is silicon. In other embodiments, the material of the channel hole is determined by the type and performance of the transistor.
[0057] The sidewalls 460 are used to separate the gate structure 200 from the channel hole 610 .
[0058] In this embodiment, the sidewall 460 includes a first sidewall 440 covering the sidewall of the gate structure 200 and a second sidewall 450 covering the sidewall of the first sidewall 440 .
[0059] The sidewall 460 consisting of the first sidewall 440 and the second sidewall 450 not only helps ensure the spacing of the sidewall 460, but also allows the first sidewall 440 and the second sidewall 450 to adjust the dielectric constant of the sidewall 460.
[0060] Specifically, in this embodiment, the material of the first sidewall 440 includes silicon nitride, and the material of the second sidewall 450 includes silicon oxide.
[0061] In this embodiment, the thickness of the first sidewall 440 is 1 nm to 8 nm, which provides the first sidewall 440 with a sufficient thickness, thereby helping to ensure the blocking performance of the sidewall 460, and the first sidewall 440 does not occupy too much space to meet the integration density of the semiconductor structure.
[0062] In this embodiment, the thickness of the second sidewall 450 is 1 nm to 8 nm, which provides the second sidewall 450 with a sufficient thickness, thereby helping to ensure the blocking performance of the sidewall 460, and the second sidewall 450 does not occupy too much space to meet the integration density of the semiconductor structure.
[0063] The compensation layer 510 is filled in the gap (shown by the dotted circle in FIG. 2) between the channel hole 610 and the gate structure 200 at the bottom of the sidewall 460, and is used to compensate for the spacing effect between the gate structure 200 at the bottom of the sidewall 460 and the channel hole 610.
[0064] In this embodiment, the gap between the channel hole 610 and the gate structure 200 at the bottom of the sidewall 460 is filled with the compensation layer 510. The compensation layer 510 can be used to supplement the blocking performance of the gate structure 200 and the channel hole 610 at the bottom of the sidewall 460, which helps to ensure the insulating effect between the gate structure 200 and the channel hole 610, thereby reducing the probability of leakage current occurring between the gate structure 200 and the channel hole 610, ensuring that the semiconductor structure meets the threshold voltage required for the process, and reducing the probability of drain-induced barrier lowering of the semiconductor structure, thereby helping to ensure the operating performance of the semiconductor structure.
[0065] It should be noted that in the semiconductor manufacturing process, the bottom of the sidewall 460 is easily damaged by the process and a gap is easily formed, so the compensation layer 510 is filled in the gap between the channel hole 610 and the gate structure 200 at the bottom of the sidewall 460.
[0066] In this embodiment, the material of the compensation layer 510 includes silicon nitride.
[0067] By using silicon nitride to form the compensation layer 510, a relatively good blocking effect can be achieved, and since silicon nitride has a relatively high hardness, it is less likely to be damaged during the semiconductor manufacturing process, thereby ensuring the blocking effect of the compensation layer 510.
[0068] In this embodiment, the semiconductor structure further includes a partition layer 480 located between the sidewall 460 and the sidewall of the channel hole 610 .
[0069] The partition layer 480 is located between the sidewall 460 and the sidewall of the channel hole 610 , and the area of the partition layer 480 is used to provide protection to the sidewall 460 during the process of forming the channel hole 610 .
[0070] In this embodiment, the compensation layer 510 also fills the gap between the channel hole 610 and the gate structure 200 at the bottom of the partition layer 480 .
[0071] Specifically, in the semiconductor manufacturing process, when the region of the partition layer 480 covers the sidewall of the sidewall 460, the bottom of the region of the partition layer 480 damages the sidewall 460 in the process of forming the sidewall 460. Accordingly, the compensation layer 510 also fills the gap between the channel hole 610 and the gate structure 200 at the position of the bottom of the partition layer 480.
[0072] In this embodiment, the thickness of the barrier layer 480 is 3 nm to 12 nm.
[0073] The thickness of the barrier layer 480 is 3 nm to 12 nm, which helps to reduce the difficulty of forming the barrier layer 480 and also helps to provide the sidewall 460 with a sufficient protective effect.
[0074] In this embodiment, the compensation layer 510 also fills the gap surrounded by the top of the sidewall 460 and the partition layer 480 .
[0075] It should be noted that in the semiconductor manufacturing process, the tops of the sidewalls 460 are also exposed from the barrier layer 480, and therefore the tops of the sidewalls 460 are also easily damaged by the process to form gaps, and therefore the compensation layer 510 also fills the gaps surrounded by the tops of the sidewalls 460 and the barrier layer 480.
[0076] Specifically, in this embodiment, at the bottom of the sidewall 460, the gap filled with the compensation layer 510 is surrounded by the bottom of the second sidewall 450, the bottom of the partition layer 480, the first sidewall 440, and the sidewall of the channel hole 610, and at the top of the sidewall 460, the gap filled with the compensation layer 510 is surrounded by the top of the second sidewall 450, the sidewall of the partition layer 480, and the sidewall of the first sidewall 440.
[0077] It should be noted that in the semiconductor manufacturing process, first, the sidewalls 460 covering the sidewalls of the gate structure 200 are formed, and then the channel hole 610 is formed between the sidewalls 460. In the manufacturing process of the sidewalls 460, the second sidewall 450 is closer to the region of the process operation than the first sidewall 440, so the second sidewall 450 is more susceptible to damage; moreover, the material of the first sidewall 440 includes silicon nitride, while the material of the second sidewall 450 includes silicon oxide, and silicon oxide is more susceptible to damage than silicon nitride, so the top and bottom of the second sidewall 450 are easily damaged and partially removed by the process. Therefore, at the bottom of the sidewall 460, the gap filled with the compensation layer 510 is surrounded by the bottom of the second sidewall 450, the bottom of the partition layer 480, the first sidewall 440, and the sidewall of the channel hole 610, and at the top of the sidewall 460, the gap filled with the compensation layer 510 is surrounded by the top of the second sidewall 450, the sidewall of the partition layer 480, and the sidewall of the first sidewall 4400.
[0078] In this embodiment, the partition layer 480 is the protective layer 470 , and the protective layer 470 covers the sidewall of the sidewall 460 .
[0079] The protective layer 470 is used to protect the sidewall 460 during the manufacturing process of the sidewall 460 and reduce damage to the sidewall 460 .
[0080] In this embodiment, the material of the protective layer 470 includes amorphous silicon, polycrystalline silicon, a combination of polycrystalline silicon with silicon oxide and tungsten, or a combination of polycrystalline silicon with silicon oxide and titanium nitride.
[0081] The protective layer 470 can be formed using amorphous silicon, polycrystalline silicon, a combination of polycrystalline silicon with silicon oxide and tungsten, or a combination of polycrystalline silicon with silicon oxide and titanium nitride, which can provide good protection. Furthermore, leaving the protective layer 470 on both sides of the channel hole 610 prevents other elements that are prone to contamination from being introduced, thereby helping to ensure the basic operating performance of the transistor.
[0082] In this embodiment, the semiconductor structure further includes a top dielectric layer 320 covering the top surface of the gate structure 200 .
[0083] The top dielectric layer 320 is used to isolate the gate structure 200 from other device structures above it.
[0084] In this embodiment, the material of the top dielectric layer 320 is an insulating material, including one or several of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.
[0085] Correspondingly, in this embodiment, the sidewall 460 also extends between the sidewall of the channel hole 610 and the top dielectric layer 320 .
[0086] In this embodiment, the semiconductor structure further includes a bottom dielectric layer 310 located between the gate structure 200 and the substrate 100 .
[0087] The bottom dielectric layer 310 is used to isolate the gate structure 200 from other device structures below it.
[0088] In this embodiment, the material of the bottom dielectric layer 310 is an insulating material, including one or several of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.
[0089] Correspondingly, in this embodiment, the channel hole 610 extends further to penetrate the top dielectric layer 320 and the bottom dielectric layer 310 .
[0090] In this embodiment, the compensation layer 510 also fills the gap between the channel hole 610 and the bottom dielectric layer 310 .
[0091] In the semiconductor manufacturing process, a protective layer 470 is first formed to cover the sidewall 460, and then a region for forming a channel hole 610 is formed through the bottom dielectric layer 310. During the process operation, the sidewall of the bottom dielectric layer 310 is also exposed to the outside, and therefore the bottom dielectric layer 310 is also partially damaged by the process operation. Therefore, in the manufacturing process of the compensation layer 510, the compensation layer 510 also fills the gap between the channel hole 610 and the bottom dielectric layer 310.
[0092] In this embodiment, the semiconductor structure further includes a source-drain doped layer 110 located within the substrate 100, with the source-drain doped layer 110 exposed at the top surface of the substrate 100.
[0093] The source / drain doped layer 110 is used as a source region or a drain region of a transistor, and specifically, the doping type of the source / drain doped layer 110 is the same as the channel conductivity type of the corresponding transistor.
[0094] In this embodiment, the source / drain doped layer 110 is exposed on the top surface of the substrate 100 and is used to bring the channel hole 610 located on the substrate 100 and the source / drain doped layer 110 into contact with each other.
[0095] Correspondingly, in this embodiment, the channel hole 610 is located on the source / drain doped layer 110 and is in contact with the source / drain doped layer 110 .
[0096] FIG. 3 is a structural schematic diagram corresponding to another embodiment of the semiconductor structure of the present invention.
[0097] The same parts of this embodiment as those of the previous embodiment will not be described again here. This embodiment differs from the previous embodiment in that the structure of the channel hole is different.
[0098] Referring to FIG. 3, a groove 620 is formed on the top side of the channel hole 611, the groove 620 being located at a part of the height of the channel hole 611, and the semiconductor structure further includes an insulating layer 640 filled in the groove 620.
[0099] The region between the channel hole 611 and the sidewall 461 is not filled, and the insulating layer 640 is filled in the groove 620, which helps to obtain a top surface of the channel hole 611 with good surface flatness.
[0100] In this embodiment, the material of the insulating layer 640 is an insulating material, which includes one or several of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.
[0101] FIG. 4 is a structural schematic diagram corresponding to another embodiment of the semiconductor structure of the present invention.
[0102] The same parts of this embodiment as those of the previous embodiment will not be described again here. This embodiment differs from the previous embodiment in that the structure of the partition layer is different.
[0103] Referring to FIG. 4, the partition layer 482 is an air gap 650 .
[0104] The air gap 650 is used in conjunction with the sidewall 462 to separate the gate structure 202 from the channel hole 612 .
[0105] Specifically, in this embodiment, the positions to be occupied by the protective layer are formed in advance, and after the channel holes 612 are formed, the protective layer is removed to form the air gaps 650 .
[0106] In this embodiment, the air gap 650, together with the sidewall 462, separates the gate structure 202 and the channel hole 612. Since air has a low dielectric constant, the air gap 650 and the sidewall 462 jointly separate the gate structure 202 and the channel hole 612, which helps to reduce the dielectric constant of the entire separation between the gate structure 202 and the channel hole 612, thereby helping to reduce parasitic capacitance and improve the operating performance of the semiconductor structure.
[0107] 5 to 12 are structural schematic diagrams corresponding to steps in one embodiment of a method for forming a semiconductor structure in the present invention.
[0108] Referring to FIG. 5, a substrate 100 is provided, on which a gate structure 200 is formed.
[0109] The substrate 100 provides a base for processing operations for the formation of semiconductor structures.
[0110] In this embodiment, the substrate 100 is a dielectric material, and specifically, the material of the substrate 100 includes silicon oxide or silicon nitride. As an example, in this embodiment, the material of the substrate 100 is silicon oxide.
[0111] The gate structure 200 is used to control the opening and closing of the channel of the transistor.
[0112] In this embodiment, the gate structure 200 is a metal gate structure, and specifically, the material of the gate structure 200 includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC. As an example, in this embodiment, the material of the gate structure 200 is W.
[0113] In this embodiment, in the step of providing a substrate 100, a top dielectric layer 320 is further formed on top of the gate structure 200, and a bottom dielectric layer 310 is further formed between the gate structure 200 and the substrate 100.
[0114] The top dielectric layer 320 is used to isolate the gate structure 200 from other device structures above it.
[0115] In this embodiment, the material of the top dielectric layer 320 is an insulating material, including one or several of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.
[0116] The bottom dielectric layer 310 is used to isolate the gate structure 200 from other device structures below it.
[0117] In this embodiment, the material of the bottom dielectric layer 310 is an insulating material, including one or several of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.
[0118] In this embodiment, in the step of providing the substrate 100, a source / drain doped layer 110 is further formed in the substrate 100, and the source / drain doped layer 110 is exposed on the top surface of the substrate 100.
[0119] The source / drain doped layer 110 is used as a source region or a drain region of a transistor, and specifically, the doping type of the source / drain doped layer 110 is the same as the channel conductivity type of the corresponding transistor.
[0120] In this embodiment, the source / drain doped layer 110 is exposed on the top surface of the substrate 100 and is used to bring the channel hole formed later on the substrate 100 and the source / drain doped layer 110 into contact with each other.
[0121] With continued reference to FIG. 5, an opening 210 is formed through the gate structure 200 .
[0122] The opening 210 is used to provide a spatial location for the subsequent formation of sidewalls and channel holes.
[0123] Correspondingly, in this embodiment, in the step of forming the opening 210 through the gate structure 200, the opening 210 also penetrates through the top dielectric layer 320 and extends through part of the thickness of the bottom dielectric layer 310.
[0124] The opening 210 extends through a portion of the thickness of the bottom dielectric layer 310, with the remaining portion of the thickness of the bottom dielectric layer 310 covering the top surface of the source / drain doped layer 110, thereby providing protection for the source / drain doped layer 110 in the subsequent step of forming sidewalls.
[0125] In this embodiment, in the step of forming the opening 210 through the gate structure 200 , the opening 210 is formed above the source / drain doped layer 110 .
[0126] By forming the opening 210 above the source / drain doped layer 110, a channel hole to be formed later can be brought into contact with the source / drain doped layer 110.
[0127] 6 and 7, a sidewall 460 is formed to cover the sidewall of the opening 210.
[0128] The sidewalls 460 are used to separate the gate structure 200 from a channel hole that will be formed later.
[0129] Referring to FIG. 6, the step of forming sidewalls 460 covering the sidewalls of the opening 210 includes forming a sidewall material layer 400 covering the sidewalls and bottom of the opening 210 and the top of the gate structure 200.
[0130] The sidewall material layer 400 is used to form the sidewalls 460 .
[0131] Specifically, in this embodiment, the step of forming a sidewall material layer 400 covering the sidewalls and bottom of the opening 210 and the top of the gate structure 200 includes forming a first sidewall material layer 410 covering the sidewalls and bottom of the opening 210 and the top of the gate structure 200.
[0132] The first sidewall material layer 410 is used to form the first sidewall.
[0133] In this embodiment, the material of the first sidewall material layer 410 includes silicon nitride.
[0134] In this embodiment, in the step of forming the first sidewall material layer 410 covering the sidewalls and bottom of the opening 210 and the top of the gate structure 200, the thickness of the first sidewall material layer 410 is 1 nm to 8 nm, which provides a sufficient thickness for the first sidewalls to be formed later, thereby helping to ensure the blocking performance of the sidewalls 460, and the first sidewalls do not occupy too much space to meet the integration density of the semiconductor structure.
[0135] In this embodiment, a second sidewall material layer 420 covering the first sidewall material layer 410 is formed.
[0136] Specifically, the second sidewall material layer 420 conformally covers the first sidewall material layer 410, and the second sidewall material layer 420 is used to form the second sidewall.
[0137] In this embodiment, the material of the second sidewall material layer 420 includes silicon oxide.
[0138] In this embodiment, in the step of forming the second sidewall material layer 420 covering the first sidewall material layer 410, the thickness of the second sidewall material layer 420 is 1 nm to 8 nm, which provides a sufficient thickness for the second sidewall to be formed later, thereby helping to ensure the blocking performance of the sidewall 460, and also preventing the second sidewall from occupying too much space to meet the integration density of the semiconductor structure.
[0139] Referring to FIG. 7, the sidewall material layer 400 at the bottom of the opening 210 and on the top of the gate structure 200 is removed, leaving the sidewall material layer 400 covering the opening sidewalls as sidewalls 460 .
[0140] In this embodiment, a dry etching process is used to remove the sidewall material layer 400 at the bottom of the opening 210 and on top of the gate structure 200 .
[0141] Since the dry etching process has anisotropic etching properties, selecting the dry etching process helps to reduce damage to the substrate 100 at the bottom of the opening 210, and at the same time, since the dry etching has stronger etching directionality, it also helps to improve the profile quality and dimensional accuracy of the sidewall 460.
[0142] Specifically, in this embodiment, in the step of removing the sidewall material layer 400 at the bottom of the opening 210 and the top of the gate structure 200, the first sidewall material layer 410 and the second sidewall material layer 420 at the bottom of the opening 210 and the top of the gate structure 200 are removed, and the first sidewall material layer 410 covering the sidewall of the opening 210 remains as the first sidewall 440, and the second sidewall material layer 420 covering the sidewall of the opening 210 remains as the second sidewall 450.
[0143] The sidewall 460 consisting of the first sidewall 440 and the second sidewall 450 not only helps ensure the spacing of the sidewall 460, but also allows the first sidewall 440 and the second sidewall 450 to adjust the dielectric constant of the sidewall 460.
[0144] Specifically, in this embodiment, the material of the first sidewall 440 includes silicon nitride, and the material of the second sidewall 450 includes silicon oxide.
[0145] This embodiment further includes forming a protective layer 470 covering the sidewalls 460 before performing gap compensation processing on the corners of the bottom of the opening 210 later.
[0146] The protective layer 470 is used to protect the sidewall 460 during the manufacturing process of the sidewall 460 and reduce damage to the sidewall 460 .
[0147] In this embodiment, in the step of forming the protective layer 470 covering the sidewalls 460, the material of the protective layer 470 includes amorphous silicon, polycrystalline silicon, a combination of polycrystalline silicon with silicon oxide and tungsten, or a combination of polycrystalline silicon with silicon oxide and titanium nitride.
[0148] The protective layer 470 can be formed using amorphous silicon, polycrystalline silicon, a combination of polycrystalline silicon with silicon oxide and tungsten, or a combination of polycrystalline silicon with silicon oxide and titanium nitride, which can provide good protection. After the channel hole is formed, the protective layer 470 can be left on both sides of the channel hole to prevent other elements that are prone to contamination from being introduced, thereby ensuring the basic operating performance of the transistor.
[0149] Specifically, referring to FIG. 6, before removing the sidewall material layer 400 at the bottom of the opening 210 and the top of the gate structure 200, the method further includes forming a protective material layer 430 covering the sidewall material layer 400.
[0150] Specifically, the protective material layer 430 conformally covers the sidewall material layer 400 , and the protective material layer 430 is used to form the protective layer 470 .
[0151] Referring to FIG. 7 , the step of removing the sidewall material layer 400 at the bottom of the opening 210 and the top of the gate structure 200 further includes removing the protective material layer 430 at the bottom of the opening 210 and the top of the gate structure 200, leaving the protective material layer 430 covering the sidewalls of the sidewalls 460 as a protective layer 470.
[0152] Specifically, in this embodiment, a dry etching process is used to remove the protective material layer 430 at the bottom of the opening 210 and on top of the gate structure 200 .
[0153] In this embodiment, the step of removing the sidewall material layer 400 at the bottom of the opening 210 and on top of the gate structure 200 further includes removing excess portions of the thickness of the bottom dielectric layer 310 to expose the top surface of the substrate 100.
[0154] Specifically, in this embodiment, the excess thickness of the bottom dielectric layer 310 is removed to expose the top surface of the source-drain doped layer 110 of the substrate 100, in preparation for later forming a channel hole that will be in contact with the source-drain doped layer 110.
[0155] Referring to FIG. 8, after removing the sidewall material layer 400 at the bottom of the opening 210 and the top of the gate structure 200, the method further includes performing a cleaning process on the sidewalls 460 before performing a gap compensation process at the bottom corners of the opening 210.
[0156] The manufacturing process for forming the sidewall 460 is likely to leave residues, particularly at the bottom of the opening 210. In particular, in this embodiment, a dry etching process is used to form the sidewall 460 and the protective layer 470, which makes it easy for dry etching residues to remain in the opening 210. Therefore, a cleaning process is performed on the sidewall 460 to remove the residues in the opening 210, reducing contamination of subsequent manufacturing processes and providing a good process platform for the subsequent manufacturing processes.
[0157] It should be noted that cleaning the sidewalls 460 may damage the top and bottom of the sidewalls 460 where the protective layer 470 is exposed. Specifically, since the first sidewalls 440 are made of silicon nitride and the second sidewalls 450 are made of silicon oxide, which is more susceptible to damage, the cleaning process removes a portion of the second sidewalls 450 at the top and bottom of the sidewalls 460. At the same time, since the opening 210 also penetrates the bottom dielectric layer 310, i.e., the opening 210 also exposes the bottom dielectric layer 310, the cleaning process also removes a portion of the bottom dielectric layer 310 at the bottom corners of the opening 210.
[0158] In this embodiment, a diluted hydrofluoric acid (DHF) solution is used as the cleaning solution for the cleaning process.
[0159] The etch rate of dilute hydrofluoric acid solutions is relatively slow and stable, which helps ensure smooth cleaning and minimizes damage to film layers. It should also be noted that cleaning solutions containing fluorine tend to cause etching damage to silicon oxide.
[0160] Specifically, in this example, the volume ratio of water to hydrofluoric acid in the diluted hydrofluoric acid solution is 100:1 to 2000:1.
[0161] In other embodiments, the cleaning solution for the cleaning process can be a diluted sulfuric acid peroxide (DSP) mixed solution or an SST-A47 organic solution.
[0162] 9 and 10, a gap compensation process is performed at the bottom corners of the opening 210 to form a compensation layer 510 that fills the gap at the bottom of the sidewall 460 (shown by the dotted circle in FIG. 10).
[0163] The compensation layer 510 is filled in the bottom of the sidewall 460 at the bottom corner portion of the opening 210, and then a channel hole is formed in the opening 210. That is, the compensation layer 510 is used to fill in the gap between the channel hole to be formed later and the gate structure 200, and to compensate for the spacing effect between the gate structure 200 at the bottom of the sidewall 460 and the channel hole.
[0164] In this embodiment, by performing gap compensation processing at the bottom corner of the opening 210, the compensation layer 510 can be used to supplement the blocking performance of the bottom of the sidewall 460 for the gate structure 200 and the channel hole 610, which helps to ensure the insulating effect between the gate structure 200 and the channel hole 610, thereby reducing the probability of leakage current occurring between the gate structure 200 and the channel hole 610, ensuring that the semiconductor structure meets the threshold voltage required for the process, and helping to reduce the probability of drain-induced barrier lowering of the semiconductor structure, which helps to ensure the operating performance of the semiconductor structure.
[0165] In this embodiment, when cleaning the sidewall 460, the sidewall 460 is damaged by the bottom of the sidewall 460 where the protective layer 470 is exposed. Therefore, in the step of performing gap compensation processing at the bottom corner portion of the opening 210, the compensation layer 510 also fills the gap at the bottom of the protective layer 470 at the bottom corner portion of the opening 210.
[0166] In this embodiment, when cleaning the sidewalls 460, the tops of the sidewalls 460 where the protective layer 470 is exposed may damage the sidewalls 460. Therefore, in the step of performing gap compensation at the bottom corners of the opening 210, the compensation layer also fills the gaps formed by the tops of the sidewalls 460 and the protective layer 470.
[0167] Specifically, in this embodiment, the material of the second sidewall 450 is silicon oxide and the material of the first sidewall 440 is silicon nitride. Silicon oxide is easily damaged, and gaps will form in parts of the second sidewall 450 after the top and bottom are removed. Therefore, in the step of performing gap compensation processing at the bottom corner portion of the opening 210, the compensation layer 510 fills the gaps formed by the bottom of the second sidewall 450, the bottom of the protective layer 470, and the first sidewall 440, and further, the compensation layer 510 also fills the gaps formed by the top of the second sidewall 450, the sidewall of the protective layer 470, and the first sidewall 440.
[0168] In this embodiment, when the cleaning process is performed on the sidewall 460, the cleaning process also removes a portion of the bottom dielectric layer 310 at the bottom corner of the opening 210, so that in the step of performing the gap compensation process at the bottom corner of the opening 210, the compensation layer 510 also fills the gap formed by the bottom dielectric layer 310 at the bottom corner of the opening 210 and the substrate 100.
[0169] In this embodiment, in the step of forming the compensation layer 510 filling the gap at the bottom of the sidewall 460, the material of the compensation layer 510 includes silicon nitride.
[0170] Using silicon nitride to form the compensation layer 510 can achieve a good blocking effect, and since silicon nitride has a relatively high hardness, it is less likely to be damaged during the semiconductor manufacturing process, thereby ensuring the blocking effect of the compensation layer 510.
[0171] Specifically, referring to FIG. 9 , the step of performing gap compensation processing on the bottom corner portion of the opening 210 and forming a compensation layer 510 to fill the gap at the bottom of the sidewall 460 includes forming a compensation material layer 500 to cover the bottom of the opening 210, the sidewalls 460 of the sidewalls of the opening 210, the top of the gate structure 200, and the gap filled at the bottom of the sidewall 460.
[0172] The compensation material layer 500 is used to form the compensation layer 510 .
[0173] Specifically, in this embodiment, the compensation material layer 500 also fills the gaps at the top of the sidewalls 460 and the gaps in the bottom dielectric layer 310 at the bottom corners of the opening 210 .
[0174] In this embodiment, in the step of forming the compensation material layer 500 to cover the gaps filling the bottom of the opening 210, the sidewalls 460 of the sidewalls of the opening 210, the top of the gate structure 200, and the bottom of the sidewalls 460, the thickness of the compensation material layer 500 is 1 nm to 10 nm.
[0175] When the thickness of the compensation material layer 500 is 1 nm to 10 nm, the compensation material layer 500 can sufficiently fill the gaps and not cause unnecessary waste of material.
[0176] In this embodiment, an atomic layer deposition (ALD) process is used to form a compensation material layer 500 that covers the bottom of the opening 210, the sidewalls 460 of the opening 210, the top of the gate structure 200, and the gap filled at the bottom of the sidewalls 460.
[0177] The compensation material layer 500 formed using an atomic layer deposition process has good thickness uniformity and good step coverage capability, allowing the compensation material layer 500 to provide suitable conformal coverage of the bottom of the opening 210, the sidewalls of the sidewalls 460 covering the sidewalls of the opening 210, the top of the gate structure 200, and the gap filling at the bottom of the sidewalls 460.
[0178] In another embodiment, a low pressure chemical vapor deposition (LPCVD) process can be used to form a compensation material layer that covers the bottom of the opening, the sidewalls of the opening sidewalls, the top of the gate structure, and the gap filled at the bottom of the sidewalls.
[0179] Referring to FIG. 10 , the bottom of the opening 210, the sidewalls of the sidewalls 460 covering the sidewalls of the opening 210, and the compensation material layer 500 on the top of the gate structure 200 are removed, and the compensation material layer filling the gap at the bottom of the sidewalls 460 remains as the compensation layer 510.
[0180] Specifically, in this embodiment, the compensation material layer 500 filling the gaps on the top surfaces of the sidewalls 460 and the gaps in the bottom dielectric layer 310 at the bottom corners of the opening 210 is also left as the compensation layer 510 .
[0181] In this embodiment, a wet etching process is used to remove the compensation material layer 500 covering the bottom of the opening 210, the sidewalls 460 of the opening 210, and the top of the gate structure 200.
[0182] The wet etching process has a relatively low cost, simple operation steps, and can achieve a relatively large etching selectivity, which helps reduce damage to other film layers in the process of removing the compensation material layer 500 covering the bottom of the opening 210, the sidewalls 460 of the opening 210, and the top of the gate structure 200.
[0183] In this embodiment, the etching solution for the wet etching process includes a phosphoric acid solution.
[0184] Phosphoric acid has a relatively high viscosity, typically 37.10 mPa.s. That is, although the viscosity of the phosphoric acid solution is relatively high, it is difficult for the phosphoric acid solution to penetrate into the gaps and to react with the compensation material layer 500 in the gaps. Therefore, when the wet etching process removes the compensation material layer 500 covering the bottom of the opening 210, the sidewalls 460 of the sidewalls of the opening 210, and the top of the gate structure 200, the compensation material layer 500 in the gaps can be easily left behind, which is helpful in forming the compensation layer 510.
[0185] In this example, the mass percentage of phosphoric acid in the phosphoric acid solution is 40 wt% to 86 wt%.
[0186] The mass percentage of phosphoric acid in the phosphoric acid solution is 40 wt% to 86 wt%, which helps to cleanly remove the compensation material layer 500 covering the bottom of the opening 210, the sidewalls 460 of the sidewalls of the opening 210, and the top of the gate structure 200, and also maintains a relatively high viscosity, making it easier to leave the compensation material layer 500 in the gap.
[0187] Specifically, in this example, the mass percentage of phosphoric acid in the phosphoric acid solution is 40 wt% to 60 wt%.
[0188] By setting the mass percentage of phosphoric acid in the phosphoric acid solution to 40 wt % to 60 wt %, the etching rate is slowed down, which helps to make it easier to control the wet etching.
[0189] In this embodiment, the process temperature for the wet etching process is 100°C to 160°C.
[0190] By setting the process temperature of the wet etching process to 100°C to 160°C, efficient etching is maintained, while at the same time, relatively good etching quality is maintained.
[0191] Specifically, in this embodiment, the process temperature for the wet etching process is 100°C to 130°C.
[0192] Setting the process temperature of the wet etching process to 100° C. to 130° C. helps to slow down the etching rate and makes it easier to control the wet etching.
[0193] 11 and 12 in combination, a channel hole 610 is formed in the opening 210, located on the substrate 100 and penetrating the gate structure 200.
[0194] The channel hole 610 is used as the channel of the transistor.
[0195] Specifically, in this embodiment, the channel hole 610 extends vertically and penetrates the gate structure 200 to form a vertical channel transistor (VCT). The vertical channel design improves the integration density of transistors, allowing more transistors to be integrated on the same wafer area, thereby improving chip performance and efficiency.
[0196] In this embodiment, the material of the channel hole 610 includes silicon, germanium, silicon germanide, or III-V semiconductor materials. As an example, in this embodiment, the material of the channel hole 610 is silicon. In other embodiments, the material of the channel hole is determined by the type and performance of the transistor.
[0197] Correspondingly, in this embodiment, in the step of forming the channel hole 610 in the opening 210, which is located on the substrate 100 and penetrates the gate structure 200, the channel hole 610 is in contact with the protective layer 470.
[0198] In this embodiment, the top surface of the source / drain doped layer 110 is exposed in the opening 210, and correspondingly, in the step of forming a channel hole 610 in the opening 210, the channel hole 610 is located on the substrate 100 and penetrates the gate structure 200, and the channel hole 610 is formed on the source / drain doped layer 110 and is in contact with the source / drain doped layer 110.
[0199] In this embodiment, in the step of forming a channel hole 610 in the opening 210 , the channel hole 610 is located on the substrate 100 and passes through the gate structure 200 , and the channel hole 610 is filled in the opening 210 .
[0200] Specifically, referring to FIG. 11 , the step of forming a channel hole 610 in the opening 210, located on the substrate 100, and penetrating the gate structure 200 includes forming a channel material layer 600 that fills the opening 210 and covers the top of the top dielectric layer 320.
[0201] The channel material layer 600 is used to form a channel hole 610 .
[0202] Referring to FIG. 12, the channel material layer 600 is planarized to remove the channel material layer 600 higher than the top dielectric layer 320, leaving the channel material layer 600 filling the opening 210 as a channel hole 610.
[0203] 13 to 15 are structural schematic diagrams corresponding to steps in another embodiment of the method for forming a semiconductor structure in the present invention.
[0204] The same parts of this embodiment as those of the previous embodiment will not be described again here. This embodiment differs from the previous embodiment in that the structure of the channel hole is different.
[0205] Referring to Figures 13 to 15 in combination, in the step of forming a channel hole 611 located on the substrate 101 and penetrating the gate structure 201 within the opening 211, a groove 620 is formed on the top side of the channel hole 611, located at a portion of the height of the channel hole 611.
[0206] The channel hole 611 is not filled in the region between the openings 211, which helps to reduce the probability of a depression occurring on the top surface of the channel hole 611 that is formed.
[0207] In this embodiment, an insulating layer 640 is formed to fill the recessed groove 620 .
[0208] Filling the groove 620 with the insulating layer 640 helps to obtain a top surface of the channel hole 611 with excellent surface flatness.
[0209] In this embodiment, in the step of forming the insulating layer 640 to fill the groove 620, the material of the insulating layer 640 is an insulating material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.
[0210] Specifically, referring to FIG. 13, a channel material layer 601 is formed to cover the sidewalls and bottom of opening 211 and the top of top dielectric layer 321, and a groove 620 is formed in channel material layer 601 within opening 211 so as to surround it.
[0211] The channel material layer 601 is used to form a channel hole 611 .
[0212] Referring to FIG. 14, an insulating material layer 630 is formed to fill the groove 620 and cover the channel material layer 601 .
[0213] The insulating material layer 630 is used to form the insulating layer 640 .
[0214] Referring to FIG. 15, the insulating material layer 630 and the channel material layer 601 are planarized, and the insulating material layer 630 and the channel material layer 601 higher than the top dielectric layer 321 are removed, leaving the channel material layer 601 in the opening 211 as a channel hole 611, and the insulating material layer 630 in the opening 211 as an insulating layer.
[0215] FIG. 16 is a structural diagram corresponding to each step in yet another embodiment of a method for forming a semiconductor structure according to the present invention.
[0216] The same parts of this embodiment as those of the previous embodiment will not be described again here. The difference between this embodiment and the previous embodiment is that the protective layer is removed.
[0217] Referring to FIG. 16, after forming the channel hole 612 in the opening 212, the channel hole 612 is located on the substrate 102 and penetrates the gate structure 202, and then the protective layer is removed to form an air gap 650 located between the sidewall 462 and the sidewall of the channel hole 612.
[0218] The air gap 650 is used in conjunction with the sidewall 462 to separate the gate structure 202 from the channel hole 612 .
[0219] In this embodiment, the air gap 650, together with the sidewall 462, separates the gate structure 202 and the channel hole 612. Since air has a low dielectric constant, the air gap 650 and the sidewall 462 jointly separate the gate structure 202 and the channel hole 612, which helps to reduce the dielectric constant of the entire separation between the gate structure 202 and the channel hole 612, thereby helping to reduce parasitic capacitance and improve the operating performance of the semiconductor structure.
[0220] Although the present invention has been disclosed as above, it is not limited thereto. Anyone skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, and therefore the scope of protection of the present invention should be determined based on the scope defined by the claims. [Explanation of symbols]
[0221] 10 Substrate 11 Source / drain doped layer 20 Gate Structure 46 Sidewall 61 Channel Hole 100 boards 101 Substrate 102 Circuit Board 110 Source / drain doped layer 200 gate structure 201 Gate Structure 202 Gate Structure 210 Aperture 211 Aperture 212 Aperture 310 bottom dielectric layer 320 top dielectric layer 321 top dielectric layer 400 Sidewall Material Layer 410 First sidewall material layer 420 Second sidewall material layer 430 Protective material layer 440 1st sidewall 450 2nd sidewall 460 sidewall 461 Sidewall 462 Sidewall 470 Protective layer 480 Partition layer 482 Partition layer 500 compensation material layer 510 Compensation layer 600 channel material layer 601 Channel material layer 610 Channel Hole 611 Channel Hole 612 Channel Hole 620 Groove 630 Insulating material layer 640 Insulating Layer 650 Air Gap
Claims
1. A substrate; a gate structure located on the substrate; a channel hole located on the substrate and passing through the gate structure along a vertical direction; a sidewall structure extending between a sidewall of the channel hole and the gate structure along the vertical direction; a compensation layer filling a gap between the channel hole and the gate structure at the bottom of the sidewall structure; a partition layer located between the sidewall structure and a sidewall of the channel hole; 1. A semiconductor structure comprising: the sidewall structure includes a first sidewall covering a sidewall of the gate structure and a second sidewall covering a sidewall of the first sidewall; At the bottom of the sidewall structure, the gap filled with the compensation layer is surrounded by the bottom surface of the second sidewall, the bottom surface of the partition layer, the first sidewall, and the sidewall of the channel hole.
2. the partition layer is a protective layer that covers the sidewall of the sidewall structure, or The partition layer is an air gap. The semiconductor structure of claim 1 .
3. 3. The semiconductor structure of claim 2, wherein the partition layer is a protective layer, and the material of the protective layer includes amorphous silicon, polycrystalline silicon, a combination of polycrystalline silicon with silicon oxide and tungsten, or a combination of polycrystalline silicon with silicon oxide and titanium nitride.
4. 2. The semiconductor structure of claim 1, wherein the compensation layer further fills a gap defined by the top of the sidewall structure and the partition layer.
5. A semiconductor structure as described in claim 4, characterized in that at the top of the sidewall structure, the gap filled with the compensation layer is surrounded by the top surface of the second sidewall, the partition layer sidewall, and the first sidewall sidewall.
6. 6. The semiconductor structure of claim 5, wherein the first sidewall material comprises silicon nitride and the second sidewall material comprises silicon oxide.
7. 2. The semiconductor structure of claim 1 wherein the material of said compensation layer comprises silicon nitride.
8. the semiconductor structure further includes a top dielectric layer covering a top surface of the gate structure and a bottom dielectric layer positioned between the gate structure and a substrate; the channel hole further extends through the top and bottom dielectric layers; the sidewall structure further extends between a sidewall of the channel hole and the top dielectric layer; the compensation layer further fills a gap between the channel hole and the bottom dielectric layer. The semiconductor structure of claim 1 .
9. the semiconductor structure further includes a source-drain doped layer located within the substrate, the source-drain doped layer being exposed at a top surface of the substrate; the channel hole is located on the source / drain doped layer and is in contact with the source / drain doped layer. The semiconductor structure of claim 1 .
10. 2. The semiconductor structure according to claim 1, wherein a groove is formed on a top side of the channel hole, the groove being positioned at a part of the height of the channel hole, and the semiconductor structure further includes an insulating layer filled in the groove.
11. providing a substrate having a gate structure formed thereon; forming an opening through the gate structure; forming a sidewall structure covering a sidewall of the opening; performing a gap compensation process at the bottom corner of the opening to form a compensation layer that fills the gap at the bottom of the sidewall structure; forming a channel hole in the opening, the channel hole being located on the substrate and passing through the gate structure; forming a protective layer covering a sidewall of the sidewall structure before performing gap compensation processing at the bottom corner portion of the opening; 1. A method for forming a semiconductor structure, comprising: In the step of forming a channel hole located on the substrate and penetrating the gate structure in the opening, the channel hole and the protection layer are in contact with each other; The step of forming a sidewall structure covering the opening sidewall includes forming a sidewall structure material layer covering the opening sidewall and bottom and a top of the gate structure; removing the sidewall structure material layer from the bottom of the opening and the top of the gate structure, and leaving the sidewall structure material layer covering the sidewall of the opening as a sidewall structure; The step of forming a sidewall structure material layer covering the sidewalls and bottom of the opening and the top of the gate structure includes forming a first sidewall material layer covering the sidewalls and bottom of the opening and the top of the gate structure; forming a second sidewall material layer overlying the first sidewall material layer; the step of removing the sidewall structure material layer from the bottom of the opening and the top of the gate structure includes removing the first sidewall material layer and the second sidewall material layer from the bottom of the opening and the top of the gate structure, leaving the first sidewall material layer covering the sidewall of the opening as a first sidewall, and leaving the second sidewall material layer covering the sidewall of the opening as a second sidewall; In the step of performing gap compensation treatment at the opening bottom corner portion, the compensation layer is filled into a gap surrounded by the bottom surface of the second sidewall, the bottom surface of the protective layer, and the first sidewall, and the compensation layer is further filled into a gap surrounded by the top surface of the second sidewall, the sidewall of the protective layer, and the sidewall of the first sidewall; a cleaning process for the sidewall structure after removing a sidewall structure material layer from the bottom of the opening and the top of the gate structure and before performing a gap compensation process at corner portions of the bottom of the opening, whereby the gap is formed by removing the second sidewall from the bottom.
12. 12. The method for forming a semiconductor structure according to claim 11, further comprising the steps of: forming a channel hole in the opening, the channel hole being located on the substrate and penetrating the gate structure; removing the protective layer; and forming an air gap located between the sidewall structure and a sidewall of the channel hole.
13. 12. The method for forming a semiconductor structure according to claim 11, wherein in the step of performing gap compensation treatment at the bottom corner portion of the opening, the compensation layer also fills the gap surrounded by the top of the sidewall structure and the protective layer.
14. the step of providing a substrate further comprises a top dielectric layer formed on top of the gate structure and a bottom dielectric layer formed between the gate structure and the substrate; forming an opening through the gate structure, the opening further extending through the top dielectric layer and through a portion of the thickness of the bottom dielectric layer; the step of removing the sidewall structure material layer at the bottom of the opening and at the top of the gate structure further comprises removing an excess portion of the thickness of the bottom dielectric layer to expose the top surface of the substrate; In the step of performing gap compensation treatment at the bottom corner portion of the opening, the compensation layer is also filled in a gap surrounded by the bottom dielectric layer and the substrate at the bottom corner portion of the opening.
12. A method for forming a semiconductor structure according to claim 11.
15. before removing the sidewall structural material layer from the bottom of the opening and the top of the gate structure, further forming a protection material layer covering the sidewall structural material layer; the step of removing the sidewall structure material layer from the bottom of the opening and the top of the gate structure further includes removing the protective material layer from the bottom of the opening and the top of the gate structure, and leaving the protective material layer covering the sidewall of the sidewall structure as the protective layer.
12. A method for forming a semiconductor structure according to claim 11.
16. removing the sidewall structure material layer at the bottom of the opening and at the top of the gate structure using a dry etching process; 16. A method for forming a semiconductor structure according to claim 15.
17. performing a gap compensation process at the bottom corner portion of the opening and forming a compensation layer to fill the gap at the bottom of the sidewall structure includes forming a compensation material layer to cover the bottom of the opening, the sidewall structure sidewalls of the opening sidewalls, the top of the gate structure, and the gap filled at the bottom of the sidewall structure; removing the compensation material layer covering the bottom of the opening, the sidewall structure sidewalls of the opening sidewalls, and the top of the gate structure, and leaving the compensation material layer filling the gap at the bottom of the sidewall structure as the compensation layer.
12. A method for forming a semiconductor structure according to claim 11.
18. 20. The method for forming a semiconductor structure of claim 17, further comprising forming a compensation material layer covering the bottom of the opening, the sidewall structure sidewalls of the opening sidewalls, the top of the gate structure, and the gap filled at the bottom of the sidewall structure using an atomic layer deposition process or a low pressure chemical vapor deposition process.
19. 20. The method of claim 17, further comprising removing the compensation material layer covering the bottom of the opening, the sidewall structure sidewalls of the opening sidewalls, and the top of the gate structure using a wet etching process.
20. the etching solution of the wet etching process comprises a phosphoric acid solution; The mass percentage of phosphoric acid in the phosphoric acid solution is 40 wt % to 86 wt %; The process temperature of the wet etching process is 100°C to 160°C.
20. A method for forming a semiconductor structure according to claim 19.
21. In the step of providing a substrate, a source / drain doped layer is further formed in the substrate, and the source / drain doped layer is exposed on a top surface of the substrate; forming an opening through the gate structure, the opening being formed above the source-drain doped layer; In the step of forming a channel hole in the opening, the channel hole being located on the substrate and penetrating the gate structure, the channel hole is formed on the source / drain doped layer and is in contact with the source / drain doped layer.
12. A method for forming a semiconductor structure according to claim 11.
22. In the step of forming a channel hole in the opening, the channel hole is located on the substrate and passes through the gate structure, the channel hole filling the opening; Alternatively, in the step of forming a channel hole located on the substrate and penetrating the gate structure in the opening, a recessed groove is formed on a top side of the channel hole at a part of the height of the channel hole, An insulating layer is formed to fill the groove.
12. A method for forming a semiconductor structure according to claim 11.
Citation Information
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