Module and method for manufacturing the same

Abstract

To provide a module that can reduce manufacturing costs when constructing a module that includes a plurality of chips.SOLUTION: The module includes a plurality of stacked memories. The module includes: a plurality of stacked memories in which memory chips are stacked by bumpless connection; internal through-electrodes that penetrate the a plurality of stacked memories in a stacked direction of; and logic chips that are arranged in a direction intersecting the stacked direction and are stacked on the stacked memories. Dicing regions that have not been diced exist between the plurality of stacked memories that overlap with the logic chips and are adjacent to each other.SELECTED DRAWING: Figure 14

Description

Technical Field

[0001] The present invention relates to a module and a method for manufacturing the same.

Background Art

[0002] Conventionally, volatile memories (RAMs) such as DRAM (Dynamic Random Access Memory) are known as storage devices. There is a demand for DRAM to have a large capacity that can withstand the high performance of arithmetic units (hereinafter referred to as logic chips or logic chips) and the increase in data volume. Therefore, miniaturization of the memory (memory cell array, memory chip) and increase in capacity by planar addition of cells have been attempted. On the other hand, due to vulnerability to noise due to miniaturization and increase in chip area, etc., this type of increase in capacity has reached its limit.

[0003] Therefore, recently, technologies have been developed to realize an increase in capacity by stacking a plurality of planar memories three-dimensionally (3D). In addition, with the increase in data volume, high-speed data communication between chips (logic chips and memory chips) has been attempted (see, for example, Patent Documents 1 and 2).

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0005] The semiconductor module described in Patent Document 1 includes a configuration in which two chips are connected by a bridge. Furthermore, Patent Document 1 includes additional chips, such as stacked memory, connected using an additional wiring structure. In addition, Patent Document 1 includes a configuration in which the entire module is sealed with a molding material while a build-up wiring layer is formed, and bumps for connecting to a package substrate are formed on the surface.

[0006] The semiconductor module described in Patent Document 2 has a configuration in which a logic chip and a memory chip are placed on a carrier substrate and sealed with a molding material. In Patent Document 2, a redistribution layer and through vias are formed on the molding material. Furthermore, in Patent Document 2, an interposer is placed so as to straddle the logic chip and the memory chip. Moreover, in Patent Document 2, a further redistribution layer and bumps are sequentially placed on the interposer.

[0007] In Patent Document 1, the I / O connection structure used for bridge connections and build-up wiring for connecting to bumps tended to be costly. Furthermore, in Patent Document 2, the need to form additional redistribution layers and through vias increased the number of processes and also tended to be costly. When constructing a module containing multiple chips, it is preferable to reduce manufacturing costs.

[0008] This invention has been made in view of the above-mentioned problems, and aims to provide a module and a method for manufacturing the same that can reduce manufacturing costs when constructing a module including multiple chips. [Means for solving the problem]

[0009] The present invention relates to a module manufacturing method for a predetermined number of stacked memories, comprising: a stacked wafer forming step of forming a stacked wafer by stacking a plurality of memory wafers in a bumpless manner; a fragmentation step of fragmenting the stacked wafer into stacked memories; a rearrangement step of rearranging the plurality of stacked memories into a predetermined shape; a molding step of molding the rearranged stacked memories; a wiring forming step of forming external wiring on the stacked memories; and a separation step of separating the molded stacked memories into memory modules containing a predetermined number.

[0010] Furthermore, the module manufacturing method further comprises an external through-electrode forming step, which is performed after the rearrangement step and before the molding step, in which an external through-electrode extending in the direction along the stacking direction of the stacked memory is formed. Preferably, in the rearrangement step, the individualized stacked memory pieces are stacked and rearranged into a predetermined shape, and in the molding step, the rearranged stacked memory pieces and the external through-electrode are molded together.

[0011] Furthermore, it is preferable to rearrange the stacked memory and logic chips into a predetermined shape in the rearrangement step, and to mold the stacked memory and logic chips in the molding step.

[0012] Furthermore, in the rearrangement process, it is preferable to stack the logic chips on a plurality of stacked memories.

[0013] Furthermore, in the rearrangement process, it is preferable to stack the logic chips across multiple stacked memories.

[0014] Furthermore, in the rearrangement process, it is preferable to stack the stacked memory on the logic chip.

[0015] Furthermore, the present invention relates to a module manufacturing method for a predetermined number of stacked memories, comprising: a stacked wafer formation step of forming a stacked wafer by stacking a plurality of memory wafers in a bumpless manner; a rearrangement step of stacking logic chips across a plurality of stacked memories contained in the stacked wafer; and a separation step of separating the stacked wafer on which the logic chips are arranged into memory modules containing a predetermined number of the stacked memories.

[0016] Furthermore, in the rearrangement process, it is preferable to stack the logic chip on a control chip that is exposed on one side of the stacking direction of the stacked wafer and controls the operation of the stacked memory.

[0017] Furthermore, the present invention relates to a module including a predetermined number of stacked memories, comprising: a predetermined number of stacked memories formed by stacking memory chips by bumpless connection; a package portion for packaging the predetermined number of stacked memories; and external wiring arranged on one surface of the stacked memory in the stacking direction.

[0018] Furthermore, the module preferably comprises a logic chip arranged on top of the stacked memory, and the package portion preferably packages the logic chip and the stacked memory.

[0019] Furthermore, the module preferably comprises logic chips arranged in parallel in a direction intersecting the stacking direction of the stacked memory, and the package portion preferably packages the logic chips and a predetermined number of memories.

[0020] Furthermore, the module preferably comprises external through-electrodes extending in the stacking direction of the stacked memory, a plurality of stacked stacked memories are arranged in the stacking direction, the package portion further packages the external through-electrodes, and the external wiring is preferably arranged on one surface of the stacked memory exposed from the package portion.

[0021] Furthermore, the present invention relates to a module including a plurality of stacked memories, the module comprising: a plurality of stacked memories in which memory chips are stacked by bump-less connection; and a logic chip disposed across the stacked memories arranged side by side in a direction intersecting the stacking direction and disposed overlapping the stacked memories.

[0022] Moreover, it is preferable that the stacked memory includes a plurality of the memory chips and a control chip exposed on one surface in the stacking direction, the control chip controlling the operation of the memory chips.

Advantages of the Invention

[0023] According to the present invention, in constructing a module including a plurality of chips, it is possible to provide a module and a method for manufacturing the same capable of reducing manufacturing costs.

Brief Description of the Drawings

[0024] [Figure 1] It is a plan view showing a module according to a first embodiment of the present invention. [Figure 2] It is a cross-sectional view taken along line A-A of FIG. 1. [Figure 3] It is a schematic view showing a process of manufacturing a module of the first embodiment. [Figure 4] It is a plan view showing a stacked wafer used in manufacturing a module of the first embodiment. [Figure 5] It is a schematic plan view showing a process of manufacturing a module of the first embodiment. [Figure 6] It is a schematic cross-sectional view showing a process of manufacturing a module of the first embodiment. [Figure 7] It is a plan view showing a module according to a second embodiment of the present invention. [Figure 8] It is a cross-sectional view showing a module according to a third embodiment of the present invention. [Figure 9] It is a cross-sectional view showing a module according to a fourth embodiment of the present invention. [Figure 10] It is a cross-sectional view showing a module according to a fifth embodiment of the present invention. [Figure 11] This is a cross-sectional view showing a module according to the sixth embodiment of the present invention. [Figure 12] This is a cross-sectional view showing a module according to a seventh embodiment of the present invention. [Figure 13] This is a cross-sectional view showing a module according to the eighth embodiment of the present invention. [Figure 14] This is a cross-sectional view showing a module according to the ninth embodiment of the present invention. [Figure 15] This is a cross-sectional view showing another example of the module of the ninth embodiment. [Figure 16] This is a cross-sectional view showing another example of the module of the ninth embodiment. [Figure 17] This is a schematic diagram showing the relationship between the stacked wafer and the processor when manufacturing the module of the ninth embodiment. [Figure 18] This schematic diagram illustrates another example of the relationship between stacked wafers and processors when manufacturing a modified module. [Figure 19] This schematic diagram shows yet another example of the relationship between stacked wafers and processors when manufacturing a modified module. [Figure 20] This schematic diagram shows yet another example of the relationship between stacked wafers and processors when manufacturing a modified module. [Modes for carrying out the invention]

[0025] Hereinafter, the module 1 and its manufacturing method according to each embodiment of the present invention will be described with reference to Figures 1 to 20. First, we will describe the overview of Module 1 according to each embodiment.

[0026] The module 1 in each embodiment is manufactured using FOWLP (Fan Out Wafer Level Package) technology without using a Si interposer or Si bridge. This allows the module 1 to be manufactured without using a package substrate, thus enabling low-cost manufacturing of the module 1. Furthermore, the module 1 in each embodiment is a multi-chip module 1 (MCM) including multiple stacked memories 11 or logic chips 20. In particular, the module 1 in each embodiment is made by forming memory chips 110, which are individual pieces of stacked memory stacked in a bumpless wafer state, into a module 1 using FOWLP technology. This makes it possible to manufacture a thin MCM with reduced height.

[0027] [First Embodiment] Next, a module 1 according to the first embodiment of the present invention and its manufacturing method will be described with reference to Figures 1 to 6. Module 1 according to the first embodiment includes a predetermined number of stacked memories 11, as shown in Figure 1. Specifically, as shown in Figure 1, the modules 1 are arranged in parallel in a direction intersecting the stacking direction d, and as shown in Figure 2, the stacked memories 11 are arranged on top of each other in the stacking direction d. In this embodiment, module 1 is composed of two sets of stacked memories 11, with two stacked memories 11 arranged on top of each other in the stacking direction d forming one set. Module 1 comprises stacked memories 11, an internal through-electrode 12, an internal redistribution layer 13, an external through-electrode 14, a package portion 15, and external wiring 16.

[0028] The stacked memory 11 is constructed by stacking memory chips 110 using bumpless connections. The stacked memory 11 is constructed by stacking memory chips 110, each having, for example, a Si layer 112 arranged on one side and a wiring layer 111 arranged on the other side, using bumpless connections. Specifically, the stacked memory 11 is constructed by stacking and bumpless connecting multiple memory chips 110, each with its wiring layer facing the other and using bumpless connections. In this embodiment, each stacked memory 11 is constructed by stacking four memory chips 110. Furthermore, the stacked memory 11 is constructed by stacking memory chips 110 that are aligned in size to form a rectangle in plan view in the direction of stacking direction d.

[0029] The internal through-electrode 12 is an electrode that penetrates the stacked memory 11. The internal through-electrode 12 is configured, for example, to penetrate the stacked memory chips 110 from one side of the stacked memory 11 along the stacking direction d. In this embodiment, the internal through-electrode 12 is configured to penetrate the wiring layers 111 of all the memory chips 110 included in one stacked memory 11 from one side of one stacked memory 11. Also, four internal through-electrodes 12 are arranged in cross-section AA of Figure 1.

[0030] The internal redistribution layer 13 is stacked on one side of the stacking direction d of a set of stacked memory 11. The internal redistribution layer 13 is electrically connected to the internal through-electrodes 12 of adjacent stacked memory 11 within the set of stacked memory 11. The internal through-electrodes 12 are configured as a rectangular shape in plan view, with dimensions larger than the rectangular shape of the stacked memory 11 in plan view. In other words, the ends of each side of the internal through-electrodes 12 are positioned to protrude beyond the edges of the stacked memory 11 in a direction intersecting the stacking direction d.

[0031] The external through-electrodes 14 extend in the stacking direction d of the stacked memory 11. The external through-electrodes 14 are, for example, Cu pillars. One end of the external through-electrodes 14 is electrically connected to the internal redistribution layer 13. In this embodiment, the external through-electrodes 14 are arranged in pairs on either side of the stacked memory 11 in the AA cross section.

[0032] The package section 15 packages a predetermined number of stacked memory modules 11. The package section 15 is constructed using a molding material such as resin. As shown in Figures 1 and 2, for example, the package section 15 packages the outer periphery of the stacked memory modules 11, excluding one side in the stacking direction d. The package section 15 also further packages the internal redistribution layer 13 and the external through-electrode 14.

[0033] The external wiring 16 is arranged on one surface of the stacked memory 11 in the stacking direction d. Specifically, the external wiring 16 is arranged on one surface of the stacked memory 11 that is exposed from the package portion 15. The external wiring 16 comprises an external rewiring layer 161 and solder balls 162.

[0034] The external redistribution layer 161 is stacked on one surface of the stacked memory 11 that is exposed from the package portion 15. The external wiring layer 16 is configured in a rectangular shape with dimensions aligned with the internal redistribution layer 13 in a plan view. The external redistribution layer 161 is electrically connected to the internal through-electrode 12 of an adjacent stacked memory 11 within a set of stacked memory 11. The external redistribution layer 161 is also electrically connected to the other end of the external through-electrode 14.

[0035] The solder balls 162 are arranged on the exposed surface of the external redistribution layer 161. The solder balls 162 are electrically connected to the external redistribution layer 161. In this embodiment, multiple solder balls 162 are arranged along the exposed surface of the external redistribution layer 161.

[0036] Next, we will explain the operation of Module 1. Module 1 is electrically connected to other substrates, etc., using solder balls 162. In the stacking direction d, the stacked memory 11 located on the external redistribution side is configured to send and receive data via the internal through-electrode 12, the external redistribution layer 161, and the solder balls 162. Also in the stacking direction d, the stacked memory 11 located on the internal redistribution layer 13 side is configured to send and receive data via the internal through-electrode 12, the internal redistribution layer 13, the external through-electrode 14, the external redistribution layer 161, and the solder balls 162.

[0037] Next, a method for manufacturing module 1 will be described. The method for manufacturing module 1 involves manufacturing a module 1 that includes a predetermined number of stacked memory 11. The method for manufacturing module 1 comprises a stacked wafer formation step, a fragmentation step, a rearrangement step, an external through-electrode formation step, a molding step, an internal redistribution layer formation step, a wiring formation step, and a separation step.

[0038] First, a stacked wafer formation process is carried out to form a stacked wafer by stacking multiple memory wafers 100 in a bumpless manner. In the stacked wafer formation process, as shown in Figure 3, a stacked wafer is formed by bumpless connection of wafers constituting memory chips 110. As a result, the stacked wafer is composed of multiple stacked memories 11, each containing a stack of memory chips 110. Internal through-electrodes 12 are also formed on the stacked memories 11.

[0039] Next, a dicing process is performed. In the dicing process, the stacked wafer is divided into stacked memory 11. In the dicing process, as shown in Figure 4, the stacked memory 11 shown in Figure 3 is formed by dicing the wafer into a rectangular shape in plan view.

[0040] Next, a rearrangement process is performed. In the rearrangement process, multiple stacked memories 11 are rearranged on a carrier substrate 200 into a predetermined shape. Silicon, glass, or the like are used for the carrier substrate 200. Generally, circular or rectangular plate-shaped carrier substrates 200 are used. In the rearrangement process, the individual stacked memories 11 are stacked and rearranged into a predetermined shape. In the rearrangement process, for example, multiple stacked memories 11 are stacked in the stacking direction d to form one set. Then, one set of stacked memories 11 is arranged in a direction intersecting the stacking direction d. In this embodiment, in the rearrangement process, as shown in Figures 1 and 2, two of the four stacked memories 11 are stacked to form one set, and two sets of stacked memories 11 are arranged side by side in a direction intersecting the stacking direction d. In the rearrangement process, multiple sets of stacked memories 11 are arranged in a direction intersecting the stacking direction d in this manner. For example, the plan view when the stacked memory 11 is rearranged on a circular carrier substrate 200 will be the same as in Figure 4. In this case, the memory wafer 100 in Figure 4 becomes the carrier substrate 200, and the area enclosed by the dashed line in Figure 5 is placed in place of the memory chip 110. The stacked memory 11 and the external through-electrode 14 are placed in this area.

[0041] Next, an external through-electrode formation process is carried out. In the external through-electrode formation process, as shown in Figures 5 and 6, an external through-electrode 14 extending in the direction along the stacking direction d of the stacked memory 11 is formed after the rearrangement process and before the molding process. In addition, an external redistribution layer 161 is formed in the external through-electrode formation process. First, in the external through-electrode formation process, an external redistribution layer 161 is formed on the carrier substrate 200 as shown in Figure 6. Then, in the external through-electrode formation process, an external through-electrode 14 is formed on one exposed surface of the external redistribution layer 161. Then, as shown in Figures 5 and 6, one set of stacked memory 11 is placed in the region surrounded by the external through-electrode 14 and the external redistribution layer 161. Note that the external through-electrode formation process and the external redistribution layer formation process may be carried out before the rearrangement process.

[0042] Next, a molding process is carried out. In the molding process, the rearranged stacked memory 11 is molded, as shown in Figure 6. In this embodiment, the external through-electrode 14 and the rearranged stacked memory 11 are molded in the molding process.

[0043] Next, the internal redistribution layer formation process is carried out. In the internal redistribution layer formation process, an internal redistribution layer 13 is formed, which is arranged side by side on one end of the external through electrode 14 and on one surface of the stacked memory 11 in the stacking direction d. In the internal redistribution layer formation process, the external through electrode 14 and one surface of the stacked memory 11 in the stacking direction d are exposed by polishing the molding material from one side in the stacking direction d. Next, the internal redistribution layer 13 is formed. Then, the internal redistribution layer 13 is molded with the molding material.

[0044] Next, a wiring formation process is carried out. In the wiring formation process, external wiring 16 is formed on the stacked memory 11. In the wiring formation process, solder balls 162 are placed on the exposed surface of the external rewiring layer 161.

[0045] Next, a separation process is carried out. In the separation process, the molded stacked memory 11 is separated into memory modules 1 containing a predetermined number of units. In the separation process, the stacked memory 11 is separated into two sets at a time in order to form the modules 1 shown in Figures 1 and 2. This forms the modules 1.

[0046] According to the module 1 and its manufacturing method as described above in the first embodiment, the following effects are achieved. (1) A method for manufacturing a module 1 containing a predetermined number of stacked memories 11, comprising: a stacked wafer forming step of forming a stacked wafer by stacking a plurality of memory wafers 100 in a bumpless manner; a fragmentation step of fragmenting the stacked wafer into stacked memories 11; a rearrangement step of rearranging the plurality of stacked memories 11 into a predetermined shape; a molding step of molding the rearranged stacked memories 11; a wiring forming step of forming external wiring 16 on the stacked memories 11; and a separation step of separating the molded stacked memories 11 into a memory module 1 containing a predetermined number. Furthermore, the module 1 includes a predetermined number of stacked memories 11, comprising a predetermined number of stacked memories 11 formed by stacking memory chips 110 by bumpless connection, a package section 15 for packaging the predetermined number of stacked memories 11, and external wiring 16 arranged on one surface of the stacking direction d of the stacked memories 11. This allows for the inexpensive manufacture of module 1, which includes multiple chips, without the need for a package substrate. The stacked memory 11 is assembled into module 1 using FOWLP technology. This enables the manufacture of a thin MCM with reduced height. In this case, since the stacked memory 11 is stacked without bumps, the thickness in the stacking direction d can be reduced to about 1 / 2 to 1 / 6 of that of a typical stacked memory using bumps, for the same number of stacks. This enables the manufacture of a thin MCM with reduced height that includes a large number of memory chips 110. Furthermore, it is possible to obtain memory chips 110 with the same height (thickness in the stacking direction d) as other stacked memory 11s. This allows for uniform height after rearrangement in the FOWLP process, improving the yield of RDL (redistribution) formation and solder ball 162 placement processes. In addition, since the individual memory chips 110 are stacked and assembled into module 1 using FOWLP technology, a small-area module 1 with a reduced footprint can be formed.

[0047] (2) The manufacturing method of module 1 further comprises an external through-electrode forming step, which is performed after the rearrangement step and before the molding step, in which an external through-electrode 14 extending in a direction along the stacking direction d of the stacked memory 11 is formed; in the rearrangement step, the individual stacked memory 11 pieces are stacked and rearranged into a predetermined shape; and in the molding step, the rearranged stacked memory 11 and the external through-electrode 14 are molded. Furthermore, module 1 further includes external through-electrodes 14 extending in the stacking direction d of the stacked memory 11, multiple stacked memory 11s are arranged in the stacking direction d, package portion 15 further packages the external through-electrodes 14, and external wiring 16 is arranged on one surface of the stacked memory 11 exposed from the package portion 15. This allows for easy transmission of power and signals even in stacked stacked memory 11, thereby improving the flexibility of placement.

[0048] [Second Embodiment] Next, a module 1 and its manufacturing method according to a second embodiment of the present invention will be described with reference to Figure 7. In the second embodiment, the same reference numerals are used for the same components, and the description is simplified or omitted. The module 1 according to the second embodiment differs from the first embodiment in that, as shown in Figure 7, it further comprises logic chips 20 arranged in parallel in a direction intersecting the stacking direction d of the stacked memory 11. Furthermore, the module 1 according to the second embodiment differs from the first embodiment in that the package portion 15 packages the logic chips 20 and a predetermined number of memories. In the module 1 according to the second embodiment, the stacked memory 11 and logic chips 20 are rearranged into a predetermined shape during the rearrangement process. The stacked memory 11 and logic chips 20 are molded during the molding process. Finally, in the separation process, the molded stacked memory 11 and logic chips 20 are separated into memory modules 1 containing a predetermined number of each.

[0049] According to the module 1 and its manufacturing method as described above in the second embodiment, the following effects are achieved.

[0050] (3) In the rearrangement step, the stacked memory 11 and logic chip 20 are rearranged into a predetermined shape; in the molding step, the stacked memory 11 and logic chip 20 are molded; and in the separation step, the molded stacked memory 11 and logic chip 20 are separated into memory modules 1 containing a predetermined number of each. Furthermore, module 1 further comprises logic chips 20 arranged in parallel in a direction intersecting the stacking direction d of the stacked memory 11, and package 15 packages the logic chips 20 and a predetermined number of memories. This also reduces the manufacturing cost of module 1, which includes the logic chip 20.

[0051] [Third Embodiment] Next, module 1 according to the third embodiment of the present invention will be described with reference to Figure 8. In the third embodiment, the same reference numerals are used for the same components, and the description is simplified or omitted. The module 1 according to the third embodiment differs from the first embodiment in that it further comprises a logic chip 20 arranged on top of the stacked memory 11. The module 1 according to the third embodiment differs from the first embodiment in that the package portion 15 packages the logic chip 20 and the stacked memory 11.

[0052] An external redistribution layer 161 is formed on one side of the logic chip 20. The stacked memory 11 is placed on top of the logic chip 20 on the other side. The internal redistribution layer 13 and the external redistribution layer 161 are configured as a rectangular shape in plan view, which is larger than the outer dimensions of the rectangular logic chip 20.

[0053] According to the module 1 and its manufacturing method as described above in the third embodiment, the following effects are achieved.

[0054] (4) In the rearrangement process, logic chips 20 are stacked on multiple stacked memory 11. Module 1 further comprises a logic chip 20 that is stacked on top of the stacked memory 11, and the package 15 packages the logic chip 20 and the stacked memory 11. This makes it possible to reduce the size of Module 1 in a plan view compared to when the logic chip 20 is placed side by side with the stacked memory 11 in a direction intersecting the stacking direction d of the stacked memory 11.

[0055] [Fourth Embodiment] Next, module 1 according to the fourth embodiment of the present invention will be described with reference to Figure 9. In the fourth embodiment, the same reference numerals are used for the same components, and the description is simplified or omitted. The module 1 according to the fourth embodiment differs from the first embodiment in that the internal redistribution layer 13 is positioned between the stacked stacked memories 11. The manufacturing method of the module 1 according to the fourth embodiment differs from the first embodiment in that a rearrangement step is performed after the internal redistribution layer formation step in which the stacked memories 11 are stacked in the stacking direction d. Furthermore, the manufacturing method of the module 1 according to the fourth embodiment differs from the first embodiment in that molding is performed after the stacked memories 11 are stacked.

[0056] According to the module 1 and its manufacturing method as described above in the fourth embodiment, the height of the internal rewiring layer 13 can be reduced and the length of the external through-electrode 14 can be shortened, making it easy to manufacture.

[0057] [Fifth Embodiment] Next, a module 1 and its manufacturing method according to a fifth embodiment of the present invention will be described with reference to Figure 10. In the fifth embodiment, the same reference numerals are used for the same components, and their descriptions are simplified or omitted. The module 1 according to the fifth embodiment differs from the first embodiment in that the stacked memory 11 is further stacked. Furthermore, the manufacturing method of the module 1 according to the fifth embodiment differs from the first embodiment in that a rearrangement step is performed after the internal redistribution layer formation step in which the stacked memory 11 is stacked in the stacking direction d. And, the manufacturing method of the module 1 according to the fifth embodiment differs from the fifth embodiment in that molding is performed after the stacked memory 11 is stacked.

[0058] According to the module 1 and its manufacturing method as described above in the fifth embodiment, a module 1 with a larger capacity can be realized.

[0059] [Sixth Embodiment] Next, a module 1 and its manufacturing method according to a sixth embodiment of the present invention will be described with reference to Figure 11. In the sixth embodiment, the same reference numerals are used for the same components, and their descriptions are simplified or omitted. The module 1 according to the sixth embodiment differs from the first and third embodiments in that it comprises a plurality of internal redistribution layers 13 sandwiched between the stacked memory 11. It also differs from the first and third embodiments in that it comprises a plurality of external through electrodes 14 in the direction along the stacking direction d. The manufacturing method of the module 1 according to the sixth embodiment differs from the first and third embodiments in that, after the internal redistribution layer formation step, a rearrangement step is performed in which the stacked memory 11 is stacked in the stacking direction d. Furthermore, the manufacturing method of the module 1 according to the sixth embodiment differs from the first and third embodiments in that molding is performed after the stacked memory 11 is stacked. The manufacturing method of the module 1 according to the sixth embodiment differs from the first and third embodiments in that these steps are repeated.

[0060] According to the module 1 and its manufacturing method as described above in the sixth embodiment, a large-capacity module 1 can be manufactured by repeating the process, making it easier to manufacture a large-capacity module 1.

[0061] [Seventh Embodiment] Next, a module 1 and its manufacturing method according to the seventh embodiment of the present invention will be described with reference to Figure 12. In the seventh embodiment, the same reference numerals are used for the same components, and their descriptions are simplified or omitted. Module 1 according to the seventh embodiment differs from the third embodiment in that the stacked memory 11 is further stacked on top of Module 1 according to the third embodiment. Furthermore, Module 1 according to the seventh embodiment differs from the second embodiment in that, instead of the configuration of Module 1 according to the second embodiment, the stacked memory 11 is stacked on top of the logic chip 20 and molded.

[0062] According to the module 1 and its manufacturing method as described in the seventh embodiment, a module 1 with a larger capacity can be easily manufactured. Furthermore, the manufacturing cost of the module 1 can be reduced.

[0063] [Eighth Embodiment] Next, a module 1 and its manufacturing method according to the eighth embodiment of the present invention will be described with reference to Figure 13. In the eighth embodiment, the same reference numerals are used for the same components, and the description is simplified or omitted. The module 1 of the eighth embodiment differs from the first to seventh embodiments in that multiple logic chips 20 are arranged on top of the stacked memory 11, which is arranged in parallel in a direction intersecting the stacking direction d, and the logic chips 20 are arranged across the stacked memory 11. The module 1 of the eighth embodiment also differs from the first to seventh embodiments in that the stacked memory 11 comprises multiple memory chips 110 and a control chip 30 exposed on one surface in the stacking direction d, which controls the operation of the memory chips 110. Furthermore, the manufacturing method of the module 1 of the eighth embodiment differs from the first to seventh embodiments in that, in the rearrangement step, the logic chips 20 are stacked on the control chip 30 exposed on one surface in the stacking direction d of the stacked wafer, which controls the operation of the stacked memory 11. Moreover, the manufacturing method of the module 1 according to the eighth embodiment differs from the first to seventh embodiments in that, before separating the molded stacked memory 11, the logic chips 20 are arranged by the rearrangement step, and then separated including a predetermined number of logic chips 20.

[0064] The control chip 30 is positioned adjacent to the internal redistribution layer 13 in the stacking direction d of the stacked memory 11. The control chip 30 includes, for example, a memory controller, a memory interface, an arbitration circuit, a router, and a switch. In the eighth embodiment, the bidirectional arrows on the connection surface between the control chip 30 and the logic chip 20 indicate the communication path between the control chip 30 and the logic chip 20. Non-contact communication methods such as magnetic field communication or capacitive coupling communication may be used as the communication method. Alternatively, a hybrid connection or a connection using microbumps may be used. In this case, the internal redistribution layer 13 does not need to be provided. Furthermore, the lower surface of the package portion 15 surrounding the side of the stacked memory 11 (chip) opposite to the side on which the control chip 30 is positioned may be provided with external wiring 16 consisting of an external redistribution layer 161 (not shown) and solder balls 162, along the stacking direction d.

[0065] According to the module 1 and its manufacturing method as described above in the eighth embodiment, good stacked memory 11 can be sorted and then rearranged to stack the logic chips 20, thereby improving yield. Furthermore, since any number of logic chips 20 can be included and separated, MCMs can be manufactured in a scalable manner.

[0066] [Ninth Embodiment] Next, a module 1 and its manufacturing method according to the ninth embodiment of the present invention will be described with reference to Figures 14 to 17. In the ninth embodiment, the same reference numerals are used for the same components, and their descriptions are simplified or omitted. Module 1 of the ninth embodiment differs from the first to eighth embodiments in that, as shown in Figures 14 to 17, the logic chip 20 is placed on the stacked wafer across the stacked memory 11 and then separated. The manufacturing method of Module 1 of the ninth embodiment differs from the first to eighth embodiments in that it does not include a piece formation process and a molding process. In this embodiment, three examples of Module 1 are shown. The first Module 1 is a configuration in which two processors are stacked on six stacked memory 11 (cross-sectional example 1), as shown in Figures 14 and 17. The second Module 1 is a configuration in which two large logic chips 20 are stacked on six stacked memory 11 (cross-sectional example 2), as shown in Figures 15 and 17. The third Module 1 is a configuration in which three logic chips 20 are stacked on four stacked memory 11 (cross-sectional example 3), as shown in Figures 16 and 17. Furthermore, Module 1 of the ninth embodiment includes a control chip and an internal redistribution layer 13 on one exposed surface of the stacked wafer. Alternatively, instead of a stacked wafer, as in the eighth embodiment (Figure 13), a stacked chip 11 and external through-electrode 14 may be rearranged and molded on a carrier substrate 200 to form an internal redistribution layer 13. In the ninth embodiment, the bidirectional arrows on the connection surface between the control chip 30 and the logic chip 20 indicate the communication path between the control chip 30 and the logic chip 20. Non-contact communication methods such as magnetic field communication or capacitive coupling communication may be used as the communication method. Alternatively, hybrid connections or connections using microbumps may also be used. In this case, the internal redistribution layer 13 does not need to be provided. Furthermore, on the lower surface of the stacked memory chip 11 along the stacking direction d opposite to the surface on which the control chip 30 is arranged, an external wiring 16 consisting of an external redistribution layer 161 (not shown) and solder balls 162 may be provided.

[0067] According to the module 1 and its manufacturing method as described above in the ninth embodiment, the following effects are achieved. (5) A module 1 including a plurality of stacked memories 11, comprising a plurality of stacked memories 11 formed by stacking memory chips 110 by bumpless connection, and a logic chip 20 arranged on top of the stacked memories 11, straddling the stacked memories 11 which are arranged in parallel in a direction intersecting the stacking direction d. A method for manufacturing a module 1 containing a predetermined number of stacked memories 11, comprising: a stacked wafer formation step of forming a stacked wafer by stacking a plurality of memory wafers 100 in a bumpless manner; a rearrangement step of stacking logic chips 20 across a plurality of stacked memories 11 contained in the stacked wafer; and a separation step of separating the stacked wafer on which the logic chips 20 are arranged into a memory module 1 containing a predetermined number of stacked memories 11. This allows for easier alignment and cost reduction compared to individually placing and connecting individual chips, as logic chips 20 are placed on stacked wafers laminated using a bumpless method, or on wafers or panels formed by separating and rearranging these wafers, before being separated again to form module 1. Furthermore, because logic chips 20 are placed on stacked wafers laminated using a bumpless method, or on wafers formed by separating and rearranging these wafers, the flexibility and density of logic placement can be increased. In addition, logic can be placed across multiple memories, allowing for scalable configuration of the number of logic and memories.

[0068] Although preferred embodiments of the module and its manufacturing method have been described above, the present invention is not limited to the embodiments described above and can be modified as appropriate.

[0069] For example, in the ninth embodiment, as shown in Figure 18, the size of the logic chip 20 can be changed as appropriate. Alternatively, one logic chip 20 may be arranged across multiple stacked memories 11. Alternatively, in module 1, instead of arranging multiple logic chips 20, one logic chip 20 may be arranged across multiple stacked memories 11.

[0070] Furthermore, in the ninth embodiment, as shown in Figures 19 and 20, the separation positions on the stacked wafer may be freely changed according to the number of memories required for module 1 and the shape of the logic chip 20. Also, the connection terminals of the logic chip 20 may be designed to match the position of the connection terminals of the stacked memory 11 and the shape of the logic chip 20. In Figures 17 to 20, the rectangular areas shown on the connection surface between the control chip 30 and the logic chip 20 indicate the electrical connection terminals between the control chip 30 and the logic chip 20.

[0071] Furthermore, in the eighth and ninth embodiments, the entire structure may be molded after the logic chip 20 is placed, and then separated as module 1.

[0072] Furthermore, in the above-described first and second embodiments, when the stacked memory 11 or logic chip 20 are arranged side by side in a direction intersecting the stacking direction d, the stacked memory 11 or logic chip 20 do not need to be stacked. In this case, the external through-electrode 14 does not need to be formed on the module 1.

[0073] Furthermore, for the electrodes that transmit signals among the internal through-electrodes 12 of the stacked memory 11, non-contact communication methods such as magnetic field communication or capacitive coupling communication may be used. Alternatively, the internal through-electrodes 12 may be hybridly connected to electrodes that penetrate each memory chip at the connection surface. These are examples of electrical connection methods in bumpless connections. [Explanation of symbols]

[0074] 1 module 11 Stacked Memory 12 Internal through electrode 13 Internal redistribution layer 14 External through electrode 15. Packaging section 16 External wiring 20 logic chips 30 control chips 100 memory wafers 200 carrier substrates d Stacking direction

Claims

1. A module including multiple stacked memories, Multiple stacked memory chips are stacked using bumpless connections, Multiple stacked memory modules are connected by internal through-electrodes that penetrate in the stacking direction, An external through-electrode extending in the stacking direction of the stacked memory, with one end electrically connected to an internal redistribution layer on the upper surface of the stacked memory in the stacking direction, and the other end electrically connected to an external redistribution layer on the lower surface of the stacked memory in the stacking direction, A logic chip is arranged across the stacked memory, which is arranged in parallel in a direction intersecting the stacking direction, and is superimposed on the stacked memory. Includes, Among the multiple stacked memories that overlap with the logic chip, there are diced regions between adjacent stacked memories that have not been diced. Module.

2. The module according to claim 1, wherein the stacked memory comprises a plurality of memory chips and a control chip exposed on one surface in the stacking direction, which controls the operation of the memory chips.

3. The module according to claim 2, wherein the control chip includes at least one of a memory controller, a memory interface, an arbitration circuit, a router, and a switch.

4. The module according to claim 2 or 3, wherein the control chip and the logic chip communicate using contactless communication means, hybrid connection, or microbump connection.

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