Semiconductor equipment

Abstract

To provide a technique for suppressing self turn-on.SOLUTION: A semiconductor layer of a semiconductor device has a first conductive type drift region, a second conductive type base region which is provided on the drift region and comes in contact with the side face of a trench gate part, a first conductive type source region which is provided the base region and is arranged at a position exposed to the upper surface of the semiconductor layer, a second conductive type contact region which comes in contact with the base region, is arranged at the position exposed to the upper surface of the semiconductor layer, and has higher concentration of second conductive type impurity than that of the base region, and a first conductive type separation region which is provided in the base region, is separated from the drift region and the source region by the base region, and comes in contact with the side face of the trench gate part. The separation region is arranged in at least a part of a range where the source region exists in plan view.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The technology disclosed herein relates to semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses an example of a semiconductor device of a type called a MOSFET, which has a trench gate. Such a semiconductor device has a built-in diode. When a forward bias is applied to the built-in diode of the semiconductor device, electrons are injected from the n-type drain region into the n-type drift region, and holes are injected from the p-type base region into the drift region. When the voltage applied to the built-in diode changes from a forward bias to a reverse bias, the electrons and holes injected into the drift region under the forward bias move in the opposite direction to that under the forward bias. This reverse flow of electrons and holes is called a recovery current. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2014-236189 [Overview of the project] [Problems that the invention aims to solve]

[0004] During the recovery operation of this built-in diode, holes injected into the drift region are discharged to the source electrode via the base region. When the potential of the base region rises due to the resulting hole current, the gate threshold voltage decreases due to the back-gate effect, causing self-turn-on. As a result, the recovery current increases, and recovery losses increase. This specification provides a technique for suppressing self-turn-on. [Means for solving the problem]

[0005] One embodiment of a semiconductor device disclosed herein may include a semiconductor layer, a first main electrode coated on the lower surface of the semiconductor layer, a second main electrode coated on the upper surface of the semiconductor layer, and a trench gate portion provided in the upper part of the semiconductor layer. The semiconductor layer may have a drift region of a first conductivity type, a base region of a second conductivity type provided on the drift region and in contact with the side surface of the trench gate portion, a source region of a first conductivity type provided on the base region and positioned to be exposed on the upper surface of the semiconductor layer and electrically connected to the second main electrode, a contact region of a second conductivity type in contact with the base region and positioned to be exposed on the upper surface of the semiconductor layer and electrically connected to the second main electrode, with a higher concentration of second conductivity type impurities than the base region, and a separation region of a first conductivity type provided within the base region, separated from the drift region and the source region by the base region, and in contact with the side surface of the trench gate portion. The isolation region, when viewed from above, is located in at least a portion of the area where the source region exists, but is not located in at least a portion of the area where the contact region exists. In this semiconductor device, when reverse bias is applied, carriers flowing from the drift region to the base region are blocked from moving by the isolation region, so they move around the isolation region and are discharged from the contact region to the second main electrode. As a result, in the portion of the base region located between the isolation region and the source region, the movement of the carriers is suppressed, and the back gate effect in that portion is suppressed. As a result, in the semiconductor device of this embodiment, the decrease in the gate threshold voltage due to the back gate effect is suppressed, and the occurrence of self-turn-on is also suppressed.

[0006] The separation region may be arranged to include the entire area where the source region exists when viewed from above. This semiconductor device more effectively suppresses the occurrence of self-turn-on.

[0007] The base region may include a lower base region portion located below the separation region, an upper base region portion located above the separation region, and a connecting base region portion that is in contact with the lower surface of the contact region and extends deeper than the lower base region portion from the lower surface of the contact region. In this case, the separation region may be in contact with the connecting base region portion. The carrier moving around the separation region is smoothly discharged from the contact region to the second main electrode via the connecting base region portion.

[0008] The semiconductor layer may be silicon carbide. When the semiconductor layer is silicon carbide, the resistance of the base region becomes particularly high at low temperatures. For this reason, in conventional structures that do not have the isolation region, the potential fluctuation is large when the carriers move within the base region, making self-turn-on due to the back-gate effect a problem. The technology disclosed herein can suppress such self-turn-on, and is therefore particularly useful when the semiconductor layer is silicon carbide. [Brief explanation of the drawing]

[0009] [Figure 1] A schematic cross-sectional view of the main parts of the semiconductor device of this embodiment is shown. [Figure 2] A schematic cross-sectional view of the main part of the semiconductor device of the comparative example is shown. [Figure 3] A schematic cross-sectional view of the main parts of a modified semiconductor device is shown. [Modes for carrying out the invention]

[0010] The semiconductor device 1, which is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) with a built-in diode, will be described below with reference to Figure 1. The semiconductor device 1 is used, for example, in an inverter device that supplies AC power to an AC motor, and the built-in diode operates as a freewheeling diode.

[0011] As shown in FIG. 1, the semiconductor device 1 includes a semiconductor layer 10, a drain electrode 22 covering the lower surface of the semiconductor layer 10, a source electrode 24 covering the upper surface of the semiconductor layer 10, and a trench gate portion 30 provided in the upper layer portion of the semiconductor layer 10. The drain electrode 22 is an example of the first main electrode, and the source electrode 24 is an example of the second main electrode. Here, the thickness direction of the semiconductor layer 10 is the z direction, the direction orthogonal to the thickness direction and the repeating direction of the unit cell is the x direction (hereinafter referred to as the lateral direction of the semiconductor layer 10), and the direction orthogonal to both the z-axis direction and the x direction is the y direction.

[0012] The semiconductor layer 10 is not particularly limited, and may be, for example, silicon carbide (SiC). The semiconductor layer 10 has an n-type drain region 11, an n-type drift region 12, a p-type base region 13, an n-type isolation region 14, an n-type source region 15, and a p-type contact region 16.

[0013] The drain region 11 is disposed at a position exposed on the lower surface of the semiconductor layer 10 and makes an ohmic contact with the drain electrode 22. The drain region 11 is, for example, a silicon carbide substrate having a plane orientation of (0001).

[0014] The drift region 12 is disposed between the drain region 11 and the base region 13 and is in contact with both the drain region 11 and the base region 13. The drift region 12 is separated from the drain electrode 22 by the drain region 11 and is separated from the source electrode 24 by the base region 13. The drift region 12 is in contact with the bottom surface and the lower end portion of the side surface of the trench gate portion 30. The drift region 12 has a lower concentration of n-type impurities than the drain region 11.

[0015] The base region 13 is provided in contact with the upper surface of the drift region 12. The base region 13 is positioned between the drift region 12 and the source region 15, separating the drift region 12 and the source region 15. The base region 13 includes a lower base region portion 13a located between the drift region 12 and the isolation region 14, and an upper base region portion 13b located between the isolation region 14 and the source region 15. These lower base region portion 13a and upper base region portion 13b are in contact with the side surface of the trench gate portion 30, and channels are formed in these portions. In the semiconductor device 1, the amount of current flowing through the channels is controlled according to the gate voltage applied to the trench gate portion 30.

[0016] The isolation region 14 is located within the base region 13, separated from the drift region 12 by the lower base region portion 13a, and separated from the source region 15 by the upper base region portion 13b. The isolation region 14 is formed at a predetermined depth in the semiconductor layer 10 and extends from the side surface of the trench gate portion 30 in a direction perpendicular to the side surface of the trench gate portion 30 (the lateral direction (x direction) of the semiconductor layer 10). The isolation region 14 is not formed in part between adjacent trench gate portions 30; that is, it is not formed continuously between adjacent trench gate portions 30.

[0017] The isolation region 14 has one end in contact with the side surface of the trench gate portion 30. When viewed from above, the isolation region 14 is located in at least a portion of the area where the source region 15 exists. In this example, the isolation region 14 is located so as to include the entire area where the source region 15 exists when viewed from above. Also, the isolation region 14 is not located in at least a portion of the area where the contact region 16 exists when viewed from above.

[0018] The source region 15 is provided in contact with the upper surface of the base region 13 and is positioned to be exposed on the upper surface of the semiconductor layer 10, and is in ohmic contact with the source electrode 24. The source region 15 is in contact with the upper end of the side surface of the trench gate portion 30.

[0019] The contact region 16 is in contact with the upper surface of the base region 13 and is positioned to be exposed on the upper surface of the semiconductor layer 10, making ohmic contact with the source electrode 24. The concentration of p-type impurities in the contact region 16 is higher than the concentration of p-type impurities in the base region 13.

[0020] The trench gate portion 30 has a gate electrode 32 and a gate insulating film 34 provided in a trench that extends from the upper surface of the semiconductor layer 10 to the drift region 12. The gate electrode 32 is formed by filling the trench, which is coated with the gate insulating film 34.

[0021] The semiconductor device 1 incorporates a diode with a drain region 11 as the anode region and a base region 13 as the cathode region. When a forward bias is applied between the drain electrode 22 and the source electrode 24 such that the source electrode 24 is at a higher potential than the drain electrode 22, electrons are injected from the drain region 11 into the drift region 12, and holes are injected from the base region 13 into the drift region 12, causing a current to flow from the source electrode 24 to the drain electrode 22. In this way, the built-in diode of the semiconductor device 1 can operate as a freewheeling diode. When a reverse bias is applied between the drain electrode 22 and the source electrode 24 such that the source electrode 24 is at a lower potential than the drain electrode 22, the electrons and holes injected into the drift region 12 under the forward bias move in the opposite direction to those under the forward bias. This reverse flow of electrons and holes is called a recovery current.

[0022] Figure 2 shows the comparative semiconductor device 100, and the hole current (I) of the recovery current. h This shows the flow of the process. Note that components common to semiconductor device 1 in Figure 1 are denoted by adding "100" to their symbols.

[0023] Hole current I h This is the current when holes injected into the drift region 112 are discharged from the contact region 116 to the source electrode 124 via the base region 113. The resistance of the base region 113 is R. bThen, as shown in the following formula, the potential V of the base region 113 increases due to the hole current I h Here, b increases.

Equation

[0024] Here, q: elementary charge of electron ε: dielectric constant of semiconductor N a : concentration of p-type impurity in base region 113 Ψ b : Fermi potential C ox : capacitance of gate insulating film 134 Then, the gate threshold voltage V th can be expressed by the following formula.

Equation

[0025] Obviously from the above formula, when the potential V of the base region 113 b increases, the gate threshold voltage V th decreases. Such a decrease in the gate threshold voltage is called the back-gate effect. In the semiconductor device 100 of the comparative example, the gate threshold voltage decreases due to the back-gate effect, resulting in self-turn-on. As a result, the recovery current increases and the recovery loss increases.

[0026] On the other hand, in the semiconductor device 1 shown in FIG. 1, the movement of the hole current I h is blocked by the separation region 14. The hole current I h moves around the separation region 14 and is discharged from the contact region 16 to the source electrode 24. Therefore, in the upper base region portion 13b, the movement of the hole current I h is suppressed, so the increase in the potential of that portion is suppressed. As a result, in the semiconductor device 1, in the portion corresponding to the upper base region portion 13b, the gate threshold voltage V due to the back-gate effect thSince the decrease is suppressed, the occurrence of self-turn-on is also suppressed.

[0027] Here, μ h : Hole mobility p b :Concentration of p-type impurities in the lower base region portion 13a W b : Length in the depth direction (y direction) of the lower base region portion 13a d b : Film thickness in the thickness direction (z direction) of the lower base region portion 13a N n :Concentration of n-type impurities in separation region 14 d n : Film thickness in the thickness direction (z direction) of the separation region 14 L b : The length of the separation region 14 from the side of the trench gate section 30 in the lateral direction (x direction) n i : True carrier density Therefore, the resistor R in the lower base region 13a b and the resistor R of the isolation region 14 n Each of these can be expressed by the following formulas.

number

number

[0028] In the semiconductor device 1, the resistor R of the lower base region portion 13a b The resistor R in the isolated region 14 n If it is smaller than, the hole current I h It moves to bypass the separation region 14, and the hole current I h The flow of the fluid through the upper base region 13b is suppressed. As a result, the occurrence of self-turn-on due to the back gate effect is more effectively suppressed. In the semiconductor device 1, the lower base region 13a and the separation region 14 are formed to satisfy the above formula.

[0029] In semiconductor device 1, the semiconductor layer 10 is silicon carbide. In silicon carbide, the hole mobility decreases significantly, especially at low temperatures. Therefore, in the case of the comparative example semiconductor device 100 shown in Figure 2, the resistance of the base region 113 increases, and the hole current I h When the current flows through the base region 113, the potential fluctuation is large, and self-turn-on due to the back-gate effect is likely to become a problem. The semiconductor device 1 of this embodiment can suppress such self-turn-on even when the semiconductor layer 10 is silicon carbide. The technology disclosed herein is particularly useful when the semiconductor layer 10 is silicon carbide.

[0030] Figure 3 shows a modified semiconductor device 2. In this semiconductor device 2, the base region 13 further has a connecting base region 13c. The connecting base region 13c is in contact with the lower surface of the contact region 16 and extends deeper than the lower base region portion 13a from the lower surface of the contact region 16. In this example, the connecting base region 13c is further formed deeper than the trench gate portion 30. The concentration of p-type impurities in the connecting base region 13c may be higher than the concentration of p-type impurities in the lower base region portion 13a and the upper base region portion 13b. When such a connecting base region 13c is provided, the electric field at the bottom surface of the trench gate portion 30 can be mitigated when the semiconductor device 2 is turned off.

[0031] In semiconductor device 2, the isolation region 14 is in contact with the connection base region 13c. In semiconductor device 2, when reverse bias is applied, the hole current I flows around the isolation region 14. h The excess material is smoothly discharged from the contact area 16 to the source electrode 24 via the connection base area 13c. This more effectively suppresses the occurrence of self-turn-on.

[0032] Although specific examples of the present invention have been described in detail above, these are merely illustrative and do not limit the scope of the claims. The technologies described in the claims include various modifications and changes to the specific examples illustrated above. Furthermore, the technical elements described in this specification or drawings exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technologies illustrated in this specification or drawings can achieve multiple objectives simultaneously, and achieving even one of these objectives itself constitutes technical usefulness. [Explanation of symbols]

[0033] 1: Semiconductor device, 10: Semiconductor layer, 11: Drain region, 12: Drift region, 13: Base region, 13a: Lower base region portion, 13b: Upper base region portion, 13c: Connecting base region, 14: Isolation region, 15: Source region, 16: Contact region, 22: Drain electrode, 24: Source electrode, 30: Trench gate portion, 32: Gate electrode, 34: Gate insulating film

Claims

1. Semiconductor layer, The first main electrode is coated on the lower surface of the semiconductor layer, A second main electrode is coated on the upper surface of the semiconductor layer, It comprises a trench gate portion provided in the upper part of the semiconductor layer, The aforementioned semiconductor layer is The drift region of the first conductivity type, A second conductive base region is provided on the drift region and is in contact with the side surface of the trench gate portion, A first conductivity type source region is provided on the base region, positioned to be exposed on the upper surface of the semiconductor layer, and electrically connected to the second main electrode, A contact region of second conductivity type is located in contact with the base region, is positioned to be exposed on the upper surface of the semiconductor layer, is electrically connected to the second main electrode, and has a higher concentration of second conductivity type impurities than the base region. It has a first conductivity type isolation region provided within the base region, separated from the drift region and the source region by the base region, and in contact with the side surface of the trench gate portion, The separation region, when viewed from above, is located in at least a portion of the area where the source region exists, and is not located in at least a portion of the area where the contact region exists. The aforementioned base region is A lower base region portion located below the aforementioned separation region, An upper base region portion located above the aforementioned separation region, It includes a connecting base region portion that is in contact with the lower surface of the contact region and extends deeper than the lower base region portion from the lower surface of the contact region, The separation region is in contact with the connection base region portion of the semiconductor device.

2. The semiconductor device according to claim 1, wherein the separation region is arranged to include the entire range in which the source region exists when viewed from above.

3. The semiconductor device according to claim 1 or 2, wherein the semiconductor layer is silicon carbide.

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