Semiconductor equipment

Abstract

The purpose of the present invention is to provide a semiconductor device capable of improving heat dissipation and reliability. A gate signal joint member (4) and a main current joint member (5) are separate bodies. The gate signal joint member (4) is disposed on the entire surface of a first gate signal electrode (2) on a first gate signal circuit pattern (6) side. The main current joint member (5) is disposed on the entire surface of a first main current electrode (3) on a first main current circuit pattern (7) side. The joint area between the gate signal joint member (4) and the first gate signal electrode (2) is smaller than the joint area between the main current joint member (5) and the first main current electrode (3). The gate signal joint member (4) is formed in a rectangular shape in a top view. The lengths a and b of two adjacent sides of the rectangular shape of the gate signal joint member (4) are both twice or more the thickness c of the gate signal joint member (4).

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device.

Background Art

[0002] Conventionally, a semiconductor device capable of suppressing poor bonding between a semiconductor element and a wiring layer and a decrease in cooling efficiency for the semiconductor element has been proposed.

[0003] As such a semiconductor device, for example, Patent Document 1 discloses a power module including a semiconductor element having an emitter electrode and a gate electrode formed on the back surface, a columnar first electrode terminal having one end connected to the emitter electrode, a columnar second electrode terminal having one end connected to the gate electrode, and a circuit board having a wiring layer joined to the other ends of the first electrode terminal and the second electrode terminal.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, in the technique described in Patent Document 1, the first electrode terminal and the second electrode terminal that contribute to cooling only contact a part of the emitter electrode and the gate electrode of the semiconductor element, respectively, so these contact areas are small. Therefore, heat diffusion to the semiconductor element becomes insufficient, and there is a risk of reduced heat dissipation.

[0006] In addition, the materials of the first electrode terminal and the second electrode terminal are selected as copper or a copper alloy from the viewpoint of heat conduction, but since copper and copper alloys have high rigidity, there is a concern that they may damage the semiconductor element during a reliability test. Therefore, there is a risk of reduced reliability of the semiconductor device.

[0007] Therefore, the present disclosure aims to provide a semiconductor device capable of improving heat dissipation and reliability. [Means for solving the problem]

[0008] The semiconductor device according to this disclosure comprises an insulating material, an insulating substrate having a first gate signal circuit pattern and a first main current circuit pattern formed on the surface of the insulating material, and a back surface circuit pattern formed on the back surface of the insulating material, a semiconductor element having a first gate signal electrode and a first main current electrode formed on the back surface and mounted on the insulating substrate, a gate signal bonding material disposed between the first gate signal electrode and the first gate signal circuit pattern and joining the two, and a main current bonding material disposed between the first main current electrode and the first main current circuit pattern and joining the two, and the gate signal bonding material and The main current bonding material is a separate component, the gate signal bonding material is arranged across the entire surface of the first gate signal electrode on the side with the first gate signal circuit pattern, the main current bonding material is arranged across the entire surface of the first main current electrode on the side with the first main current circuit pattern, the bonding area between the gate signal bonding material and the first gate signal electrode is smaller than the bonding area between the main current bonding material and the first main current electrode, the gate signal bonding material is formed in a rectangular shape when viewed from above, and the lengths of two adjacent sides of the rectangular shape of the gate signal bonding material are both at least twice the thickness of the gate signal bonding material. The semiconductor element further has a second gate signal electrode and a second main current electrode formed on its surface, the insulating substrate further has a second gate signal circuit pattern and a second main current circuit pattern formed on the surface of the insulating material, and further comprises signal wiring connecting the second gate signal electrode and the second gate signal circuit pattern, and main current wiring connecting the second main current electrode and the second main current circuit pattern, the connection point between the signal wiring and the second gate signal electrode is located on the first main current circuit pattern, and the connection point between the main current wiring and the second main current electrode is located on the first gate signal circuit pattern. ru. [Effects of the Invention]

[0009] According to this disclosure, the gate signal bonding material is arranged across the entire surface on the side of the first gate signal circuit pattern of the first gate signal electrode formed on the back surface of the semiconductor element, and the main current bonding material is arranged across the entire surface on the side of the first main current circuit pattern of the first main current electrode formed on the back surface of the semiconductor element, thereby improving the heat dissipation of the semiconductor device.

[0010] Furthermore, the bonding area between the gate signal bonding material and the first gate signal electrode is smaller than the bonding area between the main current bonding material and the first main current electrode. Since the lengths of two adjacent sides of the rectangular gate signal bonding material are both more than twice the thickness of the gate signal bonding material, deformation due to tilting of the gate signal bonding material is less likely to occur, and the thickness of the gate signal bonding material is stabilized. As a result, tilting of the semiconductor element during reliability testing can be suppressed, thereby improving the reliability of the semiconductor device.

[0011] The purpose, features, aspects, and benefits of this disclosure will become clearer from the following detailed description and accompanying drawings. [Brief explanation of the drawing]

[0012] [Figure 1] This is a top view of a semiconductor device according to Embodiment 1. [Figure 2] This is a cross-sectional view along line AA in Figure 1. [Figure 3] This is a top view of a semiconductor device according to Embodiment 2. [Figure 4] Figure 2 is a cross-sectional view along line BB. [Figure 5] This is a top view of the semiconductor device according to Embodiment 3. [Figure 6] This is a top view of the semiconductor device according to Embodiment 4. [Figure 7] Figure 6 is a cross-sectional view along the CC line. [Figure 8] This is a top view of the semiconductor device according to Embodiment 5. [Figure 9] Figure 7 is a cross-sectional view of the DD line. [Modes for carrying out the invention]

[0013] <Embodiment 1> <Configuration of semiconductor device> Embodiment 1 will be described below with reference to the drawings. Figure 1 is a top view of the semiconductor device 100 according to Embodiment 1. Figure 2 is a cross-sectional view taken along line AA of Figure 1.

[0014] As shown in FIGS. 1 and 2, the semiconductor device 100 includes an insulating substrate 20, a semiconductor element 1, a bonding material 4 for gate signals, and a bonding material 5 for main currents.

[0015] The insulating substrate 20 includes an insulating material 8, a first circuit pattern 6 for gate signals, a first circuit pattern 7 for main currents, and a back surface circuit pattern 9.

[0016] The insulating material 8 is made of an insulating resin or ceramic. The insulating resin mainly contains, for example, an epoxy resin. The ceramic mainly contains, for example, Al2O3, Si3N4, or AlN. Since the insulating material 8 also requires heat dissipation, it is generally desirable that it has a high thermal conductivity and a thin thickness. However, if the thickness of the insulating material 8 is too thin, there are concerns that a sufficient insulation withstand voltage cannot be ensured and there is a lack of structural tolerance (such as stress resistance) during manufacturing. Therefore, the thickness of the insulating material 8 is preferably 100 μm or more.

[0017] The first circuit pattern 6 for gate signals and the first circuit pattern 7 for main currents are formed on the surface of the insulating material 8, and a gap 10 is formed between the first circuit pattern 6 for gate signals and the first circuit pattern 7 for main currents. The back surface circuit pattern 9 is formed on the back surface of the insulating material 8.

[0018] The first circuit pattern 6 for gate signals, the first circuit pattern 7 for main currents, and the back surface circuit pattern 9 are made of a metal such as aluminum, an aluminum alloy, copper, or a copper alloy. The first circuit pattern 6 for gate signals, the first circuit pattern 7 for main currents, and the back surface circuit pattern 9 are located directly below the semiconductor element 1 and also have a function of diffusing the heat generated by the semiconductor element 1. Therefore, it is desirable that the first circuit pattern 6 for gate signals, the first circuit pattern 7 for main currents, and the back surface circuit pattern 9 have a sufficient thickness so that heat can be sufficiently diffused in the planar direction (lateral direction). Depending on the layout in the planar direction (lateral direction), it is desirable that they have a thickness of 0.4 mm or more.

[0019] The semiconductor element 1 is made of Si, SiC, or GaN, and is mounted on an insulating substrate 20. The semiconductor element 1 is, for example, an insulated gate bipolar transistor (IGBT) or a metal oxide semiconductor field effect transistor (MOSFET). Alternatively, the semiconductor element 1 may be a reverse-conducting IGBT (RC-IGBT) in which the IGBT and diode are integrated.

[0020] On the back surface of the semiconductor element 1, a first gate signal electrode 2 and a first main current electrode 3 are formed. The first main current electrode 3 is formed in a U-shape when viewed from above and occupies most of the back surface of the semiconductor element 1. The first gate signal electrode 2 is formed in a rectangular shape when viewed from above and is positioned between the two ends of the first main current electrode 3.

[0021] The first gate signal electrode 2 and the first main current electrode 3 are formed from a metal film with good wettability, such as Ni, Au, Cu, or Ag, because they are joined to the gate signal bonding material 4 and the main current bonding material 5, respectively.

[0022] For example, if semiconductor device 1 is an IGBT, the first gate signal electrode 2 is the gate electrode, and the first main current electrode 3 is the emitter electrode or collector electrode. Also, if semiconductor device 1 is a MOSFET, the first gate signal electrode 2 is the gate electrode, and the first main current electrode 3 is the source electrode or drain electrode.

[0023] Although not shown in Figure 1, wires or electrodes for extracting the gate signal and main current are arranged on the surface of the semiconductor element 1.

[0024] The gate signal bonding material 4 is positioned between the first gate signal electrode 2 and the first gate signal circuit pattern 6, and bonds them together. The main current bonding material 5 is positioned between the first main current electrode 3 and the first main current circuit pattern 7, and bonds them together. The gate signal bonding material 4 and the main current bonding material 5 are separate components and are spaced apart. Furthermore, the gate signal bonding material 4 and the main current bonding material 5 are made of lead-free solder mainly composed of Sn, or sintered material mainly composed of Ag or Cu.

[0025] Furthermore, the gate signal bonding material 4 is arranged across the entire surface of the first gate signal electrode 2 on the side of the first gate signal circuit pattern 6. Similarly, the main current bonding material 5 is arranged across the entire surface of the first main current electrode 3 on the side of the first main current circuit pattern 7. These arrangements ensure the thermal diffusivity of the semiconductor element 1.

[0026] Furthermore, since the top view area of ​​the first gate signal electrode 2 is smaller than that of the first main current electrode 3, the bonding area between the first gate signal electrode 2 and the gate signal bonding material 4 is smaller than the bonding area between the first main current electrode 3 and the main current bonding material 5. In addition, the lengths of two adjacent sides a and b of the rectangular shape of the gate signal bonding material 4 are both more than twice the thickness c of the gate signal bonding material 4. Therefore, during reliability testing of the semiconductor device 100, deformation due to tilting of the gate signal bonding material 4 is suppressed, and the thickness c of the gate signal bonding material 4 remains stable.

[0027] <Manufacturing method for semiconductor devices> Next, the manufacturing method of the semiconductor device 100 will be briefly described. An insulating substrate 20 is prepared, which has an insulating material 8, a first gate signal circuit pattern 6 and a first main current circuit pattern 7 formed on the surface of the insulating material 8, and a back surface circuit pattern 9 formed on the back surface of the insulating material 8. A semiconductor element 1 is mounted on the insulating substrate 20. Specifically, the semiconductor element 1 is arranged such that the first gate signal electrode 2 and the first gate signal circuit pattern 6 face each other, and the first main current electrode 3 and the first main current circuit pattern 7 face each other. At this time, the heat generated in the semiconductor element 1 is greater on the emitter electrode side in the case of an IGBT and on the source electrode side in the case of a MOSFET. Therefore, if the first main current electrode 3 is made the emitter electrode or source electrode, it becomes possible to cool the heat generated in the semiconductor element 1 more efficiently.

[0028] Furthermore, when mounting the semiconductor element 1, the gate signal bonding material 4 is placed between the first gate signal electrode 2 and the first gate signal circuit pattern 6, and the main current bonding material 5 is placed between the first main current electrode 3 and the first main current circuit pattern 7. Then, each is bonded together under the required atmosphere, temperature, and pressure. Finally, the semiconductor device 100 is completed by bonding wires or electrodes for extracting the gate signal and main current to the surface of the semiconductor element 1.

[0029] <Effects> As described above, the semiconductor device 100 according to Embodiment 1 comprises an insulating material 8, an insulating substrate 20 having a first gate signal circuit pattern 6 and a first main current circuit pattern 7 formed on the surface of the insulating material 8, and a back surface circuit pattern 9 formed on the back surface of the insulating material 8, a semiconductor element 1 having a first gate signal electrode 2 and a first main current electrode 3 formed on the back surface and mounted on the insulating substrate 20, a gate signal bonding material 4 disposed between the first gate signal electrode 2 and the first gate signal circuit pattern 6 to bond the two, and a main current bonding material 5 disposed between the first main current electrode 3 and the first main current circuit pattern 7 to bond the two. The gate signal bonding material 4 and the main current bonding material 5 are separate components, and the gate signal bonding material 4 is disposed on the entire surface of the first gate signal electrode 2 on the side of the first gate signal circuit pattern 6. The main current bonding material 5 is disposed on the entire surface of the first main current electrode 3 on the side of the first main current circuit pattern 7. The bonding area between the gate signal bonding material 4 and the first gate signal electrode 2 is smaller than the bonding area between the main current bonding material 5 and the first main current electrode 3. The gate signal bonding material 4 is formed in a rectangular shape when viewed from above, and the lengths of two adjacent sides a and b of the rectangular shape of the gate signal bonding material 4 are both at least twice the thickness c of the gate signal bonding material 4.

[0030] Since the gate signal bonding material 4 is arranged on the entire surface of the first gate signal electrode 2 formed on the back surface of the semiconductor element 1 on the side of the first gate signal circuit pattern 6, and the main current bonding material 5 is arranged on the entire surface of the first main current electrode 3 formed on the back surface of the semiconductor element 1 on the side of the first main current circuit pattern 7, the heat dissipation of the semiconductor device 100 can be improved.

[0031] Furthermore, the bonding area between the gate signal bonding material 4 and the first gate signal electrode 2 is smaller than the bonding area between the main current bonding material 5 and the first main current electrode 3. Since the lengths of two adjacent sides a and b of the rectangular shape of the gate signal bonding material 4 are both more than twice the thickness c of the gate signal bonding material 4, deformation due to tilting of the gate signal bonding material 4 is less likely to occur, and the thickness of the gate signal bonding material 4 is stabilized. As a result, tilting of the semiconductor element 1 during reliability testing can be suppressed, thereby improving the reliability of the semiconductor device 100. Therefore, miniaturization and yield improvement of the semiconductor device 100 can be achieved.

[0032] Furthermore, since the insulating material 8 is made of insulating resin or ceramic, the difference in the coefficient of linear expansion between the insulating substrate 20 and the semiconductor element 1 is reduced. Therefore, even when the semiconductor element 1 is mounted across the first gate signal circuit pattern 6 and the first main current circuit pattern 7, the stress that the semiconductor element 1 experiences due to the expansion and contraction of the insulating substrate 20 during reliability testing is suppressed. As a result, the reliability of the semiconductor device 100 can be further improved.

[0033] <Embodiment 2> Next, a semiconductor device 100A according to Embodiment 2 will be described. Figure 3 is a top view of the semiconductor device 100A according to Embodiment 2. Figure 4 is a cross-sectional view taken along line BB in Figure 2. In Embodiment 2, the same reference numerals are used for components that are the same as those described in Embodiment 1, and their descriptions are omitted.

[0034] As shown in Figures 3 and 4, in Embodiment 2, the semiconductor element 1 further has a second gate signal electrode 11 and a second main current electrode 12 formed on its surface. The insulating material 8 further has a second gate signal circuit pattern 13 and a second main current circuit pattern 14 formed on its surface.

[0035] The second main current electrode 12 is formed in a U-shape when viewed from above and occupies most of the surface of the semiconductor element 1. The second gate signal electrode 11 is formed in a rectangular shape when viewed from above and is positioned between the two ends of the second main current electrode 12.

[0036] For example, if semiconductor device 1 is an IGBT, the first gate signal electrode 2 is the gate electrode. The first main current electrode 3 is the emitter electrode, and the second main current electrode 12 is the collector electrode. Also, if semiconductor device 1 is a MOSFET, the first gate signal electrode 2 is the gate electrode. The first main current electrode 3 is the source electrode, and the second main current electrode 12 is the drain electrode.

[0037] A signal wire 15 is provided to electrically connect the second gate signal electrode 11 to the second gate signal circuit pattern 13. Similarly, a main current wire 16 is provided to electrically connect the second main current electrode 12 to the second main current circuit pattern 14. The connection point between the signal wire 15 and the second gate signal electrode 11 is located on the first main current circuit pattern 7. Specifically, this connection point is in contact with the first main current circuit pattern 7 via a semiconductor element 1 and a main current bonding material 5. The connection point between the main current wire 16 and the second main current electrode 12 is also located on the first main current circuit pattern 7. Specifically, this connection point is in contact with the first main current circuit pattern 7 via a semiconductor element 1 and a gate signal bonding material 4.

[0038] <Effects> As described above, in the semiconductor device 100A according to Embodiment 2, the semiconductor element 1 further has a second gate signal electrode 11 and a second main current electrode 12 formed on its surface. Therefore, carrier control becomes possible on both the front and back surfaces of the semiconductor element 1, and the loss (heat generation) of the semiconductor element 1 is reduced. As a result, the reliability of the semiconductor device 100A can be improved compared to the case of Embodiment 1.

[0039] Furthermore, the insulating material 8 has a second gate signal circuit pattern 13 and a second main current circuit pattern 14 formed on its surface. The semiconductor device 100A further includes a signal wiring 15 connecting the second gate signal electrode 11 and the second gate signal circuit pattern 13, and a main current wiring 16 connecting the second main current electrode 12 and the second main current circuit pattern 14. The connection point between the signal wiring 15 and the second gate signal electrode 11 is located on the first main current circuit pattern 7, and the connection point between the main current wiring 16 and the second main current electrode 12 is located on the first main current circuit pattern 7.

[0040] Therefore, since the temperature rise at these connection points is suppressed when the semiconductor device 100A is energized, the reliability of the semiconductor device 100A can be further improved.

[0041] Furthermore, the semiconductor element 1 includes an IGBT or a MOSFET, the first main current electrode 3 is either an emitter electrode or a source electrode, and the second main current electrode 12 is either a collector electrode or a drain electrode.

[0042] Therefore, by placing the emitter electrode or source electrode, which generates a large amount of heat, on the circuit pattern side in the thickness direction of the semiconductor element 1, the semiconductor element 1 can be efficiently cooled. As a result, the reliability of the semiconductor device 100A can be improved.

[0043] <Embodiment 3> Next, a semiconductor device 100B according to Embodiment 3 will be described. Figure 5 is a top view of the semiconductor device 100B according to Embodiment 3. In Embodiment 3, the same reference numerals are used for components that are the same as those described in Embodiments 1 and 2, and their descriptions are omitted.

[0044] In Embodiment 2, in a top view, the second main current electrode 12 was positioned to overlap the first main current circuit pattern 7 and the first gate signal circuit pattern 6. In contrast, in Embodiment 3, as shown in Figure 5, in a top view, the second main current electrode 12 MostThis is the circuit pattern for the first main current. 7 The first gate signal circuit pattern 6 is arranged to overlap, and not much They don't overlap.

[0045] The second gate signal electrode 11 is located at one of the four corners on the surface of the semiconductor element 1 (the lower right corner in Figure 5). The first gate signal electrode 2 is located at the same position as the second gate signal electrode 11. Therefore, the first gate signal electrode 2 is also located at one of the four corners on the back surface of the semiconductor element 1 (the lower right corner in Figure 5). Note that the first gate signal electrode 2 can be located at any of the four corners of the semiconductor element 1 and can be changed to match the positions of the first gate signal circuit pattern 6 and the second gate signal circuit pattern 13.

[0046] <Effects> As described above, in the semiconductor device 100B according to Embodiment 3, the second main current electrode 12 and the first main current circuit pattern 7 are arranged to overlap when viewed from above. The second main current electrode 12, which is the current extraction part, generates a large amount of heat, but the heat from the second main current electrode 12, which generates a large amount of heat, can be efficiently cooled, thereby improving the reliability of the semiconductor device 100B.

[0047] Furthermore, the first gate signal electrode 2 is located at one of the four corners of the semiconductor element 1. The lifespan of the bonding material bonded to the back surface of the semiconductor element 1 is often limited by crack propagation from the four corners of the semiconductor element 1. In Embodiment 3, the thickness of the gate signal bonding material 4 bonded to one of the four corners on the back surface of the semiconductor element 1 is stabilized. As a result, the thickness of the bonding material bonded to the other three corners on the back surface of the semiconductor element 1 where the first gate signal electrode 2 is not located is also stabilized, thereby improving the reliability of the semiconductor device 100B.

[0048] <Embodiment 4> Next, a semiconductor device 100C according to Embodiment 4 will be described. Figure 6 is a top view of the semiconductor device 100C according to Embodiment 4. Figure 7 is a cross-sectional view of Figure 6 along line CC. In Embodiment 4, the same reference numerals are used for components that are the same as those described in Embodiments 1 to 3, and their descriptions are omitted.

[0049] As shown in Figures 6 and 7, in Embodiment 4, an obstruction portion 17 is formed on the first gate signal circuit pattern 6, compared to the configuration of Embodiment 3. The obstruction portion 17 is provided to inhibit the wetting spread of the gate signal bonding material 4 and is formed to surround the bonding location of the gate signal bonding material 4 on the first gate signal circuit pattern 6. The obstruction portion 17 may be made of a resin-based material such as a resist, or it may be a roughened portion with a rougher surface than the parts of the first gate signal circuit pattern 6 other than the obstruction portion 17.

[0050] <Effects> In the semiconductor device 100C according to Embodiment 4, an obstructing portion 17 is formed to inhibit the wetting spread of the gate signal bonding material 4 so as to surround the bonding location of the gate signal bonding material 4 on the first gate signal circuit pattern 6. Therefore, the shape of the gate signal bonding material 4 is stabilized, and the thickness of the gate signal bonding material 4 is also stabilized. As a result, the reliability of the semiconductor device 100C can be improved.

[0051] Furthermore, the inhibiting portion 17 is made of a resin-based material. By using a resin-based material that has the property of repelling the gate signal bonding material 4, it is possible to ensure inhibition of the wetting and spreading of the gate signal bonding material 4.

[0052] Furthermore, since the inhibiting portion 17 is a roughened portion with a rougher surface than the other parts of the circuit pattern 6 for the first gate signal, it is possible to ensure inhibition of the wetting spread of the gate signal bonding material 4. Because dissimilar materials such as resin-based materials are not used, incompatibility between the inhibiting portion 17 and its surroundings is suppressed.

[0053] <Embodiment 5> Next, the semiconductor device 100D according to Embodiment 5 will be described. Figure 8 is a top view of the semiconductor device 100D according to Embodiment 5. Figure 9 is a cross-sectional view taken along the DD line in Figure 7. In Embodiment 5, the same reference numerals are used for components that are the same as those described in Embodiments 1 to 4, and their descriptions are omitted.

[0054] In Embodiment 4, an obstruction portion 17 was formed so as to surround the bonding location of the gate signal bonding material 4 on the first gate signal circuit pattern 6. In contrast, in Embodiment 5, as shown in Figures 8 and 9, an obstruction portion 18 is filled into the void 10. The obstruction portion 18 is made of a resin-based material such as a resist. Specifically, the obstruction portion 18 is formed so as to surround the bonding location of the gate signal bonding material 4 in the void 10. It is also possible to fill the void 10 in Embodiment 4 with an obstruction portion 18.

[0055] <Effects> As described above, in the semiconductor device 100D according to Embodiment 5, a gap 10 is formed between the first gate signal circuit pattern 6 and the first main current circuit pattern 7, and an obstructing portion 18 that inhibits the wetting spread of the gate signal bonding material 4 is arranged in the gap 10. Therefore, the intrusion of the gate signal bonding material 4 into the gap 10 can be suppressed, and the thickness of the gate signal bonding material 4 is stabilized. As a result, the reliability of the semiconductor device 100B can be improved.

[0056] Although this disclosure has been described in detail, the above description is illustrative and not limiting in all respects. It is understood that countless variations not illustrated are conceivable.

[0057] Furthermore, it is possible to freely combine each embodiment, or to modify or omit each embodiment as appropriate. [Explanation of Symbols]

[0058] 1 Semiconductor element, 2 Electrode for first gate signal, 3 Electrode for first main current, 4 Signal bonding material, 5 Main current bonding material, 6 Circuit pattern for first gate signal, 7 Circuit pattern for first main current, 8 Insulating material, 9 Backside circuit pattern, 10 Air gap, 11 Electrode for second gate signal, 12 Electrode for second main current, 13 Circuit pattern for second gate signal, 14 Circuit pattern for second main current, 15 Signal issue Wiring for main current, 16 wiring for main current, 17, 18 blocking section, 20 insulating substrate.

Claims

1. An insulating substrate having an insulating material, a first gate signal circuit pattern and a first main current circuit pattern formed on the surface of the insulating material, and a back surface circuit pattern formed on the back surface of the insulating material, A semiconductor element mounted on the insulating substrate has a first gate signal electrode and a first main current electrode formed on its back surface, A gate signal bonding material is placed between the first gate signal electrode and the first gate signal circuit pattern to join them together, The device comprises a main current bonding material positioned between the first main current electrode and the first main current circuit pattern, and connecting the two, The gate signal bonding material and the main current bonding material are separate components. The gate signal bonding material is arranged across the entire surface of the first gate signal electrode on the side of the first gate signal circuit pattern. The main current bonding material is arranged across the entire surface of the first main current electrode on the side of the first main current circuit pattern. The bonding area between the gate signal bonding material and the first gate signal electrode is smaller than the bonding area between the main current bonding material and the first main current electrode. The gate signal connecting material is formed in a rectangular shape when viewed from above, and the lengths of two adjacent sides of the rectangular shape of the gate signal connecting material are both at least twice the thickness of the gate signal connecting material. The semiconductor element further comprises a second gate signal electrode and a second main current electrode formed on its surface. The insulating substrate further has a second gate signal circuit pattern and a second main current circuit pattern formed on the surface of the insulating material. The system further comprises signal wiring connecting the second gate signal electrode and the second gate signal circuit pattern, and main current wiring connecting the second main current electrode and the second main current circuit pattern, The connection point between the signal wiring and the second gate signal electrode is located on the first main current circuit pattern. The connection point between the main current wiring and the second main current electrode is located on the first gate signal circuit pattern. Semiconductor equipment.

2. The semiconductor device according to claim 1, wherein the insulating material is made of an insulating resin or ceramic.

3. The semiconductor device according to claim 1, wherein, in a top view, the second main current electrode and the first main current circuit pattern are arranged to overlap.

4. The semiconductor device according to claim 1, wherein the first gate signal electrode is located at one of the four corners of the semiconductor element.

5. The semiconductor device according to claim 1, wherein an obstructing portion is formed to inhibit the wetting spread of the gate signal bonding material so as to surround the bonding location of the gate signal bonding material on the first gate signal circuit pattern.

6. A gap is formed between the first gate signal circuit pattern and the first main current circuit pattern. The semiconductor device according to claim 1, wherein an obstructing portion is disposed in the void to inhibit the wetting spread of the gate signal bonding material.

7. The semiconductor device according to claim 5 or claim 6, wherein the inhibiting portion is made of a resin-based material.

8. The semiconductor device according to claim 5, wherein the inhibiting portion is a roughened portion on the circuit pattern for the first gate signal that has a rougher surface than the portion other than the inhibiting portion.

9. The semiconductor device includes an IGBT or a MOSFET. The first main current electrode is either an emitter electrode or a source electrode. The semiconductor device according to claim 1, wherein the second main current electrode is a collector electrode or a drain electrode.

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