Semiconductor devices and power converters

Abstract

This disclosure aims to measure the degree of characteristic degradation in a semiconductor device having a MOS gate structure, even when threshold voltage fluctuations caused by switching operation and specific operation occur simultaneously. The semiconductor device (101) comprises a first-conductivity semiconductor substrate (1), a high-voltage MOSFET (21) having a MOS gate structure formed on the semiconductor substrate (1), and a monitor MOSFET (22) having a MOS gate structure formed on the semiconductor substrate (1). Between the high-voltage MOSFET (21) and the monitor MOSFET (22), either the threshold voltage fluctuation amount caused by switching operation or the threshold voltage fluctuation amount caused by a specific operation that causes the threshold voltage to fluctuate in a direction different from switching operation is different.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device.

Background Art

[0002] Patent Document 1 discloses a semiconductor device in which a high-voltage withstand MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) and a monitor MOSFET are mounted together. In a semiconductor device having a MOS gate structure such as a MOSFET, when stress is applied to the gate oxide film during market operation, the threshold voltage increases. By measuring the threshold voltage of the monitor MOSFET during inspection in the middle of market operation, it becomes possible to predict in advance the characteristic deterioration of the high-voltage withstand MOSFET after inspection and take measures such as replacing it before failure.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, considering an operation that varies the threshold voltage in the opposite direction to the switching operation, such as an avalanche operation (hereinafter referred to as "specific operation"), when fluctuations in the threshold voltage caused by the switching operation and the specific operation occur simultaneously, there is a problem that the increase and decrease cancel each other out and the degree of characteristic deterioration cannot be grasped, and failure prediction cannot be performed.

[0005] The present disclosure has been made to solve the above problems, and an object thereof is to measure the degree of characteristic deterioration even when fluctuations in the threshold voltage caused by the switching operation and the specific operation occur simultaneously in a semiconductor device having a MOS gate structure.

Means for Solving the Problems

[0006] This disclosure The first aspect The semiconductor device comprises a semiconductor substrate of a first conductivity type, a first semiconductor element having a MOS gate structure formed on the semiconductor substrate, and at least one second semiconductor element having a MOS gate structure formed on the semiconductor substrate, wherein the threshold voltage fluctuation amount due to switching operation and the threshold voltage fluctuation amount due to a specific operation that causes the threshold voltage to fluctuate in a direction different from the switching operation are different between the first semiconductor element and the second semiconductor element. Each of the first and second semiconductor elements comprises a drift layer of a first conductivity type formed on a semiconductor substrate and a well region of a second conductivity type formed on the surface layer of the drift layer, wherein the impurity concentration of the well region in the second semiconductor element is lower than that of the well region in the first semiconductor element. . [Effects of the Invention]

[0007] The semiconductor device of this disclosure makes it possible to measure the degree of characteristic degradation even when threshold voltage fluctuations caused by switching operation and specific operation occur simultaneously. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 is a top view of a semiconductor device according to embodiments 1-3 and 5. [Figure 2] Figure 2 is a cross-sectional view of a semiconductor device according to Embodiments 1-3. [Figure 3] Figure 3 is a circuit diagram of a semiconductor device according to Embodiment 1. [Figure 4] Figure 4 is a diagram showing the amount of threshold voltage fluctuation in a high-voltage MOSFET in a semiconductor device according to Embodiment 1. [Figure 5] Figure 5 is a diagram showing the amount of threshold voltage fluctuation caused by switching operation in a high-voltage MOSFET or monitor MOSFET in a semiconductor device according to Embodiment 1. [Figure 6] Figure 6 is a diagram showing the amount of threshold voltage fluctuation due to avalanche operation in a high-voltage MOSFET or monitor MOSFET in a semiconductor device according to Embodiment 1. [Figure 7] Figure 7 is a circuit diagram of a semiconductor device according to Embodiment 2. [Figure 8] FIG. 8 is a circuit diagram of the semiconductor device according to Embodiment 3. [Figure 9] FIG. 9 is a diagram showing the initial Id-Vg characteristics of the semiconductor device according to Embodiment 3. [Figure 10] FIG. 10 is a diagram showing the Id-Vg characteristics of the semiconductor device during market operation according to Embodiment 3. [Figure 11] FIG. 11 is a cross-sectional view of the semiconductor device according to Embodiment 4. [Figure 12] FIG. 12 is a diagram showing the configuration of the high-voltage MOSFET according to Embodiment 5. [Figure 13] FIG. 13 is a diagram showing the configuration of the monitor MOSFET according to Embodiment 5. [Figure 14] FIG. 14 is a cross-sectional view of the high-voltage MOSFET according to Embodiment 5. [Figure 15] FIG. 15 is a cross-sectional view of the monitor MOSFET according to Embodiment 5. [Figure 16] FIG. 16 is a cross-sectional view showing the manufacturing process of the semiconductor device according to Embodiment 5. [Figure 17] FIG. 17 is a cross-sectional view showing the manufacturing process of the semiconductor device according to Embodiment 5. [Figure 18] FIG. 18 is a cross-sectional view showing the manufacturing process of the region including the electric field relaxation layer of the semiconductor device according to Embodiment 5. [Figure 19] FIG. 19 is a cross-sectional view showing the manufacturing process of the region not including the electric field relaxation layer of the semiconductor device according to Embodiment 5. [Figure 20] FIG. 20 is a cross-sectional view showing the manufacturing process of the region including the electric field relaxation layer of the semiconductor device according to Embodiment 5. [Figure 21] FIG. 21 is a cross-sectional view showing the manufacturing process of the region not including the electric field relaxation layer of the semiconductor device according to Embodiment 5. [Figure 22] FIG. 22 is a diagram showing the configuration of the power conversion device according to Embodiment 6.

Embodiments for Carrying Out the Invention

[0009] In the following description, regarding the conductivity type of the semiconductor, the first conductivity type is an n-type and the second conductivity type is a p-type. However, these conductivity types may be opposite. That is, the first conductivity type may be a p-type and the second conductivity type may be an n-type.

[0010] <A. Embodiment 1> <A-1. Structure> FIG. 1 is a top view of a chip 30 constituting a semiconductor device 101 according to Embodiment 1. The semiconductor device 101 includes a high-voltage MOSFET 21 which is a first semiconductor element having a MOS gate structure and a monitor MOSFET 22 which is a second semiconductor element having a MOS gate structure. On the front surface side of the chip 30, a gate Gh and a source Sh of the high-voltage MOSFET 21, and a gate Gm and a source Sm of the monitor MOSFET 22 are provided. On the back surface side of the chip 30, a drain D of the high-voltage MOSFET 21 and the monitor MOSFET 22 is provided. The drains D of the high-voltage MOSFET 21 and the monitor MOSFET 22 are common.

[0011] FIG. 2 is a partial cross-sectional view showing a part of the configuration of the semiconductor device 101. The semiconductor device 101 includes a semiconductor substrate 1, an n-type drift layer 3 formed on the front surface side of the semiconductor substrate 1, and a drain electrode 12 formed on the back surface of the semiconductor substrate 1. These configurations are common to the high-voltage MOSFET 21 and the monitor MOSFET 22. In FIG. 2, the high-voltage MOSFET 21 and the monitor MOSFET 22 are planar MOSFETs.

[0012] In the high-voltage MOSFET 21, a plurality of p-type well regions 4h are formed in the surface layer of the drain electrode 12. An n-type source region 5h and a p+-type contact region 9h are formed in the surface layer of the well region 4h. [[ID=URL]]

[0013] Similarly, in the monitor MOSFET 22, a plurality of p-type well regions 4m are formed in the surface layer of the drain electrode 12. An n-type source region 5m and a p+-type contact region 9m are formed in the surface layer of the well region 4m.

[0014] The drift layer 3, well region 4h, source region 5h, contact region 9h, well region 4m, source region 5m, and contact region 9m are referred to as semiconductor layer 2.

[0015] On the surface of the well region 4h, where the source region 5h and contact region 9h are not formed, a gate electrode 8h is formed with a gate insulating film 7h in between.

[0016] An interlayer insulating film 13h is formed on the semiconductor layer 2 and the gate electrode 8h. A contact hole 31h is formed in the interlayer insulating film 13h on the contact region 9h. A barrier metal 32h is formed inside the contact hole 31h and on the interlayer insulating film 13h, and a source electrode 11h is formed on the barrier metal 32h. The source electrode 11h contacts the contact region 9h within the contact hole 31h via the barrier metal 32h.

[0017] The above describes the configuration of the high-voltage MOSFET 21, and the configuration of the monitor MOSFET 22 is the same as that of the high-voltage MOSFET 21. However, to distinguish between the two, the reference numeral 'm' is added to the end of the reference numerals of the components of the monitor MOSFET 22. Specifically, the monitor MOSFET 22 comprises a gate insulating film 7m, a gate electrode 8m, an interlayer insulating film 13m, a contact hole 31m, a barrier metal 32m, and a source electrode 11m.

[0018] The p-type impurity concentration in well region 4m of monitor MOSFET 22 is between 1 / 100 and 1 / 2 of the p-type impurity concentration in well region 4h of high-voltage MOSFET 21. Thus, the low p-type impurity concentration in well region 4m results in a lower threshold voltage and a higher avalanche current in the monitor MOSFET. Consequently, under market conditions, when avalanche operation occurs, the threshold voltage drop is greater in monitor MOSFET 22 than in high-voltage MOSFET 21.

[0019] In order to change the impurity concentration between the well region 4h and the well region 4m, two implantation masks can be used, and the set amount of impurities can be implanted into each of the well region 4h and the well region 4m. For example, with the first implantation mask, only the well region 4h is exposed, and impurities are implanted to set a predetermined concentration. Next, with the second implantation mask, only the well region 4m is exposed, and impurities are implanted to set a predetermined concentration.

[0020] FIG. 3 is a circuit diagram of the semiconductor device 101. In the semiconductor device 101, the gate Gh of the high-voltage MOSFET 21 and the gate Gm of the monitor MOSFET 22 are electrically connected.

[0021] <A-2. Operation> The operation of the semiconductor device 101 will be described. Since the gate Gh and the gate Gm are electrically connected, both the high-voltage MOSFET 21 and the monitor MOSFET 22 perform a switching operation. In both MOSFETs, an increase in the threshold voltage due to the switching operation and a decrease in the threshold voltage due to the avalanche operation occur simultaneously.

[0022] In both MOSFETs, the amount of change in the threshold voltage due to the switching operation is the same. However, since the impurity concentration in the well region 4m is lower than that in the well region 4h, a larger avalanche current flows in the monitor MOSFET 22, and the amount of change in the threshold voltage due to the avalanche operation becomes larger. Therefore, by taking the difference in the amount of change in the threshold voltage between the two MOSFETs, the difference in the amount of change in the threshold voltage due to the avalanche operation in the two MOSFETs can be extracted.

[0023] It is known how much the threshold voltage due to avalanche operation changes depending on how much the impurity concentration in the p-well region changes. Therefore, the amount of threshold voltage fluctuation due to avalanche operation in each of the high-voltage MOSFET 21 and the monitor MOSFET 22 can be identified from the difference in the amount of threshold voltage fluctuation due to avalanche operation in each of the high-voltage MOSFET 21 and the monitor MOSFET 22. In this way, the amount of threshold voltage fluctuation due to avalanche operation and the amount of threshold voltage fluctuation due to switching operation can be separated in each of the high-voltage MOSFET 21 and the monitor MOSFET 22.

[0024] Figure 4 shows the threshold voltage fluctuation ΔVth(V) in the high-voltage MOSFET 21 of the semiconductor device 101. The horizontal axis of Figure 4 is time (seconds), and the vertical axis is the threshold voltage fluctuation ΔVth(V). In Figure 4, the thin solid line shows the threshold voltage fluctuation ΔVth_sw(V) due to switching operation, the thin dashed line shows the threshold voltage fluctuation ΔVth_ava(V) due to avalanche operation, and the thick solid line shows the sum of the threshold voltage fluctuations due to switching operation and avalanche operation, ΔVth=(ΔVth_sw)+(ΔVth_ava).

[0025] Figure 5 shows the threshold voltage fluctuation ΔVth_sw(V) due to switching operation, plotted on a logarithmic scale on the vertical axis. Figure 6 shows the threshold voltage fluctuation ΔVth_ava(V) due to avalanche operation, plotted on a logarithmic scale on the vertical axis with the unit -V. As is clear from Figures 5 and 6, ΔVth_sw and ΔVth_ava can be empirically expressed as functions of time t by the following equations (1) and (2). Note that a is a positive value and c is a negative value.

[0026] ΔVth_sw=a×t^b…(1) ΔVth_ava=c×t^d…(2) Before market launch, that is, immediately after manufacturing the semiconductor device 101, the amount of change ΔVth in the threshold voltage of each of the high-voltage MOSFET 21 and the monitor MOSFET 22 is grasped. That is, a, b, c, and d in equations (1) and (2) are grasped. Then, by measuring the threshold voltage Vth of the high-voltage MOSFET and the monitor MOSFET during market operation, it is also possible to separate the amount of change ΔVth_sw(V) in the threshold voltage due to the switching operation and the amount of change ΔVth_ava(V) in the threshold voltage due to the avalanche operation.

[0027] The semiconductor device 101 according to Embodiment 1 includes an n-type semiconductor substrate 1, a high-voltage MOSFET 21 having a MOS gate structure formed on the semiconductor substrate 1, and a monitor MOSFET 22 having a MOS gate structure formed on the semiconductor substrate 1. Between the high-voltage MOSFET 21 and the monitor MOSFET 22, either the amount of change in the threshold voltage due to the switching operation or the amount of change in the threshold voltage due to a specific operation that varies the threshold voltage in a direction different from the switching operation is different. With the above configuration, by taking the difference in the amount of change in the threshold voltage between the high-voltage MOSFET 21 and the monitor MOSFET 22, it is possible to extract either the difference in the amount of change in the threshold voltage due to the switching operation or the difference in the amount of change in the threshold voltage due to the specific operation between the high-voltage MOSFET 21 and the monitor MOSFET 22. As a result, in the high-voltage MOSFET 21, it becomes possible to separate the amount of change in the threshold voltage into that due to switching and that due to the specific operation, and it becomes possible to measure the degree of deterioration of the characteristics.

[0028] <B. Embodiment 2> <B-1. Configuration> FIG. 7 is a circuit diagram of the semiconductor device 102 according to Embodiment 2. The top view and cross-sectional view of the chip of the semiconductor device 102 are as shown in FIGS. 1 and 2, and are the same as those of the semiconductor device 101 according to Embodiment 1.

[0029] In the semiconductor device 102, the gate Gm of the monitor MOSFET 22 is connected to GND. Note that the gate Gm may be connected to a potential different from the gate Gh of the high-voltage MOSFET 21. For example, it may be connected to the source Sh of the high-voltage MOSFET 21.

[0030] <B-2. Operation> In the semiconductor device 102, during market operation, even while the high-voltage MOSFET 21 is performing a switching operation, the monitor MOSFET 22 does not perform a switching operation. Therefore, in the monitor MOSFET 22, only a decrease in the threshold voltage due to the avalanche operation occurs, and the threshold voltage does not increase.

[0031] Note that it is known how much the impurity concentration in the p-well region changes and how much the threshold voltage due to the avalanche operation changes. Therefore, from the decrease in the threshold voltage measured in the monitor MOSFET 22, it is possible to grasp how much the decrease in the threshold voltage due to the avalanche operation has occurred in the high-voltage MOSFET 21. That is, from the amount of change in the threshold voltage in the high-voltage MOSFET 21, it is possible to separate the amount of change in the threshold voltage due to the switching operation and the amount of change in the threshold voltage due to the avalanche operation.

[0032] When evaluating the characteristics of the monitor MOSFET 22, it is necessary to apply a voltage to the gate Gm connected to GND. Therefore, by mounting a switch that switches the potential to the gate Gm only when evaluating the characteristics of the monitor MOSFET 22 or a circuit that controls the potential of the gate Gm in the semiconductor device 102, it becomes possible to measure the threshold voltage during the switching operation of the monitor MOSFET 22.

[0033] In the semiconductor device 102, the impurity concentration in the well region 4m of the monitor MOSFET 22 may be lower than the impurity concentration in the well region 4h of the high-voltage MOSFET 21. The smaller the impurity concentration in the well region 4m of the monitor MOSFET 22, the larger the amount of change in the threshold voltage due to the avalanche operation in the monitor MOSFET 22, so the measurement error can be reduced.

[0034] <C. Embodiment 3> <C-1. Configuration> FIG. 8 is a circuit diagram of the semiconductor device 103 according to Embodiment 3. The top view and cross-sectional view of the chip of the semiconductor device 103 are as shown in FIGS. 1 and 2, and are the same as those of the semiconductor device 101 according to Embodiment 1.

[0035] In the semiconductor device 103, the gate Gm of the monitor MOSFET 22 is connected to the gate Gh of the high-voltage MOSFET 21, and the source Sm of the monitor MOSFET 22 is connected to the source Sh of the high-voltage MOSFET 21. That is, in the semiconductor device 103, all terminals of the source, gate, and drain are common between the high-voltage MOSFET 21 and the monitor MOSFET 22.

[0036] <C-2. Operation> FIGS. 9 and 10 show the Id-Vg characteristics in the semiconductor device 103. In FIGS. 9 and 10, the thin solid line shows the Id-Vg characteristic of the monitor MOSFET 22, the thin broken line shows the Id-Vg characteristic of the high-voltage MOSFET 21, and the thick solid line shows the Id-Vg characteristic of the semiconductor device 103. FIG. 9 shows the initial Id-Vg characteristic immediately after the manufacture of the semiconductor device 103, and FIG. 10 shows the Id-Vg characteristic during market operation.

[0037] When the impurity concentration of the well region 4m of the monitor MOSFET 22 is lower than the impurity concentration of the well region 4h of the high-voltage MOSFET 21, a "bump" indicated by a broken-line frame in FIG. 9 is observed in the Id-Vg characteristic.

[0038] The reason for the "bulge" observed in the Id-Vg characteristic is that the threshold voltage differs between the monitor MOSFET 22 and the high-voltage MOSFET 21, resulting in different rise voltages for the subthreshold characteristics. Furthermore, the area of ​​the monitor MOSFET 22 and the high-voltage MOSFET 21 differs, leading to different saturation current values. The area occupied by the monitor MOSFET 22 on chip 30 is smaller than that occupied by the high-voltage MOSFET 21. For example, the cell area of ​​the monitor MOSFET 22 is between 10⁻⁷ and 10⁻³ times that of the high-voltage MOSFET 21. Therefore, the saturation current value of the monitor MOSFET 22 is more than an order of magnitude smaller than that of the high-voltage MOSFET 21. Consequently, a bulge is observed in the Id-Vg characteristic.

[0039] In Figure 9, Id = 1.0 × 10 -2 Let Vg in (A) be the first threshold voltage Vth1, and Id = 1.0 × 10 -5 The value of Vg in (A) is defined as the second threshold voltage Vth2. The first threshold voltage Vth1 is the upper threshold voltage of the "bump" caused by the high-voltage MOSFET 21, and increases with market operation as shown in Figure 10. The second threshold voltage Vth2 is the lower threshold voltage of the "bump" caused by the monitor MOSFET 22, and decreases with market operation as shown in Figure 10. In this way, the "bump" grows larger with market operation.

[0040] The above describes the case where the impurity concentration in well region 4m of monitor MOSFET 22 is lower than the impurity concentration in well region 4h of high-voltage MOSFET 21. When the impurity concentration in well region 4m of monitor MOSFET 22 is the same as the impurity concentration in well region 4h of high-voltage MOSFET 21, no "bumps" are visible in the Id-Vg characteristics of semiconductor device 103 immediately after manufacturing, i.e., at the initial time of shipment. However, as damage accumulates in semiconductor device 103 during market operation, "bumps" become visible in the Id-Vg characteristics.

[0041] Therefore, by measuring the first threshold voltage Vth1 and the second threshold voltage Vth2 above and below the "bulge," it becomes possible to calculate how much damage has accumulated in the market.

[0042] The monitor MOSFET 22 exhibits a significantly lower threshold voltage due to avalanche operation compared to the high-voltage MOSFET 21. Therefore, by observing the fluctuation of the first threshold voltage Vth1, the fluctuation of the threshold voltage due to avalanche operation in the monitor MOSFET 22 can be confirmed.

[0043] It is known how much the threshold voltage due to avalanche operation changes depending on how much the impurity concentration in the p-well region changes. Therefore, by observing the decrease in the threshold voltage due to avalanche operation in the monitor MOSFET 22, it is possible to determine the extent to which the threshold voltage decrease due to avalanche operation occurs in the high-voltage MOSFET 21. In other words, by observing the amount of threshold voltage fluctuation in the high-voltage MOSFET 21, it is possible to separate the amount of threshold voltage fluctuation due to switching operation from the amount of threshold voltage fluctuation due to avalanche operation.

[0044] Figures 9 and 10 show the Id-Vg characteristics when the semiconductor device 103 comprises one high-voltage MOSFET 21 and one monitor MOSFET 22. The semiconductor device 103 may also comprise one high-voltage MOSFET 21 and multiple monitor MOSFETs 22. In this case, the p-type impurity concentration in the p-type well region 4m differs for each of the multiple monitor MOSFETs 22.

[0045] For example, when the semiconductor device 103 includes one high-voltage MOSFET 21 and two monitor MOSFETs 22, two "bumps" can be seen in the Id-Vg characteristics. At this time, from the first bump, the amount of variation in the threshold voltage due to the avalanche operation in the first monitor MOSFET 22 can be observed. And from the observed value, the amount of variation in the threshold voltage due to the avalanche operation in the high-voltage MOSFET 21 can be estimated. Similarly, for the second bump, the amount of variation in the threshold voltage due to the avalanche operation in the second monitor MOSFET 22 can be observed, and from the observed value, the amount of variation in the threshold voltage due to the avalanche operation in the high-voltage MOSFET 21 can be estimated. When these two estimated values are different, it becomes possible to accurately estimate the amount of variation in the threshold voltage due to the avalanche operation in the high-voltage MOSFET 21 by performing processing such as taking an average.

[0046] According to the configuration of the semiconductor device 103, even if all the terminals of the drain, gate, and source are common, it is possible to measure the Vth and its variation amount of the monitor MOSFET and the high-voltage MOSFET, so that the amount of damage to the market operation can be grasped.

[0047] <D. Embodiment 4> <D-1. Configuration> FIG. 11 is a cross-sectional view of a semiconductor device 104 according to Embodiment 4. The semiconductor device 104 is different from the semiconductor device 101 according to Embodiment 1 in that, in addition to the high-voltage MOSFET 21 and the monitor MOSFET 22, a pn junction element 23 is provided in a region that is not a MOSFET. Note that the semiconductor device 104 may have a configuration in which the pn junction element 23 is added to the semiconductor devices 102 and 103 according to Embodiment 2 or Embodiment 3.

[0048] The pn junction element 23 has a structure obtained by excluding the gate insulating film and the gate electrode from the high-voltage withstand MOSFET 21 or the monitor MOSFET 22, and includes a semiconductor substrate 1, a drift layer 3, a well region 4j, a source region 5j, a contact region 9j, an interlayer insulating film 13j, a contact hole 31j, a barrier metal 32j, a source electrode 11j, and a drain electrode 12. A pn junction is formed by the n-type drift layer 3 and the p-type well region 4j. The p-type impurity concentration of the well region 4j is the same as or lower than the p-type impurity concentration of the well region 4h in the high-voltage withstand MOSFET 21.

[0049] The pn junction element 23 is formed in the same manner as the high-voltage withstand MOSFET 21 or the monitor MOSFET 22, except that the step of forming the gate electrode with gate polysilicon is not performed.

[0050] In Embodiments 1-4, each of the high-voltage withstand MOSFET 21, the monitor MOSFET 22, and the pn junction element 23 has been described as a planar MOSFET, but these may be trench MOSFETs.

[0051] The semiconductor device 104 according to Embodiment 4 includes a pn junction element 23 having no MOS gate structure in a region different from the high-voltage withstand MOSFET 21 and the monitor MOSFET 22 on the semiconductor substrate 1. The impurity concentration of the well region 4j in the pn junction element 23 is lower than the impurity concentration of the well region 4h in the high-voltage withstand MOSFETs 21. Therefore, according to the semiconductor device 104, during the avalanche operation, by dispersing the excessive current from the drain electrode 12 to the pn junction element 23, the current flowing through the well regions 4h and 4m of the high-voltage withstand MOSFET 21 and the monitor MOSFET 22 can be reduced, so that the deterioration of the high-voltage withstand MOSFET 21 and the monitor MOSFET 22 can be suppressed.

[0052] <E. Embodiment 5> <E-1. Configuration> The top view of the semiconductor device 105 according to Embodiment 5 is as shown in Figures 1 and 2, and is the same as that of the semiconductor device 101 according to Embodiment 1. The semiconductor device 105 includes a high-voltage MOSFET 21 and a monitor MOSFET 22. Figure 12 shows the configuration of the high-voltage MOSFET 21 in the semiconductor device 105. Figure 13 shows the configuration of the monitor MOSFET 22 in the semiconductor device 105.

[0053] In Figures 12 and 13, the high-voltage MOSFET 21 and the monitor MOSFET 22 are trench-type MOSFETs. In the high-voltage MOSFET 21 and the monitor MOSFET 22, the arrangement of the p+-type contact region and the p-type field relaxation layer formed in the SiC layer of the trench sidewall differs.

[0054] As shown in Figure 12, the high-voltage MOSFET 21 of this embodiment differs from the high-voltage MOSFET 21 of Embodiment 1 in that the gate electrode 8h is a trench gate and that it comprises a p-type sidewall grounding layer 41, a p-type bottom layer 42, and an n-type high-concentration layer 43.

[0055] The bottom layer 42 is formed beneath the trench gate. The sidewall grounding layer 41 and the high-concentration layer 43 are adjacent to the p-type bottom layer 42 and are formed on the sidewalls of the trench gate. The sidewall grounding layer 41 acts as an electric field mitigation layer that mitigates the electric field at the bottom of the trench gate.

[0056] As shown in Figure 13, the monitor MOSFET 22 of this embodiment differs from the monitor MOSFET 22 of Embodiment 1 in that the gate electrode 8m is a trench gate and that it includes a sidewall grounding layer 41, a bottom layer 42, and a high-concentration layer 43.

[0057] A high electric field is formed at the interface between the bottom layer 42 formed under the trench gate and the drift layer 3. When the electrons accelerated by this high electric field collide with the atoms in the drift layer 3, new electron-hole pairs are generated, and an avalanche current occurs. The electrons flow through the drift layer 3 to the drain electrode 12, and the holes flow through the sidewall grounding layer 41 to the contact region 9h.

[0058] As shown in FIG. 14, in the high-voltage withstand MOSFET 21, since the sidewall grounding layer 41 is formed directly under the contact region 9h, the holes 45 flow straight from the interface region 47 between the bottom layer 42 and the drift layer 3 through the sidewall grounding layer 41 toward the contact region 9h, without affecting the channel 44 of the MOSFET.

[0059] On the other hand, as shown in FIG. 15, in the monitor MOSFET 22, since the sidewall grounding layer 41 is not formed directly under the contact region 9h, the holes 45 flow into the contact region 9m via the p-layer that becomes the channel 44 of the MOSFET. Therefore, in the monitor MOSFET 22, the hole injection from the channel region to the gate oxide film becomes excessive, and the variation in the threshold voltage becomes larger compared to the high-voltage withstand MOSFET 21.

[0060] <E-2. Manufacturing Process> FIGS. 16 to 21 show the manufacturing process of the semiconductor device 105.

[0061] As shown in FIG. 16, Al ions and N ions are implanted into the n-type drift layer 3 to form a p-type well region 4 and an n-type source region 5. Then, a SiO2 film 48 is deposited, and photolithography is performed to form a trench. By using the SiO2 film 48 remaining after the trench formation and implanting Al ions in self-alignment, the bottom layer 42 is formed at the bottom of the trench.

[0062] Next, as shown in FIG. 第十七, after removing the SiO2 film 48, inclined N ion implantation is performed on both sidewalls of the trench to form an n-type high-concentration layer 43.

[0063] Next, photoresist 49 is formed only in the regions where the sidewall grounding layer 41 is not formed, and AI ion implantation is performed with an inclination toward one side wall of the trench. As a result, as shown in Figure 18, the sidewall grounding layer 41 is formed on the side wall of the trench in the regions where photoresist 49 is not formed, and as shown in Figure 19, the sidewall grounding layer 41 is not formed in the regions where photoresist 49 is formed.

[0064] Subsequently, as shown in Figure 20, a p-type contact region 9 is formed, and after ion implantation-activated annealing, a gate electrode 8 is formed in the trench via the gate insulating film 7. At this time, the cross-sectional shape of the region where the sidewall grounding layer 41 is not formed is as shown in Figure 21.

[0065] Following this, contact formation, metallization, and other processes are carried out to complete the semiconductor device 105.

[0066] In Figures 16 to 20, well region 4 corresponds to well region 4h or well region 4m. Similarly, source region 5 corresponds to source region 5h or source region 5m, gate insulating film 7 corresponds to gate insulating film 7h or gate insulating film 7m, gate electrode 8 corresponds to gate electrode 8h or gate electrode 8m, and contact region 9 corresponds to contact region 9h or contact region 9m.

[0067] In the semiconductor device 105 according to Embodiment 5, in the high-voltage withstand MOSFET 21, the sidewall grounding layer 41, which is an electric field relaxation layer, is provided directly below the contact region 9h, and in the monitor MOSFET 22, the sidewall grounding layer 41 is not provided directly below the contact region 9m. Thus, in the semiconductor device 105, by changing the arrangement of the electric field relaxation layer on the bottom surface of the trench gate between the high-voltage withstand MOSFET 21 and the monitor MOSFET 22, the amount of change in the threshold voltage due to the avalanche operation can be increased in the monitor MOSFET 22. As a result, by taking the difference in the amount of change in the threshold voltage between the high-voltage withstand MOSFET 21 and the monitor MOSFET 22, the difference in the amount of change in the threshold voltage due to the avalanche operation between the high-voltage withstand MOSFET 21 and the monitor MOSFET 22 can be extracted. By grasping in advance how much the threshold voltage changes due to the avalanche operation due to the difference in the arrangement of the electric field relaxation layer, from the difference in the amount of change in the threshold voltage due to the avalanche operation in the high-voltage withstand MOSFET 21 and the monitor MOSFET 22, the amount of change in the threshold voltage due to the avalanche operation in each of the high-voltage withstand MOSFET 21 and the monitor MOSFET 22 can be specified. In this way, in each of the high-voltage withstand MOSFET 21 and the monitor MOSFET 22, the amount of change in the threshold voltage due to the avalanche operation and the amount of change in the threshold voltage due to the switching operation can be separated.

[0068] <F. Embodiment 6> This embodiment applies the semiconductor device according to the above-described Embodiments 1-5 to a power conversion device. The application of the semiconductor device according to Embodiments 1-5 is not limited to a specific power conversion device, but hereinafter, as Embodiment 6, a case where the semiconductor device according to Embodiments 1-5 is applied to a three-phase inverter will be described.

[0069] FIG. 22 is a block diagram showing the configuration of a power conversion system to which the power conversion device according to this embodiment is applied.

[0070] The power conversion system shown in Figure 22 consists of a power supply 100, a power converter 200, and a load 300. The power supply 100 is a DC power supply and supplies DC power to the power converter 200. The power supply 100 can be made up of various components, for example, a DC grid, a solar cell, or a battery, or it may be made up of a rectifier circuit or AC / DC converter connected to an AC grid. Alternatively, the power supply 100 may be made up of a DC / DC converter that converts DC power output from a DC grid into a predetermined power.

[0071] The power converter 200 is a three-phase inverter connected between the power supply 100 and the load 300. It converts the DC power supplied from the power supply 100 into AC power and supplies the AC power to the load 300. As shown in Figure 22, the power converter 200 includes a main conversion circuit 201 that converts DC power into AC power and outputs it, a drive circuit 202 that outputs drive signals to drive each switching element of the main conversion circuit 201, and a control circuit 203 that outputs control signals to the drive circuit 202 to control the drive circuit 202.

[0072] Load 300 is a three-phase motor driven by AC power supplied from power converter 200. Note that Load 300 is not limited to a specific application; it is a motor installed in various electrical devices, such as hybrid vehicles, electric vehicles, railway vehicles, elevators, or air conditioning equipment.

[0073] The details of the power converter 200 are described below. The main conversion circuit 201 is equipped with switching elements and freewheeling diodes (not shown), and by switching the switching elements, it converts the DC power supplied from the power supply 100 into AC power and supplies it to the load 300. There are various specific circuit configurations for the main conversion circuit 201, but the main conversion circuit 201 according to this embodiment is a two-level three-phase full-bridge circuit and can be composed of six switching elements and six freewheeling diodes antiparallel to each switching element. A semiconductor device according to any of the above-described embodiments ○○ is applied to each switching element of the main conversion circuit 201. The six switching elements are connected in series in pairs to form upper and lower arms, and each upper and lower arm constitutes each phase (U phase, V phase, W phase) of the full-bridge circuit. The output terminals of each upper and lower arm, i.e., the three output terminals of the main conversion circuit 201, are connected to the load 300.

[0074] The drive circuit 202 generates drive signals to drive the switching elements of the main conversion circuit 201 and supplies them to the control electrodes of the switching elements of the main conversion circuit 201. Specifically, according to the control signal from the control circuit 203, which will be described later, it outputs drive signals to turn on the switching elements and drive signals to turn off the switching elements to the control electrodes of each switching element. When the switching elements are kept in the ON state, the drive signal is a voltage signal (ON signal) that is greater than or equal to the threshold voltage of the switching elements, and when the switching elements are kept in the OFF state, the drive signal is a voltage signal (OFF signal) that is less than or equal to the threshold voltage of the switching elements.

[0075] The control circuit 203 controls the switching elements of the main converter circuit 201 so that the desired power is supplied to the load 300. Specifically, it calculates the time (on time) that each switching element of the main converter circuit 201 should be in the ON state based on the power to be supplied to the load 300. For example, the main converter circuit 201 can be controlled by PWM control, which modulates the on time of the switching elements according to the voltage to be output. Then, it outputs a control command (control signal) to the drive circuit 202 so that an ON signal is output to the switching elements that should be in the ON state at each point in time, and an OFF signal is output to the switching elements that should be in the OFF state. The drive circuit 202 outputs an ON signal or an OFF signal as a drive signal to the control electrode of each switching element according to this control signal.

[0076] In the power conversion device according to this embodiment, the semiconductor device 101-105 according to Embodiment 1-5 is used as the switching element of the main conversion circuit 201. Therefore, even when fluctuations in threshold voltage caused by switching operation and specific operation occur simultaneously, the degree of characteristic degradation can be measured.

[0077] In this embodiment, an example of applying the semiconductor device 101-105 according to Embodiment 1-5 to a two-level three-phase inverter has been described. However, the application of the semiconductor device 101-105 according to Embodiment 1-5 is not limited to this, and it can be applied to various power conversion devices. In this embodiment, a two-level power conversion device is used, but a three-level or multi-level power conversion device may also be used. Furthermore, when supplying power to a single-phase load, the semiconductor device 101-105 according to Embodiment 1-5 may be applied to a single-phase inverter. In addition, when supplying power to a DC load, it is also possible to apply the semiconductor device 101-105 according to Embodiment 1-5 to a DC / DC converter or an AC / DC converter.

[0078] Furthermore, the power conversion device to which the semiconductor devices 101-105 according to Embodiments 1-5 are applied is not limited to cases where the load is an electric motor, but can also be used, for example, as a power supply device for an electrical discharge machine, a laser processing machine, an induction heating cooker, or a contactless power supply system, and can even be used as a power conditioner for a solar power generation system or an energy storage system.

[0079] Although preferred embodiments have been described in detail above, the invention is not limited to the above embodiments, and various modifications and substitutions can be made to the above embodiments without departing from the scope of the claims. [Explanation of symbols]

[0080] 1 Semiconductor substrate, 2 Semiconductor layer, 3 Drift layer, 4,4h,4j,4m Well region, 5,5h,5j,5m Source region, 7 Gate insulating film, 7h,7m Gate insulating film, 8,8h,8m Gate electrode, 9,9h,9j,9m Contact region, 11h,11j,11m Source electrode, 12 Drain electrode, 13h,13j,13m Interlayer insulating film, 23 PN junction element, 30 Chip, 31h,31m Contact hole, 32h,32j,32m Barrier metal, 41 Sidewall grounding layer, 42 Bottom layer, 43 High-concentration layer, 44 Channel, 45 Hole, 47 Interface region, 48 SiO2 film, 49 Photoresist, 100 Power supply, 101-105 Semiconductor device, 200 Power converter, 201 Main converter circuit, 202 Drive circuit, 203 control circuit, 300 load.

Claims

1. A first-type conductive semiconductor substrate and A first semiconductor element having a MOS gate structure formed on the semiconductor substrate, The semiconductor substrate comprises at least one second semiconductor element having a MOS gate structure formed on the semiconductor substrate, Between the first semiconductor element and the second semiconductor element, either the threshold voltage fluctuation amount caused by the switching operation or the threshold voltage fluctuation amount caused by a specific operation that causes the threshold voltage to fluctuate in a direction different from the switching operation is different. Each of the first semiconductor element and the second semiconductor element is, A first conductivity type drift layer formed on the semiconductor substrate, The drift layer comprises a second conductive well region formed on the surface layer, The impurity concentration in the well region of the second semiconductor device is lower than the impurity concentration in the well region of the first semiconductor device. Semiconductor equipment.

2. The aforementioned specific operation is an avalanche operation. The semiconductor device according to claim 1.

3. The gate electrode of the first semiconductor element and the gate electrode of the second semiconductor element are electrically connected. Between the first semiconductor element and the second semiconductor element, the threshold voltage amount due to the avalanche operation is different. The semiconductor device according to claim 2.

4. The aforementioned at least one second semiconductor element is a plurality of second semiconductor elements, The impurity concentrations in the well regions of each of the plurality of second semiconductor elements are different. The semiconductor device according to claim 1.

5. The gate electrode of the second semiconductor element is connected to a different potential from the gate electrode of the first semiconductor element. The semiconductor device according to claim 1.

6. The first semiconductor element and the second semiconductor element are MOSFETs. The source electrode of the first semiconductor element and the source electrode of the second semiconductor element are electrically connected. The gate electrode of the first semiconductor element and the gate electrode of the second semiconductor element are electrically connected. The drain electrode of the first semiconductor element and the drain electrode of the second semiconductor element are electrically connected. The semiconductor device according to claim 1.

7. The cell area of ​​the second semiconductor element is 10 times the cell area of ​​the first semiconductor element. －７ more than 10 times －３ It is less than double. The semiconductor device according to claim 6.

8. As the operating time progresses, the threshold voltage of the second semiconductor element decreases, and the threshold voltage of the first semiconductor element increases. The semiconductor device according to claim 6.

9. In the initial characteristics at the time of shipment, the threshold voltage of the first semiconductor element and the threshold voltage of the second semiconductor element are the same. The semiconductor device according to claim 6.

10. A semiconductor substrate of a first conductivity type, A first semiconductor element having a MOS gate structure formed on the semiconductor substrate, The semiconductor substrate comprises at least one second semiconductor element having a MOS gate structure formed on the semiconductor substrate, Between the first semiconductor element and the second semiconductor element, either the threshold voltage fluctuation amount caused by the switching operation or the threshold voltage fluctuation amount caused by a specific operation that causes the threshold voltage to fluctuate in a direction different from the switching operation is different. A pn junction element without a MOS gate structure is provided in a region on the semiconductor substrate that is different from the first semiconductor element and the second semiconductor element. Each of the first semiconductor element, the second semiconductor element, and the pn junction element is, A first conductivity type drift layer formed on the semiconductor substrate, The drift layer comprises a second conductive well region formed on the surface layer, The impurity concentration in the well region of the second semiconductor element and the pn junction element is lower than the impurity concentration in the well region of the first semiconductor element. Semiconductor equipment.

11. A semiconductor substrate of a first conductivity type, A first semiconductor element having a MOS gate structure formed on the semiconductor substrate, The semiconductor substrate comprises at least one second semiconductor element having a MOS gate structure formed on the semiconductor substrate, Between the first semiconductor element and the second semiconductor element, either the threshold voltage fluctuation amount caused by the switching operation or the threshold voltage fluctuation amount caused by a specific operation that causes the threshold voltage to fluctuate in a direction different from the switching operation is different. The first semiconductor element and the second semiconductor element are trench-type MOSFETs. The trench-type MOSFET is A first conductive drift layer, A second conductive well layer formed on the drift layer, A first conductivity type source region formed on the surface of the well layer, A trench that penetrates the source region and the well layer and reaches the drift layer, A second conductive bottom layer formed at the bottom of the trench, A second conductive field relaxation layer connects the bottom layer and the well layer in the side wall of the trench, The well layer in which the source region is not formed comprises a second conductivity type contact region that contacts the source electrode, In the first semiconductor device, the electric field relaxation layer is provided directly below the contact region. In the second semiconductor device, the electric field relaxation layer is not provided directly beneath the contact region. Semiconductor equipment.

12. A semiconductor device according to any one of claims 1 to 11, comprising a main conversion circuit that converts and outputs input power, A drive circuit that outputs a drive signal to the semiconductor device for driving the semiconductor device, The system includes a control circuit that outputs a control signal to the drive circuit for controlling the drive circuit, Power converter.

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