Photoelectric converter

Abstract

To provide a photoelectric conversion device capable of outputting signals of higher quality.SOLUTION: A photoelectric conversion device includes: a plurality of pixels arranged to form a plurality of columns; output lines arranged corresponding to each of the plurality of columns, through which signals are output from corresponding pixels; and comparison units arranged corresponding to the plurality of columns, respectively, and each having a first input terminal and a second input terminal, the first input terminal receiving an input signal corresponding to a potential of the output line, the second input terminal receiving a reference signal as input. The comparison unit performs an offset clamping operation, and then performs comparison for analog-to-digital conversion of a signal input from a pixel.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a photoelectric conversion device.

Background Art

[0002] Patent Document 1 discloses a solid-state imaging device having an analog-to-digital (AD) conversion circuit that converts a pixel signal output from a pixel into a digital signal. The solid-state imaging device disclosed in Patent Document 1 reduces image quality degradation due to streaking that may occur during the operation of the AD converter by shorting vertical signal lines between columns.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, in the method disclosed in Patent Document 1 described above, when a defect occurs in the output signal of a certain pixel, the output signals of other pixels without defects may be affected by shorting a plurality of vertical signal lines. As a result, the quality of the output signal may deteriorate.

[0005] Therefore, an object of the present invention is to provide a photoelectric conversion device that can output a higher-quality signal.

Means for Solving the Problems

[0006] According to one aspect of the present invention, the present invention comprises a plurality of pixels arranged in a plurality of rows, output lines arranged corresponding to each of the plurality of rows and from which signals are output from the corresponding pixels, and a comparison unit arranged corresponding to each of the plurality of rows and having a first input terminal and a second input terminal, wherein a signal corresponding to the potential of the output line is input to the first input terminal and a reference signal is input to the second input terminal, the plurality of pixels include a first pixel and a second pixel, the comparison unit is capable of performing an offset clamp operation to set an offset based on the potentials input to the first input terminal and the second input terminal, the comparison unit performs the offset clamp operation based on the signal output from the first pixel, and thereafter, With the comparison unit holding the result of the offset clamp operation based on the signal output from the first pixel, the comparison unit A photoelectric converter is provided, characterized by performing a comparison for analog-to-digital conversion of the signal output from the second pixel.

[0007] According to one aspect of the present invention, the present invention comprises a plurality of pixels arranged in a plurality of rows, an output line arranged corresponding to each of the plurality of rows and from which a signal is output from the corresponding pixel, a comparison unit arranged corresponding to each of the plurality of rows and having a first input terminal and a second input terminal, the first input terminal receiving a signal corresponding to the potential of the output line and the second input terminal receiving a reference signal, and a second buffer arranged between the signal line to which the reference signal is supplied and the second input terminal, corresponding to each of the plurality of rows, wherein the plurality of rows include a first row and a second row, the comparison unit is capable of performing an offset clamp operation to set an offset based on the potentials input to the first input terminal and the second input terminal, the comparison unit of the second row performs the offset clamp operation based on the signal output from the second buffer of the first row, and thereafter performs a comparison for analog-to-digital conversion of the signal output from the pixels of the second row. Based on the signal output from the second buffer of the second column A photoelectric conversion device is provided, characterized by performing the following actions. [Effects of the Invention]

[0008] According to the present invention, a photoelectric converter capable of outputting higher quality signals is provided. [Brief explanation of the drawing]

[0009] [Figure 1] This block diagram shows a schematic configuration of the photoelectric conversion device according to the first embodiment. [Figure 2] This is a circuit diagram showing the configuration of pixels and column circuits according to the first embodiment. [Figure 3] This is a timing diagram showing the driving method of the photoelectric converter according to the first embodiment. [Figure 4] This is a timing diagram showing the driving method of the photoelectric converter according to the first embodiment. [Figure 5] This is a circuit diagram showing the configuration of the pixels and column circuits according to the second embodiment. [Figure 6] This is a circuit diagram showing the configuration of pixels and column circuits according to the third embodiment. [Figure 7] This is a circuit diagram showing the configuration of the pixel and column circuits according to the fourth embodiment. [Figure 8] This is a circuit diagram showing the configuration of the pixel and column circuits according to the fifth embodiment. [Figure 9] This is a block diagram of the equipment according to the sixth embodiment. [Figure 10] This is a block diagram of the equipment according to the seventh embodiment. [Modes for carrying out the invention]

[0010] Embodiments of the present invention will be described below with reference to the drawings. Elements identical or corresponding to each other across multiple drawings are denoted by the same reference numerals, and their descriptions may be omitted or simplified.

[0011] In the first to fifth embodiments described below, the imaging device will be described as an example of a photoelectric conversion device. However, the photoelectric conversion device in each embodiment is not limited to an imaging device and can be applied to other devices as well. Examples of other devices include distance measuring devices and photometric devices. A distance measuring device may be, for example, a focus detection device or a distance measuring device using TOF (Time-Of-Flight). A photometric device may be a device that measures the amount of light incident on the device.

[0012] [First Embodiment] FIG. 1 is a block diagram showing a schematic configuration of a photoelectric conversion device according to the first embodiment. The photoelectric conversion device includes a pixel array 10, a current source 13, a vertical scanning circuit 14, a timing generator 15, a reference signal generation circuit 16, a counter 17, a digital signal processing circuit 18, and a readout circuit 19.

[0013] The pixel array 10 has a plurality of pixels 100 arranged in a matrix over a plurality of rows and a plurality of columns. Each of the plurality of pixels 100 includes a photoelectric conversion unit composed of a photoelectric conversion element such as a photodiode. The pixel 100 outputs a photoelectric conversion signal, which is an analog signal corresponding to the amount of incident light on the photoelectric conversion element. The pixel 100 also outputs a noise signal, which is an analog signal of the noise level. Note that the pixel array 10 may have optical black pixels (not shown) in which the photoelectric conversion elements are shielded from light, and the output signals thereof are used as a reference for the black level.

[0014] In each row of the pixel array 10, a plurality of control lines 11 are arranged extending in a first direction (the horizontal direction in FIG. 1). Each of the plurality of control lines 11 is connected to the pixels 100 arranged in the first direction, and forms a common signal line for these pixels 100. The first direction in which the control line 11 extends is sometimes referred to as the row direction or the horizontal direction. The control line 11 is connected to the vertical scanning circuit 14.

[0015] In each column of the pixel array 10, output lines 12 are arranged extending in a second direction (the vertical direction in FIG. 1) intersecting the first direction. Each of the output lines 12 is connected to the pixels 100 arranged in the second direction, and forms a common signal line for these pixels 100. The second direction in which the output line 12 extends is sometimes referred to as the column direction or the vertical direction. Each of the output lines 12 is connected to the readout circuit 19 and the current source 13 arranged corresponding to each column.

[0016] The vertical scanning circuit 14 is a control circuit that receives a control signal output from the timing generator 15, generates a control signal for driving the pixel 100, and supplies it to the pixel 100 via the control line 11. Logic circuits such as a shift register and an address decoder can be used for the vertical scanning circuit 14. The vertical scanning circuit 14 drives the pixels 100 of the pixel array 10 in row units. The signals read out from the pixels 100 in row units are input to the readout circuit 19 via the output lines 12 provided for each column of the pixel array 10.

[0017] In FIG. 1, only three rows and three columns of the pixel 100, the control line 11, and the output line 12 are shown, but actually, the pixel 100, the control line 11, and the output line 12 can be arranged over thousands of rows and thousands of columns.

[0018] The readout circuit 19 includes a column circuit 20 provided corresponding to the output line 12 of each column and a horizontal scanning circuit 25. The column circuit 20 has a function of reading out the noise signal and the photoelectric conversion signal output from the pixel 100 and converting them into digital signals, and a function of holding the digital signals after AD conversion. The column circuit 20 includes an amplification unit 21, an analog signal holding unit 22, an AD conversion unit 23, and a digital signal holding unit 24.

[0019] The amplification unit 21 amplifies the noise signal and the photoelectric conversion signal output from the pixel 100 and outputs an analog signal. The analog signal holding unit 22 temporarily holds the analog signal output from the amplification unit 21. Also, the analog signal holding unit 22 outputs the held signal.

[0020] The reference signal generation circuit 16 receives a control signal output from the timing generator 15 and generates a reference signal to be supplied to the AD conversion unit 23. The reference signal is a signal having a predetermined amplitude and may include, for example, a signal whose signal level (signal magnitude) changes over time. The reference signal typically includes a ramp signal. A ramp signal is a signal whose signal level changes monotonically over time, for example, a signal whose output voltage monotonically decreases or increases over time. The reference signal is not particularly limited as long as it has an amplitude applicable to AD conversion.

[0021] The AD conversion unit (analog-to-digital conversion unit) 23 compares the signal output from the analog signal holding unit 22 with the reference signal output from the reference signal generation circuit 16, and outputs a latch signal based on the comparison result to the digital signal holding unit 24.

[0022] The counter 17 generates a count signal whose value changes over time by counting the pulses of the clock signal, and outputs it to the digital signal holding unit 24.

[0023] The digital signal holding unit 24 holds the count signal output from the counter 17 as a digital signal at the timing when the latch signal output from the AD conversion unit 23 changes. The digital signal holding unit 24 can hold the digital values ​​of both the noise signal and the photoelectric conversion signal.

[0024] The horizontal scanning circuit 25 performs scanning, sequentially supplying control signals to the digital signal holding units 24 of each column. As a result, the digital signals held in the digital signal holding units 24 of each column are sequentially transferred to the digital signal processing circuit 18. The horizontal scanning circuit 25 may be configured using a shift register, an address decoder, or the like.

[0025] The digital signal processing circuit 18 processes the digital signals output from the digital signal holding units 24 of each column and outputs the processed signals to the outside of the photoelectric converter. Examples of signal processing performed by the digital signal processing circuit 18 include correction processing by digital correlation double sampling and amplification processing.

[0026] The timing generator 15 is a control circuit that supplies control signals to the vertical scanning circuit 14, the readout circuit 19, the reference signal generation circuit 16, and the counter 17 to control their operation and timing. At least a portion of the control signals supplied to the vertical scanning circuit 14, the readout circuit 19, the reference signal generation circuit 16, and the counter 17 may be supplied from outside the photoelectric converter.

[0027] Figure 2 is a circuit diagram showing the configuration of the pixel 100 and column circuit 20 according to this embodiment. Figure 2 shows in more detail the circuit configurations of two pixels 100 and a portion of the circuit configuration of the two column circuits 20 from the photoelectric converter in Figure 1. The two columns shown in Figure 2 are the nth column and the (n+1)th column (where n is a natural number). The nth column and the (n+1)th column are sometimes simply called the 1st column and the 2nd column. In some cases, the symbols of some elements in Figure 2 may be denoted by the subscript "a" to indicate that they are elements of the nth column or the (n+1)th column to indicate that they are elements of the (n+1)th column, if it is necessary to distinguish between elements of the two columns. Since the elements of the nth column and the (n+1)th column have generally the same configuration, the explanation of the elements of the (n+1)th column may be omitted.

[0028] Figure 2 shows pixels 100a and 100b, current source 13, amplification units 21a and 21b, analog signal holding units 22a and 22b, AD conversion units 23a and 23b, and switches 191 and 192. Other elements from Figure 1 are omitted from Figure 2.

[0029] Pixel 100a includes a photoelectric conversion element PD, a transfer transistor M1, a reset transistor M2, an amplification transistor M3, and a selection transistor M4.

[0030] The photoelectric conversion element PD is, for example, a photodiode. The anode of the photoelectric conversion element PD is connected to the ground node, and the cathode of the photoelectric conversion element PD is connected to the source of the transfer transistor M1. The drain of the transfer transistor M1 is connected to the source of the reset transistor M2 and the gate of the amplification transistor M3. Node FD, to which the drain of the transfer transistor M1, the source of the reset transistor M2, and the gate of the amplification transistor M3 are connected, is a so-called stray diffusion section. The stray diffusion section contains a capacitive component (stray diffusion capacitance) and functions as a charge holding section. The stray diffusion capacitance includes PN junction capacitance, wiring capacitance, etc.

[0031] The drains of reset transistor M2 and amplifier transistor M3 are connected to a power supply voltage node to which voltage VDD is supplied. The source of amplifier transistor M3 is connected to the drain of selection transistor M4. The source of selection transistor M4 is connected to output line 12.

[0032] In the pixel configuration shown in Figure 2, the control line 11 for each row includes a signal line connected to the gate of the transfer transistor M1, a signal line connected to the gate of the reset transistor M2, and a signal line connected to the gate of the selection transistor M4. The gate of the transfer transistor M1 is supplied with a control signal PTX from the vertical scanning circuit 14. The gate of the reset transistor M2 is supplied with a control signal PRES from the vertical scanning circuit 14. The gate of the selection transistor M4 is supplied with a control signal PSEL from the vertical scanning circuit 14. Multiple pixels 100a, 100b in the same row are connected to a common signal line and are controlled simultaneously by a common control signal.

[0033] In this embodiment, the explanation assumes that electrons are used as the signal charge among the electron-hole pairs generated by the photoelectric conversion element PD upon light incidence. When electrons are used as the signal charge, each transistor constituting the pixel 100a may be composed of an N-type MOS transistor. When each transistor is composed of an N-type MOS transistor, the corresponding transistor turns on when a high-level control signal is supplied from the vertical scanning circuit 14. Conversely, the corresponding transistor turns off when a low-level control signal is supplied from the vertical scanning circuit 14. However, the signal charge is not limited to electrons; holes may also be used as the signal charge. When holes are used as the signal charge, the conductivity type of each transistor will be the opposite conductivity type to that described in this embodiment. Also, the names of the source and drain of the MOS transistor may differ depending on the conductivity type of the transistor or the function of interest. Some or all of the source and drain names used in this embodiment may also be referred to by their reverse names.

[0034] The photoelectric element PD converts incident light into an amount of electric charge corresponding to the amount of light (photoelectric conversion). When the transfer transistor M1 is turned on, it transfers the charge held by the photoelectric element PD to the node FD. The charge transferred from the photoelectric element PD is held in the capacitance (stray diffusion capacitance) of the node FD. As a result, the potential of the node FD is determined by the charge-voltage conversion due to the stray diffusion capacitance, corresponding to the amount of charge transferred from the photoelectric element PD.

[0035] The select transistor M4, when turned on, connects the amplifier transistor M3 to the output line 12. The amplifier transistor M3 is configured such that a voltage VDD is supplied to its drain and a bias current is supplied to its source from the current source 13 via the select transistor M4, forming an amplifier circuit (source follower circuit) with its gate as the input node. As a result, the amplifier transistor M3 outputs a signal based on the voltage of node FD to the output line 12 via the select transistor M4. In this sense, the amplifier transistor M3 and the select transistor M4 are output sections that output a pixel signal corresponding to the amount of charge held at node FD.

[0036] The reset transistor M2 has the function of controlling the supply of a voltage (voltage VDD) to node FD for resetting node FD, which acts as a charge holder. When the reset transistor M2 is turned on, it resets node FD to a voltage corresponding to voltage VDD.

[0037] The amplifier section 21a includes an input capacitor 211, a differential amplifier 212, a feedback capacitor 213, and a switch 214. The first terminal of the input capacitor 211 is the input node of the amplifier section 21a. The first terminal of the input capacitor 211 is connected to the output line 12. The second terminal of the input capacitor 211 is connected to the inverting input terminal of the differential amplifier 212, the first terminal of the feedback capacitor 213, and the first terminal of the switch 214. A power line having a reference voltage Vc0r is connected to the non-inverting input terminal of the differential amplifier 212. The output terminal of the differential amplifier 212 is the output node of the amplifier section 21a. The output terminal of the differential amplifier 212 is connected to the second terminal of the feedback capacitor 213 and the second terminal of the switch 214.

[0038] With the circuit configuration described above, the amplification unit 21a functions as an inverting amplifier circuit that amplifies the voltage of the analog signal output to the output line 12. Switch 214 is controlled by a control signal from the timing generator 15 and is controlled to be on or off. When switch 214 transitions from on to off, the potential input to input capacitor 211 at that time is clamped. The amplification factor of the amplification unit 21a when switch 214 is off is determined by the ratio of the capacitance value of input capacitor 211 to the capacitance value of feedback capacitor 213.

[0039] The analog signal holding unit 22a includes a switch 221, a holding capacitor 222, and an amplifier 223. The output node of the amplifier 21a is connected to the first terminal of the switch 221. The first terminal of the switch 221 is the input node of the analog signal holding unit 22a. The second terminal of the switch 221 is connected to the input terminals of the holding capacitor 222 and the amplifier 223. The output terminal of the amplifier 223 is the output node of the analog signal holding unit 22a.

[0040] The holding capacitor 222 holds the analog signal output from the amplification unit 21a. The amplifier 223 (first buffer) is a buffer circuit such as a source follower and outputs an analog signal corresponding to the potential held in the holding capacitor 222. In this way, the analog signal holding unit 22a is a sample-and-hold circuit that holds the analog signal output from the amplification unit 21a.

[0041] Four switches, including switches 191, 192, switch 221 in the nth column, and switch 221 in the (n+1)th column, form a signal switching circuit. The first terminal of switch 191 is connected to the node of the first terminal of switch 221 in the nth column. The second terminal of switch 191 is connected to the node where the second terminal of switch 221 in the (n+1)th column and the holding capacitor 222 in the (n+1)th column are connected. The first terminal of switch 192 is connected to the node of the first terminal of switch 221 in the (n+1)th column. The second terminal of switch 192 is connected to the node where the second terminal of switch 221 in the nth column and the holding capacitor 222 in the nth column are connected.

[0042] Switches 191 and 192 are controlled by a control signal sw from the timing generator 15, and are switched on or off. Similarly, switch 221 is controlled by a control signal swb from the timing generator 15, and is switched on or off. The control signal swb is a signal with a potential at the opposite level to the control signal sw. When the control signal sw is at a low level and the control signal swb is at a high level, switch 221 is turned on and switches 191 and 192 are turned off. At this time, the signal output from the nth column amplifier 21a is held in the nth column holding capacitor 222, and the signal output from the (n+1)th column amplifier 21b is held in the (n+1)th column holding capacitor 222.

[0043] In contrast, when control signal sw is at a high level and control signal swb is at a low level, switches 191 and 192 are turned on, and switch 221 is turned off. At this time, the signal output from the nth column amplifier 21a is held in the (n+1)th column holding capacitor 222, and the signal output from the (n+1)th column amplifier 21b is held in the nth column holding capacitor 222. Thus, the signal switching circuit including switches 191 and 192, the nth column switch 221, and the (n+1)th column switch 221 has the function of swapping the signal in the nth column and the signal in the (n+1)th column with each other according to the control signals sw and swb.

[0044] Furthermore, the potential of the analog signal output from the analog signal holding unit 22a in the nth column is defined as comp_in[n], and the potential of the analog signal output from the analog signal holding unit 22b in the (n+1)th column is defined as comp_in[n+1].

[0045] The AD conversion unit 23a includes input capacitors 231 and 236, a comparator 232, switches 233 and 234, and an amplifier 235. The comparator 232 is a fully differential comparator having a first input terminal, a second input terminal, a first output terminal, and a second output terminal, and functions as a comparator for AD conversion. The comparator 232 compares the potentials of the first input terminal and the second input terminal, and outputs a signal based on the comparison result as an output signal OUT from the first output terminal and the second output terminal. This output signal is input to a latch circuit (not shown). The latch circuit outputs the latch signal to the digital signal holding unit 24.

[0046] The output node of the analog signal holding unit 22a is connected to the first terminal of the input capacitor 231 (first input capacitor). The first terminal of the input capacitor 231 is the input node of the AD conversion unit 23a. The second terminal of the input capacitor 231 is connected to the first input terminal of the comparator 232 and the first terminal of the switch 233. The second terminal of the switch 233 is connected to the first output terminal of the comparator 232.

[0047] The reference signal Vramp from the reference signal generation circuit 16 is input to the input terminal of amplifier 235. Amplifier 235 (second buffer) is a buffer circuit such as a source follower. The output terminal of amplifier 235 is connected to the first terminal of input capacitor 236 (second input capacitor). The second terminal of input capacitor 236 is connected to the second input terminal of comparator 232 and the first terminal of switch 234. The second terminal of switch 234 is connected to the second output terminal of comparator 232. Switches 233 and 234 are controlled by the control signal comp_res from the timing generator 15, and are controlled to be on or off. When the control signal comp_res is at a high level, switches 233 and 234 are on, and when the control signal comp_res is at a low level, switches 233 and 234 are off.

[0048] Figure 3 is a timing diagram showing the driving method of the photoelectric converter according to this embodiment. Figure 3 shows the levels of the control signals comp_res and sw, the potential of the reference signal Vramp, and the potentials of the input signals comp_in[n] and comp_in[n+1]. The level of the control signal swb is the opposite level of the control signal sw and is therefore obvious, so it is not shown. Also, "Var" in Figure 3 schematically shows the variation in the timing of the change in the level of the output signal of the comparator 232 in each column. The period from time t10 to time t17 in Figure 3 is the period during which the AD conversion of the noise signal is performed by comparing the noise signal from the pixel 100 with the reference signal Vramp in the AD conversion unit 23. The driving timing of the AD conversion of the noise signal will be explained with reference to Figure 3.

[0049] At time t10, the control signal comp_res is at a high level, and switches 233 and 234 are on. As a result, the potentials of the first input terminal, second input terminal, first output terminal, and second output terminal of comparator 232 are reset. Also, the control signal sw is at a low level and the control signal swb is at a high level, so switches 191 and 192 are off and switch 221 is on.

[0050] The input signals comp_in[n] and comp_in[n+1] are signals in which noise generated in the amplification unit 21 and the analog signal holding unit 22 is superimposed on the noise signal output from pixel 100. The noise signal clamped by the amplification unit 21 contains a charge reinjection component when switch 214 transitions from on to off. Charge reinjection is the phenomenon in which the charge under the gate of the transistor constituting switch 214 moves to the inverting input terminal and output terminal of differential amplifier 212 when switch 214 transitions from on to off. The charge reinjection component included in the noise signal is different for each amplification unit 21 in each column. Therefore, at time t10, input signals comp_in[n] and comp_in[n+1] have different potentials.

[0051] At time t11, control signal sw becomes high level and control signal swb becomes low level. This turns on switches 191 and 192 and off switch 221. This operation swaps the analog signal held in the nth column's holding capacitor 222 with the analog signal held in the (n+1th)th column's holding capacitor 222. Therefore, the signal in the nth column is input to the AD converter 23b as input signal comp_in[n+1] via the (n+1th)th column's amplifier 223, and the signal in the (n+1th)th column is input to the AD converter 23a as input signal comp_in[n] via the nth column's amplifier 223. As a result, after time t11, the potentials of input signals comp_in[n] and comp_in[n+1] are swapped. Hereafter, this state may be referred to as the first state. Also, at time t11, the reference signal Vramp is set to the offset level.

[0052] At time t12, the control signal comp_res becomes low. This turns off switches 233 and 234. At time t12, the potential of the second input terminal of comparator 232 is the reset potential based on the offset level of the reference signal Vramp. The input capacitor 236 is clamped with a charge based on the offset level potential of the reference signal Vramp at time t12. Hereafter, this operation may be referred to as the offset clamp operation.

[0053] Furthermore, the input capacitor 231 is clamped with a charge based on the output potential of the comparator 232 at time t12. The potentials of the input signal comp_in[n] and the input signal comp_in[n+1] differ by ΔV. Therefore, the input capacitors 231 of the nth and n+1th columns are clamped with a potential that differs by ΔV. At time t11, the two potentials are swapped, so the potentials clamped to the input capacitors 231 of the nth and n+1th columns by the offset clamping operation are ΔV different from the potential of the input signal before time t11. The noise signal held in the input capacitor 231 includes the noise component of the AD converter 23. This noise component includes the charge reinjection component when switch 233 transitions from on to off. Also, the signal held in the input capacitor 236 includes the charge reinjection component when switch 234 transitions from on to off.

[0054] At time t13, the offset level setting of the reference signal Vramp is released. As a result, the potential of the reference signal Vramp returns to the potential it was at time t10.

[0055] At time t14, control signal sw becomes low level and control signal swb becomes high level. As a result, switches 191 and 192 are turned off and switch 221 is turned on. Therefore, the signal in the nth column is input to the AD converter 23a as input signal comp_in[n] via the amplifier 223 in the nth column, and the signal in the (n+1)th column is input to the AD converter 23b as input signal comp_in[n+1] via the amplifier 223 in the (n+1)th column. As a result, after time t14, the swapping of potentials between input signals comp_in[n] and comp_in[n+1] is canceled. Hereafter, this state may be referred to as the second state.

[0056] At time t15, the reference signal generation circuit 16 changes the potential of the reference signal Vramp in a time-dependent manner. Also at time t15, the counter 17 starts counting the clock signal.

[0057] Time t16 is the time when the potential of the reference signal Vramp exceeds the offset level. Around time t16, the relative magnitudes of the input signals comp_in[n], comp_in[n+1] and the reference signal Vramp are reversed, and the level of the output signal of the comparator 232 changes. As a result, a latch signal is output from the latch circuit to the digital signal holding unit 24. The digital signal holding unit 24, upon receiving the change in the latch signal, holds the count signal at that point in time. The count signal held by the digital signal holding unit 24 is a digital signal corresponding to the noise signal.

[0058] At time t17, the reference signal generation circuit 16 stops the change in the potential of the reference signal Vramp. The potential of the reference signal Vramp then returns to the potential it was at time t10. Also at time t17, the counter 17 stops the counting operation of the clock signal and resets the count value.

[0059] After time t17, the photoelectric conversion signal is converted to AD in the same way as the noise signal, and the digital signal corresponding to the photoelectric conversion signal is held in the digital signal holding unit 24. Subsequently, the horizontal scanning circuit 25 sequentially scans the digital signal holding units 24 in each column and outputs the digital signals held in the digital signal holding units 24 in each column to the digital signal processing circuit 18.

[0060] As described above, a digital signal based on a noise signal and a digital signal based on a photoelectric conversion signal are output from the column circuit 20 of each column to the digital signal processing circuit 18. The digital signal based on the photoelectric conversion signal contains a noise signal component. Therefore, the digital signal processing circuit 18 can generate a signal with less noise by subtracting the digital signal based on the noise signal from the digital signal based on the photoelectric conversion signal.

[0061] Figure 4 is a timing diagram showing the driving method in the photoelectric converter of this embodiment when switches 191 and 192 are not turned on, and switch 221 is kept on. The effects of this embodiment will be explained by referring to Figures 3 and 4 together.

[0062] In the driving method shown in Figure 3, during the period from time t11 to time t14, the control signal sw is at a high level and the control signal swb is at a low level. Therefore, during this period, switches 191 and 192 are on, and switch 221 is off. In contrast, in the driving method shown in Figure 4, during the period from time t21 to time t24, which corresponds to the period from time t11 to time t14, the control signal sw is maintained at a low level and the control signal swb is maintained at a high level. As a result, switches 191 and 192 do not turn on, and switch 221 remains on. This is the difference between Figure 4 and Figure 3. In other words, Figure 4 can be said to show the case where the signal switching circuit in this embodiment is not provided.

[0063] As shown in Figure 4, at time t22, the input signals comp_in[n] and comp_in[n+1] are at different potentials. Therefore, different potentials are clamped to the input capacitor 231 of the nth row and the input capacitor 231 of the (n+1)th row. In the example in Figure 4, the input signal comp_in[n] at time t22 and the input signal comp_in[n] at time t16 are almost identical. In this case, at time t16, when the potential of the reference signal Vramp exceeds the offset level, the level of the output signal of the comparator 232 in the nth column changes. Also, the input signal comp_in[n+1] at time t22 and the input signal comp_in[n+1] at time t16 are almost identical. In this case, at time t16, when the potential of the reference signal Vramp exceeds the offset level, the level of the output signal of the comparator 232 in the (n+1)th column also changes. Therefore, as shown in Figure 4, if the switch 191 is not turned on during the offset clamp operation, the level of the output signal of the comparator 232 in the nth column and the level of the output signal of the comparator 232 in the (n+1)th column change almost simultaneously. Consequently, as shown in "Var" in Figure 4, the variation in the timing of the changes in the output signal levels of the comparators 232 in each column is small.

[0064] If the timing variation in the level changes of the output signals of each row's comparator 232 is small, the levels of the output signals of multiple comparators 232 may change simultaneously within a short period of time. This can cause noise due to factors such as IR drop and current fluctuations. This noise effect is particularly pronounced when there are many rows of pixels 100, as many comparators 232 are arranged within the photoelectric converter. This noise can propagate to other comparators 232 through power supply or signal wiring that is commonly distributed between rows, which can degrade the quality of the output signal. Furthermore, in circuits downstream of the comparator 232, this noise can also degrade the quality of the output signal by causing AD conversion errors and reduced accuracy in the counting operation of the clock signal in the counter 17.

[0065] On the other hand, in the driving method shown in Figure 3, during the offset clamp operation at time t12, switches 191 and 192 are on and switch 221 is off, so the potentials between the nth and n+1th columns are swapped and clamped. As a result, in each of the nth and n+1th columns, the input potential of comparator 232 during the offset clamp operation at time t12 and the input potential of comparator 232 during AD conversion at time t16 are different potentials. That is, the potential of the input signal comp_in[n] during AD conversion is ΔV greater than that during the offset clamp operation. Also, the potential of the input signal comp_in[n+1] during AD conversion is ΔV smaller than that during the offset clamp operation.

[0066] In the driving method shown in Figure 3, as indicated by "Var" in Figure 3, there is a large variation in the timing of changes in the output signal levels of each column's comparator 232. Therefore, the output signal levels of multiple comparators 232 are less likely to change simultaneously within a short period of time, and the noise generated when the output signal levels of each column's comparator 232 change can be reduced.

[0067] In methods that short-circuit multiple vertical signal lines, such as those disclosed in Patent Document 1, if a defect occurs in the output signal of a certain pixel, the output signals of the pixels that are not defective and the output signals of the defective pixels may be averaged. This may degrade the quality of the output signals of the pixels that are not defective. In contrast, this embodiment has a configuration that allows the signals of multiple columns to be swapped, so the signal lines are not short-circuited, and thus the degradation of the output signal quality due to the above-mentioned factors can be reduced.

[0068] As described above, this embodiment provides a photoelectric converter capable of outputting higher quality signals.

[0069] In this embodiment, the output signals are swapped between different columns during the offset clamp operation. That is, the pixel that outputs the signal to be clamped during the offset clamp operation (first pixel) is located in the same row but a different column as the pixel that outputs the signal to be converted to AD (second pixel). However, the pixel that outputs the signal to be clamped during the offset clamp operation may be located in the same column but a different row as the pixel that outputs the signal to be converted to AD.

[0070] Furthermore, in this embodiment, switches 191 and 192 are controlled to be ON and switch 221 OFF during the offset clamp operation at time t12. However, if the potential of the input signal comp_in[n] is different between the offset clamp operation and the AD conversion, switches 191 and 192 may be turned OFF and switch 221 ON at a time before time t12.

[0071] Furthermore, the photoelectric converter of this embodiment may be configured to change the gain by changing the settings of the amplification unit 21 or the amount of change (slope) of the potential of the reference signal Vramp per unit time. In this case, the operation of switches 191, 192, and 221 during offset clamping may be made different according to the gain. Depending on the gain, the variation in the timing of the change in the level of the output signal of the comparator 232 may change. Alternatively, the degree of noise generated by the change in the level of the output signal may change according to the gain of the photoelectric converter. Thus, since the optimal control method may change depending on the gain, it may be desirable to change the operation of switches 191, 192, and 221.

[0072] Furthermore, the timing variation in the change in the level of the output signal of the comparator 232 can also vary depending on the temperature of the photoelectric converter. Therefore, the temperature of the photoelectric converter may be measured using a temperature sensor, and the operation of switches 191, 192, and 221 during offset clamping may be varied according to the temperature.

[0073] [Second Embodiment] The photoelectric converter according to this embodiment will now be described. Components similar to those in the first embodiment are denoted by the same reference numerals, and their descriptions may be omitted or simplified.

[0074] Figure 5 is a circuit diagram showing the configuration of the pixel 100 and the column circuit 20 according to this embodiment. In this embodiment, the photoelectric converter is equipped with switch 193 instead of switch 192 in Figure 2. In addition, in Figure 5, in addition to the circuits of the nth and n+1th columns in Figure 2, the circuit of the n+2th column is further illustrated. Note that the n+2nd column is sometimes simply called the third column. Also, the subscript "c" is sometimes attached to the reference numerals of some elements in Figure 5 to indicate that they are elements of the n+2nd column.

[0075] Five switches, including switches 191, 193, switch 221 in the nth column, switch 221 in the (n+1)th column, and switch 221 in the (n+2)th column, form a signal switching circuit. The first terminal of switch 191 is connected to the node of the first terminal of switch 221 in the nth column. The second terminal of switch 191 is connected to the node where the second terminal of switch 221 in the (n+1)th column and the holding capacitor 222 in the (n+1)th column are connected. The first terminal of switch 193 is connected to the node of the first terminal of switch 221 in the (n+1)th column. The second terminal of switch 193 is connected to the node where the second terminal of switch 221 in the (n+2)th column and the holding capacitor 222 in the (n+2)th column are connected.

[0076] Switches 191 and 193 are controlled by a control signal sw from the timing generator 15, and are switched on or off. Similarly, switch 221 is controlled by a control signal swb from the timing generator 15, and is switched on or off. The control signal swb is a signal with a potential at the opposite level to the control signal sw. When the control signal sw is at a low level and the control signal swb is at a high level, switch 221 is turned on, and switches 191 and 193 are turned off. At this time, the signals output from the nth column amplifier 21a, the (n+1)th column amplifier 21b, and the (n+2)th column amplifier 21c are held in the nth, (n+1)th, and (n+2)th column holding capacitors 222, respectively.

[0077] In contrast, when control signal sw is at a high level and control signal swb is at a low level, switches 191 and 193 are turned on, and switch 221 is turned off. At this time, the signal output from the nth column amplifier 21a is held in the (n+1)th column holding capacitor 222, and the signal output from the (n+1)th column amplifier 21b is held in the (n+2)th column holding capacitor 222. Thus, the signal switching circuit including switches 191 and 193, the nth column switch 221, the (n+1)th column switch 221, and the (n+2)th column switch 221 has the function of outputting the signal from each column to the next column in accordance with the control signals sw and swb.

[0078] The driving method of the photoelectric converter in this embodiment is the same as that shown in Figure 3. That is, switches 191 and 193 are on and switch 221 is off during the offset clamp operation at time t12. As a result, the input potential of comparator 232 during the offset clamp operation at time t12 and the input potential of comparator 232 during AD conversion at time t16 are different from each other. Therefore, as in the first embodiment, the levels of the output signals of multiple comparators 232 are less likely to change simultaneously in a short period of time, and noise generated when the levels of the output signals of comparators 232 in each row change can be reduced.

[0079] Thus, the same effects as in the first embodiment can be obtained in this embodiment as well. Therefore, according to this embodiment, a photoelectric converter capable of outputting higher quality signals is provided.

[0080] The signal switching circuit is not limited to switching signals between two columns, as in the first embodiment, but may also switch signals between three or more columns, as in the second embodiment. Furthermore, the switches constituting the signal switching circuit may be arranged between the signal lines of each column. In this case, some or all of the signals in all columns of the pixel array 10 can be switched. Also, the combination of columns to be switched may be changed each time a row of the pixel array 10 is read. In this case, the variation in the timing of changes in the level of the output signal of the comparator 232 becomes irregular in two dimensions, making the impact on image quality caused by this variation less noticeable.

[0081] [Third Embodiment] The photoelectric converter according to this embodiment will now be described. Components similar to those in the first embodiment are denoted by the same reference numerals, and their descriptions may be omitted or simplified.

[0082] Figure 6 is a circuit diagram showing the configuration of the pixel 100 and the column circuit 20 according to this embodiment. In this embodiment, the photoelectric converter is equipped with switches 194, 195, and 196 instead of switches 191 and 192 in Figure 2.

[0083] The output terminal of amplifier 223 is connected to the first terminal of switch 194. The second terminal of switch 194 is connected to the first terminal of input capacitor 231. The first terminal of switch 195 is connected to the node where the output terminal of amplifier 223 in the nth column and the first terminal of switch 194 in the nth column are connected. The second terminal of switch 195 is connected to the node where the second terminal of switch 194 in the (n+1)th column and the first terminal of input capacitor 231 in the (n+1)th column are connected. The first terminal of switch 196 is connected to the node where the output terminal of amplifier 223 in the (n+1)th column and the first terminal of switch 194 in the (n+1)th column are connected. The second terminal of switch 196 is connected to the node where the second terminal of switch 194 in the nth column and the first terminal of input capacitor 231 in the nth column are connected.

[0084] Switches 195 and 196 are controlled by a control signal sw from the timing generator 15, and are switched on or off. Switch 194 is also controlled by a control signal swb from the timing generator 15, and is switched on or off. The control signal swb is a signal with a potential at the opposite level to the control signal sw.

[0085] When control signal sw is at a low level and control signal swb is at a high level, switch 194 is turned on and switches 195 and 196 are turned off. At this time, the signal output from the nth column analog signal holding unit 22a is input to the nth column AD conversion unit 23a, and the signal output from the (n+1)th column analog signal holding unit 22b is input to the (n+1)th column AD conversion unit 23b.

[0086] When control signal sw is at a high level and control signal swb is at a low level, switch 194 is turned off, and switches 195 and 196 are turned on. At this time, the signal output from the nth column analog signal holding unit 22a is input to the (n+1)th column AD converter 23b, and the signal output from the (n+1)th column analog signal holding unit 22b is input to the nth column AD converter 23a. The rest of the circuit configuration is the same as in Figure 2, so the explanation is omitted.

[0087] Thus, in this embodiment, a signal switching circuit including switches 195, 196, the nth column switch 194, and the n+1th column switch 194 is arranged between the analog signal holding unit 22 and the AD conversion unit 23. The signal switching circuit has the function of swapping the nth column signal and the n+1th column signal with each other according to the control signals sw and swb.

[0088] The driving method of the photoelectric converter in this embodiment is the same as that shown in Figure 3. That is, switches 195 and 196 are on and switch 194 is off during the offset clamp operation at time t12. As a result, the input potential of comparator 232 during the offset clamp operation at time t12 and the input potential of comparator 232 during AD conversion at time t16 are different from each other. That is, the potential of input signal comp_in[n] during AD conversion is ΔV greater than that during the offset clamp operation. Also, the potential of input signal comp_in[n+1] during AD conversion is ΔV smaller than that during the offset clamp operation. Therefore, similar to the first embodiment, the levels of the output signals of multiple comparators 232 are less likely to change simultaneously in a short time, and noise generated when the levels of the output signals of comparators 232 in each column change can be reduced.

[0089] Thus, the same effects as in the first embodiment can be obtained in this embodiment as well. Therefore, according to this embodiment, a photoelectric converter capable of outputting higher quality signals is provided.

[0090] [Fourth Embodiment] The photoelectric converter according to this embodiment will now be described. Components similar to those in the third embodiment are denoted by the same reference numerals, and their descriptions may be omitted or simplified.

[0091] Figure 7 is a circuit diagram showing the configuration of the pixel 100 and the column circuit 20 according to this embodiment. The photoelectric converter of this embodiment is the same as the photoelectric converter of Figure 6, but with the amplification unit 21 and the analog signal holding unit 22 omitted. The output line 12 of the nth column is connected to the first terminal of switch 194 and the first terminal of switch 195 of the nth column, and the output line 12 of the (n+1)th column is connected to the first terminal of switch 194 and the first terminal of switch 196 of the (n+1)th column. The other circuit configurations are the same as in Figure 6, so their explanation is omitted.

[0092] Even in a configuration where the amplification unit 21 and the analog signal holding unit 22 are omitted, as in this embodiment, noise generated when the level of the output signal of each row of comparators 232 changes can be reduced in the third embodiment. Therefore, according to this embodiment, a photoelectric converter capable of outputting a higher quality signal is provided.

[0093] [Fifth Embodiment] The photoelectric converter according to this embodiment will now be described. Components similar to those in the first embodiment are denoted by the same reference numerals, and their descriptions may be omitted or simplified.

[0094] Figure 8 is a circuit diagram showing the configuration of the pixel 100 and the column circuit 20 according to this embodiment. In this embodiment, the photoelectric converter is equipped with switches 197, 198, and 199 instead of switches 191 and 192 in Figure 2.

[0095] The output terminal of amplifier 235 is connected to the first terminal of switch 197. The second terminal of switch 197 is connected to the first terminal of input capacitor 236. The first terminal of switch 198 is connected to the node where the output terminal of amplifier 235 in the nth column and the first terminal of switch 197 in the nth column are connected. The second terminal of switch 198 is connected to the node where the second terminal of switch 197 in the (n+1)th column and the first terminal of input capacitor 236 in the (n+1)th column are connected. The first terminal of switch 199 is connected to the node where the output terminal of amplifier 235 in the (n+1)th column and the first terminal of switch 197 in the (n+1)th column are connected. The second terminal of switch 199 is connected to the node where the second terminal of switch 197 in the nth column and the first terminal of input capacitor 236 in the nth column are connected.

[0096] Switches 198 and 199 are controlled by a control signal sw from the timing generator 15, and are switched on or off. Switch 197 is also controlled by a control signal swb from the timing generator 15, and is switched on or off. The control signal swb is a signal with a potential at the opposite level to the control signal sw.

[0097] When control signal sw is at a low level and control signal swb is at a high level, switch 197 is turned on and switches 198 and 199 are turned off. At this time, the signal output from amplifier 235 in the nth column is input to input capacitor 236 in the nth column, and the signal output from amplifier 235 in the (n+1)th column is input to input capacitor 236 in the (n+1)th column.

[0098] When control signal sw is at a high level and control signal swb is at a low level, switch 197 is turned off, and switches 198 and 199 are turned on. At this time, the signal output from amplifier 235 in the nth column is input to input capacitor 236 in the (n+1)th column, and the signal output from amplifier 235 in the (n+1)th column is input to input capacitor 236 in the nth column. The rest of the circuit configuration is the same as in Figure 2, so the explanation is omitted. Also, the driving method of the photoelectric converter is the same as in Figure 3, so the explanation is omitted.

[0099] The effects of this embodiment will now be explained. The reference signal Vramp is input to the amplifier 235 via a common reference signal line for each column. However, due to variations in the performance of the amplifiers 235 in each column, variations in wiring resistance, etc., the output node of the amplifier 235 in the nth row and the output node of the amplifier 235 in the (n+1)th row may be at different potentials. During the offset clamp operation at time t12 in Figure 3, the signal output from the amplifier 235 in the nth column is input to the input capacitor 236 of the (n+1)th column, and the signal output from the amplifier 235 in the (n+1)th column is input to the input capacitor 236 of the nth column. As a result, the input capacitor 236 of the nth column is clamped with a potential based on the signal from the amplifier 235 of the (n+1)th column, and the input capacitor 236 of the (n+1)th column is clamped with a potential based on the signal from the amplifier 235 of the nth column. In contrast, during the period from time t13 onward, the signal output from the amplifier 235 in the nth column is input to the input capacitor 236 in the nth column, and the signal output from the amplifier 235 in the (n+1)th column is input to the input capacitor 236 in the (n+1)th column. At this time, due to the swapping of the signals during clamping, the output nodes of the amplifier 235 in the nth row and the amplifier 235 in the (n+1)th row have different potentials due to variations. As a result, during the AD conversion at time t16, the potentials of the reference signals input to the comparators 232 in the nth and (n+1)th columns are different. Therefore, the levels of the output signals of multiple comparators 232 are less likely to change simultaneously, and noise generated when the levels of the output signals of the comparators 232 in each column change can be reduced.

[0100] As described above, this embodiment provides a photoelectric converter capable of outputting higher quality signals.

[0101] The above explanation assumes that the rate of change per unit time of the potentials of the reference signals in the nth and (n+1)th columns is the same during the AD conversion period, but this is not limited to this assumption. The rate of change per unit time of the potential of the reference signal in the nth column and the rate of change per unit time of the potential of the reference signal in the (n+1)th column may be different from each other.

[0102] [Sixth Embodiment] The photoelectric converter in the above-described embodiment is applicable to various devices. Examples of such devices include digital still cameras, digital camcorders, camera heads, photocopiers, fax machines, mobile phones, in-vehicle cameras, observation satellites, and surveillance cameras. Figure 9 shows a block diagram of a digital still camera as an example of such a device.

[0103] The device 70 shown in Figure 9 includes a barrier 706, a lens 702, an aperture 704, and an imaging device 700 (an example of a photoelectric converter). The device 70 further includes a signal processing unit (processing unit) 708, a timing generation unit 720, an overall control / calculation unit 718 (control device), a memory unit 710 (storage device), a recording medium control I / F unit 716, a recording medium 714, and an external I / F unit 712. At least one of the barrier 706, lens 702, and aperture 704 is an optical device corresponding to the device. The barrier 706 protects the lens 702, and the lens 702 forms an optical image of the subject on the imaging device 700. The aperture 704 varies the amount of light passing through the lens 702. The imaging device 700 is configured as in the above-described embodiment and converts the optical image formed by the lens 702 into image data (image signal). The signal processing unit 708 performs various corrections, data compression, etc., on the imaging data output from the imaging device 700. The timing generation unit 720 outputs various timing signals to the imaging device 700 and the signal processing unit 708. The overall control / calculation unit 718 controls the entire digital still camera, and the memory unit 710 temporarily stores image data. The recording medium control I / F unit 716 is an interface for recording or reading image data to or from the recording medium 714, which is a removable recording medium such as a semiconductor memory for recording or reading imaging data. The external I / F unit 712 is an interface for communicating with an external computer or the like. Timing signals and the like may be input from outside the device. Furthermore, the device 70 may also include a display device (monitor, electronic viewfinder, etc.) that displays information obtained from the photoelectric converter. The device includes at least a photoelectric converter. Furthermore, the device 70 includes at least one of an optical device, a control device, a processing device, a display device, a storage device, and a mechanical device that operates based on information obtained from the photoelectric converter. The mechanical device is a movable part (for example, a robot arm) that operates in response to signals from the photoelectric converter.

[0104] Each pixel may include multiple photoelectric conversion units (a first photoelectric conversion unit and a second photoelectric conversion unit). The signal processing unit 708 may be configured to process a pixel signal based on the charge generated by the first photoelectric conversion unit and a pixel signal based on the charge generated by the second photoelectric conversion unit to acquire distance information from the imaging device 700 to the subject.

[0105] [Seventh Embodiment] Figures 10(a) and 10(b) are block diagrams of the equipment related to the in-vehicle camera in this embodiment. Equipment 80 includes an imaging device 800 (an example of a photoelectric converter) as described above, and a signal processing device (processing device) that processes signals from the imaging device 800. Equipment 80 includes an image processing unit 801 that performs image processing on a plurality of image data acquired by the imaging device 800, and a parallax calculation unit 802 that calculates parallax (phase difference of parallax images) from a plurality of image data acquired by Equipment 80. Equipment 80 also includes a distance measurement unit 803 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 804 that determines whether or not there is a possibility of collision based on the calculated distance. Here, the parallax calculation unit 802 and the distance measurement unit 803 are examples of distance information acquisition means that acquire distance information to an object. That is, distance information is information related to parallax, defocus amount, distance to an object, etc. The collision determination unit 804 may use any of this distance information to determine the possibility of collision. The means for acquiring distance information may be implemented by specially designed hardware, or by a software module. It may also be implemented by an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), or a combination thereof.

[0106] Device 80 is connected to a vehicle information acquisition device 810 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. Device 80 is also connected to a control ECU 820, which is a control device that outputs a control signal to generate braking force on the vehicle based on the collision determination result of the collision determination unit 804. Furthermore, device 80 is connected to a warning device 830 that issues a warning to the driver based on the collision determination result of the collision determination unit 804. For example, if the collision determination result of the collision determination unit 804 indicates a high probability of collision, the control ECU 820 performs vehicle control to avoid a collision or mitigate damage by applying the brakes, releasing the accelerator, or suppressing engine output. The warning device 830 warns the user by sounding an alarm, displaying warning information on a screen such as a car navigation system, or vibrating the seatbelt or steering wheel. As described above, device 80 functions as a control means that controls the actions that control the vehicle.

[0107] In this embodiment, the equipment 80 images the area around the vehicle, for example, in front of or behind it. Figure 10(b) shows the equipment when imaging the area in front of the vehicle (imaging range 850). The vehicle information acquisition device 810, acting as an imaging control means, sends instructions to the equipment 80 or imaging device 800 to perform the imaging operation. This configuration allows for further improvement of the accuracy of distance measurement.

[0108] The above example described controlling a vehicle to avoid collisions with other vehicles, but it can also be applied to control systems that automatically follow other vehicles, or control systems that automatically stay within their lane. Furthermore, the equipment is not limited to vehicles such as automobiles, but can be applied to mobile objects (mobile devices) such as ships, aircraft, satellites, industrial robots, and consumer robots. In addition, it can be applied not only to mobile objects, but also to a wide range of devices that utilize object recognition or biometric recognition, such as intelligent transportation systems (ITS) and surveillance systems.

[0109] [Modified Embodiment] The present invention is not limited to the embodiments described above and can be modified in various ways. For example, an example in which a part of the configuration of one embodiment is added to another embodiment, or in which a part of the configuration of another embodiment is replaced, is also an embodiment of the present invention.

[0110] The disclosures in this specification include the complements of the concepts described herein. That is, if this specification contains a statement such as "A is B" (A=B), the specification shall be deemed to disclose or imply "A is not B" (A≠B) even if a statement such as "A is not B" is omitted. This is because the statement "A is B" presupposes that the case where "A is not B" is being considered.

[0111] The present invention can also be realized by supplying a program that implements one or more of the functions of the above-described embodiments to a system or device via a network or storage medium, and by a process in which one or more processors in the computer of that system or device read and execute the program. It can also be realized by a circuit (e.g., an ASIC) that implements one or more functions.

[0112] It should be noted that the embodiments described above are merely examples of how the present invention can be implemented, and the technical scope of the present invention should not be interpreted as being limited by them. In other words, the present invention can be implemented in various ways without departing from its technical concept or its main features. [Explanation of Symbols]

[0113] 100, 100a, 100b pixels 12 Output lines 23, 23a, 23b AD conversion section 191, 192 switches

Claims

1. Multiple pixels arranged in multiple columns, An output line is arranged corresponding to each of the aforementioned multiple rows, and a signal is output from the corresponding pixel. A comparison unit is arranged corresponding to each of the aforementioned plurality of rows, and has a first input terminal and a second input terminal, wherein a signal corresponding to the potential of the output line is input to the first input terminal and a reference signal is input to the second input terminal, It has, The plurality of pixels include a first pixel and a second pixel, The comparison unit is capable of performing an offset clamp operation to set an offset based on the potentials input to the first input terminal and the second input terminal. The comparison unit performs the offset clamp operation based on the signal output from the first pixel, and then, while the comparison unit holds the result of the offset clamp operation based on the signal output from the first pixel, the comparison unit performs a comparison for analog-to-digital conversion of the signal output from the second pixel. A photoelectric conversion device characterized by the following features.

2. During the period from the completion of the offset clamping operation based on the signal output from the first pixel until the start of the comparison for the analog-to-digital conversion of the signal output from the second pixel, the offset clamping operation based on the signal output from the second pixel is not performed. The photoelectric conversion device according to feature 1.

3. The aforementioned plurality of columns include the first column and the second column, The first pixel is arranged in the first column, The second pixel is arranged in the second column. The photoelectric conversion device according to claim 1 or 2.

4. It further includes a signal switching circuit, The signal switching circuit is capable of switching between a first state in which the signal output from the first pixel is input to the comparison unit of the second column, and a second state in which the signal output from the second pixel is input to the comparison unit of the second column. The photoelectric conversion device according to feature 3.

5. In the first state, the signal output from the second pixel is input to the comparison unit of the first column. In the second state, the signal output from the first pixel is input to the comparison unit of the first column. The photoelectric conversion device according to feature 4.

6. The aforementioned plurality of columns further include a third column, In the first state, the signal output from the second pixel is input to the comparison unit of the third column. The photoelectric conversion device according to feature 4.

7. Each of the aforementioned plurality of columns is further provided with a holding capacitor that holds the signal output from the corresponding pixel, The signal switching circuit is connected to the holding capacitor. The photoelectric conversion device according to any one of claims 4 to 6.

8. It further has a first input capacity arranged corresponding to each of the aforementioned multiple columns, A signal corresponding to the output of the corresponding pixel is input to the first input terminal via the first input capacitor. The signal switching circuit is connected to the first input capacitor. The photoelectric conversion device according to any one of claims 4 to 6.

9. A holding capacitor is arranged corresponding to each of the aforementioned plurality of columns, and the signal output from the pixel is held therein. A first buffer is provided between the holding capacity and the first input capacity, corresponding to each of the plurality of columns, It further possesses, The signal switching circuit is located between the first buffer and the first input capacitor. The photoelectric conversion device according to feature 8.

10. The plurality of pixels are arranged to form a plurality of rows and a plurality of columns, The first pixel and the second pixel are located in different rows within the same column among the plurality of columns. The photoelectric conversion device according to claim 1 or 2.

11. Multiple pixels arranged in multiple columns, An output line is arranged corresponding to each of the aforementioned multiple rows, and a signal is output from the corresponding pixel. A comparison unit is arranged corresponding to each of the aforementioned plurality of rows, and has a first input terminal and a second input terminal, wherein a signal corresponding to the potential of the output line is input to the first input terminal and a reference signal is input to the second input terminal, A second buffer is provided between the signal line to which the reference signal is supplied and the second input terminal, corresponding to each of the aforementioned plurality of columns. It has, The aforementioned plurality of columns include the first column and the second column, The comparison unit is capable of performing an offset clamp operation to set an offset based on the potentials input to the first input terminal and the second input terminal. The comparison unit of the second column performs the offset clamp operation based on the signal output from the second buffer of the first column, and then performs the analog-to-digital conversion comparison of the signals output from the pixels of the second column based on the signal output from the second buffer of the second column. A photoelectric conversion device characterized by the following features.

12. It further includes a signal switching circuit, The signal switching circuit is capable of switching between a first state in which the signal output from the second buffer of the first column is input to the comparison unit of the second column, and a second state in which the signal output from the second buffer of the second column is input to the comparison unit of the second column. The photoelectric conversion device according to feature 11.

13. The operation of the signal switching circuit differs depending on the gain setting of the amplification section that amplifies the signal output to the output line. The photoelectric conversion device according to any one of claims 4 to 9 and 12.

14. The operation of the signal switching circuit differs depending on the rate of change per unit time of the potential of the reference signal. The photoelectric conversion device according to any one of claims 4 to 9, 12, and 13.

15. The operation of the signal switching circuit varies depending on the temperature of the photoelectric converter. The photoelectric conversion device according to any one of claims 4 to 9 and 12 to 14.

16. During the period before the offset clamp operation begins, the signal switching circuit enters the first state. The photoelectric conversion device according to any one of claims 4 to 9 and 12 to 15.

17. After the offset clamping operation is performed, the signal switching circuit enters the second state. The photoelectric conversion device according to any one of claims 4 to 9 and 12 to 16.

18. After the signal switching circuit enters the second state, the potential of the reference signal begins to change in a time-dependent manner. The photoelectric conversion device according to feature 17.

19. A photoelectric conversion device according to any one of claims 1 to 18, Optical device corresponding to the aforementioned photoelectric converter, A control device for controlling the aforementioned photoelectric converter, A processing device that processes the signal output from the aforementioned photoelectric converter, A display device that displays information obtained by the aforementioned photoelectric converter. A storage device for storing information obtained by the aforementioned photoelectric converter, and A device characterized by comprising at least one of the following: a mechanical device that operates based on information obtained from the photoelectric converter.

20. The apparatus according to claim 19, characterized in that the processing device processes the image signals generated by a plurality of photoelectric conversion units and acquires distance information from the photoelectric conversion device to the subject.

Images