Photoelectric converter

Abstract

To provide a photoelectric conversion device that can appropriately correct horizontal dark shading.SOLUTION: A photoelectric conversion device can execute, in reading signals from a pixel array to a reading unit, first drive of outputting a signal based on the total of electric charges generated in a plurality of photoelectric conversion parts, and second drive of outputting a signal based on electric charges generated in any one of the plurality of photoelectric conversion parts. The photoelectric conversion device can switch, for every row, between a first operation mode of reading signals from pixels in one row through the first drive, and a second operation mode of reading signals from pixels in one row by continuously performing the first drive and the second drive. A first correction unit generates a first correction value on the basis of output signals from a second pixel row read in the first operation mode, generates a second correction value on the basis of output signals from the second pixel row read in the second operation mode, and corrects output signals from a first pixel row on the basis of the first correction value and the second correction value.SELECTED DRAWING: Figure 12

Description

Technical Field

[0001] The present invention relates to a photoelectric conversion device.

Background Art

[0002] Patent Document 1 discloses a technique related to an imaging device capable of focus detection by a pupil division method. Patent Document 1 also describes a method for correcting the black level for a signal for a captured image and a signal for focus detection.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a photoelectric conversion device capable of correcting the black level as described in Patent Document 1, correction of the horizontal dark shading shape may be required in addition to correction of the black level offset.

[0005] An object of the present invention is to provide a photoelectric conversion device capable of appropriately correcting horizontal dark shading.

Means for Solving the Problems

[0006] According to one disclosure of this specification, a pixel array having a plurality of pixels arranged in a plurality of rows and a plurality of columns, comprising: a first pixel row including a first pixel, each having a plurality of photoelectric conversion units that generate charge based on incident light; and a second pixel row including non-photosensitive pixels that output a signal not based on the incident light; a readout unit that reads signals from the first pixels and the non-photosensitive pixels; and a first correction unit that corrects the signals read from the first pixels, wherein in the second pixel row, there are more non-photosensitive pixels than first pixels; and in reading signals from the pixel array to the readout unit, it is possible to perform a first drive that outputs a signal based on the sum of the charges generated by each of the plurality of photoelectric conversion units, and a second drive that outputs a signal based on the charge generated by any of the plurality of photoelectric conversion units; and it is possible to switch between a first operation mode in which signals are read from the pixels of one row by the first drive and a second operation mode in which signals are read from the pixels of one row by performing the first drive and the second drive in succession, row by row. The first correction unit includes a first correction value acquisition unit and a second correction value acquisition unit, each of which holds a plurality of correction values ​​generated based on the output signal of the second pixel row. The first correction unit, based on the output signal of the second pixel row read out in the first operating mode, Includes at least two generated values First correction value The group is held in the first correction value acquisition unit. Based on the output signal of the second pixel row read out in the second operating mode Includes at least two generated values Second correction value The group is held in the second correction value acquisition unit. , the first correction value group and the second correction value group A photoelectric converter is provided, characterized by correcting the output signal of the first pixel row based on the above. [Effects of the Invention]

[0007] According to the present invention, a photoelectric conversion device capable of appropriately correcting horizontal dark shading is provided. [Brief explanation of the drawing]

[0008] [Figure 1] This is a conceptual diagram showing the relationship between the exit pupil of the photographic lens and the effective pixels. [Figure 2] This is a block diagram showing a photoelectric converter according to the first embodiment. [Figure 3]It is a diagram showing the layout of a pixel array in the first embodiment. [Figure 4] It is a diagram showing an effective pixel and a column readout section. [Figure 5] It is a diagram showing a dummy pixel. [Figure 6] It is a timing chart showing the first operation mode. [Figure 7] It is a timing chart showing the second operation mode. [Figure 8] It is a diagram showing an example of switching of the operation mode in an effective pixel row or an OB pixel row and an example of a horizontal dark shading shape. [Figure 9] It is a diagram showing an example of switching of the operation mode in a dummy pixel row and an example of a horizontal dark shading shape. [Figure 10] It is a block diagram of a signal processing circuit. [Figure 11] It is a block diagram of a second correction unit in the first embodiment. [Figure 12] It is a block diagram of a first correction unit in the first embodiment. [Figure 13] It is a flowchart of the processing of the first correction unit in the first embodiment. [Figure 14] It is a graph showing the correction effect in the first embodiment. [Figure 15] It is a diagram showing the layout of a pixel array in the second embodiment. [Figure 16] It is a block diagram of a first correction unit in the second embodiment. [Figure 17] It is a flowchart of the processing of the first correction unit in the second embodiment. [Figure 18] It is a block diagram of a first correction unit in the third embodiment. [Figure 19] It is a flowchart of the processing of the first correction unit in the third embodiment. [Figure 20] It is a graph showing the correction effect in the third embodiment. [Figure 21] It is a diagram showing the layout of a pixel array in the fourth embodiment. [Figure 22] It is a block diagram of a device according to the fifth embodiment. [Figure 23] It is a block diagram of a device according to the sixth embodiment.

Embodiments for Carrying Out the Invention

[0009] [[ID=l1]] Hereinafter, embodiments of the present invention will be described while referring to the drawings. The same elements or corresponding elements are given common reference numerals throughout the plurality of drawings, and the description thereof may be omitted or simplified.

[0010] In the first to fourth embodiments described below, as an example of a photoelectric conversion device, an imaging device will be mainly described. However, the photoelectric conversion device in each embodiment is not limited to an imaging device and can also be applied to other devices. Examples of other devices include a distance measuring device and a photometric device. The distance measuring device can be, for example, a focus detection device, a distance measuring device using TOF (Time-Of-Flight), etc. The photometric device can be a device that measures the amount of light incident on the device.

[0011] [First Embodiment] The photoelectric conversion device according to the first embodiment will be described with reference to FIGS. 1 to 14. First, the principle of focus detection by the pupil division method performed in the photoelectric conversion device according to the present embodiment will be described with reference to FIG. 1. FIG. 1 is a conceptual diagram showing the relationship between the exit pupil of a photographing lens (not shown) and effective pixels.

[0012] The effective pixel 100 (first pixel) has a photodiode PDA and a photodiode PDB. Above the effective pixel 100, a color filter 110 and a microlens 111 are arranged. Each of the photodiodes PDA and PDB is a photoelectric conversion unit that generates electric charges according to incident light.

[0013] Light incident on the photoelectric converter is incident on the effective pixels 100 with the optical axis 113 as the center. The light beam passing through the pupil region 114, which is a part of the exit pupil 112 of the imaging lens, passes through the microlens 111 and is received by the photodiode PDA. On the other hand, the light beam passing through the pupil region 115, which is another part of the exit pupil 112 of the imaging lens, passes through the microlens 111 and is received by the photodiode PDB. In this way, the photodiode PDA and the photodiode PDB each receive light passing through separate pupil regions 114 and 115 of the exit pupil 112. By comparing the signal output from the photodiode PDA and the signal output from the photodiode PDB, a phase difference can be detected. Based on the phase difference obtained in this way, the amount of focal position shift of the imaging lens arranged on the optical axis 113 can be detected and adjusted to focus on the object to be imaged.

[0014] Here, the signal corresponding to the charge generated by the photodiode PDA is defined as the A image signal. The signal corresponding to the charge generated by the photodiode PDB is defined as the B image signal. The A and B image signals are phase difference signals used for focus detection. Furthermore, the signal obtained by summing the charges generated by the photodiodes PDA and PDB is defined as the A+B image signal. The A+B image signal is the image signal that constitutes the captured image.

[0015] Next, the configuration of the photoelectric converter will be explained using Figures 2 to 5. Figure 2 is a block diagram of the photoelectric converter according to this embodiment. As shown in Figure 2, the photoelectric converter includes a pixel array 10, a column readout unit 40, a vertical scanning circuit 31, a horizontal scanning circuit 32, a timing generation circuit 33, and a signal processing circuit 50.

[0016] The pixel array 10 includes multiple pixels arranged in multiple rows and multiple columns (matrix-like). The pixel array 10 includes an effective pixel row 101 (first pixel row) in which effective pixels 100, including two photodiodes PDA and PDB, are arranged, and a non-photosensitive pixel row 201 (second pixel row) in which non-photosensitive pixels 200 that are not sensitive to light are arranged. That is, each of the multiple pixels can be either an effective pixel 100 or a non-photosensitive pixel 200. Figure 2 shows a pixel array of 4 columns and 5 rows for simplicity of explanation, but in reality, a larger number of effective pixels 100 and non-photosensitive pixels 200 can be arranged in the pixel array 10. In this embodiment, the non-photosensitive pixel row 201 is provided with non-photosensitive pixels 200 and no effective pixels 100. However, it is not limited to this example, and the non-photosensitive pixel row 201 may include fewer effective pixels 100 than non-photosensitive pixels 200. In this embodiment, the non-photosensitive pixel row 201 comprises non-photosensitive pixels 200 in the same number of columns as the effective pixels 100 provided in one effective pixel row 101. That is, all pixel columns included in one effective pixel row 101 include a first column closest to one end of the photoelectric converter and a second column closest to the opposite end. In the non-photosensitive pixel row 201 as well, non-photosensitive pixels 200 are provided across this first column and second column.

[0017] The vertical scanning circuit 31 selects pixels in the pixel array 10 row by row and outputs a drive signal to the pixels in the selected row. Logic circuits such as a shift register and an address decoder may be used in the vertical scanning circuit 31.

[0018] The column readout units 40 are arranged to correspond to each column of the pixel array 10. The column readout units 40 convert the signals output from the pixels from analog to digital and hold them. The horizontal scanning circuit 32 outputs a horizontal scanning pulse signal to the column readout unit 40 of each column. Logic circuits such as shift registers and address decoders may be used in the horizontal scanning circuit 32. Based on the horizontal scanning pulse signal, the column readout unit 40 of each column sequentially outputs the signals it holds to the signal processing circuit 50.

[0019] The timing generation circuit 33 outputs control signals to control the column reading unit 40, the vertical scanning circuit 31, the horizontal scanning circuit 32, and the signal processing circuit 50.

[0020] The signal processing circuit 50 performs signal processing, such as correction processing, on the signal output from the column reading unit 40. The signal processing circuit 50 outputs the processed signal to the outside of the photoelectric converter.

[0021] Figure 3 shows the layout of the pixel array 10. The pixel array 10 has an effective pixel area 11, an optical black (OB) pixel area 12, and a dummy pixel area 13. The effective pixel area 11 is a rectangular area where the effective pixels 100 are located and occupies most of the pixel array 10.

[0022] The OB pixel region 12 is an L-shaped region in which OB pixels (third pixels) are arranged, and is positioned along two sides of the effective pixel region 11. The OB pixels are pixels with a structure similar to that of the effective pixels 100, but with an additional optical light-shielding structure, thereby shielding the photodiodes PDA and PDB.

[0023] The dummy pixel region 13 is a rectangular region in which dummy pixels (second pixels) are placed, and is positioned along the upper edge of the OB pixel region 12. The dummy pixels are pixels with a structure similar to that of OB pixels, but with the photodiodes PDA and PDB removed.

[0024] Rows containing dummy pixels are referred to as dummy pixel rows, and rows containing out-of-focus (OB) pixels are referred to as OB pixel rows. Furthermore, rows primarily containing effective pixels 100 are represented as effective pixel rows 101, as shown in Figure 2. Non-photosensitive pixel rows 201, as shown in Figure 2, are either dummy pixel rows or OB pixel rows.

[0025] Figure 4 shows the circuit configuration of the effective pixel 100 and the column readout unit 40. For simplification, Figure 4 shows only one effective pixel 100 and the column readout unit 40 corresponding to that effective pixel 100.

[0026] The effective pixel 100 includes a photodiode PDA, PDB, transfer transistors M1A and M1B, a reset transistor M2, an amplification transistor M3, and a selection transistor M4. The effective pixel 100 is also connected to the column readout unit 40 via an output line VL to which a current source IS is connected.

[0027] The anodes of photodiodes PDA and PDB are connected to the ground node. The cathodes of photodiodes PDA and PDB are connected to the sources of transfer transistors M1A and M1B, respectively. The drains of transfer transistors M1A and M1B are connected to the source of reset transistor M2 and the gate of amplifier transistor M3. The node to which the drains of transfer transistors M1A and M1B, the source of reset transistor M2, and the gate of amplifier transistor M3 are connected is the floating diffusion node (FD).

[0028] A floating diffusion diode (FD) contains a capacitive component and functions as a charge holder. The floating diffusion diode (FD) performs charge-voltage conversion of the charge generated by photoelectric conversion in the photodiodes PDA and PDB. The coefficient of charge-voltage conversion is determined by the junction capacitance, gate capacitance, inter-wiring parasitic capacitance, etc., of the diffusion layer and wiring that constitute the floating diffusion diode (FD). Figure 4 shows the capacitance of this floating diffusion diode (FD) equivalently represented by the circuit symbol of the capacitive element.

[0029] The drains of reset transistor M2 and amplifier transistor M3 are connected to a power supply voltage node to which voltage VDD is supplied. The source of amplifier transistor M3 is connected to the drain of selection transistor M4. The source of selection transistor M4 is connected to output line VL.

[0030] The gates of transfer transistors M1A and M1B receive control signals PTXA and PTXB, respectively, via control lines from the vertical scanning circuit 31. The gate of reset transistor M2 receives control signal PRES via control lines from the vertical scanning circuit 31. The gate of selection transistor M4 receives control signal PSEL via control lines from the vertical scanning circuit 31.

[0031] In this embodiment, each transistor constituting the effective pixel 100 is assumed to be an N-type MOS transistor. Therefore, when an H-level (high-level) control signal is supplied from the vertical scanning circuit 31, the corresponding transistor turns on. Conversely, when an L-level (low-level) control signal is supplied from the vertical scanning circuit 31, the corresponding transistor turns off. Furthermore, the names of the source and drain of a MOS transistor may differ depending on the conductivity type of the transistor or the function of interest. Some or all of the source and drain names used in this embodiment may also be referred to by the reverse names.

[0032] The photodiodes PDA and PDB receive incident light that has passed through the same microlens 111, convert it into an amount of charge corresponding to the amount of light received, and store it. When the transfer transistor M1A is turned on, it transfers the charge held by the photodiode PDA to the floating diffusion FD. When the transfer transistor M1B is turned on, it transfers the charge held by the photodiode PDB to the floating diffusion FD. The charge transferred from the photodiodes PDA and PDB is held in the capacitance of the floating diffusion FD. As a result, the floating diffusion FD becomes potential corresponding to the amount of charge transferred from the photodiodes PDA and PDB through charge-voltage conversion by the floating diffusion capacitance.

[0033] The selector transistor M4, when turned on, connects the amplifier transistor M3 to the output line VL. The amplifier transistor M3 is configured such that a voltage VDD is supplied to its drain and a bias current is supplied to its source from the current source IS via the selector transistor M4, forming an amplifier section (source follower circuit) with its gate as the input node. As a result, the amplifier transistor M3 outputs a signal based on the potential of the floating diffusion FD to the output line VL via the selector transistor M4. In this sense, the amplifier transistor M3 and the selector transistor M4 are output sections that output a signal corresponding to the amount of charge held in the floating diffusion FD.

[0034] The reset transistor M2 has the function of resetting the floating diffusion FD by controlling the supply of voltage (voltage VDD) to the floating diffusion FD. When the reset transistor M2 is turned on, the floating diffusion FD is reset to a voltage corresponding to voltage VDD.

[0035] The column reading unit 40 includes an analog-to-digital conversion unit 41 and a storage unit 42. The output line VL is connected to the analog-to-digital conversion unit 41. The analog-to-digital conversion unit 41 converts the analog signal input via the output line VL into a digital signal. The analog-to-digital conversion unit 41 is composed of, for example, a comparator circuit and a counter circuit. The comparator circuit compares a ramp signal, whose potential changes depending on time, with the input signal, and outputs a signal to the counter circuit at the timing when the relative magnitudes of the two signals are reversed. The counter circuit receives the signal from the comparator circuit and holds the count value at that timing. The count value held by the counter circuit is stored as a digital value in the storage unit 42.

[0036] The memory unit 42 has two memories 42S and 42N for holding digital signals. Memory 42S holds the A image signal, the B image signal, or the A+B image signal. Memory 42N holds the N signal (noise signal) based on the reset state of the floating diffusion. The digital signal held in memory 42S is output to the signal processing circuit 50 via the digital signal output line 45 (OUT_S). The digital signal held in memory 42N is output to the signal processing circuit 50 via the digital signal output line 46 (OUT_N).

[0037] Figure 5 shows a dummy pixel, which is an example of a non-photosensitive pixel 200. The difference between the dummy pixel and the effective pixel 100 is that it does not have photodiodes PDA and PDB, and the sources of transfer transistors M1A and M1B are connected to the ground node. The other configurations are the same as those of the effective pixel 100, so their explanation is omitted. The same signal readout operation is performed on the dummy pixel as on the effective pixel 100, making it possible to read out signals that are not based on incident light. Although the non-photosensitive pixel 200 does not have a photodiode, it can output a signal that indicates noise due to dark current leakage generated in the floating diffusion FD and reset transistor M2. This dark current leakage affects the horizontal dark shading, which will be described later.

[0038] Next, two operating modes for reading signals row by row from the pixels of the pixel array 10 will be explained using Figures 6 and 7. Figure 6 is a timing chart showing the first operating mode, and Figure 7 is a timing chart showing the second operating mode. Figures 6 and 7 show the horizontal synchronization signal SYNC, control signals PSEL, PRES, PTXA, PTXB, analog-to-digital (AD) conversion period, and horizontal scanning pulse signal. The horizontal synchronization signal SYNC is a signal that indicates the start timing of the operation to read signals from one row of pixels. The "AD conversion period" indicates the period during which analog-to-digital conversion is performed in the analog-to-digital conversion unit 41. The "horizontal scanning pulse signal" indicates the timing at which signals are sequentially transferred from the column reading unit 40 of each column to the signal processing circuit 50. Note that if the operation performed differs depending on whether the pixels to be read are effective pixels 100 or non-photosensitive pixels 200, each case may be explained separately.

[0039] First, the first operating mode will be explained using Figure 6. The first operating mode includes the operation of reading out the N signal and the operation of reading out the A+B image signal (first drive). In other words, in the first operating mode, the image signals that make up the captured image are read out, but the phase difference signal for focus detection is not read out.

[0040] At time t101, the horizontal synchronization signal SYNC becomes high, and the control signal PSEL for the selected row also becomes high. As a result, the selection transistor M4 for the selected row is turned on, and the pixels of the selected row are connected to the output line VL.

[0041] At time t102, the control signal PRES becomes high. This turns on the reset transistor M2, and the potential of the floating diffusion FD becomes the reset level.

[0042] At time t103, the control signal PRES becomes low. This turns off the reset transistor M2, releasing the reset of the floating diffusion FD. Since the selection transistor M4 remains on, an output signal corresponding to the gate potential of the amplification transistor M3 when the floating diffusion FD reset is released is output to the output line VL. The pixel signal output from the pixel at time t103, i.e., the signal based on the reset level of the floating diffusion FD, is the N signal.

[0043] Between time t104 and time t105, the N signal output to output line VL is converted to a digital signal by the analog-to-digital conversion unit 41 of the column reading unit 40. The digital signal output from the analog-to-digital conversion unit 41 is stored in the memory 42N of the storage unit 42. The operation of converting the N signal to a digital signal, which takes place between time t104 and time t105, will be referred to as N conversion.

[0044] At time t106, the control signals PTXA and PTXB become high. This turns on the transfer transistors M1A and M1B. If the pixel is an effective pixel 100, the charge stored in the photodiodes PDA and PDB is transferred to the floating diffusion FD. If the pixel is a non-photosensitive pixel 200, the charge present at the source nodes of transfer transistors M1A and M1B is transferred to the floating diffusion FD. The output line VL outputs the A+B image signal, which is the pixel signal corresponding to the combined charge.

[0045] At time t107, the control signals PTXA and PTXB become low. This turns off the transfer transistors M1A and M1B. Even after the transfer transistors M1A and M1B are turned off, the A+B image signal continues to be output to the output line VL.

[0046] Between time t108 and time t109, the A+B image signal output to output line VL is converted to a digital signal by the analog-to-digital conversion unit 41 of the column reading unit 40. The digital signal output from the analog-to-digital conversion unit 41 is stored in the memory 42S of the storage unit 42. The operation of converting the A+B image signal to a digital signal, which takes place between time t108 and time t109, will be referred to as A+B conversion.

[0047] During the period between time t110 and time t111, a horizontal scanning pulse signal is output from the horizontal scanning circuit 32 to the column reading unit 40, and the A+B image signal and N signal, which are digital signals held in the memories 42S and 42N of each column, are output sequentially. The A+B image signal is output from memory 42S to the signal processing circuit 50 via the digital signal output line 45 (OUT_S). The N signal is output from memory 42N to the signal processing circuit 50 via the digital signal output line 46 (OUT_N). By repeating this horizontal scanning from the first column to the last column, the A+B image signal and N signal of one row are read out in the first operating mode.

[0048] At time t112, the control signal PSEL for the selected row becomes low. As a result, the selection transistor M4 for that row is turned off, and the pixels of that row become disconnected from the output line VL.

[0049] Through the above operations, the N signal and the A+B image signal are read out in the first operating mode. In other words, in the first operating mode, the image signals that make up the captured image are read out, and the phase difference signal for focus detection is not read out. The signal processing circuit 50 subtracts the N signal from the A+B image signal, thereby removing fixed pattern noise.

[0050] Next, the second operating mode will be explained using Figure 7. The second operating mode includes the operation of reading out the N signal, the operation of reading out the A image signal (second drive), and the operation of reading out the A+B image signal (first drive). In other words, in the second operating mode, the image signal that constitutes the captured image and the phase difference signal for focus detection are read out. Although Figure 7 shows an example in which the A image signal of the two phase difference signals is read out, the B image signal may be read out instead of the A image signal.

[0051] The operation from time t201 to time t205 is the same as the operation from time t101 to time t105 in Figure 6, so the explanation is omitted.

[0052] At time t206, the control signal PTXA becomes high. This turns on the transfer transistor M1A. If the pixel is an effective pixel 100, the charge stored in the photodiode PDA is transferred to the floating diffusion FD. The output line VL outputs an A-image signal, which is a pixel signal corresponding to the amount of charge stored in the photodiode PDA. If the pixel is a non-photosensitive pixel 200, the charge present at the source node of the transfer transistor M1A is transferred to the floating diffusion FD. The output line VL outputs an A-image signal, which is a pixel signal corresponding to the amount of charge present in the floating diffusion FD after the transfer.

[0053] At time t207, the control signal PTXA becomes low. This turns off the transfer transistor M1A. Even after the transfer transistor M1A is turned off, the A image signal continues to be output to the output line VL.

[0054] Between time t208 and time t209, the A-image signal output to output line VL is converted to a digital signal by the analog-to-digital conversion unit 41 of the column reading unit 40. The digital signal output from the analog-to-digital conversion unit 41 is stored in the memory 42S of the storage unit 42. The operation of converting the A-image signal to a digital signal, which takes place between time t208 and time t209, will be referred to as A-conversion.

[0055] During the period between time t210 and time t211, a horizontal scanning pulse signal is output from the horizontal scanning circuit 32 to the column reading unit 40, and the A image signal and N signal, which are digital signals held in the memories 42S and 42N of each column, are output sequentially.

[0056] At time t212, the horizontal synchronization signal SYNC becomes high. During the period between time t212 and time t213, the control signal PRES remains low, so the floating diffusion FD is not reset. If the pixel is an effective pixel 100, the floating diffusion FD retains the charge generated by the photodiode PDA. If the pixel is a non-photosensitive pixel 200, the floating diffusion FD retains the charge transferred from the source node of the transfer transistor M1A.

[0057] At time t213, the control signals PTXA and PTXB become high. This turns on the transfer transistors M1A and M1B. If the pixel is an effective pixel 100, the charge stored in the photodiode PDB is transferred to the floating diffusion FD. If the pixel is a non-photosensitive pixel 200, the charge present at the source node of transfer transistor M1B is transferred to the floating diffusion FD. The output line VL outputs the A+B image signal, which is the pixel signal corresponding to the combined charge.

[0058] At time t214, the control signals PTXA and PTXB become low. This turns off the transfer transistors M1A and M1B. Even after the transfer transistors M1A and M1B are turned off, the A+B image signal continues to be output to the output line VL.

[0059] Between time t215 and time t216, the A+B image signal output to output line VL is converted into a digital signal by the analog-to-digital conversion unit 41 of the column reading unit 40. The digital signal output from the analog-to-digital conversion unit 41 is stored in the memory 42S of the storage unit 42.

[0060] During the period between time t217 and time t218, a horizontal scanning pulse signal is output from the horizontal scanning circuit 32 to the column reading unit 40, and the A+B image signal and the N signal, which are digital signals held in the memories 42S and 42N of each column, are output sequentially.

[0061] At time t219, the control signal PSEL for the selected row becomes low. As a result, the selection transistor M4 for that row is turned off, and the pixels of that row become disconnected from the output line VL.

[0062] The above operations enable the reading of the N signal, A image signal, and A+B image signal in the second operating mode. In other words, in the second operating mode, the image signal that constitutes the captured image and the phase difference signal for focus detection are read out. The signal processing circuit 50 subtracts the N signal from each of the A image signal and the A+B image signal, thereby removing fixed pattern noise.

[0063] Thus, the photoelectric converter of this embodiment is capable of performing a first drive that outputs an A+B signal and a second drive that outputs an A signal. In the first operating mode, the first drive is performed, and in the second operating mode, the first drive is performed immediately after the second drive. The B image signal used for phase difference detection is obtained, for example, by subtracting the A image signal from the A+B image signal in the signal processing circuit 50. Furthermore, the timing generation circuit 33 can appropriately switch the read operation mode for each row by appropriately switching the output state of the control signal for each row. In other words, the photoelectric converter of this embodiment can switch the row from which phase difference information is acquired as needed.

[0064] Next, we will explain the difference in horizontal dark shading shape between the first and second operating modes. Horizontal dark shading shape refers to the distribution of output signal levels within a row when there is no incident light. Figures 8(a) and 8(b) show examples of switching operating modes and horizontal dark shading shapes in an effective pixel row or an out-of-bounds pixel row.

[0065] Figure 8(a) shows an example of switching between the first and second operating modes when outputting the A+B image signal from the effective pixel row shown in Figure 3. In the 12 rows between the (N-5)th row and the (N+6)th row, the 8 rows from the (N-5th)th row to the (N-2nd)th row and the (N+1)th row to the (N+4th)th row are normal rows R1 that are read out in the first operating mode. In addition, the 4 rows from the (N-1st)th row, the (N)th row, the (N+5th)th row and the (N+6th)th row are focus detection rows R2 that are read out in the second operating mode. In Figure 8(a), the focus detection rows R2 are hatched. In this way, in multiple rows of the effective pixel region 11, the normal rows R1 read out in the first operating mode and the focus detection rows R2 read out in the second operating mode are repeated.

[0066] Figure 8(b) is a graph showing examples of horizontal dark shading shapes in the first and second operating modes, respectively. The horizontal axis of the graph represents the column address of the pixel array 10, and the vertical axis represents the output level of the signal output from the pixel. As shown in the timing charts of Figures 6 and 7, the length of the period from N conversion to A+B conversion in the first operating mode and the length of the period from N conversion to A+B conversion in the second operating mode are different. Therefore, the difference in the accumulation time of the dark current leakage component mentioned in the explanation of Figure 5 appears as a difference in the horizontal dark shading shape of the A+B image output between the operating modes. In addition, in the effective pixel row, the difference in the dark current component caused by the placement of photodiodes PDA and PDB within the pixel is superimposed on the difference in the horizontal dark shading shape. Note that although Figures 8(a) and 8(b) show examples for the effective pixel row, the same applies to the OB pixel row.

[0067] Next, we will explain the difference in horizontal dark shading shape between the first and second operating modes for a dummy pixel row. Figures 9(a) and 9(b) show examples of switching operating modes and horizontal dark shading shapes for a dummy pixel row.

[0068] Figure 9(a) shows an example of switching between the first and second operating modes when outputting the A+B image signal from the dummy pixel row shown in Figure 3. In the four rows between row M-1 and row M+2, row M-1 and row M are normal rows R1 that are read out in the first operating mode. Rows M+1 and M+2 are focus detection rows R2 that are read out in the second operating mode. Thus, multiple rows in the dummy pixel region 13 also contain normal rows R1 and focus detection rows R2.

[0069] Figure 9(b) is a graph showing examples of horizontal dark shading shapes in the first and second operating modes, respectively. Since dummy pixels do not contain photodiodes, no dark current component is generated due to photodiodes. Therefore, the horizontal dark shading shape in Figure 9(b) may differ from that in Figure 8(b). As shown in Figure 9(b), the offset difference in output levels between the two operating modes is small, and the difference in horizontal dark shading shape is the main characteristic. Such differences in characteristics between pixel types can be used to correct differences in shading shape.

[0070] Next, the signal processing performed in the signal processing circuit 50 will be explained using Figure 10. Figure 10 is a block diagram of the signal processing circuit 50. As shown in Figure 10, the signal processing circuit 50 includes an SN processing unit 51, a second correction unit 52, and a first correction unit 53.

[0071] The SN processing unit 51 receives the A+B image signal, the A image signal, or the B image signal via the digital signal output line 45. In addition, the SN processing unit 51 receives the N signal via the digital signal output line 46. The SN processing unit 51 subtracts the N signal from the A+B image signal, the A image signal, or the B image signal. This reduces fixed pattern noise. The A+B image signal, the A image signal, or the B image signal after subtracting the N signal is input to the second correction unit 52. The second correction unit 52 corrects the offset difference between operating modes. The corrected signal is input to the first correction unit 53. The first correction unit 53 corrects the shading shape difference between operating modes. Through the above processing, the offset difference and shading shape difference between operating modes are corrected. The corrected signal is output to the outside of the photoelectric converter. The following describes in more detail the configuration of the second correction unit 52 and the first correction unit 53, and the correction processing performed in the second correction unit 52 and the first correction unit 53.

[0072] The second correction unit 52 will be described with reference to Figure 11. The second correction unit 52 uses the output signals from the OB pixels in the OB pixel region 12 to perform a correction process that brings the black level closer to the reference level. Figure 11 is a block diagram of the second correction unit 52 in this embodiment. The second correction unit 52 includes a data acquisition unit 521, averaging units 522 and 523, a correction value generation unit 524, a subtraction unit 525, and switches SW21 and SW22.

[0073] The data acquisition unit 521 selects and acquires output signals from OB pixels within the OB pixel area 12 from the input signals to the second correction unit 52. The pixel signals acquired by the data acquisition unit 521 are output to the switch SW21.

[0074] Switch SW21 switches the terminal that outputs the pixel signal according to the level of the first identification signal input from the timing generation circuit 33. The first identification signal is set to L level when the pixel signal input to the second correction unit 52 is read from the normal row R1 in the first operating mode. The first identification signal is set to H level when the pixel signal input to the second correction unit 52 is read from the focus detection row R2 in the second operating mode. Switch SW21 outputs the pixel signal to the averaging unit 522 when the first identification signal is at L level, and outputs the pixel signal to the averaging unit 523 when the first identification signal is at H level. The "L" and "H" indicated in the circuit symbols of each switch indicate the output terminal corresponding to the level of the input identification signal. Switch SW22 also performs a similar switching operation according to the first identification signal.

[0075] Each of the averaging units 522 and 523 performs averaging on the input pixel signal to calculate the average black level. The averaging unit 522 normally performs averaging on the signal read from row R1, and the averaging unit 523 performs averaging on the signal read from focus detection row R2. The average black levels calculated by the averaging units 522 and 523 are input to the correction value generation unit 524 via switch SW22. If the first identification signal is at the L level, switch SW22 outputs the signal input from the averaging unit 522 to the correction value generation unit 524. If the first identification signal is at the H level, switch SW22 outputs the signal input from the averaging unit 523 to the correction value generation unit 524.

[0076] The correction value generation unit 524 generates a correction value based on the difference between the average black level and a predetermined reference level, so as to adjust the average black level to the reference level. This correction value is used in the correction processing of the signal read from the effective pixel row.

[0077] The subtraction unit 525 performs a correction process to bring the black level closer to the reference level by subtracting a correction value generated by the correction value generation unit 524 from the pixel signal output from the effective pixel 100 located in the effective pixel row. For the pixel signal output from the normal row R1, a correction value (fourth correction value) based on the average black level calculated by the averaging unit 522 for the normal row R1 is subtracted. On the other hand, for the pixel signal output from the focus detection row R2, a correction value (fifth correction value) based on the average black level calculated by the averaging unit 523 for the focus detection row R2 is subtracted.

[0078] In this way, the second correction unit 52 can appropriately switch the correction value according to the operating mode to correct the offset difference.

[0079] Next, the first correction unit 53 will be described with reference to Figures 12 and 13. The first correction unit 53 performs a correction process to reduce the horizontal dark shading shape difference of the black level, using the signal from the pixels in the dummy pixel row as the correction value. Figure 12 is a block diagram of the first correction unit 53 in this embodiment. The first correction unit 53 includes correction value acquisition units 531, 532, subtraction unit 533, and switches SW31, SW32, SW33, SW34, and SW35. Switches SW32 and SW33 are switched based on the level of the first identification signal described above. Switches SW31, SW34, and SW35 are switched based on the level of the second identification signal input from the timing generation circuit 33. The second identification signal is set to an H level when the pixel signal input to the first correction unit 53 is read from the dummy pixel row. The second identification signal is set to an L level when the pixel signal input to the first correction unit 53 is read from a pixel row other than the dummy pixel row.

[0080] Switch SW31 switches the terminals to which it outputs signals input from the second correction unit 52 according to the level of the first identification signal. Switch SW31 outputs a signal to the subtraction unit 533 when the second identification signal is at a low level, and outputs a signal to switch SW32 when the second identification signal is at a high level.

[0081] Switch SW32 outputs a signal to the correction value acquisition unit 531 when the first identification signal is at the L level, and outputs a signal to the correction value acquisition unit 532 when the first identification signal is at the H level. The correction value acquisition unit 531 holds the signal read from the normal row R1 of the dummy pixel row as the first correction value in the first operating mode. The correction value acquisition unit 532 holds the signal read from the focus detection row R2 of the dummy pixel row as the second correction value in the second operating mode. These correction values ​​may have different values ​​for each column address of the pixel array 10. Furthermore, each of the correction value acquisition units 531 and 532 may have a line memory for holding these correction values.

[0082] Switch SW33 outputs the output signal from the correction value acquisition unit 531 to switch SW34 when the first identification signal is at a low level, and outputs the output signal from the correction value acquisition unit 532 to switch SW34 when the first identification signal is at a high level. Switch SW34 outputs the output signal from switch SW33 to the subtraction unit 533 when the second identification signal is at a low level, and outputs the output signal from switch SW33 to switch SW35 when the second identification signal is at a high level.

[0083] The subtraction unit 533 subtracts the signal output from switch SW34 from the signal output from switch SW31 and outputs the result to switch SW35. In other words, the subtraction unit 533 corrects the pixel signals output from the effective pixel row using the correction value held in the correction value acquisition unit 531 or 532.

[0084] Switch SW35 outputs a signal to the outside from the subtraction unit 533 when the second identification signal is at a low level, and outputs a signal to the outside from switch SW34 when the second identification signal is at a high level.

[0085] Next, the correction processing procedure of the first correction unit 53 in this embodiment will be explained with reference to Figure 13. Figure 13 is a processing flowchart of the first correction unit 53 in this embodiment. Figure 13 shows the processing from when the signal read from one pixel row is input to the first correction unit 53 until it is output.

[0086] First, the signal of one pixel row corrected by the second correction unit 52 is input to the first correction unit 53 (step S101). If the pixel row is a dummy pixel row (YES in step S102), the second identification signal output from the timing generation circuit 33 is at the H level (step S103). In this case, switches SW31, SW34, and SW35 are switched to the terminals marked "H" as shown in Figure 12. At this time, the first correction unit 53 starts the correction value acquisition operation based on the input signal (step S104).

[0087] On the other hand, if the pixel row is not a dummy pixel row (NO in step S102), the second identification signal output from the timing generation circuit 33 is at the L level (step S112). In this case, switches SW31, SW34, and SW35 are switched to the terminals labeled "L" as shown in Figure 12. At this time, the first correction unit 53 starts correcting the input signal (step S114).

[0088] The following will explain the correction value acquisition operation that starts from step S104 and the correction operation that starts from step S113 in order. First, we will explain the correction value acquisition operation that starts from step S104.

[0089] The signals of the dummy pixel rows input to the first correction unit 53 are read from the pixel array 10 in either the first or second operating mode. If the signals of the dummy pixel rows were read in the first operating mode (YES in step S105), the first identification signal output from the timing generation circuit 33 is at the L level (step S106). In this case, switches SW32 and SW33 are switched to the terminals labeled "L" as shown in Figure 12. The signals of the dummy pixel rows read in the first operating mode are input to the correction value acquisition unit 531 via switches SW31 and SW32.

[0090] The correction value acquisition unit 531 stores the signals of the input dummy pixel rows in line memory for each pixel (step S107). The signals held in this line memory are used as the first correction values. The correction value acquisition unit 531 may also have an averaging unit. If there are multiple dummy pixel rows read out in the first operation mode, the averaging unit may perform an averaging process of the correction values.

[0091] The input dummy pixel row signals are held in the correction value acquisition unit 531 and are also output to the outside of the first correction unit 53 via switches SW33, SW34, and SW35 in sequence (step S108).

[0092] On the other hand, if the signal of the dummy pixel row is read out in the second operating mode (NO in step S105), the first identification signal output from the timing generation circuit 33 is at the H level (step S109). In this case, switches SW32 and SW33 are switched to the terminals marked "H" as shown in Figure 12. The signal of the dummy pixel row read out in the second operating mode is input to the correction value acquisition unit 532 via switches SW31 and SW32.

[0093] The correction value acquisition unit 532, like the correction value acquisition unit 531, stores the signals of the input dummy pixel row in line memory for each pixel (step S110). The signals held in this line memory are used as the second correction value. The signals of the input dummy pixel row are held in the correction value acquisition unit 532 and are also output to the outside of the first correction unit 53 via switches SW33, SW34, and SW35 in order (step S111).

[0094] In this manner, depending on the operating mode during the reading of the dummy pixel row, the correction value acquisition units 531 and 532 hold the output signals from the dummy pixel row as a first correction value and a second correction value, respectively. These correction values ​​are used when correcting the signals read from the effective pixel row for each pixel.

[0095] Next, the correction operation starting from step S114 will be described. The first and second correction values ​​mentioned above are assumed to already be held in the correction value acquisition units 531 and 532 by the process described above.

[0096] The signals input during the correction operation are those other than those from dummy pixel rows. In the following explanation, the input signals are assumed to be signals output from the effective pixel rows. Furthermore, the correction process is performed on the A+B image signal. The signals from the effective pixel rows are input to the subtraction unit 533 via switch SW31 (step S114).

[0097] The subtraction unit 533 corrects the horizontal dark shading shape by subtracting one of the first correction value and the second correction value from the signal output from the effective pixel row. The method for switching these correction values ​​will be explained below.

[0098] The signal of the effective pixel row input to the first correction unit 53 is read from the pixel array 10 in either the first or second operating mode. If the signal of the effective pixel row was read in the first operating mode (YES in step S115), the first identification signal output from the timing generation circuit 33 is at the L level (step S116). In this case, switch SW33 is switched to the terminal labeled "L" as shown in Figure 12. As a result, the first correction value held in the correction value acquisition unit 531 is output to the subtraction unit 533 via switches SW33 and SW34 (step S117). The subtraction unit 533 corrects the horizontal dark shading shape by subtracting the first correction value from the signal of the effective pixel row (step S118). The signal corrected by the subtraction unit 533 is output to the outside of the first correction unit 53 via switch SW35 (step S119).

[0099] On the other hand, if the signal of the effective pixel row is read out in the second operating mode (NO in step S115), the first identification signal output from the timing generation circuit 33 is at the H level (step S120). In this case, switch SW33 is switched to the terminal marked "H" as shown in Figure 12. As a result, the second correction value held in the correction value acquisition unit 532 is output to the subtraction unit 533 via switches SW33 and SW34 (step S121). The subtraction unit 533 corrects the horizontal dark shading shape by subtracting the second correction value from the signal of the effective pixel row (step S122). The signal corrected by the subtraction unit 533 is output to the outside of the first correction unit 53 via switch SW35 (step S123).

[0100] In this way, the subtraction unit 533 performs correction using different correction values ​​depending on the operating mode when the signal from the effective pixel row is read out. This makes it possible to appropriately correct the difference in the horizontal dark shading shape.

[0101] In this embodiment, the first correction unit 53 can perform the same correction on OB pixel rows as on effective pixel rows. However, the first correction unit 53 may be configured to output OB pixel row output signals to the outside without correction by appropriately arranging switches to switch the path through which the signal passes.

[0102] Figures 14(a), 14(b), and 14(c) are graphs showing the effect of correction in the signal processing circuit 50. The vertical and horizontal axes of the graphs are the same as those shown in Figure 8(b), so their explanation is omitted.

[0103] Figure 14(a) is a graph showing the shape of the horizontal dark shading before correction. As mentioned above, there are differences in both the offset and shape of the horizontal dark shading between the first and second operating modes.

[0104] Figure 14(b) is a graph showing the shape of the horizontal dark shading for each operating mode, corrected by the second correction unit 52. The offset component difference is reduced because the correction value corresponding to the dark current component calculated by the averaging units 522 and 523 of the second correction unit 52 is subtracted.

[0105] Figure 14(c) is a graph showing the shape of the horizontal dark shading for each operating mode, corrected by the first correction unit 53. Because the correction values ​​calculated by the correction value acquisition units 531 and 532 of the first correction unit 53 are subtracted, a generally uniform horizontal dark shading shape is obtained with respect to the column address in both the first and second operating modes. As a result, the horizontal dark shading shapes of the first and second operating modes are sufficiently similar, which reduces the signal level difference in the image that may occur at the boundary between normal rows and focus detection rows.

[0106] As described above, this embodiment provides a photoelectric converter capable of appropriately correcting horizontal dark shading.

[0107] In this embodiment, the output signal from the dummy pixel row is used in the calculation of the correction value in the first correction unit 53, but the output signal from the OB pixel row may also be used for a similar correction process. For example, in environments where the dark current component is sufficiently small, such as in low-temperature environments, the output signal from the OB pixel row can be substituted for the output signal from the dummy pixel row. Furthermore, although the processing performed in the subtraction unit 533 is subtraction, the correction may be performed by another arithmetic process. For example, depending on the horizontal dark shading shape, the subtraction performed in the subtraction unit 533 may be replaced with addition.

[0108] [Second Embodiment] A photoelectric conversion device according to the second embodiment will be described with reference to Figures 15 to 17. In this embodiment, an example of a configuration in which dummy pixel regions are intermittently arranged within the same row and a method for calculating the correction value in that case will be described. Elements common to the first embodiment may be omitted or simplified as appropriate.

[0109] Figure 15 shows the layout of the pixel array 10 in this embodiment. In this embodiment, dummy pixel areas 13a, 13b, and 13c are arranged in the pixel array 10 instead of the dummy pixel area 13 in Figure 3. Multiple dummy pixel areas 13a, 13b, and 13c are arranged intermittently within the same row, as shown in Figure 15. OB pixel areas 12 are arranged between dummy pixel area 13a and dummy pixel area 13b, and between dummy pixel area 13b and dummy pixel area 13c. This expands the range of the OB pixel area 12, which can improve the accuracy of the correction process (OB clamping) of the output signal of the effective pixel 100 using the output signal of the OB pixels. In this embodiment, a row containing the intermittently arranged dummy pixel areas 13a, 13b, and 13c is called a dummy pixel row.

[0110] Next, the first correction unit 53 in this embodiment will be described with reference to Figures 16 and 17. The first correction unit 53 in this embodiment performs a correction process to reduce the horizontal dark shading shape difference of the black level using a correction value estimated using the signal from the dummy pixels in the dummy pixel row.

[0111] Figure 16 is a block diagram of the first correction unit 53 of the photoelectric converter in this embodiment. The first correction unit 53 includes correction value acquisition units 531, 532, subtraction unit 533, correction value estimation units 534, 535, and switches SW31, SW32, SW33, SW34, SW35, SW36, and SW37. Switches SW32 and SW33 are switched based on the level of the first identification signal, similar to the first embodiment. Switches SW31, SW34, SW35, SW36, and SW37 are switched based on the level of the second identification signal, similar to the first embodiment. In other words, in this embodiment, correction value estimation units 534, 535 and switches SW36 and SW37 are added to the configuration of the first embodiment.

[0112] The correction value acquisition units 531 and 532, similar to the first embodiment, each store the signals read from the pixels of the dummy pixel row in the first and second operating modes, respectively. The correction value estimation units 534 and 535 receive the output values ​​of the dummy pixel regions 13a, 13b, and 13c within the dummy pixel row and the column address values ​​within the row of those regions, respectively, from the correction value acquisition units 531 and 532. Based on the output information of the dummy pixel regions 13a, 13b, and 13c, each of the correction value estimation units 534 and 535 calculates the output values ​​assuming that dummy pixels exist in all columns of the dummy pixel row and stores them as correction values. This makes it possible to estimate the correction values ​​for columns in the dummy pixel row that do not contain dummy pixels. One example of a calculation method is to use the information of intermittently arranged dummy pixel regions 13a, 13b, and 13c to calculate the values ​​corresponding to the pixels between them using polynomial approximation.

[0113] As an example of polynomial approximation, we will explain an example of a calculation method using a quadratic equation. Let A be the average output value of dummy pixel region 13a, and B be the average value of the address values ​​in the column direction of that region. Let C be the average output value of dummy pixel region 13b, and D be the average value of the address values ​​in the column direction of that region. Let E be the average output value of dummy pixel region 13c, and F be the average value of the address values ​​in the column direction of that region. In this case, the quadratic equation for estimating the horizontal dark shading shape of the entire row of dummy pixels is calculated by solving the following system of three equations consisting of equations (1), (2), and (3) to find P, Q, and R. A=B 2 P+B·Q+R (1) C=D 2 P+D·Q+R (2) E=F 2 P+F·Q+R (3) The quadratic equation representing the horizontal dark shading shape calculated from equations (1), (2), and (3) is given by equation (4) below. Y=P·X 2 +Q·X+R (4) Here, X is the column address, Y is the correction value for each column address, and P, Q, and R are coefficients calculated from the system of equations.

[0114] Switch SW36 outputs the output signal from the correction value acquisition unit 531 to switch SW33 when the second identification signal is at an H level, and outputs the output signal from the correction value estimation unit 534 to switch SW33 when the second identification signal is at an L level.

[0115] Switch SW37 outputs the output signal from the correction value acquisition unit 532 to switch SW33 when the second identification signal is at an H level, and outputs the output signal from the correction value estimation unit 535 to switch SW33 when the second identification signal is at an L level.

[0116] The subtraction unit 533 subtracts the signal output from switch SW34 from the signal output from switch SW31 and outputs the result to switch SW35. In other words, the subtraction unit 533 performs a process to correct the pixel signals output from the effective pixels 100 of the effective pixel row using the correction value estimated by the correction value estimation unit 534 or 535.

[0117] Next, the correction processing procedure of the first correction unit 53 in this embodiment will be described with reference to Figure 17. Figure 17 is a processing flowchart of the first correction unit 53 in this embodiment. Figure 17 shows the processing from when a signal read from one pixel row is input to the first correction unit 53 until it is output. In Figure 17, steps that are common with the flowchart in Figure 13 of the first embodiment are denoted by the same reference numerals, and their explanations may be omitted or simplified.

[0118] Similar to the first embodiment, in this embodiment as well, when a signal is input to the first correction unit 53, a correction value acquisition operation (step S104) is performed if the second identification signal is at an H level, and a correction operation (step S113) is performed if the second identification signal is at an L level. When the second identification signal is at an H level, switches SW31, SW34, SW35, SW36, and SW37 are switched to the terminals marked "H" as shown in Figure 16. The correction value acquisition operation starting from step S104 and the correction operation starting from step S113 will be described in order below. First, the correction value acquisition operation starting from step S104 will be described.

[0119] If the signal of the dummy pixel row input to the first correction unit 53 is read out in the first operating mode (YES in step S105), the first identification signal output from the timing generation circuit 33 is at the L level (step S106). In this case, switch SW32 is switched to the terminal labeled "L" as shown in Figure 16. The signal of the dummy pixel row read out in the first operating mode is input to the correction value acquisition unit 531 via switches SW31 and SW32.

[0120] The correction value acquisition unit 531 stores the signals of the input dummy pixel rows in line memory for each pixel (step S107). The signals held in this line memory are used in calculations by the correction value estimation unit 534. The correction value acquisition unit 531 may also have an averaging unit. If there are multiple dummy pixel rows read out in the first operation mode, the averaging unit may perform an averaging process of the signals of the multiple rows.

[0121] The input dummy pixel row signals are held in the correction value acquisition unit 531 and are also output to the outside of the first correction unit 53 via switches SW36, SW33, SW34, and SW35 in order (step S108).

[0122] The correction value estimation unit 534 obtains output information in the dummy pixel regions 13a, 13b, and 13c from the correction value acquisition unit 531 and estimates the horizontal dark shading shape assuming that the entire row of dummy pixels is a dummy pixel (step S124). A specific calculation process that may be used for this estimation could be, for example, the polynomial approximation described above. The estimated horizontal dark shading shape is used as the first correction value.

[0123] On the other hand, if the signal of the dummy pixel row is read out in the second operating mode (NO in step S105), the first identification signal output from the timing generation circuit 33 is at the H level (step S109). In this case, switch SW32 is switched to the terminal marked "H" as shown in Figure 16. The signal of the dummy pixel row read out in the second operating mode is input to the correction value acquisition unit 532 via switches SW31 and SW32.

[0124] The correction value acquisition unit 532, like the correction value acquisition unit 531, stores the signals of the input dummy pixel rows in line memory for each pixel (step S110). The signals held in this line memory are used in calculations by the correction value estimation unit 535. The signals of the input dummy pixel rows are held in the correction value acquisition unit 532 and are also output to the outside of the first correction unit 53 via switches SW37, SW33, SW34, and SW35 in order (step S111).

[0125] The correction value estimation unit 535 obtains output information in the dummy pixel regions 13a, 13b, and 13c from the correction value acquisition unit 532 and estimates the horizontal dark shading shape assuming that the entire row of dummy pixels is a dummy pixel (step S125). A specific calculation process that may be used for this estimation is, for example, the polynomial approximation described above. The estimated horizontal dark shading shape is used as the second correction value.

[0126] In this manner, depending on the operating mode during the reading of the dummy pixel row, the correction value acquisition units 531 and 532 acquire the output signal from the dummy pixel row, and the correction value estimation units 534 and 535 estimate the first correction value and the second correction value. These correction values ​​are used when correcting the signal read from the effective pixel row for each pixel.

[0127] Next, the correction operation starting from step S113 will be described. The first and second correction values ​​described above are assumed to already be held in the correction value estimation units 534 and 535 by the process described above.

[0128] The signals input during the correction operation are those other than those from dummy pixel rows. In the following explanation, the input signals are assumed to be signals output from the effective pixel rows. Furthermore, the correction process is performed on the A+B image signal. The signals from the effective pixel rows are input to the subtraction unit 533 via switch SW31 (step S114).

[0129] The subtraction unit 533 corrects the horizontal dark shading shape by subtracting one of the first correction value and the second correction value from the signal output from the effective pixel row. The method for switching these correction values ​​will be explained below.

[0130] The signal of the effective pixel row input to the first correction unit 53 is read from the pixel array 10 in either the first or second operating mode. If the signal of the effective pixel row was read in the first operating mode (YES in step S115), the first identification signal output from the timing generation circuit 33 is at the L level (step S116). In this case, switch SW33 is switched to the terminal marked "L" as shown in Figure 16. Also, because the second identification signal is at the L level, switches SW36 and SW34 are also switched to the terminals marked "L" as shown in Figure 16. As a result, the first correction value held in the correction value estimation unit 534 is output to the subtraction unit 533 via switches SW36, SW33, and SW34 (step S126). The subtraction unit 533 corrects the horizontal dark shading shape by subtracting the first correction value from the signal of the effective pixel row (step S118). The signal corrected by the subtraction unit 533 is output to the outside of the first correction unit 53 via the switch SW35 (step S119).

[0131] On the other hand, if the signal of the effective pixel row is read out in the second operating mode (NO in step S115), the first identification signal output from the timing generation circuit 33 is at the H level (step S120). In this case, switch SW33 is switched to the terminal marked "H" as shown in Figure 16. Also, because the second identification signal is at the L level, switches SW36 and SW34 are switched to the terminals marked "L" as shown in Figure 16. As a result, the second correction value held in the correction value estimation unit 535 is output to the subtraction unit 533 via switches SW37, SW33, and SW34 (step S127). The subtraction unit 533 corrects the horizontal dark shading shape by subtracting the second correction value from the signal of the effective pixel row (step S122). The signal corrected by the subtraction unit 533 is output to the outside of the first correction unit 53 via switch SW35 (step S123).

[0132] In this way, the subtraction unit 533 performs correction using different correction values ​​depending on the operating mode when the signal from the effective pixel row is read out. This makes it possible to appropriately correct the difference in the horizontal dark shading shape.

[0133] As described above, this embodiment provides a photoelectric converter that can appropriately correct horizontal dark shading, similar to the first embodiment, even when dummy pixel regions are intermittently arranged within the same row. Furthermore, since the range of the OB pixel region 12 can be expanded, the accuracy of the OB clamping process can be improved.

[0134] In this embodiment, there are three dummy pixel regions intermittently arranged in the same row, but the number of pixel regions is not limited to this. Furthermore, even in a configuration where the dummy pixel regions are not intermittently arranged, as in the first embodiment, the correction value estimation process of this embodiment may be applied by dividing the region used for calculations within the dummy pixel region into several parts. In addition, although an example is shown where the degree of the polynomial used for estimation in the estimation of the correction value is second, the degree may be changed as appropriate. Values ​​obtained by calculations inside the photoelectric converter may be applied to the coefficients of the polynomial, or the coefficients may be set by providing a register to hold the coefficients inside the photoelectric converter and inputting the coefficients from the outside.

[0135] In this embodiment, the output signal from the dummy pixel row is used in the calculation of the correction value in the first correction unit 53, but the output signal from the OB pixel row may also be used for the same correction process. For example, in environments where the dark current component is sufficiently small, such as in low-temperature environments, the output signal from the OB pixel row can be substituted for the output signal from the dummy pixel row. In this case, instead of the dummy pixel regions 13a, 13b, and 13c in Figure 15, multiple OB pixel regions may be intermittently arranged within the same row. The correction value estimation process of this embodiment may then be applied similarly to the output signals from multiple OB pixel regions intermittently arranged within the same row. This provides a photoelectric converter that can appropriately correct horizontal dark shading in the same way as in the first embodiment, even when the OB pixel regions are intermittently arranged within the same row.

[0136] [Third Embodiment] A photoelectric conversion device according to the third embodiment will be described with reference to Figures 18 to 20. In this embodiment, a correction method is described in which focus detection lines are corrected but normal lines are not. In this method, although the horizontal dark shading shape is not reduced, the difference in horizontal dark shading shape due to differences in the readout operation mode can be reduced. The configuration of this embodiment is suitable when a signal processing circuit that corrects the horizontal dark shading shape of the entire image to be uniform is arranged downstream of the photoelectric conversion device. Elements common to the first embodiment may be omitted or simplified as appropriate.

[0137] The first correction unit 53 in this embodiment will be described with reference to Figures 18 and 19. The first correction unit 53 in this embodiment performs a correction process to bring the shape of the horizontal dark shading in the two operating modes closer together.

[0138] Figure 18 is a block diagram of the first correction unit 53 of the photoelectric converter in this embodiment. The first correction unit 53 includes correction value acquisition units 531 and 532, a correction value calculation unit 536, an addition unit 537, and switches SW31, SW32, SW35, SW38, SW39, SW40, SW41, and SW42. Switches SW32, SW38, SW41, and SW42 are switched based on the level of a first identification signal, similar to the first embodiment. Switches SW31, SW35, SW39, and SW40 are switched based on the level of a second identification signal, similar to the first embodiment.

[0139] The correction value acquisition units 531 and 532, similar to the first embodiment, each store the signals read from the pixels of the dummy pixel row in the first and second operating modes, respectively. The correction value calculation unit 536 calculates the difference between the signal of the dummy pixel row input to the correction value acquisition unit 531 and the signal of the dummy pixel row input to the correction value acquisition unit 532. As a result, the correction value calculation unit 536 calculates the relative amount of shift in horizontal dark shading in the two operating modes and stores this as the third correction value.

[0140] Switch SW38 outputs the output signal from the correction value acquisition unit 531 to switch SW39 when the first identification signal is at an L level, and outputs the output signal from the correction value acquisition unit 532 to switch SW39 when the first identification signal is at an H level.

[0141] Switch SW39 outputs the output signal from the correction value calculation unit 536 to switch SW40 when the second identification signal is at an L level, and outputs the output signal from switch SW38 to switch SW40 when the second identification signal is at an H level.

[0142] Switch SW40 outputs the output signal from switch SW39 to the adder 537 when the second identification signal is at a low level, and outputs the output signal from switch SW39 to switch SW35 when the second identification signal is at a high level.

[0143] Switch SW31 outputs a signal to switch SW41 when the second identification signal is at a low level, and outputs a signal to switch SW32 when the second identification signal is at a high level. Switch SW41 outputs a signal to switch SW42 when the first identification signal is at a low level, and outputs a signal to the adder 537 when the first identification signal is at a high level.

[0144] The adder 537 adds the signal output from switch SW41 and the signal output from switch SW40 and outputs the result to switch SW42. In other words, the adder 537 corrects the pixel signal output from the effective pixel row using a third correction value held in the correction value calculation unit 536.

[0145] Switch SW42 outputs the output signal from switch SW41 to switch SW35 when the first identification signal is at a low level, and outputs the output signal from the adder 537 to switch SW35 when the first identification signal is at a high level. In other words, when the first identification signal is at a high level, correction processing is performed in the adder 537, but when the first identification signal is at a low level, no correction processing is performed in the adder 537.

[0146] Next, the correction processing procedure of the first correction unit 53 in this embodiment will be described with reference to Figure 19. Figure 19 is a processing flowchart of the first correction unit 53 in this embodiment. Figure 19 shows the processing from when a signal read from one pixel row is input to the first correction unit 53 until it is output. In Figure 19, steps that are common with the flowchart in Figure 13 of the first embodiment are denoted by the same reference numerals, and their explanations may be omitted or simplified.

[0147] Similar to the first embodiment, in this embodiment as well, when a signal is input to the first correction unit 53, a correction value acquisition operation (step S104) is performed if the second identification signal is at an H level, and a correction operation (step S113) is performed if the second identification signal is at an L level. When the second identification signal is at an H level, switches SW31, SW35, SW39, and SW40 are switched to the terminals marked "H" as shown in Figure 18. The correction value acquisition operation starting from step S104 and the correction operation starting from step S113 will be described in order below. First, the correction value acquisition operation starting from step S104 will be described.

[0148] If the signal of the dummy pixel row input to the first correction unit 53 is read out in the first operating mode (YES in step S105), the first identification signal output from the timing generation circuit 33 is at the L level (step S106). In this case, switch SW32 is switched to the terminal labeled "L" as shown in Figure 18. The signal of the dummy pixel row read out in the first operating mode is input to the correction value acquisition unit 531 via switches SW31 and SW32.

[0149] The correction value acquisition unit 531 stores the signals of the input dummy pixel rows in line memory for each pixel (step S107). The signals held in this line memory are used in calculations by the correction value calculation unit 536. The correction value acquisition unit 531 may also have an averaging unit. If there are multiple dummy pixel rows read out in the first operation mode, the averaging unit may perform an averaging process of the signals of the multiple rows.

[0150] The input dummy pixel row signals are held in the correction value acquisition unit 531 and are also output to the outside of the first correction unit 53 via switches SW38, SW39, SW40, and SW35 in order (step S108).

[0151] On the other hand, if the signal of the dummy pixel row is read out in the second operating mode (NO in step S105), the first identification signal output from the timing generation circuit 33 is at the H level (step S109). In this case, switch SW32 is switched to the terminal marked "H" as shown in Figure 18. The signal of the dummy pixel row read out in the second operating mode is input to the correction value acquisition unit 532 via switches SW31 and SW32.

[0152] The correction value acquisition unit 532, like the correction value acquisition unit 531, stores the signals of the input dummy pixel row in line memory for each pixel (step S110). The signals held in this line memory are used for calculations in the correction value calculation unit 536. The signals of the input dummy pixel row are held in the correction value acquisition unit 532 and are also output to the outside of the first correction unit 53 via switches SW38, SW39, SW40, and SW35 in order (step S111).

[0153] The correction value calculation unit 536 calculates the difference between the dummy row signals held in the correction value acquisition units 531 and 532, and calculates the relative amount of the horizontal dark shading shift in the two operating modes as a third correction value (step S128). This third correction value is used when correcting the signal read out from the focus detection row of the effective pixel row for each pixel.

[0154] Next, the correction operation starting from step S113 will be described. Assume that the third correction value described above is already stored in the correction value calculation unit 536 as a result of the above process.

[0155] The signals input during the correction operation are those other than those from dummy pixel rows. In the following explanation, the input signals are assumed to be those output from the effective pixel rows. Furthermore, the correction process is performed on the A+B image signal. The signals from the effective pixel rows are input to switch SW31.

[0156] The signals of the effective pixel rows input to the first correction unit 53 are read from the pixel array 10 in either the first or second operating mode. If the signals of the effective pixel rows were read in the first operating mode (YES in step S115), the first identification signal output from the timing generation circuit 33 is at the L level (step S116). In this case, switches SW41 and SW42 are switched to the terminals marked "L" as shown in Figure 18. Also, because the second identification signal is at the L level, switches SW31 and SW35 are also switched to the terminals marked "L" as shown in Figure 18. As a result, the signals of the effective pixel rows input to the first correction unit 53 are output to the outside of the first correction unit 53 via switches SW31, SW41, SW42, and SW35 without passing through the summing unit 537 (step S119). In other words, no horizontal dark shading correction is performed on the signals of the effective pixel rows read in the first operating mode.

[0157] On the other hand, if the signal of the effective pixel row is read out in the second operating mode (NO in step S115), the first identification signal output from the timing generation circuit 33 is at the H level (step S120). In this case, switches SW41 and SW42 are switched to the terminals marked "H" as shown in Figure 18. Also, because the second identification signal is at the L level, switches SW31 and SW35 are switched to the terminals marked "L" as shown in Figure 18. As a result, the signal of the effective pixel row input to the first correction unit 53 is input to the adder 537 via switches SW31 and SW41 (step S129).

[0158] Furthermore, because the second identification signal is at an L level, switches SW39 and SW40 are switched to the terminals labeled "L" as shown in Figure 18. As a result, the third correction value held in the correction value calculation unit 536 is output to the adder 537 via switches SW39 and SW40 (step S130). The adder 537 corrects the horizontal dark shading shape by adding the third correction value to the signal of the effective pixel row (step S122). The signal corrected by the adder 537 is output to the outside of the first correction unit 53 via switches SW42 and SW35 (step S123).

[0159] Thus, the first correction unit 53 of this embodiment corrects only the signal read out in the second operation mode, using the horizontal dark shading shape of the signal read out in the first operation mode as a reference. This reduces the relative difference in the horizontal dark shading shapes.

[0160] Figures 20(a), 20(b), and 20(c) are graphs showing the effect of correction in the signal processing circuit 50. The vertical and horizontal axes of the graphs are the same as those shown in Figure 8(b), so no explanation is given.

[0161] Figure 20(a) is a graph showing the shape of the horizontal dark shading before correction. As mentioned above, there are differences in both the offset and shape of the horizontal dark shading between the first and second operating modes.

[0162] Figure 20(b) is a graph showing the shape of the horizontal dark shading for each operating mode, corrected by the second correction unit 52. The offset component difference is reduced because the correction value corresponding to the dark current component calculated by the averaging units 522 and 523 of the second correction unit 52 is subtracted.

[0163] Figure 20(c) is a graph showing the shape of horizontal dark shading for each operating mode, corrected by the first correction unit 53. The shape of horizontal dark shading in the first operating mode is not corrected. However, the shape of horizontal dark shading in the second operating mode is corrected to approximate the shape of horizontal dark shading in the first operating mode. This makes it possible to reduce the signal level difference in the image that may occur at the boundary between the normal row and the focus detection row.

[0164] As described above, this embodiment also provides a photoelectric converter capable of appropriately correcting horizontal dark shading.

[0165] In this embodiment, a correction method is applied in which the focus detection line is corrected but the normal line is not; however, the reverse may also be applied. That is, the first correction unit 53 may not correct the shape of the horizontal dark shading in the second operating mode, but rather correct only the signal read out in the first operating mode based on the horizontal dark shading shape of the signal read out in the second operating mode. In this case as well, the relative difference in the horizontal dark shading shapes is reduced.

[0166] [Fourth Embodiment] A photoelectric conversion device according to the fourth embodiment will be described with reference to Figure 21. In this embodiment, the arrangement and reading order of the OB pixel rows and dummy pixel rows have been changed. Elements common to the first embodiment may be omitted or simplified as appropriate.

[0167] Figure 21 shows the layout of the pixel array 10 in this embodiment. As shown in Figure 21, the dummy pixel row (third pixel row) is positioned between the effective pixel row (first pixel row) and the out-of-bounds pixel row (fourth pixel row).

[0168] The signal readout for each row is performed sequentially, starting from the first row in Figure 21. That is, in this embodiment, the dummy pixel row is read out after the OB pixel row is read out. Then, the effective pixel row is read out after the dummy pixel row has been read out.

[0169] Immediately after reading the first row, the power supply state from the power source may not be sufficiently settled in the photoelectric converter circuit due to the short elapsed time since power-on. This effect may appear in the output signal as variation or fixed pattern noise. In horizontal dark shading correction, it is necessary to obtain highly accurate correction values ​​for each pixel in the column direction. If the reading of the dummy pixel row signal used to obtain these correction values ​​is performed relatively later than the reading of the out-of-bounds (OB) pixel row, the accuracy degradation due to the above-mentioned factors can be reduced, and the correction accuracy can be improved. Therefore, according to this embodiment, the accuracy of the correction process can be further improved.

[0170] In this embodiment, the reading of dummy pixel rows is performed immediately before the reading of effective pixel rows, but this is not limited to this. If the power supply state is sufficiently stable, the reading of dummy pixel rows does not have to be immediately before the reading of effective pixel rows. For example, the reading of dummy pixel rows may be performed in the middle of the reading of multiple OB pixel rows. In other words, the reading order may be OB pixel row, dummy pixel row, OB pixel row, effective pixel row.

[0171] [Fifth Embodiment] The photoelectric converter in the above-described embodiment is applicable to various devices. Examples of such devices include digital cameras, digital camcorders, camera heads, photocopiers, fax machines, mobile phones, in-vehicle cameras, observation satellites, and surveillance cameras. Figure 22 shows a block diagram of a digital camera as an example of such a device.

[0172] The device 70 shown in Figure 22 includes a barrier 706, a lens 702, an aperture 704, and a photoelectric converter 700. The device 70 further includes a signal processing unit (processing unit) 708, a timing generation unit 720, an overall control / calculation unit 718 (control device), a memory unit 710 (storage device), a recording medium control I / F unit 716, a recording medium 714, and an external I / F unit 712. At least one of the barrier 706, lens 702, and aperture 704 is an optical device corresponding to the device. The barrier 706 protects the lens 702, and the lens 702 forms an optical image of the subject on the photoelectric converter 700. The aperture 704 makes the amount of light passing through the lens 702 variable. The photoelectric converter 700 is configured as in the above-described embodiment and converts the optical image formed by the lens 702 into image data (image signal). The signal processing unit 708 performs various corrections, data compression, etc., on the image data output from the photoelectric converter 700. The timing generation unit 720 outputs various timing signals to the photoelectric converter 700 and the signal processing unit 708. The overall control / calculation unit 718 controls the entire digital camera, and the memory unit 710 temporarily stores image data. The recording medium control I / F unit 716 is an interface for recording or reading image data to or from the recording medium 714, which is a removable recording medium such as a semiconductor memory for recording or reading image data. The external I / F unit 712 is an interface for communicating with an external computer or the like. Timing signals and the like may be input from outside the device. Furthermore, the device 70 may also include a display device (monitor, electronic viewfinder, etc.) that displays information obtained from the photoelectric converter. The device includes at least a photoelectric converter. Furthermore, the device 70 includes at least one of an optical device, a control device, a processing device, a display device, a storage device, and a mechanical device that operates based on information obtained from the photoelectric converter. The mechanical device is a movable part (for example, a robot arm) that operates in response to signals from the photoelectric converter.

[0173] Each pixel circuit may include multiple photoelectric conversion units (a first photoelectric conversion unit and a second photoelectric conversion unit). The signal processing unit 708 may be configured to process the pixel signal based on the charge generated in the first photoelectric conversion unit and the pixel signal based on the charge generated in the second photoelectric conversion unit, and to acquire distance information from the photoelectric conversion device 700 to the subject.

[0174] [Sixth Embodiment] Figures 23(a) and 23(b) are block diagrams of the equipment related to the in-vehicle camera in this embodiment. Equipment 80 includes a photoelectric converter 800 of the above-described embodiment and a signal processing device (processing device) that processes signals from the photoelectric converter 800. Equipment 80 includes an image processing unit 801 that performs image processing on a plurality of image data acquired by the photoelectric converter 800, and a parallax calculation unit 802 that calculates parallax (phase difference of parallax images) from a plurality of image data acquired by Equipment 80. Equipment 80 also includes a distance measurement unit 803 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 804 that determines whether or not there is a possibility of collision based on the calculated distance. Here, the parallax calculation unit 802 and the distance measurement unit 803 are examples of distance information acquisition means that acquire distance information to an object. That is, distance information is information related to parallax, defocus amount, distance to an object, etc. The collision determination unit 804 may use any of this distance information to determine the possibility of collision. The means for acquiring distance information may be implemented by specially designed hardware, or by a software module. It may also be implemented by an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), or a combination thereof.

[0175] Device 80 is connected to a vehicle information acquisition device 810 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. Device 80 is also connected to a control ECU 820, which is a control device that outputs a control signal to generate braking force on the vehicle based on the collision determination result of the collision determination unit 804. Furthermore, device 80 is connected to a warning device 830 that issues a warning to the driver based on the collision determination result of the collision determination unit 804. For example, if the collision determination result of the collision determination unit 804 indicates a high probability of collision, the control ECU 820 performs vehicle control to avoid a collision or mitigate damage by applying the brakes, releasing the accelerator, or suppressing engine output. The warning device 830 warns the user by sounding an alarm, displaying warning information on a screen such as a car navigation system, or vibrating the seatbelt or steering wheel. As described above, device 80 functions as a control means that controls the actions that control the vehicle.

[0176] In this embodiment, the device 80 images the area around the vehicle, for example, in front of or behind it. Figure 23(b) shows the device when imaging the area in front of the vehicle (imaging range 850). The vehicle information acquisition device 810, acting as an imaging control means, sends instructions to the device 80 or the photoelectric converter 800 to perform the imaging operation. This configuration allows for further improvement of the accuracy of distance measurement.

[0177] The above example described controlling a vehicle to avoid collisions with other vehicles, but it can also be applied to control systems that automatically follow other vehicles, or control systems that automatically stay within their lane. Furthermore, the equipment is not limited to vehicles such as automobiles, but can be applied to mobile objects (mobile devices) such as ships, aircraft, satellites, industrial robots, and consumer robots. In addition, it can be applied not only to mobile objects, but also to a wide range of devices that utilize object recognition or biometric recognition, such as intelligent transportation systems (ITS) and surveillance systems.

[0178] [Modified Embodiment] The present invention is not limited to the embodiments described above and can be modified in various ways. For example, an example in which a part of the configuration of one embodiment is added to another embodiment, or an example in which a part of the configuration of one embodiment is replaced with a part of the configuration of another embodiment, is also an embodiment of the present invention.

[0179] The disclosures in this specification include the complements of the concepts described herein. That is, if this specification contains a statement such as "A is B" (A=B), the specification shall be deemed to disclose or imply "A is not B" (A≠B) even if a statement such as "A is not B" is omitted. This is because the statement "A is B" presupposes that the case where "A is not B" is being considered.

[0180] The disclosures in this specification include the following components: (Composition 1) A pixel array in which multiple pixels are arranged across multiple rows and multiple columns, comprising: a first pixel row including a first pixel having multiple photoelectric conversion units, each of which generates an electric charge based on incident light; and a second pixel row including non-photosensitive pixels that output a signal not based on the incident light; A readout unit that reads signals from the first pixel and the non-photosensitive pixel, A first correction unit corrects the signal read out from the first pixel, It has, In the second row of pixels, there are more non-photosensitive pixels than in the first row of pixels. In reading signals from the pixel array to the readout unit, it is possible to perform a first drive that outputs a signal based on the sum of the charges generated by each of the plurality of photoelectric conversion units, and a second drive that outputs a signal based on the charge generated by any of the plurality of photoelectric conversion units. A first operating mode, in which a signal is read from the pixels of one row by the first drive, and a second operating mode, in which a signal is read from the pixels of one row by performing the first drive and the second drive consecutively, can be switched on a row-by-row basis. The first correction unit generates a first correction value based on the output signal of the second pixel row read out in the first operating mode, generates a second correction value based on the output signal of the second pixel row read out in the second operating mode, and corrects the output signal of the first pixel row based on the first correction value and the second correction value. A photoelectric conversion device characterized by the following features. (Configuration 2) The second pixel row includes a second pixel that does not have a photoelectric conversion unit. A photoelectric conversion device according to configuration 1, characterized in that it is a photoelectric conversion device. (Composition 3) The second row of pixels includes a third pixel having multiple light-shielded photoelectric conversion units. A photoelectric conversion device according to configuration 1 or 2, characterized by the above. (Composition 4) The first correction unit corrects the output signal of the first pixel row read out in the first operating mode by the first correction value, and corrects the output signal of the first pixel row read out in the second operating mode by the second correction value. A photoelectric conversion device according to any one of configurations 1 to 3, characterized by the above. (Composition 5) The aforementioned second pixel row includes a second pixel that does not have a photoelectric conversion unit, The aforementioned second pixels are arranged intermittently in multiple locations within a single row. The first correction unit generates the first correction value and the second correction value based on the output signals of the plurality of second pixels. A photoelectric conversion device according to any one of configurations 1 to 4, characterized by the above. (Composition 6) The first correction unit performs the following process in generating the first and second correction values: it estimates the first and second correction values ​​for rows where no second pixels are present, based on the output signals of a plurality of second pixels. The photoelectric conversion device according to configuration 5, characterized in that it is a photoelectric conversion device. (Composition 7) The first correction unit performs the following process in generating the first and second correction values: it estimates the first and second correction values ​​for columns where no second pixels are present by approximating the output signals of each of the multiple second pixels with a polynomial. A photoelectric conversion device according to configuration 5 or 6, characterized by the above. (Composition 8) The second row of pixels includes a third pixel having a plurality of light-shielded photoelectric conversion units, The aforementioned third pixels are arranged intermittently in multiple locations within a single row. The first correction unit generates the first correction value and the second correction value based on the signals of the plurality of third pixels. A photoelectric conversion device according to any one of configurations 1 to 4, characterized by the above. (Composition 9) The first correction unit performs the following process in generating the first and second correction values: it estimates the first and second correction values ​​for rows where no third pixels are present, based on the output signals of a plurality of third pixels. The photoelectric conversion device according to configuration 8, characterized by the above. (Composition 10) The first correction unit performs the process of estimating the first and second correction values ​​for columns where no third pixels are present by approximating the output signals of each of the plurality of third pixels with a polynomial in the generation of the first and second correction values. A photoelectric conversion device according to configuration 8 or 9, characterized by the above. (Composition 11) The first correction unit generates a third correction value based on the first correction value and the second correction value, and corrects the output signal of the first pixel row based on the third correction value. A photoelectric conversion device according to any one of configurations 1 to 3, characterized by the above. (Composition 12) The first correction unit corrects only one of the output signals read from the first pixel row in the first operating mode and the output signals read from the first pixel row in the second operating mode based on the third correction value. A photoelectric conversion device according to configuration 11, characterized by the features described above. (Composition 13) The second pixel row is composed of multiple rows, including a third pixel row containing a second pixel that does not have a photoelectric conversion unit, and a fourth pixel row containing a third pixel that has multiple light-shielded photoelectric conversion units. In the reading of signals from the pixel array to the readout unit, the reading of the third pixel row is performed between the reading of the fourth pixel row and the reading of the first pixel row. A photoelectric conversion device according to any one of configurations 1 to 12, characterized by the above. (Composition 14) The first pixel row further includes a third pixel having a plurality of light-shielded photoelectric conversion units. A photoelectric conversion device according to any one of configurations 1 to 13, characterized by the above. (Composition 15) The system further includes a second correction unit that generates a fourth correction value based on the output signal of the third pixel in the first pixel row read out in the first operating mode, generates a fifth correction value based on the output signal of the third pixel in the first pixel row read out in the second operating mode, and corrects the output signal of the first pixel row based on the fourth correction value and the fifth correction value. A photoelectric conversion device according to configuration 14, characterized by the features described above. (Composition 16) The second correction unit corrects the output signal of the first pixel row read out in the first operating mode by the fourth correction value, and corrects the output signal of the first pixel row read out in the second operating mode by the fifth correction value. A photoelectric conversion device according to configuration 15, characterized by the features described above. (Composition 17) It further has microlenses, The incident light that has passed through one of the microlenses is then incident on the plurality of photoelectric conversion units. A photoelectric conversion device according to any one of configurations 1 to 16, characterized by the above. (Composition 18) In the second operating mode, the first drive is performed after the second drive. A photoelectric conversion device according to any one of configurations 1 to 17, characterized by the above. (Composition 19) In the first pixel row, the first pixels are arranged from the first column closest to one end of the photoelectric converter to the second column closest to the end opposite to the one end. In the second pixel row, the second pixel is arranged from the first column to the second column. A photoelectric conversion device according to any one of configurations 1 to 18, characterized by the above. (Composition 20) A photoelectric conversion device according to any one of items 1 to 19, Optical device corresponding to the aforementioned photoelectric converter, A control device for controlling the aforementioned photoelectric converter, A processing device that processes the signal output from the aforementioned photoelectric converter, A display device that displays information obtained by the aforementioned photoelectric converter. A storage device for storing information obtained by the aforementioned photoelectric converter, and The system comprises at least one of the following: a mechanical device that operates based on information obtained from the photoelectric converter; A device characterized by the following features. (Composition 21) The processing device processes the image signals generated by each of the multiple photoelectric conversion units and acquires distance information from the photoelectric conversion device to the subject. The apparatus according to configuration 20, characterized by the features described above.

[0181] The present invention can also be realized by supplying a program that implements one or more of the functions of the above-described embodiments to a system or device via a network or storage medium, and by a process in which one or more processors in the computer of that system or device read and execute the program. It can also be realized by a circuit (e.g., an ASIC) that implements one or more functions.

[0182] It should be noted that the embodiments described above are merely examples of how the present invention can be implemented, and the technical scope of the present invention should not be interpreted as being limited by them. In other words, the present invention can be implemented in various ways without departing from its technical concept or its main features. [Explanation of Symbols]

[0183] 10-pixel array 40-column reading section 53. First Correction Section 100 effective pixels 101 effective pixel rows 200 non-photosensitive pixels 201 non-photosensitive pixel rows

Claims

1. A pixel array in which multiple pixels are arranged in multiple rows and multiple columns, comprising: a first pixel row including a first pixel having multiple photoelectric conversion units, each having multiple photoelectric conversion units that generate charge based on incident light; and a second pixel row including non-photosensitive pixels that output signals not based on the incident light; A readout unit that reads signals from the first pixel and the non-photosensitive pixel, A first correction unit corrects the signal read from the first pixel, It has, In the second row of pixels, there are more non-photosensitive pixels than the first row of pixels. In reading signals from the pixel array to the readout unit, it is possible to perform a first drive that outputs a signal based on the sum of the charges generated by each of the plurality of photoelectric conversion units, and a second drive that outputs a signal based on the charge generated by any of the plurality of photoelectric conversion units. A first operating mode, in which a signal is read from the pixels of one row by the first drive, and a second operating mode, in which a signal is read from the pixels of one row by performing the first drive and the second drive consecutively, can be switched on a row-by-row basis. The first correction unit includes a first correction value acquisition unit and a second correction value acquisition unit, each of which holds a plurality of correction values ​​generated based on the output signal of the second pixel row. The first correction unit holds a first correction value group in the first correction value acquisition unit, which includes at least two values ​​generated based on the output signal of the second pixel row read out in the first operation mode; a second correction value group in the second correction value acquisition unit, which includes at least two values ​​generated based on the output signal of the second pixel row read out in the second operation mode; and corrects the output signal of the first pixel row based on the first correction value group and the second correction value group. A photoelectric conversion device characterized by the following features.

2. The second pixel row includes a second pixel that does not have a photoelectric conversion unit. The photoelectric conversion device according to feature 1.

3. The second row of pixels includes a third pixel having a plurality of light-shielded photoelectric conversion units. The photoelectric conversion device according to feature 1.

4. The first correction unit corrects the output signal of the first pixel row read out in the first operating mode using the first correction value group, and corrects the output signal of the first pixel row read out in the second operating mode using the second correction value group. The photoelectric conversion device according to feature 1.

5. The second pixel row includes a second pixel that does not have a photoelectric conversion unit. The aforementioned second pixels are arranged intermittently in multiple locations within a single row. The first correction unit generates the first correction value group and the second correction value group based on the output signals of the plurality of second pixels. The photoelectric conversion device according to feature 1.

6. The first correction unit performs the following process in generating the first and second correction value groups: it estimates the first and second correction value groups for rows where no second pixels are present, based on the output signals of a plurality of second pixels. The photoelectric conversion device according to feature 5.

7. The first correction unit performs the following process in generating the first and second correction value groups: it estimates the first and second correction value groups for columns where no second pixels are present by approximating the output signals of each of the multiple second pixels with a polynomial. The photoelectric conversion device according to feature 5.

8. The aforementioned second row of pixels includes a third pixel having a plurality of light-shielded photoelectric conversion units, The aforementioned third pixels are arranged intermittently in multiple locations within a single row. The first correction unit generates the first correction value group and the second correction value group based on the signals of the plurality of third pixels. The photoelectric conversion device according to feature 1.

9. The first correction unit performs the following process in generating the first and second correction value groups: it estimates the first and second correction value groups for rows where no third pixels are present, based on the output signals of a plurality of third pixels. The photoelectric conversion device according to feature 8.

10. The first correction unit performs the following process in generating the first and second correction value groups: it estimates the first and second correction value groups for columns where no third pixels are present by approximating the output signals of each of the plurality of third pixels with a polynomial. The photoelectric conversion device according to feature 8.

11. The first correction unit generates a third correction value group based on the first correction value group and the second correction value group, and corrects the output signal of the first pixel row based on the third correction value group. The photoelectric conversion device according to feature 1.

12. The first correction unit corrects only one of the output signals read from the first pixel row in the first operating mode and the output signals read from the first pixel row in the second operating mode, based on the third correction value group. The photoelectric conversion device according to feature 11.

13. The second pixel row is composed of multiple rows, including a third pixel row containing a second pixel that does not have a photoelectric conversion unit, and a fourth pixel row containing a third pixel that has a plurality of light-shielded photoelectric conversion units. In the reading of signals from the pixel array to the readout unit, the reading of the third pixel row is performed between the reading of the fourth pixel row and the reading of the first pixel row. The photoelectric conversion device according to feature 1.

14. The first pixel row further includes a third pixel having a plurality of light-shielded photoelectric conversion units. The photoelectric conversion device according to feature 1.

15. The system further includes a second correction unit that generates a fourth correction value group based on the output signal of the third pixel in the first pixel row read out in the first operating mode, generates a fifth correction value group based on the output signal of the third pixel in the first pixel row read out in the second operating mode, and corrects the output signal of the first pixel row based on the fourth and fifth correction value groups. The photoelectric conversion device according to feature 14.

16. The second correction unit corrects the output signal of the first pixel row read out in the first operating mode using the fourth correction value group, and corrects the output signal of the first pixel row read out in the second operating mode using the fifth correction value group. The photoelectric conversion device according to feature 15.

17. It further has microlenses, The incident light that has passed through one of the microlenses is then incident on the plurality of photoelectric conversion units. The photoelectric conversion device according to feature 1.

18. In the second operating mode, the first drive is performed after the second drive. The photoelectric conversion device according to feature 1.

19. In the first pixel row, the first pixels are arranged from the first column closest to one end of the photoelectric converter to the second column closest to the end opposite to the one end. In the second pixel row, the second pixel is arranged from the first column to the second column. The photoelectric conversion device according to feature 2.

20. A photoelectric conversion device according to any one of claims 1 to 19, Optical device corresponding to the aforementioned photoelectric converter, A control device for controlling the aforementioned photoelectric converter, A processing device that processes the signal output from the aforementioned photoelectric converter, A display device that displays information obtained by the aforementioned photoelectric converter. A storage device for storing information obtained by the aforementioned photoelectric converter, and The system comprises at least one of the following: a mechanical device that operates based on information obtained from the photoelectric converter; A device characterized by the following features.

21. The processing device processes the image signals generated by each of the multiple photoelectric conversion units and acquires distance information from the photoelectric conversion device to the subject. The apparatus according to claim 20.

Images