Photoelectric conversion devices and equipment

Abstract

To solve the problem in a correlation detection of higher time resolution.SOLUTION: A photoelectric conversion device comprises: an avalanche photodiode; and an integration circuit that performs an integration of an output signal of the avalanche photodiode by using a predetermined weight corresponded to an acquisition of an optical flow.SELECTED DRAWING: Figure 6

Description

Technical Field

[0001] The present disclosure relates to a photoelectric conversion device and a device including the photoelectric conversion device.

Background Art

[0002] As one of imaging sensors, a time-correlated image sensor is known.

[0003] Non-Patent Document 1 discloses a structure in which a correlation detection structure is embedded in pixels as a time-correlated image sensor. By providing this structure, a time-varying pattern with a bandwidth wider than the frame rate can be detected. As this correlation detection structure, a structure provided with a photodiode that generates a photocurrent and a plurality of capacitors that accumulate this photocurrent is disclosed.

Prior Art Documents

Non-Patent Documents

[0004]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In the structure described in Non-Patent Document 1, there is a problem in performing correlation detection with higher time resolution.

Means for Solving the Problems

[0006] The technology of the present disclosure is a photoelectric conversion device characterized by including an avalanche photodiode and an integration circuit that integrates an output signal of the avalanche photodiode using a predetermined weighting corresponding to acquisition of an optical flow. The circuit comprises a first logic circuit that outputs a first pulse signal using a plurality of input pulse signals, a quench element connected to the avalanche photodiode and to which the first pulse signal is input, a waveform shaping unit connected to the avalanche photodiode, a second logic circuit connected to the waveform shaping unit, and a third logic circuit that outputs a second pulse signal using the output of the second logic circuit and some of the pulse signals of the plurality of pulse signals, and the integration circuit performs the integration using the output of the third logic circuit.

[0007] The technology of the present disclosure is multiple an avalanche photodiode and the aforementioned multiple avalanche photodiode One of our avalanche photodiodes First integration circuit that performs integration of output signals First counter section having and, A second avalanche photodiode among the plurality of avalanche photodiodes. Second integration circuit that performs integration of output signals Second counter section having It comprises a weight control unit that outputs a weight amount, before The signal converted from the weight quantity to the number of pulses, the first Counter section and the second Counter section Give a weighting to it, The weighting amount in the first counter unit for the first output signal and the weighting amount in the second counter unit for the second output signal are different. This is a photoelectric conversion device characterized by [the following]. [Effects of the Invention]

[0008] The technology disclosed herein enables correlation detection with higher temporal resolution. [Brief explanation of the drawing]

[0009] [Figure 1] Diagram showing the configuration of a photoelectric converter. [Figure 2] A diagram showing the relationship between the mainframe, subframe, and weighting amount. [Figure 3] Diagram showing the structure of pixels [Figure 4] Diagram showing the structure of a stacked sensor [Figure 5] Diagram showing the configuration and operation of a pixel equipped with an avalanche photodiode. [Figure 6] Diagram showing the structure of pixels [Figure 7] Diagram showing the structure of pixels [Figure 8] Diagram showing the structure of pixels [Figure 9] Diagram showing the structure of pixels [Figure 10] Diagram showing the configuration of a photoelectric converter. [Figure 11] Timing diagram showing pixel drive [Figure 12] Diagram showing the configuration of the weight control unit. [Figure 13] Timing diagram showing the operation of the weight control unit. [Figure 14]Diagram showing the configuration of the weight control unit [Figure 15] Timing diagram showing the drive of the weight control unit [Figure 16] Diagram showing the configuration of the weight control unit [Figure 17] Timing diagram showing the drive of the weight control unit [Figure 18] Diagram showing the relationship between the memory configuration in the weight control unit and the weighting amount [Figure 19] Diagram showing the configuration of the device

Mode for Carrying Out the Invention

[0010] Hereinafter, each embodiment will be described with reference to the drawings.

[0011] In each of the embodiments described below, as an example of the photoelectric conversion device, an imaging device will be mainly described.However, each embodiment is not limited to the imaging device and can also be applied to other examples of the photoelectric conversion device.For example, there are ranging devices (devices for distance measurement using focus detection or TOF (Time Of Flight)), photometry devices (devices for measuring the incident light amount), and the like.

[0012] Note that the conductivity type of the transistor described in the embodiments below is an example and is not limited to only the conductivity type described in the examples.With respect to the conductivity type described in the embodiments, the conductivity type can be appropriately changed, and along with this change, the potentials of the gate, source, and drain of the transistor are appropriately changed.

[0013] For example, for a transistor that operates as a switch, the low level and high level of the potential supplied to the gate may be reversed with respect to the description in the examples along with the change in the conductivity type.Also, the conductivity type of the semiconductor region described in the examples below is an example and is not limited to only the conductivity type described in the examples.With respect to the conductivity type described in the examples, the conductivity type can be appropriately changed, and along with this change, the potential of the semiconductor region is appropriately changed.

[0014] Furthermore, in the following examples, connections between circuit elements may be described. In this case, even if another element is interposed between the elements of interest, unless otherwise specified, the elements of interest will be treated as connected. For example, suppose element A is connected to one node of a capacitive element C with multiple nodes, and element B is connected to the other node. Even in such a case, elements A and B will be treated as connected unless otherwise specified.

[0015] (First Embodiment) This embodiment will be described with reference to the drawings.

[0016] A sensor performing time-correlated imaging can be configured to include a photodiode and a mechanism for distributing the signals output by the photodiode. This distribution, where each pixel generates an image, can be expressed by the following equation (1).

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[0017] Here, f(x, y, t) is the brightness of pixel (x, y) at time t, and v is the velocity of pixel (x, y).

[0018] Let T be the exposure time for acquiring one frame of image. Also, let g(x, y) be expressed as shown in equation (2) below.

number

[0019] As shown in equation (2), the image has a brightness f(x, y, g) and a complex number e -inΔwt Multiplying by the reference signal yields the integral value over one frame. Assume that the captured image g(x, y) satisfies the following equation (3).

number

[0020] The second term in equation (3) is the integral boundary value. Since equation (3) is a system of equations, the integral boundary value can be eliminated by solving the system of equations using, for example, two images g0(x,y) and g1(x,y). The time-correlated image sensor can output an intensity image g0(x,y) consisting only of the real part, and the real and imaginary parts of a complex correlation image gn(x,y) (hereinafter, the complex correlation image will also be called the time-correlated signal). Therefore, by substituting the sensor detection results into the system of equations in equation (3) and solving it, the velocity v at each pixel, i.e., optical flow, can be obtained.

[0021] In a time-correlated image sensor, it is necessary to calculate the integral of one frame time, as shown in equation (2). Therefore, the output timing of the correlated image is limited to one frame time unit. In a time-correlated image sensor, the period of the reference signal and the shutter opening time are matched. Therefore, the output of the correlated image is output according to the period timing of the shutter opening time.

[0022] Here, we will provide an overview of event-based sensors.

[0023] An event-based sensor detects changes in brightness within its field of view and outputs an event signal for each detection. An event-based sensor is formed, for example, by including multiple pixels arranged in a matrix. An event signal is a signal associated with an event. An event is a change in the brightness of a pixel. An event signal, for example, includes the detection time of the event, the pixel location where the event occurred, and the change in pixel value. The time of event detection can be measured relative to the event-based sensor's internal clock (event camera time).

[0024] The time reference for event detection can be reset as needed. A change in pixel value is, for example, a change in brightness. A change in pixel value may be the amount of change itself, or it may be information indicating whether the brightness change is positive or negative.

[0025] An event-based sensor outputs an event signal only when a change in brightness occurs. In other words, an event-based sensor outputs event signals asynchronously. Here, "asynchronous output" means that the output is time-independent on a pixel-by-pixel basis.

[0026] The operation of the event-based sensor can be expressed mathematically as follows: Equation (4).

number

[0027] This Y(x,y,t) is the image at time t. Time t0 is the time when the measurement started. Image Y(x,y,t0) is the initial image stored at time t0. Generally, image Y(x,y,t0) can be set to 0. ΔY is the threshold for event occurrence (absolute value of brightness change). p(x,y,si) is the i-th event signal that occurred at pixel (x,y), and p(x,y,si) = ±1.

[0028] An event-based sensor can be equipped with the functionality to output a time-correlated signal, similar to that of a time-correlated image sensor. If time t is the end of the frame, the signal from the time-correlated image sensor can be expressed using the following equations (5) to (7), where ω = 2π / T.

number

[0029] Time-correlated image sensors represent brightness by storing the current output by a photodiode in a capacitor. On the other hand, event-based sensors represent brightness by quantizing the change in current from the photodiode. Therefore, in an event-based sensor, the current from the photodiode at time s can be divided into a term that remains constant over the measurement period and a displacement term from that point, as shown in equation (8) below.

number

[0030] Furthermore, considering the properties of the reference signal, the following equations (9) and (10) are satisfied.

number

[0031] This allows us to express it as shown in the following equations (11) to (13).

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[0032] In an event-based sensor, the current output by the photodiode of the time-correlated image sensor is converted into an event signal for the event-based sensor, as shown in the following equation (14).

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[0033] As a result, equations (11) to (13) can be transformed into equations (15) to (17) below.

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[0034] As shown in equations (15) to (17), a time correlation signal can be output using events that occur during the period (period T) over which the correlation is obtained.

[0035] (Configuration of the photoelectric converter) Figure 1 shows the configuration of the photoelectric conversion device according to this embodiment.

[0036] The photoelectric converter of this embodiment has a pixel array 51. The pixel array 51 has a plurality of pixels 110 arranged in multiple rows and multiple columns. The control unit 52 controls the reset operation and signal output operation of the plurality of pixels 110.

[0037] The weight control unit 53 controls the weighting (weighting amount) of the signal generated by the pixel 110. The readout unit 54 reads the signal output by the pixel 110, which has been instructed by the control unit 52 to perform a signal output operation. After performing various calculations, the readout unit 54 outputs a signal to the outside of the photoelectric converter. These various calculations may include processing related to time-correlated imaging.

[0038] Figure 2 shows an example of weighting control by the weight control unit 53. The unit exposure period is divided into multiple sub-exposure periods. The weighting amount (coefficient for the signal generated by the pixel 110) in these sub-exposure periods is changed, for example, along a sine wave. By changing the weighting amount in this way, a signal corresponding to the above-mentioned equation (17) can be generated. Alternatively, the weighting amount may be changed to a cosine wave. In this case, a signal corresponding to equation (16) can be generated.

[0039] Figure 3 shows the configuration of an APD pixel 110 (also referred to as pixel 110), which is an example of the pixel 110 shown in Figure 1. APD stands for Avalanche Photo Diode. The APD201 (avalanche photodiode) generates charge pairs corresponding to incident light through photoelectric conversion. A voltage VL (first voltage) is supplied to the anode of the APD201. A voltage VH (second voltage), higher than the voltage VL supplied to the anode, is supplied to the cathode of the APD201. A reverse bias voltage is supplied to the anode and cathode such that the APD201 performs avalanche multiplication. By supplying these voltages, the charge generated by the incident light undergoes avalanche multiplication, generating an avalanche current. As shown in Figure 4, the pixel 110 has a stacked structure consisting of a first chip 11 and a second chip 21. The first chip 11 is equipped with the APD201 shown in Figure 3. Furthermore, the other components of the pixel 110 in Figure 3 are provided on the second chip 21. The photoelectric converter of this embodiment has a so-called stacked sensor structure in which the first chip 11 and the second chip 21 are stacked.

[0040] When a reverse bias voltage is supplied, there are two modes of operation: Geiger mode, where the potential difference between the anode and cathode is greater than the breakdown voltage, and linear mode, where the potential difference between the anode and cathode is near or below the breakdown voltage. An APD operating in Geiger mode is called a SPAD. For example, voltage VL (first voltage) is -30V and voltage VH (second voltage) is 1V.

[0041] The quench unit 202 is connected to the APD201 and a power supply that provides voltage VH. The quench unit 202 has the function of converting the change in avalanche current generated in the APD201 into a voltage signal. When the signal is multiplied by avalanche multiplication, the quench unit 202 functions as a load circuit (quench circuit) and suppresses the voltage supplied to the APD201, thereby suppressing avalanche multiplication (quench operation).

[0042] The signal processing unit 103 includes a waveform shaping unit 210, a counter unit 211, and a selection circuit 212. In this specification, the signal processing unit 103 may include any one of the waveform shaping unit 210, the counter unit 211, or the selection circuit 212.

[0043] The waveform shaping unit 210 shapes the cathode potential change of the APD201 obtained during photon detection and outputs a pulse signal. For example, an inverter circuit can be used as the waveform shaping unit 210. Figure 3 shows an example in which one inverter is used as the waveform shaping unit 210, but a circuit in which multiple inverters are connected in series may be used, or other circuits that have a waveform shaping effect may be used.

[0044] The counter unit 211 counts the pulse signals output from the waveform shaping unit 210 and holds the count value. When a control pulse pRES is supplied via the drive line 213, the signal held in the counter unit 211 is reset.

[0045] The selection circuit 212 receives control pulses pSEL from the vertical scanning circuit section 110 in Figure 1 via the drive line 214 in Figure 3, which switches the electrical connection between the counter section 211 and the signal line 113. The selection circuit 212 includes, for example, a buffer circuit for outputting signals.

[0046] A switch such as a transistor may be placed between the quench unit 202 and the APD 201, or between the photoelectric conversion unit 102 and the signal processing unit 103, to switch the electrical connection. Similarly, the supply of voltage VH or voltage VL to the photoelectric conversion unit 102 may be electrically switched using a switch such as a transistor.

[0047] Figure 5 schematically shows the relationship between the operation of APD201 and the output signal. Here, we will explain assuming that the weighting amount by the weight control unit 53 is 1. Figure 5(a) is an excerpt of APD201, quench unit 202, and waveform shaping unit 210 from Figure 2. Here, the input side of the waveform shaping unit 210 is denoted as nodeA and the output side as nodeB. Figure 5(b) shows the waveform change of nodeA in Figure 5(a), and Figure 5(c) shows the waveform change of nodeB in Figure 5(a).

[0048] Between times t0 and t1, a potential difference of VH-VL is applied to APD201 in Figure 5(a).

[0049] When a photon is incident at time t1, an avalanche multiplication current flows through the quench section 202, causing the voltage at nodeA to drop. As the voltage drop increases further and the potential difference applied to APD201 decreases, the avalanche multiplication of APD201 stops, and the voltage level at nodeA no longer drops below a certain value. Subsequently, a current flows through nodeA to compensate for the voltage drop from the voltage VL, and at time t3, nodeA settles back to its original potential level.

[0050] At this time, any portion of the output waveform at nodeA that exceeds a certain threshold is reshaped by the waveform shaping unit 210 and output as a signal at nodeB.

[0051] Figure 6 is a configuration diagram showing the configuration of the pixel 110 in this embodiment in more detail. In Figure 6, components having the same function as those shown in Figure 2 are denoted by the same reference numerals as those used in Figure 2.

[0052] The quench unit 202 includes a quench element 202-1. The quench element 202-2 is a P-type MOS transistor. The signal PCLKB is input to this quench element 202-2 from the control unit 52 shown in Figure 1. This signal PCLKB is a clock signal, and is, for example, a pulse signal with a frequency of 1MHz to 200MHz. The number of pulses in one main frame can be set according to the number of bits of the counter unit 211, which will be described later, but if the counter unit 211 performs counting with 11 bits, the number of pulses is 2048.

[0053] The counter unit 211 includes a third integrator 211-3, a first integrator 211-1, and a second integrator 211-2. It also includes a multiplexer (MUX) 320-1, MUX 320-2, and an AND gate 330. The AND gate 330 outputs the logical AND signal of the output of the waveform shaping circuit 210 and the signal PCLKB to the third integrator 211-3, MUX 320-1, and MUX 320-2. The third integrator 211-3 counts the signal from the AND gate 330 with a weight of 1. In other words, it generates a counting result corresponding to the number of photons incident on the avalanche photodiode 211.

[0054] The weight control unit 53 shown in Figure 1 includes a sine wave generation unit 311 (first waveform generation unit) and a cosine wave generation unit 313 (second waveform generation unit). The sine wave generation unit 311 outputs multiple pulse signals as bus signals to the input node of the MUX320-1.

[0055] When the output of the AND circuit 330 is high, the MUX320-1 outputs the output of the sine wave generation unit 311 to the first integrator circuit 211-1. On the other hand, when the output of the AND circuit 330 is low, it outputs output 0 (ground voltage) to the first integrator circuit 211-1. The first integrator circuit 211-1 does not count up when output 0 is provided. The signal output by the sine wave generation unit 311 is set so that the counting operation of the first integrator circuit 211-1 becomes the weighted amount shown in Figure 2.

[0056] In this way, the first integrating circuit 211-1 counts up according to the value of the bus signal output by the sine waveform generation unit 311, provided that the output of the AND circuit 330 is at a high level. As a result, the first integrating circuit 211-1 can generate a signal with a sine component represented by equation (17).

[0057] The cosine waveform generation unit 313 outputs a bus signal, which is a series of pulse signals, to the input node of the MUX320-2.

[0058] When the output of the AND circuit 330 is high level, the MUX320-2 outputs the output of the cos waveform generation unit 313 to the second integrator circuit 211-2. On the other hand, when the output of the AND circuit 330 is low level, it outputs output 0 (ground voltage) to the second integrator circuit 211-2. The second integrator circuit 211-2 does not count up when output 0 is given. The signal output by the cos waveform generation unit 313 is set so that the counting operation of the second integrator circuit 211-2 corresponds to a weighting amount corresponding to a waveform in which the weighting of the sine waveform shown in Figure 2 is changed to a cosine waveform. In other words, at a predetermined time (timing), the weighting amounts of the first integrator circuit 211-1 and the second integrator circuit 211-2 are different. This is because one is a weighting amount corresponding to a sine waveform, and the other is a weighting amount corresponding to a cosine waveform. Furthermore, the weighting amounts of the first integration circuit 211-1 and the second integration circuit 211-2 do not need to be different at all time points. At a certain predetermined time (timing), the weighting amounts of the first integration circuit 211-1 and the second integration circuit 211-2 may be the same.

[0059] In this way, the second integrating circuit 211-2 counts up according to the value of the bus signal, which is a set of multiple pulse signals output by the cos waveform generation unit 313, when the output of the AND circuit 330 is at a high level. As a result, the second integrating circuit 211-2 can generate the cos component signal represented by equation (16).

[0060] The control unit 52 shown in Figure 1 outputs the signal P_RES to the first integrating circuit 211-1, the second integrating circuit 211-2, and the third integrating circuit 211-3. When this signal P_RES becomes high level, the signals held in each of the first integrating circuit 211-1, the second integrating circuit 211-2, and the third integrating circuit 211-3 are reset to their initial values. At the timing of starting the main frame shown in Figure 2, the signal P_RES becomes high level and then low level. This starts the counting operation in the main frame by the counting unit 211. Note that one main frame corresponds to one image.

[0061] The third integrating circuit 211-3 assigns a weight of 1 to the output of APD201, and this weight remains constant throughout the entire period during which the first and second integrating circuits perform integration with weighting. The weighting of the output of APD201 in the first integrating circuit 211-1 is a predetermined weight corresponding to a sine wave. The weighting of the output of APD201 in the second integrating circuit 211-2 is a predetermined weight corresponding to a cosine wave. In other words, the weighting of the output of APD201 in the third integrating circuit 211-3, the first integrating circuit 211-1, and the second integrating circuit 211-2 are all different from each other. That is, among the multiple integrating circuits, some integrating circuits and some other integrating circuits assign different weights to the output of APD201. By having this configuration, the photoelectric converter of this embodiment can realize time-correlated imaging. Furthermore, the photoelectric converter of this embodiment performs time-correlated imaging using APD201. This allows for suitable time-correlated imaging in low-luminance shooting scenes.

[0062] The sine wave generation unit 311 and the cosine wave generation unit 313 may be provided for each of the multiple pixels 110. Alternatively, the sine wave generation unit 311 and the cosine wave generation unit 313 may be provided for each of the multiple blocks, which are each made up of a portion of the multiple pixels 110.

[0063] (Second Embodiment) This description will focus on the differences between the photoelectric conversion device of this embodiment and the first embodiment.

[0064] In Embodiment 1, the pixels were equipped with integration circuits for obtaining cosine and sine components. In this embodiment, the signal input to the quench unit 202 is set to signals corresponding to the sine and cosine components. This makes it possible to perform time-correlated imaging using the APD201 without providing two integration circuits, one for the cosine component and one for the sine component.

[0065] Figure 7 shows the configuration of the pixel 110 in this embodiment. In Figure 7, components having the same function as those shown in Figure 6 are denoted by the same reference numerals as those used in Figure 6.

[0066] In this embodiment, the pixel 110 has a quench section 202 which includes a quench element 202-2. The output of the NAND circuit 411 (first logic circuit) (the first pulse signal, signal PCLKB) is input to the quench element 202-2. Multiple pulse signals are input to the NAND circuit 411. These multiple pulse signals are the signal P_DECI_CLK and the signal P_RCH_TRG shown in Figure 1. The logic circuit 401 is also input to the signal P_RCH_TRG output by the control unit 52. The output of the logic circuit 401 is shown as the signal TCLK. The signal P_DECI_CLK is generated by decimating some of the pulse signals from the clock signal input to the weight control unit 53. This clock signal decimation process is performed so that the integration circuit 460 integrates at a period corresponding to the weighting corresponding to the sin or cos component. Details will be described later. The signal P_RCH_TRG is high level at the start of a subframe. Furthermore, the signal P_RCH_TRG remains at a low level for the duration of one subframe. When both the signal P_RCH_TRG and the signal P_DECI_CLK are at a high level, the output of the NAND gate 411 becomes low. This turns on the quench element 202-2, which is a P-type MOS transistor, and performs a recharge operation on the APD201. This recharge operation is performed only once per subframe.

[0067] The output signal of the waveform shaping circuit 210 is input to the input terminal D of the flip-flop circuit 450 (second logic circuit). The signal P_RES output by the control unit 52 is input to the reset terminal R. The signal P_RCH_TRG is input to the clock input terminal. The AND circuit 455 (third logic circuit) generates a second pulse signal, which is the logical AND of the outputs of the logic circuit 401 and the flip-flop circuit 450. This second pulse signal obtained by the logical AND is input to the integrator circuit 460. The signal P_RES goes high at the start of one main frame. This resets the flip-flop circuit 450 and the integrator circuit 460.

[0068] In the pixel 110 of this embodiment, when a photon is incident on the APD201, the output of the waveform shaping circuit 210 becomes high level. This change in the output of the waveform shaping circuit 210 causes the output Q of the flip-flop circuit 450 to become high level. Then, each time the pulse signal P_DECI_CLK transitions from low level to high level (i.e., each time the TCLK signal becomes high level), the output of the AND circuit 455 transitions from low level to high level. As a result, the integrator circuit 460 performs integration for the number of transitions from low level to high level of TCLK after the output Q of the flip-flop circuit 450 has changed to high level.

[0069] In other words, the signal generated by the integration circuit 460 when a single photon is incident is weighted by the signal TCLK. This allows the integration circuit 460 to perform weighted integration for the incident of a single photon.

[0070] Furthermore, the weighting for this single subframe is set as shown in Figure 2 when the integration circuit 460 is to generate a signal corresponding to the sine component. The control unit 52 sets the period of the signal P_DECI_CLK to correspond to the weighting assigned to a single subframe. This allows the integration circuit 460 to generate a signal corresponding to the subframe weighting shown in Figure 2.

[0071] Similarly, when generating a signal corresponding to the cosine component using the integration circuit 460, the control unit 52 should be configured to weight the period of the signal P_DECI_CLK with subframes corresponding to the cosine component.

[0072] This allows for time-correlated imaging using the APD201 in this embodiment as well.

[0073] Let me explain the variations.

[0074] Figure 8 shows the configuration of a modified pixel 110 of this embodiment. In this modified configuration, the device is equipped with integration circuits 470 and 480. Integration circuit 480 performs integration by weighting, similar to integration circuit 460 shown in Figure 7. On the other hand, integration circuit 470 performs integration in response to changes in the output of APD201 without weighting. In other words, it is an integration circuit that acquires components of normal imaging.

[0075] Pixel 110 in Figure 8 further includes an OR gate 415 and a logic gate 421. The NAND gate 412 receives the output of the OR gate 415 and the output of the signal P_RCH_TRG. The logic gate 402 receives the signal P_DECI_CLK and the inverted signal of P_RCH_TRG. The logic gate 421 receives the signal P_DECI_CLK2 and the inverted signal of P_RCH_TRG. The signal P_DECI_CLK2 is a signal that is high only once at the end of the duration of one subframe. The AND gate 458 (fourth logic gate) outputs a third pulse signal using the output of the logic gate 421 and the output of the flip-flop gate 450. If the output Q of the flip-flop 450 changes to a high level during the duration of one subframe (i.e., a photon is incident on APD201), the integrator gate 470 counts up. On the other hand, if the output Q of the flip-flop 450 remains low during the duration of one subframe (i.e., no photons are incident on the APD201), the integrator circuit 470 does not count up. As a result, the integrator circuit 470 performs integration without weighting.

[0076] In this modified example, the integration circuits 470 and 480 can perform integration with different weights for the detection of an incident photon.

[0077] (Third embodiment) This description will focus on the differences between the photoelectric conversion device of this embodiment and the modified version of the second embodiment.

[0078] The photoelectric converter of this embodiment divides the pulse signal P_DECI_CLK shown in Figure 7 into multiple signals P_DECI_CLK3 and P_DECI_CLK4. Compared to the case where the signal P_DECI_CLK is transmitted in single phase as shown in Figure 7, this embodiment has the effect of being able to handle higher frequencies. Furthermore, the integration process of the integration circuit 490 generates signals P_DECI_CLK3 and P_DECI_CLK4 so that they correspond to the upper and lower bits of the count signal generated by the integration circuit 490. This allows the integration circuit 490 to perform integration processing divided into upper and lower bits.

[0079] Figure 9 shows the configuration of the pixel 110 of the photoelectric converter in this embodiment. Components having the same function as those shown in Figure 8 are represented in Figure 9 with the same reference numerals as those used in Figure 8.

[0080] In the pixel 110 of this embodiment, the OR circuit 415 receives signals P_DECI_CLK3 and P_DECI_CLK4 from the weight control unit 53. Furthermore, signal P_DECI_CLK3 is generated as the signal corresponding to the higher bits, and signal P_DECI_CLK4 as the signal corresponding to the lower bits. These signals P_DECI_CLK3 and P_DECI_CLK4 can be pulse signals representing portions of the signal P_DECI_CLK shown in Figure 7. The OR circuit 415 outputs signals corresponding to the signal P_DECI_CLK shown in Figure 7 to the NAND circuit 412. By providing this configuration, compared to outputting the signal P_DECI_CLK as a single phase, transmitting it in two separate signals, P_DECI_CLK3 and P_DECI_CLK4, makes it easier to increase the frequency of the signals output to the NAND circuit 412. However, since the signal P_DECI_CLK is transmitted from the weight control unit 53 to multiple pixels 110, the parasitic capacitance of the transmitted signal lines limits the improvement of the signal frequency. On the other hand, in this embodiment, an OR circuit 415 is provided inside the pixel 110, and the signal P_DECI_DLK is generated inside the pixel 110, making it easier to improve the signal frequency.

[0081] The pixel 110 of this embodiment is equipped with a shift arithmetic unit 485. The shift arithmetic unit 485 receives the output of the AND circuit 458 and performs a bit shift operation on the signal generated by the integrator circuit 490. Signal P_DECI_CLK4 is the signal corresponding to the signal for the higher bits. Therefore, if the output Q of the flip-flop circuit 450 is high at the timing when signal P_DECI_CLK4 is high, the integrator circuit 490 is instructed to perform an operation to integrate the signals for the higher bits. For example, suppose signal P_DECI_CLK4 is used to generate a signal that is 2 bits higher relative to signal P_DECI_CLK3. In this case, if the output Q of the flip-flop circuit 450 is high at the timing when signal P_DECI_CLK4 is high, the integrator circuit 490 is instructed to perform a count that is 2 bits higher. In other words, when signal P_DECI_CLK4 is at a low level, the integration circuit 490 is made to perform an integration process that is 4 times (a 2-bit bit shift) compared to the integration of signal P_DECI_CLK3. This allows the integration circuit 490 to perform integration processing corresponding to the upper and lower bits, using signal P_DECI_CLK4 for the upper bits and signal P_DECI_CLK3 for the lower bits.

[0082] In this embodiment, signals P_DECI_CLK3 and P_DECI_CLK4 were described as pulse signals corresponding to the upper and lower bits of the integration circuit 490. However, the invention is not limited to this example; for example, the signal P_DECI_CLK shown in Figure 7 may be equally divided into signals P_DECI_CLK3 and P_DECI_CLK4. In this configuration, logic circuits 421 and 459 and the shift arithmetic unit 485 can be omitted. Furthermore, this configuration also has the effect of making it easier to set the frequency of signal PCLKB to a higher frequency compared to the configuration in Figure 7.

[0083] Furthermore, the first to third embodiments described above can be implemented in combination. For example, the weighting amounts of the second integration circuit 211-2 and the third integration circuit 211-3 may be made different from those of the configuration described in the first embodiment, as described in Figures 7 and 8 of the second embodiment. In other words, in the second integration circuit 211-2 of the first embodiment, the signal corresponding to the sin component may be integrated with the first weighting during the period of the first subframe, and integrated with the second weighting during the period of the second subframe.

[0084] Furthermore, although the integration circuit described in each embodiment reads a signal from each mainframe, it is not limited to this configuration. The integration circuit may be configured to perform integration continuously across multiple mainframes.

[0085] (Fourth Embodiment) Figure 10 shows the configuration of the photoelectric conversion device according to this embodiment.

[0086] This will be explained by the difference from Figure 1 mentioned above.

[0087] The weighting signal lines 61 to 64 output from the weighting control unit 53 are alternately connected to pixels 110 in pairs of two pixels vertically and horizontally. That is, of the two pixels vertically and horizontally in a pair of pixels 110, the top left pixel 110 is connected to weighting signal line 61, the bottom left pixel 110 is connected to weighting signal line 62, the top right pixel 110 is connected to weighting signal line 63, and the bottom right pixel 110 is connected to weighting signal line 64. The connection configuration within the pixel array 51 is repeated in this manner.

[0088] Furthermore, the weighting signal lines 61 to 64 are controlled either solely by the weight amount control unit 55 within the weight control unit 53, or by two blocks: the weight amount control unit 55 and the pulse generation unit 56. Details will be described later.

[0089] Pixel 110 used in Figure 10 is the same as that described in Figure 7 above.

[0090] The timing diagram in Figure 11 describes the operation of the pixel 110 configuration as described in Figure 7 above.

[0091] At time t10, the signal P_RCH_TRG goes high, initiating the subframe. Next, at time t11, the signal P_DECI_CLK also goes high. At this time, the output PCLKB of the NAND circuit 411 goes low. This turns on the quench element 202-2, a P-type MOS transistor, and performs a recharge operation on the APD201. This recharge operation is performed only once per subframe.

[0092] At time t12, a photon is first incident on the APD201 in this subframe. As a result, at time t13, the output of the waveform shaping circuit 210 becomes high, and the D input of the connected flip-flop circuit 450 also becomes high. Thereafter, even if more photons arrive within this subframe, no change in circuit operation is observed, and the state is maintained until time t14.

[0093] Next, at time t14, the signal P_RCH_TRG goes high. This starts the next subframe. Also, since this signal is connected to the clock input terminal of the flip-flop circuit 450, the Q output of the flip-flop circuit 450 goes high. At time t15, the signal P_DECI_CLK also goes high, so the output PCLKB goes low. This triggers a recharge operation on the APD201, and the output of the waveform shaping circuit 210, i.e., the D input of the flip-flop circuit 450, goes low.

[0094] Meanwhile, a pulse signal is input to the signal P_DECI_CLK between times t18 and t23. At this time, since the signal P_RCH_TRG is Low, the same pulse signal is output as the signal TCLK from the logic circuit 401 between times t18 and t23. Also, since the Q output of the flip-flop circuit 450 is High at these times, the signal TCLK is output directly from the AND circuit 455. The signal TCLK from times t18 to t23 is then integrated by the integration circuit 460.

[0095] Also, at time t16, just like at time t12, a photon is first incident on the APD201 in this subframe. As a result, at time t17, the output of the waveform shaping circuit 210 becomes high, and the D input of the connected flip-flop circuit 450 also becomes high.

[0096] Next, at time t24, the signal P_RCH_TRG becomes high, just as at time t14. This initiates the next subframe. The subsequent operation is the same, so the explanation is omitted.

[0097] In this way, it becomes possible to weight the detection of photons in the previous subframe by the number of TCLK signals in the current subframe.

[0098] Figure 12 shows the internal configuration of the weight control unit 53. In this embodiment, the weight control unit 55 controls the internal weights only.

[0099] This system has four memories (storage units): memories 501 through 504. In this diagram, the vertical direction of each memory represents the direction in which the address advances. Reading from these four memories is controlled by the read control unit 513, which reads from all four memories by specifying the same address. For example, when reading from the first address, data 16 is read from memories 501 through 503, and data 32 is read from memory 504. Next, when the address is advanced one position, data 21 is read from memory 501, data 16 is read from memories 502 and 503, and data 31 is read from memory 504. These data represent the weights output by the weight control unit 55.

[0100] Furthermore, prior to the actual operation of the photoelectric converter, configuration information is written to the memory via communication from outside the photoelectric converter.

[0101] The data read from memory 501 is output to counter 505, and similarly, data from memory 502 is output to counter 506, data from memory 503 to counter 507, and data from memory 504 to counter 508.

[0102] A common signal, CLK, is input to counters 505 through 508. Each of counters 505 through 508 uses this signal CLK to perform counting operations. In addition, each of counters 505 through 508 outputs a signal (signals en1 through en4 in Figure 12) that goes high when counting is in progress.

[0103] Counters 505-508 are one embodiment of a measurement unit that measures data (weight amounts) read from memories 501-504.

[0104] Next, AND gates 509 to 512 receive signals en1 to en4 and signal CLK from counters 505 to 508, respectively. Each AND gate 505 to 508 outputs signals P_DECI_CLK1 to P_DECI_CLK4 as the logical AND of the two input signals. As a result, the weight amounts held in memory 501 to 504 are converted into pulse counts and output as signals P_DECI_CLK1 to P_DECI_CLK4.

[0105] The timing diagram shown in Figure 13 illustrates the operation of the weight control unit 53 in Figure 12.

[0106] Figure 13 shows the timing of the operation of the counter 505 from the reading of memory 501 by the weight control unit 55. The operation of other memories 502-504 and counters 506-508 can be the same as the operation of memory 501 and counter 505, so it is omitted from the description.

[0107] At time t10, the signal P_RCH_TRG becomes High, as in Figure 11. This initiates the operation of the subframe. Note that at time t11 in Figure 11, the signal P_DECI_CLK was also High. In the operation shown in Figure 11, during the period when the signal P_RCH_TRG is High, the rising edge pulses of the signal P_DECI_CLK are individually controlled within the weight control unit 53. The OR circuit 415 outputs a signal which is the logical OR of one of the signals P_DECI_CLK1 to 4 and the signal P_DECI_CLK.

[0108] Next, at time t30, the signal rd_str goes high. This initiates read control from the memory read control unit 513. As a result, at time t31, the address of memory 501 is specified. Here, the starting address of memory 501 is specified. Then, at time t32, the data 16 held in memory 501 is output.

[0109] Time 33 marks the start of the counting operation by counter 505. Here, in order to wait for a series of operations from addressing memory 501 to reading the signal from memory 501, counter 505 starts counting after a predetermined delay has elapsed following the signal rd_str becoming high. At the same time, the signal en1 output from counter 505 is set to high.

[0110] Counter 505 uses the input signal CLK to perform a count-up operation, counting up to 15, which is the data 16 read from memory 501 minus 1. At time t34, the signal en1 of counter 505 is changed from High to Low. This allows 16 pulses to be output as the signal P_DICE_CLK1. This means that the control outputs the same number of pulses as the data 16 held in memory 501. Also at time t34, the internal counter of counter 505 sets the count value to a predetermined value (maximum value) in preparation for the next operation. This state can also be described as the reset state of counter 505.

[0111] Next, the signal P_RCH_TRG becomes high again, and the operation proceeds to the next subframe.

[0112] At time t35, a start signal is again applied to the signal rd_str, just as at time t30, and the subframe operation begins.

[0113] Next, at time t36, the following address is specified in memory 501. Then, at time t37, the data 21 held in memory 501 is read out.

[0114] At time t38, the counter 505 starts operating, just as at time t33. The signal CLK input to the counter 505 causes the counter 505 to start counting up. The counter 505 also continues counting up until it reaches 20, which is obtained by subtracting 1 from the data 21 read from memory 501.

[0115] At time t39, the signal en1 of counter 505 is set to Low. This allows the signal P_DICE_CLK1 to output 21 pulses.

[0116] This operation allows the number of pulses in the signal P_DECI_CLK to be changed on a subframe basis, and thus the weighting amount can be changed.

[0117] Furthermore, since the data held in memories 501 to 504 can be modified, it is possible to individually modify signals P_DECI_CLK1 to P_DECI_CLK4. For example, memory 501 can hold data that results in a sine wave as shown in Figure 2, memory 504 can hold data that results in a cosine wave, and memories 502 and 503 can be assigned a certain weighting. This makes it possible to acquire optical flow signals using a 2x2 pixel grid.

[0118] Furthermore, the effects described in the first to third embodiments can be obtained in the same manner in this embodiment as well.

[0119] Furthermore, although this embodiment describes an example where signals P_DECI_CLK1 to P_DECI_CLK4 are connected to different pixels 110, it is also possible to apply this to the pixels shown in Figure 8, which have two integration circuits within a single pixel 110.

[0120] (Fifth embodiment) This embodiment will be described focusing on the differences from the fourth embodiment. Parts omitted in this embodiment can be the same as those in the fourth embodiment.

[0121] Figure 14 shows the internal configuration of the weight control unit 53. In this embodiment, the signals P_DECI_CLK1 to P_DECI_CLK4 are controlled by two units: the weight amount control unit 55 and the pulse generation unit 56. The weight amount control unit 55, counters 505 to 508, and AND circuits 509 to 512 are the same as those shown in Figure 12, so their explanation is omitted.

[0122] The pulse generation unit 56 in Figure 14 of this embodiment includes counters 514 to 517 and AND gates 518 to 521. First, a common signal CLK is input to counters 514 to 517. Each of counters 514 to 517 uses this signal CLK to perform a count-up operation. In addition, each of these counters 514 to 517 can have a maximum count value set. After reaching the maximum count value, counters 514 to 517 can return to the initial count value and repeat the count-up operation. As this periodic signal, counters 514 to 517 output signals en5 to en8.

[0123] Next, the AND gates 518-521 receive signals en5-en8 and signal CLK as inputs. The AND gates 518-521 then output the logical AND signal of signals en5-en8 and signal CLK as signal pulses 5-8 shown in Figure 14.

[0124] The signal pulses 5 to 8 output from the pulse generation unit 56 are input to counters 505 to 508, as well as to AND gates 509 to 512, similar to Figure 12.

[0125] Counters 505 to 508 use signal pulses 5 to 8 to perform a count-up operation. Counters 505 to 508 continue the count-up operation until the value obtained by subtracting 1 from the value of the data read from memory 501 to 504 is reached, after which signals en1 to en4 go low.

[0126] Next, AND gates 509 to 512 generate signals that are the logical AND of signals en1 to en4 and signal pulses 5 to pulse 8, respectively, and output them as signals P_DECI_CLK1 to P_DECI_CLK4.

[0127] Figure 15 is a timing diagram illustrating the operation of each circuit block shown in Figure 14.

[0128] Figure 15(A) shows a pulse signal output from the pulse generation unit that is in continuous oscillation mode, while Figure 15(B) shows a pulse signal with periodic intervals.

[0129] Similar to Figure 13, this timing diagram describes the operation timing from memory 501 to counter 505 in the weight control unit 55, and the other three components with the same circuit configuration operate similarly, so their explanations are omitted. Content similar to that explained in Figure 13 is also omitted, and the explanation focuses on the differences. At time t10 in Figure 15(A), the subframe starts when the signal P_RCH_TRG goes high, similar to Figure 13. Also, similar to Figure 13, at time t30, the read control by the memory read control unit 513 starts when the signal rd_str goes high. At time t31, the address of memory 501 is specified, and at time t32, data 16 is output from memory 501.

[0130] Next, at time t40, the operation of the counter 514 in the pulse generation unit 56 begins. This is because the count-up operation of the counter 505 uses data read from memory 501 and output pulses from counter 514. For this reason, counter 514 starts operating before counter 505. In addition, counter 514 is set to perform continuous oscillation with period setting 1 set to 0. Therefore, the internal counter value of counter 514 starts from 0, but remains at 0 without counting up.

[0131] At the next time t33, counter 514 sees an internal counter value of 0 and sets signal en5 high in the next clock cycle. A logical AND gate 518 generates a logical AND of this signal en5 and signal CLK, so signal pulse 5 becomes a continuous oscillation pulse.

[0132] Next, the counter 505 performs a count-up operation at time t33 using the continuously oscillating signal pulse 5. The signal en1, which is the output of the counter 505, is set to High during the count operation. The signal P_DECI_CLK1 output from the AND circuit 509 is output as the logical AND signal of signal pulse 5 and signal en1.

[0133] At the next time t34, counter 505 sets signal en1 to Low at 15, which is the data 16 read from memory 501 minus 1. As a result, signal P_DICE_CLK1 can output 16 pulses.

[0134] The same operation can be repeated in subsequent subframes.

[0135] Regarding Figure 15(B), we will now explain the differences between it and Figure 15(A).

[0136] Counter 514 counts up until it reaches the value set in period setting 1, and then returns to 0. In this diagram, period setting 1 of counter 514 is set to 1, and as a result, the internal count value of counter 514 repeats between 0 and 1 in a periodic operation.

[0137] As a result, at time t33, counter 514 sees an internal counter value of 0 and sets signal en5 high with the next signal CLK. Therefore, in a periodic counting operation of 0 and 1, the output is a pulse that outputs one clock cycle every two clock cycles.

[0138] As a result, the signal P_DECI_CLK1 will also output a pulse that outputs one clock cycle every two clock cycles of the signal CLK, and this operation will be repeated 16 times, resulting in 16 pulse outputs.

[0139] The same operation can be repeated in subsequent subframes.

[0140] Furthermore, although the pulse generation unit 56 in this embodiment is shown as having a logical AND configuration of the counter output and the signal CLK, this is just one example, and it can be implemented in other configurations as well. For example, the counter output and the count values ​​that make the pulse signal High and Low are stored as set values, and a pulse signal is output according to these settings. The signal obtained by taking the logical AND of that pulse signal and the signal CLK is used as the output of the pulse generation unit 56. Even in such a configuration, the timing of the issuance of the signal P_DECI_CLK can be controlled between multiple pixels 110 (between adjacent pixels 110).

[0141] As described above, by using the pulse generation unit 56, it becomes possible to adjust the pulse interval for data with the same weighting amount. In addition to the effects of the first to fourth embodiments, this makes it possible to individually set the operating speed of the internal counts from counter 505 to counter 508, thereby distributing the current peaks among multiple pixels (adjacent pixels) 110.

[0142] (Sixth Embodiment) This embodiment is a modification of the fifth embodiment.

[0143] Figure 16 shows the internal configuration of the weight control unit 53. In this embodiment, the weight amount control unit 55 and the pulse generation unit 56 control P_DECI_CLK1 to P_DECI_CLK4, respectively. The difference from Figure 14 is the configuration of the pulse generation unit 56. The pulse generation unit 56 in Figure 16 includes a memory read control 522, four memories 523 to 526, and parallel serial circuits PS527 to PS530.

[0144] In this description, the four memories 523 through 526 are described as having addresses that advance vertically within each memory. Reading from these four memories is controlled by the read control unit 522, which reads from all four memories by specifying the same address. For example, if the starting address is specified for reading, the 8-bit data 8'b0101_0101' will be read from memories 523 through 526.

[0145] Next, when the address is advanced by one, the same 8-bit data 8'b0101_0101' is read from memory 523 to memory 526.

[0146] This 8-bit data is converted from parallel to serial by PS527 at the signal load timing from memory read control 522. As a result, the pulse generation unit 56 outputs it as PS527~PS530 (labeled ps5~ps8 in the diagram).

[0147] The ps5~ps8 signals output from the pulse generation unit 56 are input to counters 505~508 and simultaneously to AND gates 509~512, as shown in Figures 12 and 14.

[0148] Counters 505 to 508 use the ps5 to ps8 signals to perform counting operations, operating until they reach a value obtained by subtracting 1 from the value of the data read from memory 501 to memory 504, and then setting signals en1 to en4 low.

[0149] Next, AND gates 509 to 512 take the logical AND of these signals en1 to en4 and signals ps5 to ps8, respectively, and output them as signals P_DECI_CLK1 to P_DECI_CLK4.

[0150] Figure 17 is a timing diagram of the configuration shown in Figure 16.

[0151] Figure 17(A) shows a pulse signal output from the pulse generation unit that is in continuous oscillation mode, while Figure 17(B) shows a pulse signal with periodic intervals.

[0152] Similar to Figures 13 and 15, this timing diagram describes the operation timing from memory 501 to counter 505 in the weight control unit 55. The other three components with the same circuit configuration operate similarly, so their explanations are omitted. Furthermore, the same information as that explained in Figures 13 and 15 is omitted, and the explanation focuses on the differences.

[0153] At time t10 in Figure 17(A), the signal P_RCH_TRG becomes High, similar to Figures 13 and 15, and the subframe begins. At time t30, the signal rd_str initiates read control from memory read control 513 and memory read control 522.

[0154] Next, at time t31, memory 501 and memory 523 are addressed, and at time t32, data 16 is output from memory 501, and the 8-bit binary data 8'b0101_0101 is output from memory 523.

[0155] Next, at time t41, a signal load is issued during the memory 523 data output period. Here, a signal load is output once every 8 clock cycles, corresponding to the 8 bits of data.

[0156] This signal load causes the ps527 to take in parallel data and convert it into a serial signal. This conversion causes the ps5 signal to output a Low signal when the 8-bit data is Low, and a High signal when the 8-bit data is High.

[0157] At time t33, the counter 505 performs a count-up operation using the Low / High signal from signal ps5. Signal en1, which is the output of counter 505, is the signal that becomes High during the counting operation. The signal P_DECI_CLK1, output from AND gate 509, is the logical AND of signal ps5 and signal en1.

[0158] Next, at time t42, the address of memory 523 is specified again, and at time t43, the 8-bit binary data 8'b0101_0101 is read. By performing this read operation every 8 clock cycles, 8-bit data is read one after another, and a continuous pulse signal ps5 is output.

[0159] At the next time t34, counter 505 changes signal en1 to Low with a value of 15, which is obtained by subtracting 1 from the data 16 read from memory 501. This allows signal P_DICE_CLK1 to output 16 pulses.

[0160] From here on, the explanation will be omitted as the same content will be repeated in the next subframe.

[0161] The explanation in Figure 17(B) will be further explained by comparing it with Figure 17(A).

[0162] In this diagram, memory 523 holds the 8-bit binary data 8'b0100_0100. Therefore, when a parallel-to-serial conversion is performed by the signal load at time t41, a pulse output is produced at time t33 that outputs one clock cycle every two clock cycles.

[0163] As a result, the signal P_DECI_CLK1 will also output a pulse every two clock cycles, and this operation will be repeated 16 times, resulting in 16 pulse outputs.

[0164] The operation of subsequent subframes can be a repetition of the operation of the subframe described above.

[0165] As described above, by using the pulse generation unit 56, it becomes possible to adjust the pulse interval for data with the same weighting amount. In addition to the effects of the first to fourth embodiments, this makes it possible to individually set the operating speed of the internal counts from counter 505 to counter 508, thereby distributing the current peaks among multiple pixels (adjacent pixels) 110.

[0166] Furthermore, since the operating speed of counters 505 to 504 can be slowed down according to the weighting amount, a reduction in power consumption can be achieved.

[0167] (Seventh Embodiment) This embodiment is a modification of the 4th to 6th embodiments.

[0168] In this embodiment, the weight control unit 55 is configured as a circuit rather than a memory.

[0169] Furthermore, the weights set in this embodiment require the generation of sine and cosine waveforms to correspond to the acquisition of optical flow in this invention. Therefore, in this embodiment, a sine waveform is output as data to counter 505, and a cosine waveform is output as data to counter 508 (not shown).

[0170] Next, we will explain an example of generating sine and cosine waveforms using the following equations (18), (19), (20), and (21).

[0171]

number

[0172] Here, f(n) represents the sine function and g(n) represents the cosine function.

[0173] Equation (18) means that the derivative of the sine function is the cosine function, and equation (19) means that the derivative of the cosine function is the -sine function.

[0174] By transforming these

[0175]

number

[0176] Here, we set f(0) to 0 as an initial value and g(0) to, for example, 30. The coefficient k is calculated by multiplying the result of dividing the period of the sin and cos waveforms (which is 2π) by n. In other words, if we realize one period of the sin and cos waveforms with 1024 data points, then it will be 2π / 1024. When these calculations are performed, decimal places will appear, but these are rounded to integers and output to counts 505 and 508. Thus, even with the weight control unit 55 using these circuits, the same effects as in the fourth to sixth embodiments can be obtained.

[0177] (Eighth embodiment) This embodiment will be described focusing on the differences from the seventh embodiment.

[0178] In this embodiment, a method for reducing the capacity of the memory configured in the weight control unit 55 is described.

[0179] Furthermore, the weights set will need to generate sine and cosine waveforms to correspond to the acquisition of optical flow in this invention.

[0180] Since these sine and cosine waveforms are periodic functions, they can be realized by storing only half or a quarter of the period, rather than having memory for an entire period.

[0181] Figure 18(A) shows the case where only half-period data of the sine and cosine functions is stored in memory. The horizontal axis represents the memory address, which is represented as the vertical axis in Figure 12. The vertical axis in Figure 18(A) shows the data value stored in memory.

[0182] When generating a sine wave using this data, it is achieved solely through address control, as shown in Figure 18(A). That is, the address starts from the middle and is decremented down to the starting address. Once the starting address is reached, it is then incremented to control the address up to the maximum address shown in Figure 18. Once the maximum address is reached, it is decremented again down to the middle address.

[0183] Similarly, generating a cosine waveform can also be achieved using only address control. That is, the address is incremented from the starting address, and once the maximum address is reached, it is decremented back down to the starting address.

[0184] By performing this type of address control, sine and cosine waveforms can be generated. Therefore, a reduction in memory capacity can be achieved.

[0185] Next, Figure 18(B) shows the case where only 1 / 4 period data of the sin and cos functions is stored in memory. The horizontal axis represents the memory address, which is represented as the vertical axis in Figure 12. The vertical axis in Figure 18(B) shows the data value stored in memory.

[0186] To generate a sine wave using this data, address control is performed while performing data calculations, as shown in Figure 18(B). Specifically, the address is decremented from the maximum address, and then incremented when the starting address is reached. When the starting address is read, this data is stored separately. Up to this point, control is performed using only the address. Next, the address is decremented again, but this time the read data is subtracted from the previously stored maximum value while the address is decremented. When the starting address is reached in this state, the address is incremented again. Here again, the read data is subtracted from the previously stored maximum value while the address is incremented. Through these operations, it is possible to generate a sine wave.

[0187] Similarly, generating a cosine waveform is also achieved through address control and data calculation. That is, the address is incremented from the starting address to the maximum address. Here, only address control is involved. Furthermore, the data of the starting address is stored separately when it is read.

[0188] Next, the address is decremented down to the starting address 0. During this decrement, the read data is subtracted from the previously held maximum value while the address is decremented. Once the starting address is reached, the address is incremented again. Again, the read data is subtracted from the previously held maximum value while the address is incremented.

[0189] Once the maximum address is reached, decrementing is performed again, but this time only the address is controlled. This process makes it possible to generate a cosine waveform.

[0190] By performing address control while carrying out such data calculations, sine and cosine waveforms can be generated. Therefore, the effect of reducing memory capacity can be achieved.

[0191] (Ninth Embodiment) This embodiment is applicable to any of the first to eighth embodiments. Figure 19(a) is a schematic diagram illustrating a device 9191 equipped with the semiconductor device 930 of this embodiment. The semiconductor device 930 can be any of the semiconductor devices described in the first to third embodiments, or a combination of multiple embodiments. The device 9191 equipped with the semiconductor device 930 will be described in detail. The semiconductor device 930 may include a semiconductor device 910. In addition to the semiconductor device 910, the semiconductor device 930 may include a package 920 that houses the semiconductor device 910. The package 920 may include a substrate to which the semiconductor device 910 is fixed, and a lid made of glass or the like that faces the semiconductor device 910. The package 920 may further include bonding members such as bonding wires or bumps that connect terminals provided on the substrate and terminals provided on the semiconductor device 910.

[0192] The device 9191 may include at least one of the following: an optical device 940, a control device 950, a processing device 960, a display device 970, a storage device 980, and a mechanical device 990. The optical device 940 corresponds to the semiconductor device 930. The optical device 940 is, for example, a lens, shutter, or mirror, and is an optical system that guides light to the semiconductor device 930. The control device 950 controls the semiconductor device 930. The control device 950 is, for example, a semiconductor device such as an ASIC.

[0193] The processing unit 960 processes the signals output from the semiconductor device 930. The processing unit 960 is a semiconductor device such as a CPU or ASIC for configuring an AFE (analog front end) or DFE (digital front end). The display device 970 is an EL display device or liquid crystal display device that displays the information (image) obtained by the semiconductor device 930. The storage device 980 is a magnetic device or semiconductor device that stores the information (image) obtained by the semiconductor device 930. The storage device 980 is a volatile memory such as SRAM or DRAM, or a non-volatile memory such as flash memory or a hard disk drive. The processing unit 960 may also acquire optical flow using the signals output by the photoelectric conversion device of each embodiment described above. In other words, the processing unit 960 may generate three images: an image with a sin component, an image with a cos component, and a normal image, and acquire optical flow from these three images.

[0194] The mechanical device 990 has movable parts or propulsion parts such as motors and engines. The device 9191 displays signals output from the semiconductor device 930 on the display device 970 or transmits them to the outside using a communication device (not shown) provided in the device 9191. For this purpose, it is preferable that the device 9191 further includes a storage device 980 and a processing device 960, separate from the memory circuits and arithmetic circuits of the semiconductor device 930. The mechanical device 990 may be controlled based on signals output from the semiconductor device 930.

[0195] Furthermore, the device 9191 is suitable for electronic devices such as information terminals with shooting capabilities (e.g., smartphones and wearable devices) and cameras (e.g., interchangeable lens cameras, compact cameras, video cameras, and surveillance cameras). In a camera, the mechanical device 990 can drive components of the optical device 940 for zooming, focusing, and shutter operation. Alternatively, the mechanical device 990 in a camera can move the semiconductor device 930 for vibration damping.

[0196] Furthermore, the device 9191 may be a transport device such as a vehicle, ship, or aircraft (drone, aircraft, etc.). The mechanical device 990 in the transport device may be used as a mobile device. The device 9191 as a transport device is suitable for transporting the semiconductor device 930 or for assisting and / or automating driving (piloting) through its imaging function. The processing device 960 for assisting and / or automating driving (piloting) can perform processing to operate the mechanical device 990 as a mobile device based on information obtained from the semiconductor device 930. Alternatively, the device 9191 may be a medical device such as an endoscope, a measuring instrument such as a distance sensor, an analytical instrument such as an electron microscope, office equipment such as a copier, or industrial equipment such as a robot.

[0197] According to the embodiments described above, it is possible to obtain good pixel characteristics. Therefore, the value of the semiconductor device can be increased. Increasing value here means at least one of the following: addition of functions, improvement of performance, improvement of characteristics, improvement of reliability, improvement of manufacturing yield, reduction of environmental impact, cost reduction, miniaturization, and weight reduction.

[0198] Therefore, by using the semiconductor device 930 according to this embodiment in the device 9191, the value of the device can also be improved. For example, by mounting the semiconductor device 930 on a transport device, excellent performance can be obtained when taking external images of the transport device or measuring the external environment. Therefore, when manufacturing and selling transport devices, deciding to mount the semiconductor device according to this embodiment on the transport device is advantageous in improving the performance of the transport device itself. In particular, the semiconductor device 930 is suitable for transport devices that use information obtained from the semiconductor device to assist in driving and / or perform automated driving.

[0199] Furthermore, the photoelectric conversion system and mobile body of this embodiment will be explained using Figures 19(b) and (c).

[0200] Figure 19(a) shows an example of a photoelectric conversion system for an in-vehicle camera. The photoelectric conversion system 8 has a photoelectric conversion device 80. The photoelectric conversion device 80 is a photoelectric conversion device (imaging device) as described in any of the embodiments above. The photoelectric conversion system 8 has an image processing unit 801 that performs image processing on a plurality of image data acquired by the photoelectric conversion device 80, and a parallax acquisition unit 802 that calculates parallax (phase difference of parallax image) from the plurality of image data acquired by the photoelectric conversion system 8. Here, the photoelectric conversion system 8 may include an optical system (not shown) that guides light to the photoelectric conversion device 80, such as a lens, shutter, or mirror. In addition, a plurality of photoelectric conversion units that are substantially conjugate to the pupil of the optical system may be arranged in pixels of the photoelectric conversion device 80. For example, a plurality of photoelectric conversion units substantially conjugate to the pupil may be arranged corresponding to one microlens. Multiple photoelectric conversion units receive light beams that have passed through different positions in the pupil of the optical system, and the photoelectric conversion device 80 outputs image data corresponding to the light beams that have passed through different positions. The parallax acquisition unit 802 may then calculate the parallax using the output image data. The photoelectric conversion system 8 also includes a distance acquisition unit 803 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 804 that determines whether or not there is a possibility of collision based on the calculated distance. Here, the parallax acquisition unit 802 and the distance acquisition unit 803 are examples of distance information acquisition means that acquire distance information to an object. That is, distance information is information related to parallax, defocus amount, distance to an object, etc. The collision determination unit 804 may use any of this distance information to determine the possibility of collision. Note that the distance information may be acquired using ToF (Time of Flight) technology. The distance information acquisition means may be implemented by specially designed hardware or by a software module. Furthermore, it may be implemented using FPGAs (Field Programmable Gate Arrays) or ASICs (Application Specific Integrated Circuits), or a combination thereof.

[0201] The photoelectric conversion system 8 is connected to the vehicle information acquisition device 810 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The photoelectric conversion system 8 is also connected to the control ECU 820, which is a control device that outputs a control signal to generate braking force on the vehicle based on the judgment result of the collision judgment unit 804. The photoelectric conversion system 8 is also connected to the warning device 830, which issues a warning to the driver based on the judgment result of the collision judgment unit 804. For example, if the collision judgment result of the collision judgment unit 804 indicates a high probability of collision, the control ECU 820 performs vehicle control to avoid a collision or mitigate damage by applying the brakes, releasing the accelerator, or suppressing engine output. The warning device 830 warns the user by sounding an alarm, displaying warning information on a screen such as a car navigation system, or vibrating the seat belt or steering wheel.

[0202] In this embodiment, the photoelectric conversion system 8 images the area around the vehicle, for example, the front or rear. Figure 19(c) shows the photoelectric conversion system when imaging the area in front of the vehicle (imaging range 850). The vehicle information acquisition device 810 sends instructions to the photoelectric conversion system 8 or the photoelectric conversion device 80. This configuration can further improve the accuracy of distance measurement.

[0203] The above example illustrates control to prevent collisions with other vehicles, but it can also be applied to control systems that automatically follow other vehicles or automatically drive to prevent vehicles from straying from their lanes. Furthermore, the photoelectric conversion system can be applied not only to vehicles such as automobiles, but also to mobile objects (mobile devices) such as ships, aircraft, or industrial robots. In addition, it can be applied not only to mobile objects but also to a wide range of devices that utilize object recognition, such as intelligent transportation systems (ITS).

[0204] The embodiments described above can be modified as appropriate without departing from the technical concept. Furthermore, the disclosures in this specification include not only what is described herein, but also all matters that can be understood from this specification and the drawings attached thereto. The disclosures in this specification also include the complement of the concepts described herein. That is, if this specification states, for example, "A is greater than B," then even if the statement "A is not greater than B" is omitted, this specification can be said to disclose that "A is not greater than B." This is because the statement "A is greater than B" presupposes that the case where "A is not greater than B" is being considered.

[0205] The technology disclosed herein comprises the following configuration.

[0206] (Composition 1) Avalanche photodiode and A photoelectric conversion device characterized by comprising: an integration circuit that integrates the output signals of the avalanche photodiode using predetermined weighting corresponding to the acquisition of optical flow.

[0207] (Configuration 2) Avalanche photodiode and A first integration circuit that performs integration of the output signals of the avalanche photodiode, The system includes a second integration circuit that performs integration of the output signals, A photoelectric converter characterized in that the weighting amount for integration by the first integration circuit with respect to the output signal is different from the weighting amount for integration by the second integration circuit with respect to the output signal.

[0208] (Composition 3) The photoelectric converter according to configuration 2, characterized in that the weighting amount used in the integration of the output signal by the first integration circuit at a predetermined time is different from the weighting amount used in the integration of the output signal by the second integration circuit.

[0209] (Composition 4) The first integration circuit performs integration on the output signal using a coefficient corresponding to the sine component. The photoelectric conversion device according to configuration 2 or 3, characterized in that the second integration circuit performs integration on the output signal using a coefficient corresponding to the cos component.

[0210] (Composition 5) The system further includes a third integration circuit that integrates the aforementioned output signals, The photoelectric conversion device according to any one of configurations 2 to 4, characterized in that the third integration circuit performs integration with a constant coefficient during the period in which the first integration circuit performs integration.

[0211] (Composition 6) It has a waveform shaping unit connected to the avalanche photodiode, The photoelectric converter according to any one of configurations 1 to 5, characterized in that the output signal is the output of the waveform shaping unit.

[0212] (Composition 7) It has a first waveform generation unit that outputs a pulse signal that is high level with a period corresponding to the sine component, A photoelectric converter according to any one of configurations 2 to 6, characterized in that the first waveform generation unit and the first integration circuit perform integration of the output signals using the output signals.

[0213] (Composition 8) It has a second waveform generation unit that outputs a pulse signal that is high level with a period corresponding to the cosine component, The photoelectric conversion device according to configuration 7, characterized in that the second waveform generation unit and the second integration circuit perform integration of the output signals using the output signals.

[0214] (Composition 9) A first logic circuit that outputs a first pulse signal using multiple input pulse signals, A quench element connected to the avalanche photodiode and to which the first pulse signal is input, A waveform shaping unit connected to the avalanche photodiode, A second logic circuit connected to the waveform shaping unit, The system includes a third logic circuit that outputs a second pulse signal using the output of the second logic circuit and some of the pulse signals of the plurality of pulse signals, The photoelectric converter according to configuration 1, characterized in that the integration circuit performs the integration using the output of the third logic circuit.

[0215] (Composition 10) A first logic circuit that outputs a first pulse signal using multiple input pulse signals, A quench element connected to the avalanche photodiode and to which the first pulse signal is input, A waveform shaping unit connected to the avalanche photodiode, A second logic circuit connected to the waveform shaping unit, The system includes a third logic circuit that outputs a second pulse signal using the output of the second logic circuit and some of the pulse signals of the plurality of pulse signals, A photoelectric converter according to any one of configurations 2 to 8, characterized in that the first integration circuit performs the integration using the output of the third logic circuit.

[0216] (Composition 11) A first logic circuit that outputs a first pulse signal using multiple input pulse signals, A quench element connected to the avalanche photodiode and to which the first pulse signal is input, A waveform shaping unit connected to the avalanche photodiode, A second logic circuit connected to the waveform shaping unit, A third logic circuit that outputs a second pulse signal using the output of the second logic circuit and some of the pulse signals of the plurality of pulse signals, The circuit includes a fourth logic circuit that generates a third pulse signal using some of the signals from the plurality of pulse signals and the output of the second logic circuit, The first integration circuit performs the integration using the output of the third logic circuit. The photoelectric conversion device according to configuration 5, characterized in that the third integration circuit performs the integration using the output of the fourth logic circuit.

[0217] (Composition 12) A first logic circuit that outputs a first pulse signal using multiple input pulse signals, A quench element connected to the avalanche photodiode and to which the first pulse signal is input, A waveform shaping unit connected to the avalanche photodiode, A second logic circuit connected to the waveform shaping unit, A third logic circuit that outputs a second pulse signal using the output of the second logic circuit and some of the pulse signals of the plurality of pulse signals, A fourth logic circuit that generates a third pulse signal using some of the signals from the plurality of pulse signals and the output of the second logic circuit, It has an arithmetic unit, The integration circuit performs the integration using the output of the third logic circuit. The photoelectric converter according to configuration 1, characterized in that the arithmetic unit multiplies the signal held by the integration circuit using the output of the fourth logic circuit.

[0218] (Composition 13) The photoelectric conversion device according to configuration 2, comprising a weight control unit that outputs a weight amount and a measurement unit that measures the weight amount, wherein a weighting amount is provided to the first integration circuit and the second integration circuit by a signal converted from the weight amount to the number of pulses.

[0219] (Composition 14) The photoelectric conversion device according to configuration 2, comprising a weight control unit that outputs a weight amount, a measurement unit that measures the weight amount, and a pulse generation unit that supplies pulses to the measurement unit, wherein the pulse signal output at the pulse issuance timing is converted into a number of pulses corresponding to the number of pulses issued until the weight amount is reached, and the weight amount is supplied to the first integration circuit and the second integration circuit by the signal of the number of pulses.

[0220] (Composition 15) The photoelectric conversion device according to configuration 13, characterized in that the weight control unit has a holding unit that holds a predetermined value of the measurement unit, and by reading the predetermined value held in the holding unit, it provides a weighting amount to the first integration circuit and the second integration circuit.

[0221] (Composition 16) The photoelectric conversion device according to configuration 13, characterized in that the weight control unit has a holding unit that holds a predetermined value of the measurement unit, the holding unit holds a signal of a first value and a signal of a second value, generates a pulse signal by reading the signal of the first value and the signal of the second value from the holding unit, and the measurement unit driven by the pulse signal provides a weighting amount to the first integration circuit and the second integration circuit.

[0222] (Composition 17) The photoelectric conversion device according to configuration 13, characterized in that the weight control unit has a calculation circuit that generates calculated values ​​by calculating coefficients corresponding to the sin component and coefficients corresponding to the cos component, and the measurement unit, which is driven with the calculated value as the maximum value, provides weighting amounts to the first integration circuit and the second integration circuit.

[0223] (Composition 18) The photoelectric conversion device according to configuration 14, characterized in that the measurement unit generates a periodic pulse signal based on a set value, and the measurement unit measures the weight amount using the periodic pulse signal to provide a weighting amount to the first integration circuit and the second integration circuit.

[0224] (Composition 19) The photoelectric conversion device according to configuration 13, characterized in that the maximum value is half a period of the coefficient corresponding to the sin component and half a period of the coefficient corresponding to the cos component, and the measurement unit, which is driven by the maximum value being equal to one period, provides a weighting amount to the first integration circuit and the second integration circuit.

[0225] (Composition 20) The maximum value is 1 / 4 of the period of the coefficient corresponding to the sin component and 1 / 4 of the period of the coefficient corresponding to the cos component. The measurement unit driven by setting the weight amount for one period gives the weighting amounts to the first integration circuit and the second integration circuit. The photoelectric conversion device according to Configuration 13.

[0226] (Configuration 21) An apparatus comprising the photoelectric conversion device according to any one of Configurations 1 to 20, an optical device corresponding to the photoelectric conversion device, a control device that controls the photoelectric conversion device, a processing device that processes a signal output from the photoelectric conversion device, a display device that displays information obtained by the photoelectric conversion device, a storage device that stores information obtained by the photoelectric conversion device, and, a mechanical device that operates based on the information obtained by the photoelectric conversion device, and further comprising at least any one of them. The apparatus is characterized by this.

[0227] (Configuration 22) An apparatus comprising the photoelectric conversion device according to any one of Configurations 1 to 21, comprising a processing device that processes a signal output from the photoelectric conversion device, The processing device is characterized in that it acquires an optical flow using a signal output by the photoelectric conversion device. The apparatus.

Explanation of Signs

[0228] 201 Avalanche Photodiode 202 Quench Section 210 Waveform Shaping Section 211 Integration Section 211-1 First Integration Circuit 211-2 Second Integration Circuit 211-3 Third Integration Circuit 212 Selection Circuit 311 sin Waveform Generation Section 313 cos Waveform Generation Section

Claims

1. Avalanche photodiode and An integration circuit that integrates the output signals of the avalanche photodiode using predetermined weighting corresponding to the acquisition of optical flow, A first logic circuit that outputs a first pulse signal using multiple input pulse signals, A quench element connected to the avalanche photodiode and to which the first pulse signal is input, A waveform shaping unit connected to the avalanche photodiode, A second logic circuit connected to the waveform shaping unit, The system includes a third logic circuit that outputs a second pulse signal using the output of the second logic circuit and some of the pulse signals of the plurality of pulse signals, A photoelectric converter characterized in that the integration circuit performs the integration using the output of the third logic circuit.

2. A plurality of avalanche photodiodes, A first counter unit having a first integration circuit that integrates the first output signals of one of the plurality of avalanche photodiodes, A second counter unit having a second integration circuit that integrates the second output signals of another avalanche photodiode among the plurality of avalanche photodiodes, It includes a weight control unit that outputs a weight amount, The signal converted from the weight amount to the number of pulses is used to assign a weight amount to the first counter unit and the second counter unit. A photoelectric converter characterized in that the weighting amount in the first counter unit for the first output signal and the weighting amount in the second counter unit for the second output signal are different.

3. The photoelectric conversion apparatus according to claim 2, characterized in that the weighting amount in the first counter unit and the weighting amount in the second counter unit are different at a predetermined time.

4. The first integration circuit performs integration on the first output signal using a coefficient corresponding to the sine component. The photoelectric converter according to claim 2, characterized in that the second integration circuit performs integration of the second output signal using a coefficient corresponding to the cos component.

5. The photoelectric converter according to claim 1, characterized in that the output signal is the output of the waveform shaping unit.

6. It has a first waveform shaping unit connected to one of the avalanche photodiodes, The photoelectric converter according to claim 2, characterized in that the first output signal is the output of the first waveform shaping unit.

7. It has a first waveform generation unit that outputs a pulse signal that is high level with a period corresponding to the sine component, The photoelectric conversion apparatus according to claim 2, characterized in that the first integration circuit performs integration of the first output signal using the first waveform generation unit and the first output signal.

8. It has a second waveform generation unit that outputs a pulse signal that is high level with a period corresponding to the cos component, The photoelectric conversion apparatus according to claim 7, characterized in that the second integration circuit performs integration of the second output signal using the second waveform generation unit and the second output signal.

9. Avalanche photodiode and A first integration circuit that performs integration of the output signals of the avalanche photodiode, A second integration circuit that performs integration of the output signals, A first logic circuit that outputs a first pulse signal using multiple input pulse signals, A quench element connected to the avalanche photodiode and to which the first pulse signal is input, A waveform shaping unit connected to the avalanche photodiode, A second logic circuit connected to the waveform shaping unit, The system includes a third logic circuit that outputs a second pulse signal using the output of the second logic circuit and some of the pulse signals of the plurality of pulse signals, The weighting amount used in the integration of the output signal by the first integration circuit and the weighting amount used in the integration of the output signal by the second integration circuit are different. A photoelectric converter characterized in that the first integration circuit performs the integration using the output of the third logic circuit.

10. Avalanche photodiode and An integration circuit that integrates the output signals of the avalanche photodiode using predetermined weighting corresponding to the acquisition of optical flow, A first logic circuit that outputs a first pulse signal using multiple input pulse signals, A quench element connected to the avalanche photodiode and to which the first pulse signal is input, A waveform shaping unit connected to the avalanche photodiode, A second logic circuit connected to the waveform shaping unit, A third logic circuit that outputs a second pulse signal using the output of the second logic circuit and some of the pulse signals of the plurality of pulse signals, A fourth logic circuit that generates a third pulse signal using some of the signals from the plurality of pulse signals and the output of the second logic circuit, It has an arithmetic unit, The integration circuit performs the integration using the output of the third logic circuit. The photoelectric converter is characterized in that the arithmetic unit multiplies the signal held by the integration circuit using the output of the fourth logic circuit.

11. The photoelectric conversion device according to claim 2, characterized in that it has a measuring unit for measuring the weight amount.

12. Multiple avalanche photodiodes, A first counter unit having a first integration circuit that integrates the first output signals of one of the plurality of avalanche photodiodes, A second counter unit having a second integration circuit that integrates the second output signals of another avalanche photodiode among the plurality of avalanche photodiodes, The system comprises a weight control unit that outputs a weight amount, a measurement unit that measures the weight amount, and a pulse generation unit that supplies pulses to the measurement unit. The pulse signal output at the pulse issuance timing is converted into a number of pulses corresponding to the number of pulses issued until the weight amount is reached, and the first counter unit and the second counter unit are given a weighting amount based on the signal of the number of pulses. A photoelectric converter characterized in that the weighting amount in the first counter unit for the first output signal and the weighting amount in the second counter unit for the second output signal are different.

13. The photoelectric conversion device according to claim 11, characterized in that the weight control unit has a holding unit that holds a predetermined value of the measurement unit, and by reading the predetermined value held in the holding unit, it provides a weighting amount to the first integration circuit and the second integration circuit.

14. The photoelectric conversion device according to claim 11, characterized in that the weight control unit has a holding unit that holds a predetermined value of the measurement unit, the holding unit holds a signal of a first value and a signal of a second value, generates a pulse signal by reading the signal of the first value and the signal of the second value from the holding unit, and the measurement unit driven by the pulse signal provides a weighting amount to the first integration circuit and the second integration circuit.

15. The photoelectric conversion apparatus according to claim 11, wherein the weight control unit has a calculation circuit that generates a calculated value obtained by calculating a coefficient corresponding to the sine component and a coefficient corresponding to the cosine component, and the measurement unit, which is driven with the calculated value as the maximum value, provides a weighting amount to the first integration circuit and the second integration circuit.

16. The photoelectric conversion device according to claim 12, characterized in that the measurement unit generates a periodic pulse signal based on a set value, and the measurement unit, which measures the weight amount using the periodic pulse signal, provides a weighting amount to the first integration circuit and the second integration circuit.

17. The photoelectric conversion device according to claim 15, characterized in that the maximum value is half a period of the coefficient corresponding to the sine component and half a period of the coefficient corresponding to the cosine component, and the measurement unit, which is driven by setting the maximum value to a weight amount equivalent to one period, provides a weight amount to the first integration circuit and the second integration circuit.

18. The photoelectric conversion device according to claim 15, characterized in that the maximum value is 1 / 4 period of the coefficient corresponding to the sin component and 1 / 4 period of the coefficient corresponding to the cos component, and the measurement unit, which is driven by setting the maximum value to a weight amount equivalent to one period, provides a weight amount to the first integration circuit and the second integration circuit.

19. A plurality of pixels, each having an avalanche photodiode and an integration circuit that performs integration of the output signals of the avalanche photodiode using predetermined weightings, It includes a weight control unit that outputs a weight amount, The aforementioned plurality of pixels include a first pixel, a second pixel, and a third pixel. During a predetermined period, the weighting amount in the integration circuit for the first pixel, the weighting amount in the integration circuit for the second pixel, and the weighting amount in the integration circuit for the third pixel are different from each other. A photoelectric conversion device characterized by applying a weighting amount to the integration circuit of the first pixel and the integration circuit of the second pixel using a signal converted from the weighting amount to the number of pulses.

20. The aforementioned plurality of pixels further include a fourth pixel, The photoelectric conversion device according to claim 19, characterized in that, during the predetermined period, the weighting amount in the integration circuit for the first pixel, the weighting amount in the integration circuit for the second pixel, the weighting amount in the integration circuit for the third pixel, and the weighting amount in the integration circuit for the fourth pixel are all different from each other.

21. The integration circuit of the first pixel performs integration with the output signal using a coefficient corresponding to the sine component. The photoelectric converter according to claim 19, characterized in that the integration circuit of the second pixel performs integration with the output signal using a coefficient corresponding to the cos component.

22. The photoelectric conversion device according to claim 21, characterized in that during the period in which the integration circuit of the first pixel performs integration of the output signal using a coefficient corresponding to the sine component, and the integration circuit of the second pixel performs integration of the output signal using a coefficient corresponding to the cosine component, the integration circuit of the third pixel performs integration of the output signal using a constant weighting amount.

23. The integration circuit of the first pixel performs integration with the output signal using a coefficient corresponding to the sine component. The integration circuit of the second pixel performs integration with the output signal using a coefficient corresponding to the cos component. The photoelectric conversion device according to claim 20, characterized in that during the period in which the integration circuit of the first pixel performs integration on the output signal using a coefficient corresponding to the sine component, and the integration circuit of the second pixel performs integration on the output signal using a coefficient corresponding to the cosine component, the integration circuits of the third pixel and the fourth pixel perform integration on the output signal using a constant weighting amount.

24. The photoelectric conversion device according to claim 23, characterized in that the first pixel, the second pixel, the third pixel, and the fourth pixel are arranged across two rows and two columns.

25. It has a weight control unit that outputs a weight amount and a measurement unit that measures the weight amount, The photoelectric conversion device according to claim 19, wherein the weight control unit has a calculation circuit that generates a calculated value obtained by calculating a coefficient corresponding to the sine component and a coefficient corresponding to the cosine component, and the measurement unit, which is driven with the calculated value as the maximum value, provides a weighting amount to the integration circuit of the first pixel and the integration circuit of the second pixel.

26. The system has a plurality of pixels, each having an avalanche photodiode and an integration circuit that performs integration of the output signals of the avalanche photodiode using predetermined weightings. The aforementioned plurality of pixels include a first pixel, a second pixel, and a third pixel. Each of the aforementioned first pixel, second pixel, and third pixel is, A first logic circuit that outputs a first pulse signal using multiple input pulse signals, A quench element connected to the avalanche photodiode and to which the first pulse signal is input, A waveform shaping unit connected to the avalanche photodiode, A second logic circuit connected to the waveform shaping unit, The system includes a third logic circuit that outputs a second pulse signal using the output of the second logic circuit and some of the pulse signals of the plurality of pulse signals, A photoelectric converter characterized in that the integration circuits of the first pixel, the second pixel, and the third pixel each perform the integration using the output of the corresponding third logic circuit.

27. The photoelectric conversion device according to claim 26, characterized in that, during a predetermined period, the weighting amount in the integration circuit for the first pixel, the weighting amount in the integration circuit for the second pixel, and the weighting amount in the integration circuit for the third pixel are different from each other.

28. The aforementioned plurality of pixels further include a fourth pixel, The photoelectric conversion device according to claim 27, characterized in that, during the predetermined period, the weighting amount in the integration circuit for the first pixel, the weighting amount in the integration circuit for the second pixel, the weighting amount in the integration circuit for the third pixel, and the weighting amount in the integration circuit for the fourth pixel are all different from each other.

29. The integration circuit of the first pixel performs integration with the output signal using a coefficient corresponding to the sine component. The photoelectric converter according to claim 26, characterized in that the integration circuit of the second pixel performs integration with the output signal using a coefficient corresponding to the cos component.

30. The photoelectric converter according to claim 26, characterized in that during the period in which the integration circuit of the first pixel performs integration on the output signal using a coefficient corresponding to the sine component, and the integration circuit of the second pixel performs integration on the output signal using a coefficient corresponding to the cosine component, the integration circuit of the third pixel performs integration on the output signal using a constant weighting amount.

31. The integration circuit of the first pixel performs integration with the output signal using a coefficient corresponding to the sine component. The integration circuit of the second pixel performs integration with the output signal using a coefficient corresponding to the cos component. The photoelectric converter according to claim 28, characterized in that during the period in which the integration circuit of the first pixel performs integration on the output signal using a coefficient corresponding to the sine component, and the integration circuit of the second pixel performs integration on the output signal using a coefficient corresponding to the cosine component, the integration circuits of the third pixel and the fourth pixel perform integration on the output signal using a constant weighting amount.

32. The photoelectric conversion device according to claim 31, characterized in that the first pixel, the second pixel, the third pixel, and the fourth pixel are arranged in two rows and two columns.

33. It has a weight control unit that outputs a weight amount and a measurement unit that measures the weight amount, The photoelectric conversion apparatus according to claim 26, wherein the weight control unit has a calculation circuit that generates a calculated value obtained by calculating a coefficient corresponding to the sine component and a coefficient corresponding to the cosine component, and the measurement unit, which is driven with the calculated value as the maximum value, provides a weighting amount to the integration circuit of the first pixel and the integration circuit of the second pixel.

34. A device comprising a photoelectric converter according to any one of claims 1 to 33, Optical device corresponding to the aforementioned photoelectric converter, A control device for controlling the aforementioned photoelectric converter, A processing device that processes the signal output from the aforementioned photoelectric converter, A display device that displays information obtained by the aforementioned photoelectric converter. A storage device for storing information obtained by the photoelectric converter, and The apparatus is characterized by further comprising at least one of the following: a mechanical device that operates based on information obtained from the photoelectric converter.

35. A device comprising a photoelectric converter according to any one of claims 1 to 33, The system includes a processing unit that processes the signal output from the aforementioned photoelectric converter, The processing device is characterized by acquiring optical flow using the signal output by the photoelectric converter.

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