Method for improving shape control during selective etching of silicon nitride spacers

Abstract

To provide an atomic layer etching method for spacer patterning in semiconductor applications.SOLUTION: An etching method includes a step of exposing a SiN layer covering a structure on a substrate in a reaction chamber to a plasma of hydrofluorocarbon (HFC) and forming a polymer layer deposited on the SiN layer that modifies the surface of the SiN layer. The HFC has a formula CxHyFz, and is a saturated or unsaturated, linear or cyclic HFC. The method also includes a step of exposing the polymer layer deposited on the SiN layer to a plasma of inert gas, and removing, by the plasma of inert gas, the polymer layer deposited on the SiN layer and the modified surface of the SiN layer on an etch front. The steps are repeated until the SiN layer on the etch front is selectively removed, thereby forming a vertically straight SiN spacer comprising the SiN layer on the sidewall of the structure.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] Cross-reference of related applications This application claims the interests of U.S. Patent Application No. 16 / 265,782, filed on February 1, 2019, which is incorporated herein by reference in its entirety for all purposes.

[0002] A cycle atomic layer etching (ALE) method for spacer patterning in semiconductor applications is disclosed. In particular, a cycle ALE process for forming vertically straight silicon nitride (SiN) spacers using a hydrofluorocarbon (HFC) gas is disclosed. The HFC gas in this disclosure is saturated or unsaturated, linear or cyclic C for selective plasma etching of SiN. x H y F z The equation has the following properties: (where x = 2 to 5, and y > z). [Background technology]

[0003] The continuous downscaling of semiconductor devices presents an increasing number of challenges to semiconductor manufacturing processes. At technology nodes below 14nm, one of the most critical steps is spacer etching. This requires completely anisotropic etching (no critical dimension (CD) loss) without damaging or consuming the exposed material, such as silicon or silicon oxide. This is typically done by plasma etching using fluorocarbon-based chemicals. However, with the increasing aspect ratios associated with state-of-the-art technology nodes, conventional etching processes can no longer achieve etching specifications such as shape control (e.g., footing and surface roughness), intact underlayers, and CD control.

[0004] In the industry, the standard etching process used for SiN etching is CH3F combined with an oxidizing agent and / or a rare gas, such as an oxidizing agent (e.g., O2), a rare gas (e.g., Ar or He), and optionally an additional gas containing F or O (e.g., CH4, CF4). However, it is difficult to manage the trade-off between etching selectivity, shape control, and damage to the underlying layer. Previous patents regarding SiN etching have claimed to selectively etch SiN spacers using different HFCs, but there has been no quantifiable information regarding shape control.

[0005] U.S. Patent Application Publication No. 20130105916A1 by Chang et al. discloses a high-selectivity nitride etching process that includes anisotropically etching SiN x of various thicknesses using an HFC plasma to form an HFC polymer on SiN x , SiO2, and Si. This process is a selective etching of SiN x H y F <00​​​​​​​​​​​​​​Discloses selective etching to SiO2. As shown in the examples, Suzuki et al. etched SiN flat wafers and SiO flat wafers using 2,2-difluoro-n-butane.

[0007] U.S. Patent No. 8,501,630 to Metz et al. or U.S. Patent Application Publication No. 20120077347A1 discloses a plasma etching method for selectively etching a substrate. The plasma etching process uses a process composition having a process gas containing C, H, and F and an additive gas not containing oxygen. The process gas includes CH3F, CHF3, CH2F2, or any combination of two or more thereof. The plasma etching process disclosed by Metz et al. is not a cycle process.

[0008] U.S. Patent Application Publication No. 20010005634A1 to Kajiwara discloses a dry etching method for forming contact holes by performing highly selective etching of SiN on SiO2 using CH2F2 as an etching gas.

[0009] U.S. Patent Application Publication No. 20130105996 to Brink et al. discloses a low-energy etching process for a nitrogen-containing dielectric layer included in a stack including, from bottom to top, a nitrogen-containing dielectric layer formed on a substrate, a wiring-level dielectric material layer, and a hard mask layer. The nitrogen-containing dielectric layer is plasma-etched using an HFC having C x H y F z (x = 3 to 6, y > z). Brink et al. do not mention selectivity to Si or SiO2.

[0010] U.S. Patent Application Publication No. 20140273292A1 by Posseme et al. discloses a method of forming a SiN spacer, including the steps of depositing a SiN layer on an exposed silicon-containing layer and at least partially formed gate stack disposed on a substrate; modifying a part of the SiN layer by exposing the SiN layer to a plasma containing substantially fluorine-free hydrogen or helium; and removing the modified part of the SiN layer by performing a wet cleaning process to form a SiN spacer. In one embodiment, Posseme et al. disclose that they etched the SiN layer using HFC-containing gases such as CH2F2, CH4, or CHF3.

[0011] U.S. Patent Application Publication No. 20150270140A1 by Gupta et al. discloses the chemistry and process of atomic layer or cycle plasma etching for etching films including Si, Ti, Ta, W, Al, Pd, Ir, Co, Fe, B, Cu, Ni, Pt, Ru, Mn, Mg, Cr, Au, alloys thereof, oxides thereof, nitrides thereof, and combinations thereof. Examples include the etching of Fe and Pd using Cl2 and ethanol (EtOH), and the etching of Ni, Co, Pd, or Fe using Cl2 and acetylacetonate (Acac).

[0012] U.S. Patent Application Publication No. 20160293438A1 by Zhou et al. discloses a cycle spacer etching process with improved shape control, but this method is based on NF3 / NH3 plasma rather than HFC gas.

[0013] International Publication No. 2018 / 044713A1 by Sherpa et al. discloses a method of quasi-atomic layer etching of SiN, including a first step of a process gas containing H and an optional noble gas (H2 or H2 and Ar); and a second step of a process gas containing N, F, O, and an optional noble gas element (NF3, O2, and Ar).

[0014] Ranjan et al.'s U.S. Patent No. 9318343B2 states that C x H y F z A method for improving etching selectivity during SiN spacer etching is disclosed, which includes a cyclic etching and oxidation process of SiN spacers and silicon (such as polycrystalline silicon) using a process gas containing an HFC gas represented as (x, y, and z are non-zero). The HFC disclosed by Renjan et al. is CH3F. Ranjan et al. do not mention the shape of the spacer, such as the footing or surface roughness of the spacer. [Overview of the Initiative] [Problems that the invention aims to solve]

[0015] The applications for etching silicon-containing spacers require meeting etching shape requirements such as minimal or no footing, minimal or no fluoride formation, and a smooth spacer surface after etching. Therefore, discovering novel and unprecedented etching components applicable to improve shape control for etching silicon-containing spacers such as SiN spacers is a challenge. Thus, there is a need to provide such etching components that meet these requirements. [Means for solving the problem]

[0016] i) A step of exposing a SiN layer covering a structure on a substrate in a reaction chamber to a hydrofluorocarbon (HFC) plasma to modify the surface of the SiN layer and form a polymer layer deposited on the SiN layer, wherein the HFC is of formula C x H y F zA cyclic etching method is disclosed, comprising the steps of: ii) having (wherein x = 2 to 5, y > z) and being saturated or unsaturated, linear or cyclic HFC; ii) exposing a polymer layer deposited on a SiN layer to an inert gas plasma to remove the polymer layer deposited on the SiN layer of the etch front and the modified surface of the SiN layer by the inert gas plasma; and iii) repeating steps i) and ii) until the SiN layer covering the etch front is removed, thereby forming a vertically straight SiN spacer having a SiN layer covering the sidewall of the structure.

[0017] i) A step of exposing a SiN layer covering a structure on a substrate in a reaction chamber to a hydrofluorocarbon (HFC) plasma to modify the surface of the SiN layer and form a polymer layer deposited on the SiN layer, wherein the HFC is of formula C x H y F z A cycle etching method for forming a vertically straight SiN spacer is also disclosed, comprising the steps of: ii) having (wherein x = 2 to 5, y > z) and being saturated or unsaturated, linear or cyclic HFC; ii) exposing a polymer layer deposited on a SiN layer to an inert gas plasma to remove the polymer layer deposited on the SiN layer of the etch front and the modified surface of the SiN layer by the inert gas plasma; and iii) repeating steps i) and ii) until the SiN layer covering the etch front is removed, thereby forming a vertically straight SiN spacer having a SiN layer covering the sidewall of the structure.

[0018] i) Exposing the SiN layer covering the gate stack on a substrate in a reaction chamber to a plasma of a hydrofluorocarbon (HFC) selected from the group consisting of C2H5F and C3H7F to modify the surface of the SiN layer and form a polymer layer deposited on the SiN layer; ii) Exposing the polymer layer deposited on the SiN layer to an inert gas plasma to remove the polymer layer deposited on the SiN layer and the modified surface of the SiN layer at the etch front with the inert gas plasma; and iii) Repeating steps i) and ii) until the SiN layer covering the etch front is removed, thereby forming a vertically straight SiN gate spacer having a SiN layer covering the sidewall of the gate stack. A cyclic etching method for forming a vertically straight SiN gate spacer is also disclosed, which includes a step of repeating the steps.

[0019] Any of the methods disclosed may include one or more of the following forms: After step i), Steps include: evacuating the reaction chamber with a pump to create a vacuum; Steps include purging the reaction chamber with N2, The steps include: evacuating the reaction chamber with a pump to create a vacuum, and A step of introducing an inert gas into a reaction chamber to generate an inert gas plasma, Includes further; After step ii), Steps include: evacuating the reaction chamber with a pump to create a vacuum; Steps include purging the reaction chamber with N2, The steps include: evacuating the reaction chamber with a pump to create a vacuum, and A step of introducing HFCs into a reaction chamber to generate an HFC plasma, Includes further; • Expose the SiN layer to a plasma of a mixed gas of HFC and an inert gas; • At least a large portion of the SiN layer on the sidewalls of the gate stack is not removed; • Less than 10% of the SiN layer thickness of the gate stack sidewalls is removed; • Less than 5% of the SiN layer thickness of the gate stack sidewalls is removed; • Less than 1% of the SiN layer thickness on the sidewalls of the gate stack is removed; • There is no measurable decrease in the thickness of the SiN layer on the sidewalls of the gate stack; • The inert gas is selected from N2, Ar, Kr, or Xe; • The inert gas is Ar; • HFC is C2H5F; • HFC is C3H7F; • The substrate contains silicon-containing material; • The substrate is silicon; • The structure is a gate stack; • HFC plasma interacts with SiN to form a polymer rich in carbon (C:F > 1); • A polymer layer in which a polymer containing a large amount of carbon is deposited on top of a SiN layer; HFCs selectively etch the structural SiN layer; HFC selectively etches the SiN layer on the substrate; • Infinite selectivity of SiN for structural applications; • Infinite selectivity of SiN for gate stacks; • Infinite selectivity of SiN over p-Si, SiO, SiON, and SiCN; • The ALE overetching recipe is applied; The ALE overetching recipe ranges from approximately 10% ALE overetching to approximately 200% ALE overetching; The ALE overetching recipe ranges from approximately 50% ALE overetching to approximately 200% ALE overetching; • Introduce HFC gas into the reaction chamber at a flow rate ranging from approximately 1 sccm to approximately 10 slm; • Introduce HFC gas into the reaction chamber at a flow rate ranging from approximately 1 sccm to approximately 100 sccm; • Introduce the inert gas into the reaction chamber at a flow rate ranging from approximately 1 sccm to approximately 10 slm; • Introduce the inert gas into the reaction chamber at a flow rate ranging from approximately 10 sccm to approximately 200 sccm; The reaction chamber has a pressure ranging from approximately 1 mTorr to approximately 50 Torr; The reaction chamber has a pressure ranging from approximately 1 mTorr to approximately 10 Torr; The reaction chamber has a pressure ranging from approximately 300 mTorr to approximately 1 Torr; • The substrate temperature inside the chamber is in the range of approximately -110°C to approximately 2000°C; • The substrate temperature inside the chamber is in the range of approximately -20°C to approximately 1000°C. • The substrate temperature inside the chamber is in the range of approximately 25°C to 700°C. • The substrate temperature inside the chamber is in the range of approximately 25°C to 500°C. The substrate temperature inside the chamber is in the range of approximately 25°C to 50°C. The temperature of the reaction chamber walls is in the range of approximately 25°C to 100°C; • Plasma processing time varies from 0.01 seconds to 10,000 seconds; • Plasma processing time varies from 1 second to 30 seconds; • The N2 purge time varies from 1 second to 10,000 seconds; • The N2 purge time varies from 10 seconds to 60 seconds; • Footing is almost completely absent at each corner between the SiN spacer and the substrate; • Little to no excess material remaining in the vicinity of the SiN layer and substrate; • No fluoride residue remains on the vertically straight SiN spacer and etch front; • The surface roughness of the vertically straight SiN spacer surface and the etch front surface after cycle etching is improved compared to before cycle etching; • Remove the polymer layer using an ion shock process; The step further includes adding an oxygen-containing gas; and The oxygen-containing gas is selected from the group consisting of O2, O3, CO, CO2, NO, NO2, N2O, SO2, COS, H2O, and combinations thereof.

[0020] formula C x H y F z HFC etching gases having the equation (where x = 2 to 5 and y > z) are also disclosed. The HFC etching gases of this disclosure include one or more of the following embodiments: • The HFCs are saturated or unsaturated, linear or cyclic HFCs; • Possesses a purity higher than approximately 99% by volume; • Possesses a purity higher than approximately 99.9% by volume; • Contains trace gaseous impurities of less than 1% by volume; • Trace gaseous impurities include water; • Trace gaseous impurities include CO2; • Trace gaseous impurities containing N2; and • The water content of the HFC etching gas is less than 20 ppmw.

[0021] Notation and Nomenclature The following detailed description and claims utilize several abbreviations, symbols, and terms commonly known in the art, including:

[0022] As used herein, the indefinite articles "a" or "an" refer to one or more.

[0023] As used herein, the terms “about,” “approximately,” or “about” in the text or claims mean ±10% of the stated value.

[0024] As used herein, "room temperature" in the text or claims means approximately 20°C to approximately 25°C.

[0025] The terms "wafer" or "patterned wafer" refer to a wafer having a stack of silicon-containing films on a substrate, and having a patterned hard mask layer on top of the stack of silicon-containing films formed for pattern etching.

[0026] The term "substrate" refers to one or more materials on which a process is performed. A substrate may refer to a wafer having one or more materials on which a process is performed. A substrate may be any suitable wafer used in the manufacture of semiconductors, photovoltaics, flat panels, or LCD-TFT devices. A substrate may also have one or more layers of different materials already deposited on it from a previous manufacturing step. For example, a wafer may include silicon layers (e.g., crystalline, amorphous, porous, etc.), silicon-containing layers (e.g., SiO2, SiN, SiON, SiCOH, etc.), metal-containing layers (e.g., copper, cobalt, ruthenium, tungsten, platinum, palladium, nickel, ruthenium, gold, etc.), or combinations thereof. Furthermore, a substrate may be planar or patterned. A substrate may be a photoresist film patterned with organic material. The substrate may include an oxide layer used as a dielectric material in MEMS, 3D NAND, MIM, DRAM, or FeRam device applications (e.g., ZrO2-based materials, HfO2-based materials, TiO2-based materials, rare earth oxide-based materials, ternary oxide-based materials, etc.) or a nitride-based film used as an electrode (e.g., TaN, TiN, NbN). Those skilled in the art will recognize that the terms “film” or “layer” as used herein refer to the thickness of any material that is arranged or spread over a surface, which may be a trench or a line. Throughout this specification and the claims, the wafer and any associated layers thereon are referred to as the substrate.

[0027] The term "pattern etching" or "patterned etching" refers to etching non-planar structures, such as stacks of silicon-containing films beneath a patterned hard mask layer.

[0028] As used herein, the terms “etch” or “etch” refer to isotropic etching processes and / or anisotropic etching processes. Isotropic etching processes involve a chemical reaction between an etching compound and a substrate, resulting in the removal of a portion of the material on the substrate. This type of etching process includes chemical dry etching, vapor-phase chemical etching, and thermal dry etching. Isotropic etching processes create lateral or horizontal etching patterns on the substrate. Isotropic etching processes create recesses or horizontal recesses in the sidewalls of pre-formed apertures on the substrate. Anisotropic etching processes remove only material perpendicular to the surface of the substrate, resulting in precise transfer of the mask pattern. Dry etching processes may be plasma etching processes. Plasma is any gas in which a significant proportion of atoms or molecules are ionized. Plasma may be capacitively coupled plasma (CCP) generated by a CCP system consisting essentially of two metal electrodes placed in a reactor and separated by a small distance. A typical CCP system is driven by a single radio frequency (RF) power supply. One of the two electrodes is connected to the power supply, and the other is grounded. When an electric field is generated between electrodes, atoms are ionized and emit electrons. Electrons in the gas can be accelerated by the RF field and, through collisions, directly or indirectly ionize the gas to generate secondary electrons. The plasma may be an inductively coupled plasma (ICP) or transformer-coupled plasma (TCP) generated by an ICP system, which is energized by electromagnetic induction, i.e., by an ICP system generated by a current produced by a time-varying magnetic field. ICP discharge is 10 15 cm -3This results in a relatively high electron density of the order of . As a result, ICP discharge has a wide range of applications where high-density plasma (HDP) is required. Another advantage of ICP discharge is that contamination is relatively low because the electrodes are completely outside the reaction chamber. Plasma etching processes produce etching shapes perpendicular to the substrate. Plasma etching processes produce apertures, trenches, channel holes, gate trenches, stepped contacts, capacitor holes, contact holes, etc., perpendicular to the substrate.

[0029] The term "100% etching" means that the ALE process completely etched through the material to its thickness. This means etching the material. The term "over-etching" means that the ALE process continues even after etching has passed through the material. For example, in the method of this disclosure, if one ALE recipe has an etching rate of 1 nm / cycle for a SiN layer and the SiN layer has a thickness of 10 nm, then 10 cycles are required to completely etch through the 10 nm thick SiN. This means 100% etching. If more than 10 etching cycles are set to etch the SiN layer, the ALE is "over-etching". For example, if 15 etching cycles are set to etch the SiN layer, the etching process is 50% over-etched. If 20 etching cycles are set to etch the SiN layer, the etching process is 100% over-etched.

[0030] The term "deposit" or "deposition" refers to a series of processes in which materials at the atomic or molecular level are deposited on a wafer surface or substrate from a gaseous state (vapor) to a solid state as a thin layer. Chemical reactions are involved in the processes that occur after the generation of a plasma of the reacting gases. The plasma may be the aforementioned CCP, which is typically formed by a radio frequency (RF) (alternating current (AC)) or direct current (DC) discharge between two electrodes, with the space between them filled with the reacting gas. Deposit methods may include atomic layer deposition (ALD) and chemical vapor deposition (CVD).

[0031] The term "mask" refers to a layer that resists etching. A hard mask layer can be placed on top of the layer being etched.

[0032] The term "aspect ratio" refers to the ratio of the height of a trench (or aperture) to its width (or aperture diameter).

[0033] The term "selectivity" refers to the ratio of the etching rate of one material to the etching rate of another material. The terms "selective etching" or "to etch selectively" mean etching one material more than another, in other words, having an etching selectivity greater than or less than 1:1 between the two materials.

[0034] In this specification, the terms “film” and “layer” are interchangeable. It will be understood that a film may correspond to or be related to a layer, and a layer may refer to a film. Furthermore, those skilled in the art will understand that the terms “film” or “layer” as used herein refer to the thickness of any material that is placed on or spread over a surface, and that the surface may range in size from an entire wafer to as small as a trench or line.

[0035] Furthermore, in this specification, the terms "etching compound" and "etching gas" can be used interchangeably when the etching compound is in a gaseous state at room temperature and ambient pressure. It is understood that the etching compound may correspond to or be related to the etching gas, and the etching gas may refer to the etching compound.

[0036] Standard abbreviations for elements from the periodic table are used herein. It is important to understand that elements may be referred to by these abbreviations (for example, Si refers to silicon, N refers to nitrogen, O refers to oxygen, C refers to carbon, H refers to hydrogen, F refers to fluorine, etc.).

[0037] To identify the specific molecule being disclosed, a unique CAS registry number (i.e., "CAS") assigned by the Chemical Abstract Service is provided.

[0038] Note that silicon-containing films such as SiN and SiO are described throughout this specification and the claims without considering their appropriate stoichiometry. Silicon-containing films include pure silicon (Si) layers such as crystalline Si, polysilicon (p-Si or polycrystalline silicon), or amorphous silicon; silicon nitride (Si k N l ) layer; or silicon dioxide (Si n O m ) layers; or mixtures thereof, where k, l, m, and n are comprehensively in the range of 0.1 to 6. Preferably, the silicon nitride is Si with k and I in the range of 0.5 to 1.5 each. k N l More preferably, silicon nitride is Si3N4. In this specification, SiN in the following description refers to Si k N l It may be used to represent the containing layer. Preferably, the silicon dioxide is Si where n is in the range of 0.5 to 1.5 and m is in the range of 1.5 to 3.5. n O mMore preferably, silicon dioxide is SiO2. In this specification, SiO in the following description is Si n O m It may be used to represent the containing layer. The silicon-containing film can also be an organic-based or silicon oxide-based low-k dielectric material such as Applied Materials, Inc.'s Black Diamond II or III material, which has the formula SiOCH. The silicon-containing film is a Si film where a, b, and c are in the range of 0.1 to 6. a O b N c This may also include: Silicon-containing films may also contain dopants such as B, C, P, As, and / or Ge.

[0039] In this specification, a range may be expressed as approximately from one specific value and / or approximately to another specific value. Where such a range is expressed, it should be understood that other embodiments, along with all combinations within the range, are from one specific value and / or to another specific value.

[0040] Any reference in this specification to “one embodiment” or “a particular embodiment” means that certain features, structures, or characteristics described in relation to an embodiment may be included in at least one embodiment of the present invention. The phrase “in one embodiment” appearing in various places in this specification does not necessarily refer to the same embodiment, and another or alternative embodiment is not necessarily mutually exclusive with other embodiments. The same applies to the term “implementation.”

[0041] To further understand the nature and purpose of the present invention, it is necessary to refer to the following detailed description in conjunction with the accompanying drawings. In the accompanying drawings, similar elements are given the same or similar reference numerals. [Brief explanation of the drawing]

[0042] [Figure 1a]This shows a side cross-sectional view of an exemplary pattern formed to generate a SiN spacer on a substrate in the art. [Figure 1b] The image below shows a side cross-sectional view of an exemplary SiN spacer on a substrate, illustrating the ideal etching result for a SiN spacer in this art. [Figure 1c] This shows a side cross-sectional view of an exemplary SiN spacer on a substrate below, resulting from an actual spacer etching process in the relevant technical field, which produces a footing at the bottom of the spacer. [Figure 2] This disclosure shows the process flow per cycle of the cycle ALE process. [Figure 3] This is a graph showing the relationship between etching thickness and ALE cycles using CH3F. [Figure 4] This is a graph showing the relationship between etching thickness and ALE cycles using C2H5F. [Figure 5] This is a graph showing the relationship between etching thickness and ALE cycles using C3H7F. [Figure 6a] The images show EDS mapping of ALE-treated SiN spacers with 100% etched sidewalls and 100% over-etched sidewalls, respectively, using C2H5F - horizontal scan of the sidewalls. [Figure 6b] The images show EDS line scans using atoms of SiN spacers after ALE, with 100% etched sidewalls and 100% over-etched sidewalls, respectively, using C2H5F - vertical scan of the spacer bottom. [Figure 7] The image shows continuous etching of a SiN spacer using C2H5F: EDS mapping (left) and EDS line scan (right). [Modes for carrying out the invention]

[0043] A method for improving shape control for forming silicon nitride (SiN) spacers on Si-containing substrates with high selectivity in semiconductor applications is disclosed. The disclosed method utilizes a cycle atomic layer etching (ALE) process using HFC plasma and noble gas plasma to selectively etch the SiN layer on a structure covered with the SiN layer and / or the underlying Si-containing layer (e.g., substrate). In this specification, the structure may be a gate or a gate stack.

[0044] The method of this disclosure has significantly improved shape control for forming SiN spacers. Key features of the formed SiN spacers include high selectivity of SiN over underlying Si-containing layers such as poly-Si (or Si) or SiO2. Other key features of the formed SiN spacers include no chemical damage to the underlying Si-containing layer even when using an over-etching recipe, little to no excess material in proximity to the SiN layer and the substrate, little to no footing at the bottom edge of the spacer, and no F residue remaining on the sidewalls of the spacer.

[0045] In semiconductor applications, a spacer is a layer of material deposited on a structure such as a gate or gate stack by CVD or ALD in a metal oxide semiconductor field-effect transistor (MOSFET) to separate the gate contact from the source and drain contacts. The material may be SiN, for example. The spacer passivates the sidewalls of the gate stack. The disclosed method can be applied to any type of spacer in semiconductor applications, including gate spacers, patterning spacers having self-aligned double patterning (SADP) spacers or self-aligned quadruple patterning (SAQP) spacers. In this specification, the gate stack may be a digital switch, random access memory (RAM), amplifier, biosensor based on a field-effect transistor (BioFET), DNA field-effect transistor (DNAFET), ferroelectric, magnetic, electrolytic, etc. More specifically, the gate stack may be a high-k gate stack including flash memory such as 3D NAND or NOR, silicon-oxide-nitride-oxide-silicon (SONOS), strain interfaces including global strain and local strain, ferroelectric gate stacks, electrolytic interfaces, etc.

[0046] Figures 1a and 1c show exemplary side cross-sectional views of the formation of exemplary SiN spacers on a substrate below. Figure 1a shows, but is not limited to, a trench pattern formed to manufacture a SiN spacer. SiN-coated structures 10 and 12 are formed on the top of substrate 102. Multiple SiN-coated structures can be formed on the top of substrate 102, but only two structures 10 and 20 are shown. Substrate 102 may be a FinFET (fin-type field-effect transistor) substrate made of a Si-containing material such as Si, poly-Si, or SiO2. The number 104 represents a layer of SiN covering structure 106 on substrate 102. Structure 106, also called a pillar in the art, may be a gate stack covered by the SiN layer 104. In an ideal scenario, the SiN layer horizontally covering the top of the structure 106 or the top of the pillar, which is the etch front, and the top of the substrate 102 or the bottom of the trench, should be removed, and a straight and uniform SiN sidewall in the vertical direction with little or no footing at the bottom corner should be obtained on the structure 106. In this specification, "a1" and "a2" represent the thickness of the SiN layer on the side wall 104 at different heights of the structure or gate stack. The height of "a1" can be, for example, about one-third of the total height of the lower structure 106 below the top of the pillar, and can be close to the top of the pillar, while "a2" can be about one-third of the total height of the upper structure 106 above the substrate 102, and can be close to the substrate 102. Since the structure 106 below the SiN layer 104 may be curved at the bottom adjacent to the substrate 102 (not shown), the value of "a2" may be smaller than the value of "a1" which has a vertically straight SiN spacer. "b" and "c" represent the thickness of the SiN layer at the top of the structure 106 and the top of the substrate 102, respectively. In this specification, "b" and "c" are the thickness of the etch front. Furthermore, "c" may also represent the removal thickness of the substrate 102 after the SiN layer has been removed. In this case, "c" may be a negative value. As shown in Figure 1b, an ideal SiN spacer etching result is represented in which a vertically straight and uniform SiN sidewall 204 covering is formed on the structure 206, and the SiN layer of the etch front horizontally covering the top of the structure 206 and the top of the substrate 202 is removed. However, in actual spacer etching processes, as shown in Figure 1c, excess material often remains near the SiN layer and the substrate, creating a footing 308 at the bottom of the spacer. In this specification, the horizontal length "d" of the footing 308 adjacent to the substrate 302 is defined to represent the size of the footing.

[0047] The cycle ALE process of this disclosure for controlling the etching shape of SiN spacers formed on a Si-containing substrate overcomes footing defects when manufacturing SiN spacers. The cycle ALE process of this disclosure for controlling the etching shape of SiN spacers formed on a Si-containing substrate also produces vertically straight spacers without tapering when manufacturing SiN spacers. The cycle ALE process of this disclosure comprises a surface modification step or deposition step and a surface removal step or etching step in one ALE cycle. During the surface modification step, a thin layer of polymer that modifies the surface of the SiN layer (see Figure 1a, SiN layer 104) is deposited on the surface of the SiN layer in a reaction chamber. The thin layer of polymer is formed by a plasma of HFC gas, or a plasma of a gas mixture of HFC gas and an inert gas (such as N2, Ar, Kr, Xe, preferably Ar). The HFC gas reacts with the SiN material on the surface of the SiN layer to form a thin layer of polymer, which is a C-rich polymer (C:F>1), also known as the modified surface layer of the SiN layer, where a chemical bond is formed in the intermediate layer between the polymer layer and the surface of the SiN layer. In the surface removal step, the modified surface layer is etched or removed by a plasma of a highly volatile, pure inert gas (e.g., Ar) that can be pumped out of the chamber by high-energy ion bombardment to sputter the modified surface layer. After the surface removal step, the surface modification step is repeated to form a cycle ALE process. In cycle ALE, an ALE over-etching recipe can be applied to further remove the SiN layer at the etch front due to the infinite selectivity of SiN to the structure or gate stack. The ALE over-etching recipe may range from about 10% ALE over-etching to about 200% ALE over-etching, preferably from about 50% ALE over-etching to about 200% ALE over-etching. These processes can be cycled, allowing for gradual removal of the material, which improves pattern fidelity and minimizes footing of the SiN spacers.An N2 purging step is applied between the surface modification step and the surface removal step, or after the deposition step and the etching step. The N2 purging step includes a vacuum pumping step to pump HFC gas out of the reaction chamber before the N2 purging step, and a vacuum pumping step to pump N2 out of the reaction chamber after the N2 purging step.

[0048] An ideal cycle ALE process is based on a self-limiting reaction. This is because the reactants are at the bottom This means that the reaction occurs only with available surface areas on the substrate, while keeping the layer intact. ALE process conditions can be optimized by tracking the auto-limiting properties of reactant flow rate and exposure time. To avoid synergistic reactions, a constant N2 purge was used at the end of each step to remove excess etchant from the system.

[0049] Referring to Figure 2, in one cycle of the ALE process of this disclosure, a plasma etching gas formed from a gas mixture of HFC gas and Ar deposits a thin layer of polymer on the surface of a SiN layer in the reaction chamber in step 1. Then, in step 2, the thin layer of polymer is etched or removed by a plasma of pure inert gas (e.g., Ar). After each step, the reaction chamber undergoes a pump / N2 purge / pump process, which includes pumping the reaction chamber into a vacuum, filling the reaction chamber with N2 for purging, and pumping the reaction chamber into a vacuum again before proceeding to the next step.

[0050] The cycle ALE method disclosed herein is used to selectively plasma etch SiN using formula C x H y F zThe method may include using saturated or unsaturated, linear or cyclic HFC gases having (x=2~5, y>z). The HFC plasma interacts with SiN to form a C-rich polymer (C:F>1), which is deposited on the SiN layer to form a polymer layer. The HFC gas of this disclosure can be mixed with an inert gas in a plasma chamber to selectively etch not only the polymer layer but also a single atomic layer of the SiN layer. Thus, the SiN spacer is formed with improved shape control, such as high selectivity, minimized footing, limited fluorine generation, and a smooth surface of the SiN spacer. The inert gas may be Ar, Kr, and Xe. Preferably, it is Ar.

[0051] The HFC gases of this disclosure for forming a polymer layer on a SiN layer may include the following HFC gases, namely fluoroethane C2H5F (CAS #353-36-6) and 1-fluoropropane C3H7F (CAS #460-13-9). These HFC gases are mixed with an inert gas in a plasma chamber and used to deposit a polymer layer on the SiN layer. An intermediate layer is formed between the polymer layer and the SiN layer to modify the surface of the SiN layer. Then, a plasma of an inert gas such as Ar selectively removes not only the polymer layer but also the intermediate layer. This is equivalent to removing a single atomic layer of the SiN layer. In this way, the SiN spacer is formed with improved shape control, such as high selectivity, minimized footing, limited fluorine generation, and a smooth surface of the SiN spacer. The inert gas may be Ar, Kr, and Xe. Preferably, it is Ar.

[0052] The HFC gases disclosed herein contain N2 and CO2 as major impurities. x , SO x By removing H2O and other elements, the product is supplied with a purity exceeding 99% v / v, preferably exceeding 99.9% v / v.

[0053] The HFC gas of this disclosure contains trace gaseous impurities of less than 1% by volume, and among these trace gaseous impurities are impurity gases such as N2 and / or H2O and / or CO2 in amounts of less than 150 ppm by volume. Preferably, the water content of the plasma etching gas is less than 20 ppmw by weight. A purified product can be produced by distillation and / or by passing the gas or liquid through a suitable adsorbent such as a 4 Å molecular sieve.

[0054] The cycle ALE method of this disclosure includes preparing a plasma processing chamber having a substrate placed therein. The plasma processing chamber is, but is not limited to, reactive ion etching (RIE), capacitively coupled plasma (CCP) using one or more frequency RF sources, inductively coupled plasma (ICP), electron cyclotron resonance (ECR), microwave plasma reactor, remote plasma reactor, pulsed plasma reactor, or other types of etching systems capable of selectively removing a portion of a silicon-containing film or generating active species. This may be any enclosure or chamber within the device in which the etching method is performed, such as any chamber or enclosure used for plasma etching. A preferred chamber is a CCP chamber.

[0055] Those skilled in the art will recognize that different plasma reaction chamber designs offer different electronic temperature control. Suitable commercially available plasma reaction chambers include, but are not limited to, Applied Materials' magnetically enhanced reactive ion etchers sold under the trademark eMAX®, or Lam Research's dual CCP reactive ion etcher dielectric etching products sold under the trademark 2300® Flex®. The RF output in these may be pulsed to control plasma characteristics, thereby further improving etching performance (selectivity and damage).

[0056] To eliminate or reduce polymer deposition, an oxygen-containing gas may be introduced into the reaction chamber. Examples of oxygen-containing gases include, but are not limited to, oxidizing agents such as O2, O3, CO, CO2, NO, NO2, N2O, SO2, COS, H2O, and combinations thereof. The addition of oxygen or an oxygen-containing gas to plasma chemicals is known to increase the F / C ratio of plasma species and reduce polymer formation (see, for example, U.S. Patent No. 6,387,287 by Hung et al.). The HFC gas and oxygen-containing gas of this disclosure may be mixed together before being introduced into the reaction chamber.

[0057] Alternatively, the oxygen-containing gas is continuously introduced into the chamber, while the HFC gas of this disclosure is introduced into the chamber in a pulsed manner. The oxygen-containing gas accounts for approximately 0.01% to approximately 99.99% by volume of the mixture introduced into the chamber.

[0058] In the cycle ALE method of this disclosure, the plasma treatment time can vary from 0.01 seconds to 10,000 seconds, preferably from 1 second to 30 seconds. The N2 purging time can vary from 1 second to 10,000 seconds, preferably from 10 seconds to 60 seconds.

[0059] The temperature and pressure inside the reaction chamber are maintained under conditions suitable for the silicon-containing film to react with the activated etching gas. For example, the pressure inside the chamber can be maintained between about 1 mTorr and about 50 Torr, preferably about 1 mTorr and about 10 Torr, and more preferably about 300 mTorr and about 1 Torr, as required by the etching parameters. Similarly, the substrate temperature inside the chamber can be in the range of about -110°C to about 2000°C, preferably about -70°C to about 1500°C, more preferably about -20°C to about 1000°C, even more preferably about 25°C to about 700°C, even more preferably about 25°C to about 500°C, and even more preferably about 25°C to about 50°C. The temperature of the chamber walls can be in the range of about 25°C to about 100°C, depending on the processing requirements.

[0060] In one embodiment, the HFC gas of the present disclosure is introduced into a reaction chamber containing a substrate having a structure such as a gate stack on which a coated SiN layer is formed. The gas can be introduced into the chamber at a flow rate in the range of about 1 sccm to about 10 slm, preferably 1 sccm to 100 sccm. The inert gas can be introduced into the chamber at a flow rate in the range of about 1 sccm to about 10 slm, preferably 10 sccm to 200 sccm. Those skilled in the art will recognize that the flow rates may vary from tool to tool.

[0061] The cycle etching method of the present disclosure is a step of i) placing a patterned substrate on a substrate holder in a plasma processing chamber or reaction chamber, wherein the patterned substrate has a SiN layer covering at least one structure on the substrate, and the structure therein is ii) a step in which the substrate may be a stack and may include a Si-containing layer; ii) a step in which an HFC gas or a mixture of HFC gas and an inert gas is introduced into a reaction chamber to generate a plasma therein, wherein once the plasma is generated, the plasma deposits a polymer layer on the SiN layer that modifies the SiN surface, and the HFC gas is of formula C x H y F ziii) A saturated or unsaturated linear or cyclic HFC gas having (x=2~5, y>z), and the inert gas being N2, Ar, Kr, Xe, preferably Ar; iv) Pumping the HFC gas or a mixture of HFC gas and inert gas out of the reaction chamber until the reaction chamber reaches a high vacuum; iv) Purge the reaction chamber with N2; v) Pumping the reaction chamber to create a high vacuum again, i.e., pumping N2 out of the reaction chamber until the reaction chamber reaches a high vacuum; vi) Introducing the inert gas into the reaction chamber to generate an inert gas plasma; vii) Exposing the polymer layer deposited on the SiN layer to the inert gas plasma. The process further includes the steps of: using an inert gas plasma to remove the polymer layer deposited on the SiN layer of the etch front and the modified surface of the SiN layer of the etch front by ion bombardment; vii) pumping the reaction chamber to create a high vacuum, i.e., pumping the inert gas out of the reaction chamber until a high vacuum is reached; viiii) purging the reaction chamber with N2; ix) pumping the reaction chamber to create a high vacuum; and x) repeating steps ii) through ix) until the SiN layer of the etch front is selectively removed, thereby forming a substantially vertically straight SiN spacer containing the SiN layer on the sidewall of the gate stack. Over-etching recipes can be applied here, for example, from 50% over-etching to 200% over-etching.

[0062] In an ideal scenario, the ion bombardment process removes only the modified surfaces of the polymer and SiN layers at the etch fronts, i.e., the SiN layers at the tops of the pillars and the bottoms of the trenches, while leaving the SiN layers on the sidewalls unchanged. In practice, the thickness of the SiN layers on the sidewalls may vary slightly due to structures with slight deviations and / or curved bottoms. The cycle etching method of this disclosure provides that at least a large portion of the SiN layers on the sidewalls of the gate stack are not removed. Preferably, less than 10% of the thickness of the SiN layers on the sidewalls of the gate stack are removed, particularly the SiN layers near the bottom of the structure. More preferably, less than 5% of the thickness of the SiN layers on the sidewalls of the gate stack are removed. Even more preferably, less than 1% of the thickness of the SiN layers on the sidewalls of the gate stack are removed. Even more preferably, no measurable reduction in the thickness of the SiN layers on the sidewalls of the gate stack occurs.

[0063] Compared to conventional SiN spacer etching processes, the cycle ALE process of this disclosure using the HFC gas disclosed herein can reduce SiN footing at the bottom edge of the spacer by more than 70% while maintaining chemical integrity without causing significant surface roughness or chemical contamination (e.g., fluoride residue) in the underlying material, as shown in the following examples. More specifically, the cycle ALE process using C2H5F does not generate fluoride residue at the bottom and sidewalls of the trench. Here, the absence of fluoride residue means that the amount of fluoride residue remaining at the bottom and sidewalls of the trench is less than about 0.05%, preferably less than 0.03%. The cycle ALE process of this disclosure using the HFC gas disclosed herein also produces a smooth surface on the SiN spacer. [Examples]

[0064] Subsequent non-limiting embodiments are provided to further illustrate embodiments of the present invention. However, these embodiments are not intended to be exhaustive or to limit the scope of the invention disclosed herein.

[0065] The following examples are performed using a CCP plasma chamber under variable conditions for each step. The plasma output, pressure, gas flow rate, and reaction time were very well controlled. The pressure range was 300 mTorr to 1 Torr. The temperature range was 25°C to 50°C. The gas flow rate of CH3F, C2H5F, or C3H7F was varied from 1 sccm to 10 sccm. The flow rate of the noble gas was varied from 10 sccm to 200 sccm. The noble gas used was Ar. The RF plasma output was in the range of 50W to 100W. The plasma processing time or reaction time was varied from 1 second to 30 seconds. The N2 purge time was varied from 10 seconds to 60 seconds. N2, CO x , C x H y F z , SO x By removing major impurities such as H2O, the desired purity of CH3F, C2H5F, or C3H7F was >99.9%.

[0066] The sample used in the following examples was a patterned spacer wafer as shown in Figure 1a, and the substrate was a Si substrate.

[0067] The ellipsometer was a JAWololam Co. M-2000. The scanning electron microscope (SEM) for imaging patterned structures was a JOEL JSM-7500SEM. The XPS for surface characterization was a Kratos XPS-Supra Model. The atomic force microscope (AFM) for surface examination was a Park NX10 AFM. The transmission electron microscope (TEM) for imaging patterned structures was an FEI Tecnai Osiris operating at 200kV in bright-field (BF) TEM mode and high-resolution (HR) TEM mode. The analysis was performed using FEG / TEM. Electron diffusion spectroscopy (EDS) was acquired using a Bruker Quantax EDS system.

[0068] Example 1: CH3F cycle ALE process The CH3F cycle ALE process was performed under optimized ALE conditions. Referring to Figure 2, the etching gas was CH3F. The deposition step (Step 1) using CH3F was performed with an RF output of 75W, a pressure of 300mTorr, an Ar gas flow rate of 100sccm, and a CH3F flow rate of 5sccm. The reaction time for the deposition step was 4 seconds. The removal step (Step 2) was performed with an RF output of 50W, a pressure of 500mTorr, an Ar gas flow rate of 100sccm, no CH3F, and a reaction time of 30 seconds. The time for the pump / N2 purge / pump process between Step 1 and Step 2, and vice versa, was 90 seconds. Figure 3 shows the etched thickness for each ALE cycle with CH3F. As the ALE cycle increases, the etching thickness of SiN increases, the selectivity of SiN for p-Si, SiO, and SiON increases, while the selectivity of SiN for SiCN remains unchanged. Table 1 lists the etching thickness of SiN per cycle using CH3F for various ALE cycles.

[0069] [Table 1]

[0070] Example 2: C2H5F cycle ALE process The C2H5F cycle ALE process was performed under optimized ALE conditions. See Figure 2. Upon inspection, the etching gas was identified as C2H5F. The deposition step (Step 1) using C2H5F was performed with an RF output of 75W, a pressure of 300mTorr, an Ar gas flow rate of 100sccm, and a C2H5F flow rate of 5sccm. The reaction time for the deposition step was 4 seconds. The removal step (Step 2) was performed with an RF output of 50W, a pressure of 500mTorr, an Ar gas flow rate of 100sccm, no C2H5F, and a reaction time of 35 seconds. The time for the pump / N2 purge / pump process between Step 1 and Step 2, and vice versa, was 90 seconds. Figure 4 shows the etched thickness for C2H5F against the ALE cycle. With increasing ALE cycles, the etching thickness of SiN increased linearly, and no etching occurred to p-Si, SiO, and SiCN. The results of the C2H5F cycle ALE process demonstrate very high selectivity, almost infinite selectivity, for SiN against p-Si, SiO, SiCN, and SiCN.

[0071] Compared to the cycled ALE process using CH3F, C2H5F gas exhibits higher etching selectivity for SiN compared to p-Si, SiO, SiON, and SiCN, and a lower etching rate, resulting in less etching per cycle. The etching thickness of SiN per cycle using C2H5F for various ALE cycles is shown in Table 1.

[0072] Example 3: C3H7F Cycle ALE Process The C3H7F cycle ALE process was performed under optimized ALE conditions. Referring to Figure 2, the etching gas was C3H7F. The deposition step (Step 1) using C3H7F was performed with an RF output of 75W, a pressure of 300mTorr, an Ar gas flow rate of 100sccm, and a C3H7F flow rate of 5sccm. The reaction time for the deposition step was 4 seconds. The removal step (Step 2) was performed with an RF output of 50W, a pressure of 500mTorr, an Ar gas flow rate of 100sccm, no C3H7F, and a reaction time of 40 seconds. The time for the pump / N2 purge / pump process between Step 1 and Step 2, and vice versa, was 150 seconds. Figure 5 shows the etched thickness for C3H7F over ALE cycles. The amount of etched thickness increased linearly with the number of ALE cycles at an etching rate of 2.0–2.4nm / cycle. Infinite etching selectivity of SiN over other materials can also be obtained under optimized conditions. Table 1 shows the SiN etching thickness per cycle using C3H7F for various ALE cycles.

[0073] Example 4: SEM of cycle ALE of SiN spacer patterned wafers using CH3F and C2H5F Regarding Figure 1a, the dimensions of the SiN spacer patterned wafer before etching are as follows: "a" is 34 nm; "b" is 34 nm; and "c" is 34 nm. Substrate 102 is a Si substrate. The main concerns after etching are damage to the Si substrate, sidewall deposition, footing at the corners between the spacer and the substrate, fluoride residue on the SiN layer and the substrate or etch front, and surface roughness of the SiN layer and the substrate or etch front. Table 2 lists the etch front thickness after cycle ALE for SiN spacers using CH3F and C2H5F in various cycle ALE modes such as 50% etching, 100% etching, 100% over-etching, and 200% over-etching. Optimized results for ALE 100% etching and ALE 100% over-etching using C2H5F are shown, noting that there is little to no footing formed at the bottom of the spacer.

[0074] [Table 2]

[0075] Example 5: TEM of cycle ALE of SiN spacer patterned wafer using C2H5F The 100% ALE etching and 100% over-etching using C2H5F as shown in Example 4 were further tested by TEM.

[0076] Regarding Figure 1a, the dimensions of the SiN spacer patterned wafer before etching are as follows: "a" is 34 nm; "b" is 34 nm; and "c" is 34 nm. Substrate 102 is a Si substrate. Samples for TEM were prepared using in situ focused ion beam (FIB) lift-out technique on an FEI Strata400 dual-beam FIB / SEM. Samples were capped with protective carbon and e-Pt / I-Pt before grinding. The TEM lamellar thickness was approximately 100 nm. Samples were imaged in bright-field (BF) TEM mode and high-resolution (HR) TEM mode using an FEI Tecnai Osiris FEG / TEM operating at 200 kV. TEM results for cycled ALE using C2H5F are shown in Table 3.

[0077] In ALE-100% etching, no over-etching occurred, the SiN at the top of the pillars was not completely etched, and the thicknesses of the left (L) and right (R) SiN layers on the sidewalls ("a2", approximately one-third of the total gate stack height near the substrate) were 32.6 nm and 32.3 nm, respectively, while the left and right footings ("d") were 6.6 nm and 8.2 nm. The thickness of the SiN layer on the sidewalls ("a2") decreased by approximately 5%. In contrast, in ALE-100% over-etching, the SiN at the top of the pillars was completely etched, and the thicknesses of the left and right SiN layers on the sidewalls ("a2") were 30.4 nm and 31.1 nm, respectively, while the left and right footings were 6.0 nm and 3.9 nm. The thickness of the SiN layer on the sidewalls ("a2") decreased by approximately 9.5%. Therefore, less than 10% of the thickness of the SiN layer on the sidewalls of the gate stack is removed. A decrease in the thickness (a2) of the SiN layer on the sidewall may be due to curvature of the adjacent structure or gate stack on the substrate, causing the SiN layer adjacent to the structure or gate stack to curve inward. A decrease in the thickness (a2) of the SiN layer on the sidewall may also be due to small deviations.

[0078] Si recess refers to the thickness of the etched Si substrate. Si recess was measured 10 nm away from the bottom edge of the SiN sidewall in the left-right direction. In ALE-100% etching, no over-etching occurred, and the left and right Si recesses were 1.446 nm each. The two were 1.285 nm and 1.285 nm. In contrast, with ALE-100% overetching, the left and right Si recesses were 4.096 nm and 4.194 nm, respectively.

[0079] The surface roughness of the SiN spacers after ALE (Automated Laser Etching) using C2H5F, both 100% etching and 100% over-etching, includes surface roughness at the pillar tops (T) and trench bottoms (B). Table 3 also includes the surface roughness results. In 100% ALE etching, a SiN layer of 2-3 atomic layers (al) remained at the pillar tops (positive value). This means that the SiN layer at the pillar tops was not completely removed. In this case, the interface between the SiN layer and the pillar tops was smooth and flat, corresponding to the surface roughness without etching. The trench bottoms etched with 100% ALE etching also showed that a SiN layer of 2-3 atomic layers remained at the trench bottoms. In 100% ALE over-etching, both the pillar tops and trench bottoms were etched to the 2-3 atomic layer level (negative value).

[0080] [Table 3]

[0081] Example 6: EDS of Cycle ALE of SiN Spacer Patterned Wafer Using C2H5F Figure 6a shows the EDS mapping (horizontal scan of the sidewall) of ALE-treated SiN spacers with 100% etched sidewalls and 100% over-etched sidewalls, respectively, using C2H5F. With 100% etching, no over-etching occurs, and no F residue is produced on the sidewalls. Even with 100% over-etching, no F residue is produced on the sidewalls.

[0082] Figure 6b shows an EDS line scan using atoms of a SiN spacer after cycle ALE with 100% etched sidewalls and 100% over-etched sidewalls, respectively, using C2H5F (vertical scan of the spacer bottom). No F residue is produced on the sidewalls at 100% etching. No F residue is produced on the sidewalls even at 100% over-etching.

[0083] Example 7: Cycle ALE vs. Continuous Etching using C2H5F Table 4 compares continuous etching and cyclic ALE. The results show that in the continuous etching process, the Si recess was 2.9 nm; a polymer layer was formed on the sidewall; and footing was 16.2 nm at the left corner and 15.3 nm at the right corner. On the other hand, in the cyclic ALE process, the results show that the Si recess was 4.1–4.2 nm; a minimal polymer layer was formed on the sidewall; and footing was 6.0 nm on the left and 3.9 nm on the right. Compared to continuous etching, the cyclic ALE process reduces footing by approximately 75%. Thus, in the cyclic ALE process, both Si recess and surface roughness are improved, and the SiN spacer is etched using C2H5F. Compared to a continuous etching process, little to no footing is formed. In this specification, little to no footing can be defined by "d" ≤ approximately 6 nm.

[0084] [Table 4]

[0085] Figure 7 shows the continuous etching of a SiN spacer using C2H5F: EDS mapping (left) and EDS line scan (right). In the continuous etching, F residue was clearly present on the sidewalls (approximately 22–36 nm) and at the bottom of the trenches (approximately 36–58 nm). In contrast, no F residue was shown in Figures 6a and 6b.

[0086] Table 5 shows the measured percentage of fluoride residue remaining at the trench bottom and sidewalls after cycled ALE and continuous etching, respectively. In the cycled ALE process mode, almost no fluoride remained at the trench bottom and sidewalls, whereas the continuous etching method generated fluoride residue at the trench bottom and sidewalls.

[0087] Thus, the cycle ALE process mode using C2H5F does not generate fluoride residue and reduces residual etchant on the etch front and sidewall surfaces. In the cycle ALE process mode using C2H5F, SiN footing is minimized, and there is little to no damage to the SiN spacer top.

[0088] [Table 5]

[0089] Example 8 Surface roughness of a SiN flat wafer using C2H5F in cycle ALE Surface Roughness - The RMS of a thin SiN film on a flat wafer was measured by AFM before and after cycle ALE using C2H5F. Before cycle ALE with C2H5F, the RMS (root mean square) was 2.9 nm. After cycle ALE with C2H5F, the RMS was 1.1 nm. Thus, a smaller RMS was achieved after cycle ALE with C2H5F. This indicates the improved surface smoothing effect of ALE using C2H5F. It shows the result.

[0090] In summary, the cycle ALE of SiN spacers using the HFCs of the present disclosure, such as C2H5F and C3H7F, can minimize SiN footing (for example, reducing footing by approximately 75% compared to continuous etching), does not generate F residues at pillar tops, trench bottoms, and sidewalls, and does not result in chemical contamination or a decrease in surface roughness after the cycle ALE process. The cycle ALE of SiN spacers using the HFCs of the present disclosure, such as C2H5F and C3H7F, improves the control of etching shapes for etching SiN spacers formed on Si-containing substrates in semiconductor applications with high selectivity.

[0091] It will be understood that many additional modifications in the details, materials, steps, and arrangement of the parts described and illustrated herein to illustrate the nature of the present invention can be made by those skilled in the art within the principles and scope of the invention set forth in the appended claims. Accordingly, the present invention is not intended to be limited to the specific embodiments shown above and / or in the appended drawings.

[0092] While embodiments of the present invention have been shown and described, modifications thereof can be made by those skilled in the art without departing from the spirit or teachings of the invention. The embodiments described herein are illustrative and not limiting. Many variations and modifications of the compositions and methods are possible and fall within the scope of the invention. Accordingly, the scope of protection is not limited to the embodiments described herein but is limited only by the subsequent claims, which include all equivalents of the subject matter of the claims.

Claims

1. A cycle etching method, i) Exposing a SiN layer covering a structure on a substrate in a reaction chamber to a plasma of a hydrofluorocarbon (HFC) selected from the group consisting of C2H5F and C3H7F to modify the surface of the SiN layer and form a polymer layer deposited on the SiN layer; ii) Exposing the polymer layer deposited on the SiN layer to an inert gas plasma, and removing the polymer layer deposited on the SiN layer at the etch front and the modified surface of the SiN layer by the inert gas plasma; and iii) Repeating steps i) and ii) until the SiN layer covering the etch front is removed, thereby forming a vertically straight SiN spacer having the SiN layer covering the side wall of the structure; A cycle etching method wherein the HFC plasma in step i) is a remote plasma.

2. After step i) above, Steps include: evacuating the reaction chamber with a pump to create a vacuum; The reaction chamber is N ２ The step to purge; The steps of pumping the reaction chamber to create a vacuum; and A step of introducing the inert gas into the reaction chamber to generate the plasma of the inert gas; and, After step ii) above, Steps include: evacuating the reaction chamber with a pump to create a vacuum; The reaction chamber is N ２ The step to purge; The steps of pumping the reaction chamber to create a vacuum; and A step of introducing the HFC into the reaction chamber to generate a plasma of the HFC, The cycle etching method according to claim 1, further comprising:

3. The hydrofluorocarbon (HFC) is mixed with an oxygen-containing gas selected from O ２ , O ３ , CO, CO ２ , NO, NO ２ , N ２ O, SO ２ , COS, H ２ O, and combinations thereof. The cycle etching method according to claim 1 or 2.

4. The inert gas is N ２ The cycle etching method according to claim 1 or 2, wherein the material is Ar, Kr, or Xe.

5. The cycle etching method according to claim 1 or 2, wherein the HFC selectively etches the SiN layer on the structure.

6. The cycle etching method according to claim 1 or 2, wherein no footing is formed at all at each corner between the vertically straight SiN spacer and the substrate.

7. A cycle etching method for forming a straight SiN spacer in the vertical direction, i) A step of modifying the surface of the SiN layer by exposing a SiN layer covering a structure on a substrate in a reaction chamber to a plasma of a mixture of hydrofluorocarbon (HFC) and an oxygen-containing gas to form a polymer layer deposited on the SiN layer, wherein the HFC is selected from the group consisting of C2H5F and C3H7F, and the oxygen-containing gas is O ２ , O ３ CO, CO ２ No, no ２ , N ２ O, SO ２ , COS, H ２ Steps selected from O, and combinations thereof; ii) Exposing the polymer layer deposited on the SiN layer to an inert gas plasma, and removing the polymer layer deposited on the SiN layer at the etch front and the modified surface of the SiN layer by the inert gas plasma; and iii) Repeat steps i) and ii) until the SiN layer covering the etch front is removed, thereby forming a vertically straight SiN spacer having the SiN layer covering the side wall of the structure; Includes, A cycle etching method wherein the plasma of the mixture in step i) is a remote plasma.

8. The cycle etching method according to claim 7, wherein no footing is formed at all at each corner between the vertically straight SiN spacer and the substrate.

9. A cycle etching method for forming a straight SiN gate spacer in the vertical direction, i) The SiN layer covering the gate stack on the substrate inside the reaction chamber is C ２ H ５ F and C ３ H ７ A step of modifying the surface of the SiN layer by exposing it to a plasma of a hydrofluorocarbon (HFC) selected from the group consisting of F and to form a polymer layer deposited on the SiN layer; ii) Exposing the polymer layer deposited on the SiN layer to an Ar plasma, wherein the Ar plasma removes the polymer layer deposited on the SiN layer at the etch front and the modified surface of the SiN layer; and iii) Repeating steps i) and ii) until the SiN layer of the etch front is selectively removed, thereby forming a vertically straight SiN gate spacer having the SiN layer covering the sidewall of the gate stack; Includes, A cycle etching method wherein the HFC plasma in step i) is a remote plasma.

10. The cycle etching method according to claim 9, wherein no footing is formed at all at each corner between the vertically straight SiN gate spacer and the substrate.

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