Microelectronic device having multiple step contacts spread in stepped layers, and related systems and methods

Abstract

The microelectronic device includes a stack structure having a vertically alternating sequence of insulating and conductive structures arranged in layers. At least one of the stadiums in the stack structure includes a staircase having a step provided by a group of conductive structures. The step contacts extend to a step of the staircase of at least one of the stadiums. Each conductive structure of the group of conductive structures has a plurality of step contacts contacting it at at least one of the staircase steps. Additional microelectronic devices are also disclosed, as are methods of fabrication and electronic systems.

Description

[Technical Field]

[0001] This application claims the benefit as of the filing date of U.S. Provisional Patent Application No. 63 / 239,984, filed on September 2, 2021. This application is also related to U.S. Non-Provisional Patent Application No. 17 / 476,334, filed on September 15, 2021, which claims priority to the aforementioned U.S. Provisional Patent Application.

[0002] Embodiments of this disclosure relate to the field of microelectronic device design and manufacturing. More specifically, this disclosure relates to microelectronic devices (for example, memory devices such as 3D NAND memory devices) that include contacts extending to conductive structures in a layered stack including insulating structures and perpendicularly alternating conductive structures. This disclosure also relates to methods for forming such devices and systems for incorporating such devices. [Background technology]

[0003] Memory devices provide data storage for electronic systems. Flash memory devices are one of various types of memory devices and have numerous applications in modern computers and other electrical devices. Conventional flash memory devices may include a memory array having a large number of charge storage devices (memory cells such as non-volatile memory cells) arranged in rows and columns. In the NAND architecture type of flash memory, the memory cells arranged in columns are sequentially linked, and the first memory cell in a column is linked to a data line (e.g., a bit line). In a "three-dimensional NAND" memory device (which may also be referred to herein as a "3D NAND" memory device), the vertical memory device type is not only memory cells arranged in row and column form in a horizontal array, but the layers of the horizontal array are stacked on top of each other (e.g., as vertical strings of memory cells) to provide a "three-dimensional array" of memory cells. The stack of layers alternates conductive and insulating (e.g., dielectric) materials vertically. The conductive material acts as a control gate, for example, for the access lines (e.g., word lines) of the memory cells. Vertical structures (e.g., struts including channel and tunnel structures) extend along vertical strings of memory cells. The drain ends of the strings are adjacent to one of the top and bottom ends of the vertical structures (e.g., struts), while the source ends of the strings are adjacent to the other of the top and bottom ends of the struts. The drain ends are operably connected to bit lines, while the source ends are operably connected to source structures (e.g., source plates, source lines). The 3D NAND memory device also includes electrical connections between, for example, the device's access lines (e.g., word lines) and other conductive structures, so that memory cells in the vertical strings can be selected for write, read, and erase operations.

[0004] One method for forming such electrical connections involves forming so-called "staircase" structures having "steps" (or "steps") at the ends of the layers of the stack (e.g., adjacent ends). The steps define contact areas of conductive structures in the device, such as access lines (e.g., word lines), which may be formed by the conductive material of the layered stack. Contact structures may be formed in physical contact with the steps to provide electrical access to the conductive structures associated with the steps (e.g., word lines). Contact structures may communicate electrically via conductive paths to additional contact structures communicating with source / drain regions.

[0005] The ongoing objective in the microelectronic device manufacturing industry is to ensure that the features of microelectronic devices are manufactured in such a way that the device functions as intended, including effective electrical communication between conductive features, such as contact structures and steps formed in layered stacks. However, this remains a challenge, as failure to accurately manufacture a single contact structure, in particular, can render the corresponding conductive structure (e.g., word lines) electrically inaccessible in conventional device designs, and can even render the entire group of device features inoperable. [Overview of the project]

[0006] Disclosed is a microelectronic device. The microelectronic device includes a stack structure comprising a vertically alternating sequence of insulating and conductive structures arranged in layers. Each layer comprises at least one conductive structure and at least one insulating structure. The microelectronic device also includes stadiums within the stack structure. At least one of the stadiums comprises two steps having steps provided by a group of conductive structures. The step contacts extend to the steps of the two steps of at least one of the stadiums. Each conductive structure in the group of conductive structures has a plurality of step contacts that contact it at least one of the steps of the two steps.

[0007] Microelectronic devices are also disclosed, including a stack structure, a series of stadiums within the stack structure, and conductive contacts within the horizontal area of ​​the stadiums among the series of stadiums. The stack structure includes insulating structures arranged in layers and perpendicularly sandwiched with the conductive structures. At least one of the stadiums among the series of stadiums has a step that is at least partially defined by the conductive structures of a first group of layers. At least one other stadium has an additional step that is at least partially defined by the conductive structures of a second group of layers. The first group of layers is at a lower elevation than the elevation of the second group of layers. Conductive contacts include pairs of conductive contacts and conductive contacts among those conductive contacts. Each pair of conductive contacts extends from each other to one of the different conductive structures of the first group of layers. The conductive contacts among those conductive contacts extend from each other to one of the different conductive structures of the second group of layers.

[0008] Furthermore, a method for forming a microelectronic device is disclosed. The method comprises forming a layered stack on a base structure. The layered stack comprises a vertically alternating sequence of insulating structures and other structures. Stadiums are formed in the layered stack. Each stadium comprises one or more steps defined at least partially by several horizontal ends of the other structures. At least one dielectric material is formed in grooves lying vertically on top of the stadium. Contact openings are formed through at least one dielectric material. At least one pair of contact openings extends vertically to a common one of the other structures. Conductive contact structures are formed at each contact opening.

[0009] An electronic system is also disclosed. The electronic system includes a three-dimensional memory device, at least one processor operably communicating with the three-dimensional memory device, and at least one peripheral device operably communicating with the at least one processor. The three-dimensional memory device includes a stack structure including conductive structures arranged alternately and in layers perpendicular to insulating structures. A series of stepped stadiums are defined in blocks of the stack structure. Pairs of step contacts extend through a dielectric material covering at least one of the stadiums. Pairs of step contacts extend to those of each other in conductive structures that define at least one step of at least one stadium. [Brief explanation of the drawing]

[0010] [Figure 1] This is a schematic cross-sectional, perspective view of a microelectronic device structure according to an embodiment of the present disclosure, in which at least one stadium ("multi-step stadium per layer"), each stepped layer includes multiple steps, and the multiple-step contacts extend to each stepped layer. [Figure 2A]An embodiment of the present disclosure is an enlarged, schematic, cross-sectional, and elevation view of the outline of a multi-step, layered stadium staircase, the illustrated portion of which may replace any or all portions of Figure 1 indicated by box 140, where a descending staircase descends toward an ascending staircase, and the two staircases share a common lowest step. [Figure 2B] An enlarged, schematic, cross-sectional, and elevation view of the outline of a multi-step, layered stadium staircase, the illustrated portion of which may replace any or all portions of Figure 1 indicated by box 140, wherein the ascending staircase rises toward the descending staircase, and the two staircases share a common highest step. [Figure 2C] An embodiment of the present disclosure is an enlarged, schematic, cross-sectional, and elevation view of the outline of a multi-step, layered stadium staircase, the illustrated portion of which may replace any or all portions of Figure 1 indicated by box 140, where the staircase outline includes one pair of ascending steps. [Figure 2D] An embodiment of the present disclosure is an enlarged, schematic, cross-sectional, and elevation view of the outline of a multi-step, layered stadium staircase, the illustrated portion of which may replace any or all portions of Figure 1 indicated by box 140, where the staircase outline includes a pair of descending steps. [Figure 3A] An embodiment of the present disclosure is an enlarged, schematic, cross-sectional, and elevation view of the outline of a single-step, layered stadium staircase, the portion shown may replace any or all portions of Figure 1 indicated by box 146, where the lowest step of a descending staircase is vertically offset below the lowest step of an ascending staircase. [Figure 3B]A schematic cross-sectional elevation view of a single-step stadium staircase profile, enlarged by layer, where the portion shown can replace any or all of the portions of FIG. 1 shown by box 146, and where the highest step of the ascending staircase is vertically offset above the highest step of the descending staircase. [Figure 3C] A schematic cross-sectional elevation view of a single-step stadium staircase profile, enlarged by layer, where the portion shown can replace any or all of the portions of FIG. 1 shown by box 146, and where the highest step of the ascending staircase is vertically offset below the highest step of the descending staircase. [Figure 3D] A schematic cross-sectional elevation view of a single-step stadium staircase profile, enlarged by layer, where the portion shown can replace any or all of the portions of FIG. 1 shown by box 146, and where the ascending staircase rises across the full width of the stadium. [Figure 3E] A schematic cross-sectional elevation view of a single-step stadium staircase profile, enlarged by layer, where the portion shown can replace any or all of the portions of FIG. 1 shown by box 146, and where the descending staircase descends across the full width of the stadium. [Figure 4] A schematic cross-sectional perspective view of a microelectronic device structure of FIG. 1 further showing a path configured to share electrical communication between contacts through a stack, step contacts, and conductive structures to which the step contacts extend. [Figure 5] A schematic cross-sectional elevation view of the microelectronic device structures of FIGS. 1 and 4 schematically showing the path of FIG. 4 and contacts through the stack. [Figure 6]Schematic cross-sectional and elevation views of the microelectronic device structures of FIGS. 1, 4, and 5, where the step contacts are fabricated irregularly and do not physically contact or electrically connect to the steps of the respective conductive structures. [Figure 7] Schematic cross-sectional and elevation views of a microelectronic device structure according to an embodiment of the present disclosure, schematically showing contacts through paths and stacks, where the conductive structures providing multiple steps each provide those multiple steps at different stadia. [Figure 8] Schematic cross-sectional and elevation views of a microelectronic device structure according to an embodiment of the present disclosure, schematically showing contacts through paths and stacks, where at least one stadium defines a relatively wide and / or relatively long step where the respective multiple-step contacts extend. [Figure 9] Schematic cross-sectional and elevation views of a microelectronic device structure according to an embodiment of the present disclosure, schematically showing contacts through paths and stacks, where each stadium of a series of stadia defines multiple steps for each stepped layer. [Figure 10] Schematic cross-sectional and elevation views of various stages of a process for manufacturing a microelectronic device structure according to an embodiment of the present disclosure, or any of the aforementioned microelectronic device structures. [Figure 11] Schematic cross-sectional and elevation views of various stages of a process for manufacturing a microelectronic device structure according to an embodiment of the present disclosure, or any of the aforementioned microelectronic device structures. [Figure 12] Schematic cross-sectional and elevation views of various stages of a process for manufacturing a microelectronic device structure according to an embodiment of the present disclosure, or any of the aforementioned microelectronic device structures. [Figure 13]These are schematic cross-sectional and elevational views of various stages of a process for manufacturing a microelectronic device structure according to an embodiment of the present disclosure, or any of the aforementioned microelectronic device structures. [Figure 14] These are schematic cross-sectional and elevational views of various stages of a process for manufacturing a microelectronic device structure according to an embodiment of the present disclosure, or any of the aforementioned microelectronic device structures. [Figure 15] These are schematic cross-sectional and elevational views of various stages of a process for manufacturing a microelectronic device structure according to an embodiment of the present disclosure, or any of the aforementioned microelectronic device structures. [Figure 16] These are schematic cross-sectional and elevational views of various stages of a process for manufacturing a microelectronic device structure according to an embodiment of the present disclosure, or any of the aforementioned microelectronic device structures. [Figure 17] These are schematic cross-sectional and elevational views of various stages of a process for manufacturing a microelectronic device structure according to an embodiment of the present disclosure, or any of the aforementioned microelectronic device structures. [Figure 18] These are schematic cross-sectional and elevational views of various stages of a process for manufacturing a microelectronic device structure according to an embodiment of the present disclosure, or any of the aforementioned microelectronic device structures. [Figure 19] These are schematic cross-sectional and elevational views of various stages of a process for manufacturing a microelectronic device structure according to an embodiment of the present disclosure, or any of the aforementioned microelectronic device structures. [Figure 20] These are schematic cross-sectional and elevational views of various stages of a process for manufacturing a microelectronic device structure according to an embodiment of the present disclosure, or any of the aforementioned microelectronic device structures. [Figure 21]These are schematic cross-sectional and elevational views of various stages of a process for manufacturing a microelectronic device structure according to an embodiment of the present disclosure, or any of the aforementioned microelectronic device structures. [Figure 22] These are schematic cross-sectional and elevational views of various stages of a process for manufacturing a microelectronic device structure according to an embodiment of the present disclosure, or any of the aforementioned microelectronic device structures. [Figure 23] These are schematic cross-sectional and elevational views of various stages of a process for manufacturing a microelectronic device structure according to an embodiment of the present disclosure, or any of the aforementioned microelectronic device structures. [Figure 24] These are schematic cross-sectional and elevational views of various stages of a process for manufacturing a microelectronic device structure according to an embodiment of the present disclosure, or any of the aforementioned microelectronic device structures. [Figure 25] These are schematic cross-sectional and elevational views of various stages of a process for manufacturing a microelectronic device structure according to an embodiment of the present disclosure, or any of the aforementioned microelectronic device structures. [Figure 26] This is a block diagram of an electronic system including a microelectronic device, which includes at least one microelectronic device structure according to an embodiment of the present disclosure. [Modes for carrying out the invention]

[0011] Embodiments of the present disclosure include structures (e.g., microelectronic device structures), apparatus (e.g., microelectronic devices), and systems (e.g., electronic systems) comprising a stack of vertically alternating conductive and insulating structure layers arranged in layers. A series of stadiums are formed in the layered stack. A stadium includes a staircase structure having steps defined by at least one end of the conductive structure in the layer of the stack (e.g., a horizontal surface adjacent side wall) and risers defined by at least one end of the conductive structure and at least one end of the insulating structure in the layer (e.g., a vertical surface). For at least some of the layers of the stack, e.g., the deepest layer of the stack, multiple steps are formed layer by layer (e.g., per conductive structure (e.g., per word line)), or relatively wide and / or relatively long steps are formed layer by layer. At least one conductive "step contact" (e.g., access line contact, word line contact) extends to each step. For layers having multiple defined steps (or relatively wide and / or relatively long defined steps), the multiple step contacts are formed to be in electrical communication with the conductive structures (e.g., word lines) of each such layer. Thus, if one of the step contacts is not manufactured precisely—for example, due to the challenge of manufacturing a step contact that extends to the deepest layer—the precisely manufactured step contact that extends to another part of that layer (e.g., another step) still directly provides physical contact with and electrical communication with the conductive structures (e.g., access lines, word lines) of the layer. Thus, the multiple step contacts can function as "backup" step contacts for a particular layer in the stack, significantly reducing the possibility of complete failure to electrically access any one conductive structure (e.g., word lines) in the manufactured microelectronic device.Therefore, if a telecommunications failure with any one layer of the stadium could otherwise manifest as a total stadium failure (e.g., a stadium "read" or "write" error), including multi-step contacts per layer can significantly reduce the likelihood of such a total stadium failure.

[0012] In this specification, the term “descending stairs” refers to stairs that generally exhibit a negative gradient.

[0013] In this specification, the term “ascending stairs” refers to and is used to mean stairs that generally exhibit a positive gradient.

[0014] When used individually herein, the terms “multiple,” “group,” and “set” each mean and refer to the existence of two or more of the indicated features (e.g., “multiple”), and these terms may be used synonymously. When used in combination herein (e.g., “multiple sets,” “multiple groups”), the terms mean and refer to the existence of two or more of the multiple indicated features.

[0015] In this specification, the term “high aspect ratio” means and refers to a height-to-width ratio (e.g., the ratio of maximum height to maximum width) greater than approximately 10:1 (for example, greater than approximately 20:1, greater than 30:1, greater than approximately 40:1, greater than approximately 50:1, greater than approximately 60:1, greater than approximately 70:1, greater than approximately 80:1, greater than approximately 90:1, greater than approximately 100:1).

[0016] In this specification, the adjective “source / drain” refers to and means a feature configured for association with either or both of the source and drain regions of a device containing a “source / drain” feature. The “source region” may otherwise be configured as the “drain region” and vice versa, without departing from the scope of this disclosure.

[0017] In this specification, the terms “opening,” “groove,” “slit,” “recess,” and “void” mean and include volumes that extend through or into at least one structure or material, leaving a gap within at least one structure or material, or volumes that extend between structures or materials, leaving a gap between structures or materials. Unless otherwise stated, “opening,” “groove,” “slit,” and / or “recess” are not necessarily the absence of material. That is, “opening,” “groove,” “slit,” or “recess” are not necessarily voids. “Opening,” “groove,” “slit,” or “recess” formed in or between structures or materials may include structures or materials other than those in which the opening is formed. Structures or materials “exposed” to an opening, groove, slit, or recess are not necessarily in contact with the atmosphere or a non-solid environment. Structures or materials “exposed” to an opening, groove, slit, or recess may be adjacent to or in contact with other structures or materials located within the opening, groove, slit, or recess. On the other hand, unless otherwise stated, a “void” may be substantially or completely devoid of material. A “void” formed in or between a structure or material does not have to contain any other structure or material other than the one in which the “void” is formed. And a structure or material “exposed” to a “void” may come into contact with the atmosphere or a non-solid environment.

[0018] In this specification, the terms “substrate” and “basic structure” mean and include a basic material or other structure on which components, such as those in memory cells, are formed. A substrate or basic structure may be a semiconductor substrate, a basic semiconductor material on a support structure, a metal electrode, or a semiconductor substrate having one or more materials, structures, or regions formed thereon. A substrate may be a conventional silicon substrate or other bulk substrate containing a semiconducting material. In this specification, the term “bulk substrate” means not only a silicon wafer, but also a silicon-on-insulator ("SOI (silicon-on-insulator)") substrate, such as a silicon-on-sapphire ("SOS (silicon-on-sapphire)") substrate or a silicon-on-glass ("SOG (silicon-on-glass)") substrate, an epitaxial layer of silicon on a basic semiconductor substrate, or other semiconductor or optoelectronic materials, such as silicon germanium (Si) in particular. 1-x Ge x Here, x is, for example, a mole fraction between 0.2 and 0.8), germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN), or indium phosphide (InP) also mean and include. Furthermore, where “substrate” or “foundation structure” is referred to in the following description, a previous process stage may have been used to form materials, structures, or junctions on a foundation semiconductor structure, foundation structure, or other foundation.

[0019] In this specification, the terms “insulator” and “insulate” mean, and include, electrically insulating or electrically insulating materials or structures when used in reference to materials or structures. An “insulator” or “insulate” material or structure is at least one dielectric oxide material (for example, silicon dioxide (SiO₂)). x ), phosphate glass, borosilicate glass, borosilicate glass, fluorosilicate glass, aluminum oxide (AlO x ), hafnium oxide (HfO x ), niobium oxide (NbO x ), titanium dioxide (TiO x ), zirconium oxide (ZrO x), tantalum oxide (TaO x ), and magnesium oxide (MgO x ), one or more of which), at least one dielectric nitride material (e.g., silicon nitride (SiN y )), at least one dielectric oxynitride material (e.g., silicon oxynitride (SiO x N y )), at least one dielectric carboxynitride material (e.g., silicon carboxynitride (SiO x C z N y )), and / or one or more of air. As used herein, a chemical formula (e.g., SiO x , AlO x , HfO x , NbO x , TiO x , SiN y , SiO x N y , SiO x C z N y ) containing one or more of "x", "y", and / or "z" represents a material that includes, for every one atom of any one element (e.g., Si, Al, Hf, Nb, Ti), the average ratio of the "x" atoms of one element, the "y" atoms of another element, and / or the "z" atoms of an additional element (if any). Since the chemical formula represents the relative atomic ratio rather than a precise chemical structure, an insulating material or an insulating structure may include one or more stoichiometric compounds and / or one or more non-stoichiometric compounds, and the values of "x", "y", and "z" (if any) may be integers or non-integers. As used herein, the term "non-stoichiometric compound" means and includes a compound having an elemental composition that cannot be represented by a well-defined ratio of natural numbers and that violates the law of definite proportions. In addition, an "insulating structure" means and includes a structure formed of and including an insulating material.

[0020] In this specification, the term “sacrificial” means, when used in reference to a material or structure, a material or structure that is formed during a manufacturing process but is removed (e.g., substantially removed) before the completion of the manufacturing process.

[0021] In this specification, the term “horizontal” means and includes the direction parallel to the primary surface of the substrate on which the referenced material or structure lies. The “width” and “length” of each material or structure may be defined as dimensions in the horizontal plane. Referring to the figure, the “horizontal” direction may be perpendicular to the indicated “Z” axis, parallel to the indicated “X” axis, or parallel to the indicated “Y” axis.

[0022] In this specification, the term “transverse” means, and includes, the direction in a horizontal plane parallel to the primary surface of the substrate on which the referenced material or structure lies and substantially perpendicular to the “longitudinal” direction. The “width” of each material or structure may be defined as the dimension in the transverse direction of the horizontal plane. Referring to the figure, the “transverse” direction may be parallel to the indicated “X” axis, perpendicular to the indicated “Y” axis, and perpendicular to the indicated “Z” axis.

[0023] In this specification, the term “longitudinal” means, and includes, the direction in a horizontal plane parallel to the primary surface of a substrate on which the referenced material or structure lies and substantially perpendicular to the “transverse” direction. The “length” of each material or structure may be defined as the dimension in the longitudinal direction of the horizontal plane. Referring to the figure, the “longitudinal” direction may be parallel to the indicated “Y” axis, perpendicular to the indicated “X” axis, or perpendicular to the indicated “Z” axis.

[0024] In this specification, the term “perpendicular” means and includes the direction perpendicular to the primary surface of the substrate on which the referenced material or structure lies. The “height” of each material or structure may be defined as a dimension in the vertical plane. Referring to the figure, the “perpendicular” direction may be parallel to the indicated “Z” axis, perpendicular to the indicated “X” axis, or perpendicular to the indicated “Y” axis.

[0025] In this specification, the term “width” means and includes the dimension of the material or structure in question along the indicated “X” axis in the horizontal plane (for example, at a certain altitude, if identified), defining the maximum distance along such “X” axis in the horizontal plane.

[0026] In this specification, the term “length” means and includes the dimension along the indicated “Y” axis in the horizontal plane (for example, at a certain altitude, where identified), defining the maximum distance along such “Y” axis in the horizontal plane of the material or structure in question.

[0027] In this specification, the terms “thickness” or “thinness” are spatially relative terms meaning and including the dimension in a straight line perpendicular to the nearest surface of a directly adjacent material or structure that is otherwise distinguishable from a material or structure of a different composition or whose thickness, thinness, or height is being discussed.

[0028] In this specification, the term “between” is a spatially relative term used to describe the relative placement of one material or structure to at least two other materials or structures. The term “between” may encompass both the placement of one material or structure directly adjacent to other materials or structures and the placement of one material or structure indirectly adjacent to other materials or structures.

[0029] In this specification, the term “proximity” is a spatially relative term used to describe the arrangement of one material or structure that is close to another material or structure. The term “proximity” includes arrangements that are indirectly adjacent, directly adjacent, and internal to each other.

[0030] In this specification, the term “neighboring” is a spatially relative term that, when referring to a material or structure, means and refers to the nearest material or structure adjacent to the identified composition or property. Materials or structures of other compositions or properties other than the identified composition or property may be located between one material or structure and its “neighboring” material or structure of the identified composition or property. For example, a “neighboring” material X structure of material Y is the first material X structure of a multi-material X structure that is closest to a particular structure of material Y. A “neighboring” material or structure may be directly or indirectly adjacent to a structure or material of the identified composition or property.

[0031] In this specification, the term “consistent” is a relative term meaning and including the parameters, properties, or conditions of two such structures, materials, features, or parts that are equivalent, substantially equivalent, or nearly equivalent, at least with respect to the respective arrangements of such structures, materials, features, or parts, when referring to the parameters, properties, or conditions of one such structure, material, feature, or part in comparison to the parameters, properties, or conditions of another such structure, material, feature, feature, or part of the same aforementioned structure, material, or feature. For example, two structures having “consistent” thicknesses may each define the same, substantially the same, or nearly the same thickness in the X-lateral distance from the feature, even though the two structures are at different elevations along the feature.

[0032] In this specification, the terms “about” and “approximately” include, when used in reference to a numerical value of a particular parameter, the numerical value and the degree of dispersion from the numerical value that would be understood by those skilled in the art to be within the tolerance of the particular parameter. For example, “about” or “approximately” when referring to a numerical value may include additional numerical values ​​within a range of 90.0 percent to 110.0 percent of the numerical value, for example, within a range of 95.0 percent to 105.0 percent of the numerical value, within a range of 97.5 percent to 102.5 percent of the numerical value, within a range of 99.0 percent to 101.0 percent of the numerical value, within a range of 99.5 percent to 100.5 percent of the numerical value, or within a range of 99.9 percent to 100.1 percent of the numerical value.

[0033] In this specification, the term “substantially” means, and includes, a parameter, property, or condition that is equivalent to or within a degree of dispersion from a given value such that a given value is acceptablely satisfied, for example, within acceptable manufacturing tolerances, as a person skilled in the art would understand. In examples, depending on the specific parameter, property, or condition that is substantially satisfied, the parameter, property, or condition may be “substantially” a given value if the value is satisfied at least 90.0 percent, at least 95.0 percent, at least 99.0 percent, or even at least 99.9 percent.

[0034] In this specification, the terms “above” or “overlapping” are spatially relative terms that, when referring to an element as something that is “above” or “overlapping” another element, mean and include elements that are directly on top of the other element, adjacent to the other element (e.g., adjacent horizontally, horizontally, vertically, or perpendicularly), below the other element, or directly touching the other element. It also includes elements that are indirectly on top of the other element, adjacent to the other element (e.g., adjacent horizontally, horizontally, vertically, or perpendicularly), below the other element, or near the other element, with the other elements existing between them. On the other hand, when an element is referred to as something that is “directly above” or “directly adjacent” another element, there is no intervening element.

[0035] In this specification, other spatially relative terms, such as “lower,” “bottom,” “up,” “above,” and “top,” may be used to simplify the description of the relationship of one element or feature to another element or feature, as shown in the figures. Unless otherwise specified, any spatially relative terms used in this disclosure are intended to encompass different orientations of the material in addition to the orientations depicted in the figures. For example, if the material in the figures is inverted, the element described as “lower,” “below,” or “above the bottom” of another element or feature will then be oriented “up,” or “top” of the other element or feature. Thus, the term “lower” may encompass both up and down orientations, depending on the context in which the term is used, as will be obvious to those skilled in the art. The material may be oriented in other ways (e.g., rotated 90 degrees, inverted), and the spatially relative descriptive terms used herein shall be interpreted accordingly.

[0036] In this specification, the terms “level” and “height” are spatially relative terms used to describe the relationship of one material or feature to another material or feature as shown in the figures, using the lowest illustrated surface of a structure containing material or feature as the reference point. In this specification, “level” and “height” are defined, respectively, by the primary surface of the substrate on which the structure (containing material or feature) is formed, or by a horizontal plane parallel to the foundation structure. When used with reference to the drawings, “lower level” and “lower height” are closest to the lowest illustrated surface of each structure, while “higher level” and “higher height” are further away from the lowest illustrated surface of each structure.

[0037] In this specification, the term “depth” is a spatially relative term used to describe the relationship of one material or feature to another material or feature as shown in the drawings, using the highest illustrated surface of the structure containing the material or feature as the reference point. When used in reference to drawings, “depth” is defined by a horizontal plane parallel to the highest illustrated surface of the structure containing the material or feature.

[0038] Unless otherwise specified, any spatially relative terms used in this disclosure are intended to encompass different orientations of the material in addition to the orientations depicted in the drawings. For example, the material in the drawings may be inverted, rotated, etc., with the “upper” level and elevation then indicated near the bottom of the page, the “lower” level and elevation then indicated near the top of the page, and the maximum “depth” extending upwards by the maximum vertical distance.

[0039] In this specification, “compose,” “include,” “have,” and their grammatical synonyms are inclusive, unrestrictive terms that do not exclude additional, unenumerated elements or method steps. These terms also include the more restrictive terms “composed of” and “essentially composed of” and their grammatical synonyms. Thus, a structure described as “composes,” “includes,” and / or “has” a material may, in some embodiments, also be a structure that includes additional material, and / or, in some embodiments, a structure that does not include other material. Similarly, a material (e.g., composition) described as “composes,” “includes,” and / or “has” a species may, in some embodiments, also be a material that includes additional species, and / or, in some embodiments, a material that does not include other species.

[0040] In this specification, “get, or may” with respect to materials, structures, features, or method behaviors indicates that such is intended for use in embodiments of the present disclosure, and such terminology is used in preference to the more restrictive term “is” to avoid any implication that other compatible materials, structures, features, and methods that can be used in conjunction with it should be excluded or must be excluded.

[0041] In this specification, "and / or" means any and all combinations of one or more of the items described relating to the subject matter.

[0042] In this specification, the singular forms "a, an" and "the" are intended to include the plural forms as well, unless otherwise clearly indicated by the context.

[0043] In this specification, the "(s)" at the end of a term means and includes the singular and / or plural forms of the term unless the context clearly indicates otherwise.

[0044] In this specification, the terms “configured” and “configuration” mean and refer to the size, shape, material composition, orientation, and arrangement of a referenced material, structure, assembly, or device in such a manner as to facilitate the referenced operation or properties of that material, structure, assembly, or device.

[0045] The illustrations presented herein are not intended to be actual views of any particular material, structure, substructure, region, subregion, device, system, or stage of manufacture, but are merely idealized representations used to illustrate embodiments of the present disclosure.

[0046] Embodiments are described herein with reference to schematic cross-sectional illustrations. Therefore, variations in the resulting shape from those depicted, for example, due to manufacturing techniques and / or tolerances, are to be expected. Accordingly, embodiments described herein should not be construed as being limited to specific shapes or structures as illustrated, but may include deviations in shape due to, for example, manufacturing techniques. For example, a structure illustrated or described as box-shaped may have rough and / or non-linear features. Furthermore, illustrated acute angles may be rounded, vertically illustrated surfaces and features may be non-vertical, curved, and / or arched, and / or a structure illustrated with a consistent cross-sectional width and / or length over the height of the structure may taper in cross-sectional width and / or length. Therefore, the materials, features, and structures shown in the figures are schematic in nature, and their shapes are not intended to represent the exact shape of the materials, features, or structures and do not limit the scope of these claims.

[0047] The following description provides specific details, such as material types and processing conditions, in order to provide a complete description of the embodiments of the disclosed apparatus (e.g., devices, systems) and methods. However, it will be understood by those skilled in the art that embodiments of the apparatus and methods may be carried out without these specific details. In fact, embodiments of the apparatus and methods may be carried out in conjunction with conventional semiconductor manufacturing techniques used in the industry.

[0048] The manufacturing processes described herein do not constitute a complete process flow for an apparatus (e.g., a device, a system) or its structure. The remainder of the process flow is known to those skilled in the art. Therefore, only the methods and structures necessary to understand embodiments of the apparatus (e.g., a device, a system) and method are described herein.

[0049] Unless otherwise indicated in the context, the materials described herein may be formed by any suitable technique, including but not limited to spin coating, blanket coating, chemical vapor stacking ("CVD (chemical vapor deposition)"), atomic layer stacking ("ALD (atomic layer deposition)"), plasma-enhanced ALD, physical vapor stacking ("PVD (physical vapor deposition)") (e.g., sputtering), or epitaxial growth. Depending on the specific material to be formed, a technique for precipitation or growth of the material may be selected by those skilled in the art.

[0050] Unless otherwise indicated in the context, the removal of materials described herein may be achieved by any suitable technique, including but not limited to etching (e.g., dry etching, wet etching, vapor etching), ion milling, polishing planarization, or other known methods.

[0051] Referring to the drawings, similar numerals refer to similar components throughout. The drawings are not necessarily drawn to a consistent scale.

[0052] Referring to Figure 1, the illustration shows a microelectronic device structure 100 comprising a stack 102 (which may be otherwise referred to as a “stack structure” or “layered stack”) of vertically alternating (e.g., vertically sandwiched) insulating structures 104 and conductive structures 106 arranged in layer 108. Each layer 108 may contain at least one insulating structure 104 and at least one conductive structure 106. In some embodiments, each layer 108 contains only one insulating structure 104 and only one conductive structure 106.

[0053] Figure 1 shows approximately 60 layers 108 (e.g., 60 conductive structures 106) in a stack 102, but the disclosure is not so limiting. For example, a microelectronic device structure according to embodiments of the disclosure may include a different number of layers 108 (e.g., and conductive structures 106) in a stack 102. In some embodiments, the stack 102 includes 128 layers 108 (and conductive structures 106). The number (e.g., quantity) of layers 108—and therefore conductive structures 106—in the stack 102 may be in the range of 32 to 300 or more.

[0054] The conductive structure 106 may be formed of and include (for example, each of) one or more conductive materials, for example, one or more of the following: at least one metal (for example, one or more of tungsten, titanium, nickel, platinum, rhodium, ruthenium, iridium, aluminum, copper, molybdenum, silver, gold), at least one alloy (for example, an alloy of one or more of the aforementioned metals), or at least one metal-containing material including one or more of the aforementioned metals (for example, metal nitrides, metal silicides, metal carbides, metal oxides, for example, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), iridium oxide (IrO2). x ), ruthenium oxide (RuO x), a material comprising one or more of the alloys thereof, at least one conductively doped semiconductor material (e.g., conductively doped silicon, conductively doped germanium, conductively doped silicon germanium), polysilicon, and at least one other material exhibiting electrical conductivity. In some embodiments, the conductive structure 106 comprises at least one of the aforementioned conductive materials, along with the addition of at least one of the aforementioned conductive materials formed as a liner. Some or all of the conductive structures 106 may have the same (e.g., consistent) or different thicknesses (e.g., height) to one another.

[0055] The insulating structure 104 is formed of and may include (for example, each is formed of and includes) at least one insulating material, for example, a dielectric oxide material (for example, silicon dioxide). In this and other embodiments described herein, the insulating material of the insulating structure 104 may be substantially the same as or different from the other insulating materials of the microelectronic device structure 100. Some or all of the insulating structures 104 may have the same (for example, consistent) or different thicknesses (for example, height) to one another. In some embodiments, some of the insulating structures 104 (for example, the uppermost, lowest, and / or intermediate insulating structures 104) are relatively thicker than the other insulating structures 104 in the stack 102.

[0056] The stack 102 may be provided on or covering the base structure 110, for example, by being formed of or including one or more semiconductor materials (e.g., polycrystalline silicon (polysilicon)) doped with one or more P-type conductive chemical species (e.g., one or more of boron, aluminum, and gallium) or one or more N-type conductive chemical species (e.g., one or more of arsenic, phosphorus, and antimony), in order to provide source / drain regions for the microelectronic device structure 100.

[0057] In addition to the semiconductor material and / or source / drain region, the base structure 110 may include conductive regions for making electrical connections with other base materials or structures, such as other conductive structures of the device including the microelectronic device structure 100. In some such embodiments, a CMOS (complementary metal-oxide-semiconductor) electrical circuit configuration is included in the base structure 110 in a CMOS region below the source / drain region, and that CMOS region may be characterized as a so-called "CuA (CMOS under Array)" region.

[0058] A series of slits or other elongated structures may extend through the stack 102 to divide the stack 102 into a series of blocks 112 that extend laterally (for example, having a larger dimension in the "X" axis direction (e.g., width) than in the dimension in the "Y" axis direction (e.g., length)). For example, a pair of slits may be formed parallel to the "X" axis in Figure 1 to define the front and rear of block 112 of the microelectronic device structure 100 shown in Figure 1. Blocks adjacent to block 112 in the longitudinal front and / or rear of block 112 in Figure 1 may be constructed similarly to block 112 in Figure 1, so that the illustration in Figure 1 may also represent such adjacent blocks. Alternatively, such adjacent blocks may have a structure substantially mirrored to that of block 112 in Figure 1, with respect to the slits separating the blocks 112 from each other.

[0059] Other parts of the microelectronic device structure 100 (for example, parts positioned horizontally relative to the part shown in Figure 1) may include an array of struts (e.g., including channel material and memory material) extending through the stack 102 and into and / or within the base structure 110 (e.g., into and / or within the source / drain region). The struts may implement the organization of strings of memory cells in a memory device (e.g., a memory device comprising any of the microelectronic device structures described or illustrated herein). Conductive structures 106 of layer 108 may be coupled to memory cells implemented by the struts, or may form their control gates. For example, each conductive structure 106 may be coupled to individual memory cells of a particular string of memory cells (e.g., implemented by a particular strut).

[0060] To facilitate electrical communication to specific selected conductive structures 106 within the stack 102, conductive contact structures extend to (or extend from) and physically contact with the conductive structures 106 of layer 108. Each such conductive contact structure is positioned to physically contact one of the conductive structures 106 in step 114 (for example, a landing area provided by an exposed upper (e.g., horizontal) surface portion of one of the conductive structures 106). These conductive contact structures that physically contact in step 114 may be referred to herein as “step contacts 116”.

[0061] To provide step 114 of the conductive structure 106, the stack 102 is patterned (e.g., etched) to expose one or more upper (e.g., horizontal) surface portions of each conductive structure 106 at various levels. That is, layer 108 is selectively patterned to remove portions of layer 108 that would otherwise cover it, leaving at least one upper surface area of ​​the conductive structure 106 of the next lower layer 108 exposed. Each exposed area provides one of step 114 of the respective layer 108 (and conductive structure 106).

[0062] Since individual conductive structures 106 in the stack 102 may occupy different altitudes of the stack 102 (also referred herein to as different “layer altitudes”), steps 114 are formed at various altitudes of the conductive structures 106, and step contacts 116 extend downward to physically contact (e.g., “land on”) each step 114. The height of individual step contacts 116 may be adapted according to the depth (e.g., altitude) of each step 114. A step contact 116 extending to a step 114 at the highest altitude of the stack 102 may generally be shorter than a step contact 116 extending to a step 114 at the lowest altitude (and deepest point) of the stack 102. The microelectronic device structure 100 may include at least one step contact 116 for each step 114 and therefore at least one step contact 116 for each layer 108 in the stack 102 (for example, therefore each conductive structure 106) in each respective block 112.

[0063] The layers 108 of the stack 102 are patterned such that at least some of the layers 108 of the stack 102 (and therefore at least some of the conductive structures 106) provide multiple steps 114 or relatively wide and / or relatively long steps 114 for each of the landings of at least one of each step contact 116. The multiple step contacts 116 extend to each such layer 108 (and its conductive structure 106).

[0064] In some embodiments, the layer 108 connected to the multiple step contacts 116 (and having multiple steps 114 in some embodiments) may be the deepest (e.g., lowest) layer 108 of the stack 102, where the step contacts 116 have a relatively large vertical distance spread, and therefore a relatively large height and a higher aspect ratio compared to step contacts 116 that extend to higher-made steps 114. High-reliability manufacturing of such high-aspect-ratio step contacts 116 tends to be particularly difficult, as will be discussed further below. Therefore, if one such step contact 116 is manufactured irregularly in such a way that it results in a step contact 116 that does not physically contact each conductive structure 106, the other multiple step contacts 116 may still provide electrical communication to the conductive structure 106, for example, through a physical connection to the other multiple steps 114 of layer 108 (or to another relatively wide and / or relatively long part of the step 114 of layer 108).

[0065] Steps 114 can be grouped, for example, according to depth, in a staircase having a series of steps 114. For example, one series of steps 114 may be formed at a continuously increasing layer 108 (and conductive structure 106) depth (e.g., decreasing layer 108 height) to define a descending staircase 118 having a generally negative gradient. Elsewhere, another series of steps 114 may be formed at a continuously decreasing layer 108 (and conductive structure 106) depth (e.g., increasing layer 108 height) to define an ascending staircase 120 having a generally positive gradient. In some embodiments, the height difference between adjacent steps 114 of a staircase (e.g., one of the descending staircases 118, one of the ascending staircases 120) is an "ascendance" or "descent" of the height of one layer 108.

[0066] Stairs (for example, descending stairs 118 and ascending stairs 120) can be grouped in so-called “stadiums” 122 that can be arranged in a sequence across the width of a block 112 of the microelectronic device structure 100 (for example, a first stadium 124, a second stadium 126, a third stadium 128, a fourth stadium 130). The microelectronic device structure 100 may include a number of stadiums 122 within each block 112, which are necessary to include at least one step 114 for each layer 108 of the stack 102 (and each conductive structure 106).

[0067] Neighboring stadiums 122 can be separated from each other by so-called "tops" 132 of stack 102. Tops 132 can be formed by areas of stack 102 where layer 108 has not been patterned. Thus, tops 132 can increase the overall height of stack 102.

[0068] Another unpatterned portion of stack 102 forms a so-called “bridge” 134 that widens block 112. The bridge 134 may face one of the boundaries of the slit that defines block 112. Through the bridge 134, the end portions of a given conductive structure 106 of each layer 108 are part of a continuous, single conductive structure 106 at that layer 108 height. Thus, the multiple steps 114 provided by a given layer 108 (e.g., its given conductive structure 106) maintain electrical communication with one another, regardless of where along block 112 (e.g., horizontally or vertically) each multiple step 114 is provided for its layer 108 (e.g., its conductive structure 106).

[0069] In some embodiments, for example, in the microelectronic device structure 100 of Figure 1, a layer 108 including multiple steps 114 and associated with a multiple step contact 116 provides multiple steps 114 within a staircase of a single stadium 122, which is referred to herein as a “layer-by-layer multiple step stadium” 136. At least one layer-by-layer multiple step stadium 136 within each individual block 112 of the stack 102 may be the deepest stadium 122 of the stack 102. Thus, in a layer-by-layer multiple step stadium 136, each of at least some of the “staircase layers” 138 of the stadium 122 includes multiple steps 114.

[0070] In this specification, “staircase layer” means and refers to layer 108 of stack 102 that defines at least one step 114 (for example, at least one landing area of ​​the conductive structure 106 of layer 108).

[0071] In a multi-step stadium 136 with multiple steps per layer, to provide multiple steps 114 for each stepped layer 138, the layers 108 can be patterned to define a stadium outline with multiple steps, where at least a portion of each is defined at the same altitude as the others (e.g., the same layer 108 level of stack 102). Thus, each stepped layer 138 providing multiple steps includes one step 114 in one step and one or more additional steps 114 in one or more of the additional steps of the multi-step stadium 136 with multiple steps per layer.

[0072] The portion of Figure 1 indicated by box 140 shows the staircase outline of the multi-step stadium 136. Alternative staircase outlines of the multi-step stadium 136 are shown in Figures 2A to 2D, respectively, any one of which may supersede the one shown in any or both boxes 140 of Figure 1 (or any other box 140 of the microelectronic device structure shown in the figure).

[0073] In some embodiments, one or more pairs of opposing stairs provide a multi-step staircase, providing multi-steps 114 for each stepped layer 138 of a multi-step stadium 136, for example, a descending staircase 118 and an ascending staircase 120 shown in box 140 in Figures 1, 2A, and 2B. As shown in these figures, the shape and structure of the descending staircase 118 may substantially reflect the shape and structure of the ascending staircase 120. Thus, each stepped layer 138 includes one step 114 in the descending staircase 118 and one step 114 in the ascending staircase 120.

[0074] With respect to box 140 in Figure 1, the descending stairs 118 go down and the ascending stairs 120 go up from there, and the stair landing 142 may be exposed through an opening in the lowest conductive structure 106 of the stepped layer 138 of the multi-step stadium 136 for each layer, and provided by one of the upper surfaces of the insulating structure 104. Thus, the multi-steps 114 of the lowest stepped layer 138 of the multi-step stadium 136 for each layer may extend to the left and right sides of the stair landing 142.

[0075] With respect to box 140 in Figure 2A, in some embodiments, each of the lowest stepped layers 138 of the layer-by-layer multi-step stadium 136 may be an unpatterned conductive structure 106 such that the lowest step 114 of each opposite staircase (e.g., an ascending staircase 120, a descending staircase 118) is shared, rather than multiple separate steps 114 as in the box 140 area of ​​Figure 1. This single lowest step 202 provides the lowest step 114 of the descending staircase 118 and the lowest step 114 of the ascending staircase 120, and the multi-step contact 116 extends down to this single lowest step 114. The lowest step 114 may be relatively wider than the individual steps 114 at the upper levels 108 above the descending stairs 118 and the ascending stairs 120.

[0076] In Figures 1 and 2A, the box 140 provides a "V" shaped stair outline that traverses the width of the layer-by-layer multi-step stadium 136, showing the descending staircase 118 of each layer-by-layer multi-step stadium 136 as descending toward the ascending staircase 120 of that layer-by-layer multi-step stadium 136. In other embodiments, such as the embodiment shown in Figure 2B, the ascending staircase 120 provides an inverted "V" shaped stair outline that ascends toward the descending staircase 118. A single highest step 204 (e.g., one single exposed upper surface portion of the conductive structure 106) can provide both the highest step 114 of the ascending staircase 120 and the highest step 114 of the descending staircase 118. The multi-step contact 116 may extend to this single highest step 114, which may be relatively wider than the individual steps 114 of the ascending staircase 120 and the descending staircase 118 at lower layer 108 heights.

[0077] The box 140 in Figures 1, 2A, and 2B shows a multi-staircase configured as an opposite pair of stairs (e.g., a descending staircase 118 and an ascending staircase 120) having substantially laterally reflected structures and outlines, but in other embodiments, the multi-staircase of a multi-step stadium 136 per layer may share substantially the same structure without lateral reflection. Referring to Figure 2C, for example, the multi-step stadium 136 per layer may include multiple ascending staircases 120, each having substantially the same elevation outline. In another embodiment, referring to Figure 2D, the multi-step stadium 136 per layer may include multiple descending staircases 118, each having substantially the same elevation outline.

[0078] Therefore, at least one layer-by-layer multi-step stadium 136 of the microelectronic device structure 100 is configured with a staircase shape that provides multi-steps 114 for at least some of the stepped layers 138, each having multi-steps formed through the same layer 108 elevation to one another. At least one step contact 116 extends to each step 114 of the multi-steps 114 in the layer-by-layer multi-step stadium 136. Thus, if one step contact 116 accidentally fails to provide electrical communication to each of its steps 114 and stepped layers 138 (e.g., due to a manufacturing error or other reason), at least one other step contact 116 is associated with the same stepped layer 138 to provide electrical communication (e.g., word lines) to the conductive structure 106 of the stepped layer 138 via the same or additional steps 114.

[0079] Referring to Figure 1, at least one stadium 122 in block 112 is configured as a multi-step stadium 136 with layers, while one or more other stadiums 122 in block 112 may consist only of single steps 114 with stepped layers 138. Such stadiums 122 may be referred herein as “single-step stadiums with layers” 144.

[0080] To provide a single step 114 for each stepped layer 138 in a layer-by-layer single-step stadium 144, the layer-by-layer single-step stadium 144 may include one or more steps that together provide a step 114 at different layer heights 108. The portion of Figure 1 indicated by box 146 shows the staircase outline of the layer-by-layer single-step stadium 144. Alternative staircase outlines of the layer-by-layer single-step stadium 144 are shown in Figures 3A to 3E, any one of which may supersede the one shown in any or both of the boxes 146 in Figure 1 (or any other box 146 of the microelectronic device structure shown in the figure).

[0081] In some embodiments, one or more pairs of opposite and vertical offset stairs may provide a multi-staircase, for example, a descending staircase 118 and an ascending staircase 120 shown in box 140 of any of Figures 1, 3A, 3B, and 3C, which together define a single step 114 for each stepped layer 138 of a stadium 144 of single steps per layer. Thus, one staircase is formed at a layer 108 height above the layer 108 height in which at least one other staircase is formed. The offset 148 of the multi-layer 108 vertically separates the final step 114 of one staircase from the starting step 114 of the opposite staircase. The offset 148 may be at least the number of layers 108 in which the lower of the pair of opposite, vertical offset stairs is formed (for example, the number of stepped layers 138).

[0082] In some embodiments—such as those shown in box 146 in Figures 1 and 3A—the descending staircase 118 descends toward the offset 148 and the ascending staircase 120, and the ascending staircase 120 ascends away from the offset 148 and the descending staircase 118. Thus, the opposite, vertical offset staircase is generally angled toward the center of the single-step stadium 144 per layer. In other embodiments—such as those shown in box 146 in Figures 3B and 3C—the ascending staircase 120 ascends toward the offset 148 and the descending staircase 118, and the descending staircase 118 descends away from the offset 148 and the ascending staircase 120. Thus, the opposite, vertical offset staircase is generally angled away from the center of the single-step stadium 144 per layer.

[0083] In some embodiments—such as those shown in box 146 in Figures 1 and 3C—the descending stairs 118 are formed at a height of 108 layers above the layer on which the ascending stairs 120 are formed. In other embodiments—such as those shown in box 146 in Figures 3A and 3B—the ascending stairs 120 are formed at a height of 108 layers above the layer on which the descending stairs 118 are formed.

[0084] In some embodiments—such as those shown in box 146 in Figure 1—the final (e.g., lowest) step 114 of a descending staircase 118 is vertically spaced above the starting (e.g., lowest) step 114 of an ascending staircase 120 by an offset 148. In some embodiments—such as those shown in box 146 in Figure 3A—the final (e.g., lowest) step 114 of a descending staircase 118 is vertically spaced below the starting (e.g., lowest) step 114 of an ascending staircase 120 by an offset 148. In some embodiments—such as those shown in box 146 in Figure 3B—the final (e.g., highest) step 114 of an ascending staircase 120 is vertically spaced above the starting (e.g., highest) step 114 of a descending staircase 118 by an offset 148. In some embodiments—such as those shown in box 146 of Figure 3C—the final (e.g., highest) step 114 of an ascending staircase 120 is vertically spaced below the starting (e.g., highest) step 114 of a descending staircase 118 by an offset 148.

[0085] Box 146 in Figures 1 and 3A to 3C shows a multi-staircase configured as an opposite, vertically offset pair having a descending staircase 118 and an ascending staircase 120. In other embodiments, however, a single staircase may extend through all the staircase heights 108 of the stepped layers 138 to provide a single step 114 for each stepped layer 138 in a single-step-per-layer stadium 144. For example, referring to Figure 3D, a single-step-per-layer stadium 144 may include a single ascending staircase 120. In another embodiment, referring to Figure 3E, a single-step-per-layer stadium 144 may include a single descending staircase 118.

[0086] Therefore, at least one of the single-step stadiums 144 of the microelectronic device structure 100 is configured to have a staircase shape that provides a single step 114 for each stepped layer 138, for example, having at least one staircase that provides a step 114 at different layer heights 108 of the single-step stadium 144. A single step contact 116 extends to each of the steps 114.

[0087] Continuing to refer to Figure 1, in embodiments in which the microelectronic device structure 100 includes one or more layer-by-layer single-step stadiums 144, for example, if the height of a step contact 116 is relatively shorter than the height of a step contact 116 that extends to a relatively lower altitude of the stack 102, then the layer-by-layer single-step stadiums 144 may be formed at a relatively higher altitude of the stack 102. Relatively short step contacts 116 may experience relatively fewer manufacturing challenges compared to relatively tall step contacts 116, and thus may be less likely to experience manufacturing errors that would cause telecommunications failures in each conductive structure 106 (e.g., word lines) at the upper altitude of the stack 102.

[0088] The stadiums 122 of the microelectronic device structure 100 may be arranged continuously across the width of the block 112, and the stepped outline of the stadiums 122 may be formed to provide at least one step 114 for each layer 108 of the stack 102 (for example, each conductive structure 106). For example, in some embodiments shown in Figure 1, the depth of the stadiums 122 may increase with increasing lateral distance across the block 112. Thus, the step 114 of the first stadium 124 may be at a layer 108 height above the step 114 of the fourth stadium 130, at a layer 108 height above the step 114 of the third stadium 128, at a layer 108 height above the step 114 of the second stadium 126, and so on. In other embodiments, the stadiums 122 may not be arranged with a depth that decreases or increases relative to its series of blocks 112. For example, one stadium 122 may be relatively deeper than a neighboring stadium 122, and / or one stadium 122 may be relatively shallower than a neighboring stadium 122.

[0089] In some embodiments, regardless of the order and sequence of depths of the various stadiums 122, one or more of the relatively deep stadiums 122 (e.g., the third stadium 128 and the fourth stadium 130 in Figure 1) may be configured as multi-step stadiums 136 per layer, while one or more of the relatively shallow stadiums 122 (e.g., the first stadium 124 and the second stadium 126 in Figure 1) may be configured as single-step stadiums 144 per layer. The stair outlines of each multi-step stadium 136 per layer in block 112 may be the same or different from each other, and / or, if any, the stair outlines of each single-step stadium 144 per layer in block 112 may be the same or different from each other.

[0090] Figure 1 shows a series of four stadiums 122, but the disclosure is not limited thereto. A series of block stadiums 112 may include additional stadiums 122, for example, in an intermediate area 150 or in an area laterally adjacent to any of the stadiums 122 shown in Figure 1. The additional stadiums 122 may be either a multi-step stadium 136 per layer (for example, having the staircase outline of any of the boxes 140 in Figures 1, 2A, 2B, 2C, and 2D or any other staircase outline configured for multi-step contacts 116 per layer of stepped 138) or a single-step stadium 144 per layer (for example, having the staircase outline of any of the boxes 146 in Figures 1, 3A, 3B, 3C, 3D, and 3E).

[0091] Therefore, disclosed is a microelectronic device. The microelectronic device includes a stack structure comprising a vertically alternating sequence of insulating and conductive structures arranged in layers. Each layer comprises at least one conductive structure and at least one insulating structure. The microelectronic device also includes stadiums within the stack structure. At least one of the stadiums comprises two steps having steps provided by a group of conductive structures. The step contacts extend to the steps of the two steps of at least one of the stadiums. Each conductive structure in the group of conductive structures has a plurality of step contacts that contact it at at least one of the steps of the two steps.

[0092] Referring to Figure 4, the illustrated structure is the microelectronic device structure 100 of Figure 1, and further shows a path 402 formed to electrically connect an additional conductive contact structure (referred herein to as “through-stack contacts” 404) to the step contact 116, which may be located within the horizontal area of ​​the top 132 of the stack 102. The through-stack contacts 404 may extend through the height of the stack 102 to the base structure 110 (for example, to or through the source / drain region within the base structure 110, for example, to additional paths or other conductive features below the stack 102).

[0093] For each stepped layer 138 of the single-step stadium 144, one path 402 may extend between one stack-through contact 404 and one step contact 116. Thus, one (e.g., single) path 402 may electrically connect one (e.g., single) stack-through contact 404, one (e.g., single) step contact 116, and one (e.g., single) step 114 to which the step contact 116 extends (and therefore, one conductive structure 106 providing step 114). Thus, one conductive structure 106 may have telecommunications shared with one stack-through contact 404 via a single (e.g., only one) telecommunications route (e.g., conductive path).

[0094] For each stepped layer 138 of the multi-step stadium 136, at least one path 402 extends between one stacked contact 404 and each of the multi-step contacts 116 that extend to the conductive structure 106 of the stepped layer 138 (for example, to the multi-step 114 of one conductive structure 106). Thus, one conductive structure 106 communicates with one stacked contact 404 through a multiple telecommunication route (for example, a multiple conductive path). In some embodiments, one or more junctions 406 facilitate telecommunication between the multi-step contacts 116 and the single stacked contact 404. For example, one path 402 may extend between one of the multiple step contacts 116 and the junction 406, one additional path 402 may extend between another of the multiple step contacts 116 and the junction 406, and one further path 402 may extend between the junction 406 and one of the stacked contacts 404. However, the disclosure is not limited to this arrangement, and the paths 402 connecting the multiple step contacts 116 to each of the single stacked contacts 404 may be configured in other ways.

[0095] Referring to Figure 5, the microelectronic device structure 100 of Figures 1 and 4 is illustrated, including a schematic diagram of the path 402 and the contact 404 through the stack of The physical, junction 404 structure through the stack may extend into and / or within the source / drain region of the foundation structure 110 (for example, as shown in Figure 4) through the height of the stack 102 and be formed and positioned within the horizontal area of ​​the apex 132, although the junction 404 through the stack is schematically represented by a rectangle above the apex 132.

[0096] In some embodiments, each stepped layer 138 provides a multiple step 114—at each layer 108 height of the stack 102—which corresponds to one of the multiple step contacts 116 communicating with a single contact 404 through the stack.

[0097] Referring further to Figure 5, one or more dielectric materials 502 may substantially fill openings (e.g., grooves) referred herein as “stadium openings” (e.g., “stadium grooves”), which vertically cover and are partially defined by the stadiums 122 (e.g., single-step stadiums 144, if any, and multi-step stadiums 136, per layer) and electrically insulate the step contacts 116 from one another. The step contacts 116 extend vertically through the dielectric material 502 of the filled stadium openings to the step 114 of the stadium 122. For simplicity of illustration, Figures 1 to 4 do not show the dielectric material 502. The dielectric material 502 may be formed of any one or more of the insulating materials described herein, and may include them.

[0098] Referring to Figure 6, the structure shown is that of Figure 5, where one of the step contacts 116—the so-called "poorly formed step contact" 604—is irregularly manufactured (for example, due to a manufacturing error such as an incomplete arrangement of the contact opening in which the step contact 116 is formed, as will be discussed further below), leaving a gap 602 between the base of the poorly formed step contact 604 and the step 114 that, if manufactured correctly, was intended to extend to that point.

[0099] If a poorly formed step contact 604 is formed for one of the single-step stadiums 144 per layer (or otherwise directed to a step 114 of a single-step stepped layer 138), the failure of the poorly formed step contact 604 to physically contact its associated step 114 will suppress electrical communication between the conductive structure 106 providing its step 114 and its associated, stack-through contact 404. However, for a multi-step stadium 136 per layer, the inclusion of multi-step contacts 116 per stepped layer 138 facilitates electrical communication to the conductive structure 106 despite the poorly formed step contact 604. That is, if one of the multi-step contacts 116 associated with a particular stepped layer 138 (for example, the lowest stepped layer 138 of a multi-step stadium 136 per layer) fails to make physical contact with the conductive structure 106 of the stepped layer 138 and is accidentally formed as a poorly formed step contact 604, then one or more of the other multi-step contacts 116 that are precisely manufactured and associated with that particular stepped layer 138 (for example, the lowest stepped layer 138) will still provide electrical communication to the conductive structure 106.

[0100] The inclusion of multiple step contacts 116 (for example, and, in some embodiments, multiple step 114) per step layer 138 of the layer-by-layer multiple step stadium 136 can significantly reduce the likelihood of electrical communication failure to a particular conductive structure 106 in the layer-by-layer multiple step stadium 136. That is, for each multiple step contact 116 (per conductive structure 106) per step layer 138, the so-called “failure rate” (hereinafter “TFR”) of the step layer 138—meaning the likelihood of being unable to electrically communicate with a particular step layer 138 (conductive structure 106)—is statistically equal to the likelihood of failure of an individual step contact 116 (hereinafter “IRF”) raised to the power of the number of multiple step contacts 116 (hereinafter “n”) per step layer 138. That is, TFR = (IRF)^n.

[0101] For example, in embodiments such as that shown in Figure 6, where two step contacts 116 (i.e., n=2) are associated with a particular stepwise layer 138 (and therefore a particular conductive structure 106), if the probability of one step contact 116 experiencing a manufacturing failure is, for example, 10% (i.e., IRF=0.10), then the layer failure rate (TFR) (for example, the probability of both stepwise step contacts 116 experiencing a failure as necessary to suppress electrical communication to the particular stepwise layer 138 (conductive structure 106)) is 1% (i.e., TFR=(0.10)^2=0.01=1%). In another embodiment, which includes three steps 114 for each stepped layer 138 (and conductive structure 106) (i.e., n=3), an individual failure rate of 10% (i.e., IFR=0.10) is equal to a layer (conductive structure 106) failure rate (TFR) of 0.1% (i.e., TFR=(0.10)^3=0.001=0.1%).

[0102] When considering the probability of failure of any one stepwise step 138 in a stepwise multi-step stadium 136, this “stadium failure rate” (hereinafter “SFR”) can be further significantly improved by the inclusion of multi-step contacts 116 (and, in some embodiments, multi-steps 114) for each stepwise step 138 in the stepwise multi-step stadium 136. Statistically, SFR is equal to TFR multiplied by the number of stepwise steps 138 in the stepwise multi-step stadium 136 (hereinafter “m”), i.e., SFR = TFR × m = ((IFR)^n) × m.

[0103] For example, in embodiments such as that shown in Figure 6, which include five stepped layers 138 (conductive structures 106) (i.e., m=5), each having two steps 114 and associated with two step contacts 116 (i.e., n=2), if the probability of one step contact 116 experiencing a manufacturing failure is, for example, 10% (i.e., IFR=0.10), then the stadium failure rate (SFR) will be 5% (i.e., SFR=((0.1)^2)×5=(0.01)×5=0.05=5%). On the other hand, the SFR of a single-step layer stadium 144 is statistically equal to IFR×m. Therefore, if a single-step stadium 144 per layer includes five stepped layers 138 (conductive structures 106) (i.e., m=5), an individual failure rate of 10% (e.g., IFR=0.10) is equal to a 50% SFR (i.e., SFR=0.10×5=0.50=50%), which is a significantly larger stadium failure rate than the 5% SFR of the multi-step stadium 136 example per layer.

[0104] As shown in Figures 1 and 4 through 6, a multi-step contact 116 associated with only one conductive structure 106 (e.g., providing a multi-step 114) of the stepped layers 138 may also be a step contact 116 located in one common horizontal area of ​​the stadium 122 (e.g., a common, layer-by-layer multi-step stadium 136). Each group (e.g., a pair) of multi-step contacts 116 may extend to a different step 114 provided by the same stepped layers 138, or to the same step provided by the stepped layers 138 (e.g., a single lowest step 202 in Figure 2A, a single highest step 204 in Figure 2B).

[0105] The microelectronic device structure 100 in Figures 1 and 4 to 6 includes a stepped layer 138 that provides (and is associated with) multiple steps 114 of at least several stepped layers 138 (e.g., a multi-step stadium 136 per layer) of a single stadium 122, but in other embodiments, the multiple steps 114 provided by at least one stepped layer 138 may be steps 114 of different stadiums 122. Furthermore, the step contacts 116 associated with one stepped layer 138 may be step contacts 116 in the horizontal area of ​​different stadiums 122.

[0106] For example, referring to Figure 7, the microelectronic device structure 700 includes at least one stepped layer 138 (at least one conductive structure 106) having multiple steps 114 defined in each of the double stadiums 702 of a group (e.g., a pair), for example, adjacent, relatively deep stadiums 122. Each of the double stadiums 702 of each group (e.g., a pair) may have a stepped outline having steps 114 provided through the same layer 108 height as each other of the double stadiums 702 of the group, so as to provide one step 114 of each stepped layer 138 in one of the double stadiums 702 and multiple steps 114 of each stepped layer 138 in another of the double stadiums 702. Thus, each of the double stadiums 702 of each group (e.g., a pair) may be at the same (e.g., common) depth in the stack 102.

[0107] Step contacts 116 extend to step 114 in a one-to-one relationship, and for example, a path 402 (and, in some embodiments, a junction 406) can electrically connect a single step contact 116—extending to one step 114 of one stepped layer 138 of the double stadium 702—to multiple step contacts 116—extending to multiple steps 114 of multiple stepped layers 138 of the double stadium 702—and to each of the contacts 404 through the stack in the adjacent apex 132.

[0108] Figure 7 shows a microelectronic device structure 700 having a single pair of double stadiums 702 that together provide two steps 114 for each stepped layer 138 at the lowest 10 layers 108 of the stack 102, but in other embodiments, one or more additional double stadiums 702 may be formed with steps 114 (and steps) at the same layer 108 height to provide three or more double stadiums 702 that together provide three or more multiple steps 114 for each stepped layer 138. Thus, three or more step contacts 116 may extend to each stepped layer 138 (and conductive structure 106), each located within a horizontal area of ​​one of the different double stadiums 702 of the group of multiple double stadiums 702.

[0109] A double stadium 702 of one or more additional groups (e.g., pairs) having a stepped outline at the height of the additional group of layers 108 may provide an additional group of multiple steps 114 for each stepped layer 138 at the next 10 layers 108 height of the stack 102 (e.g., in the intermediate region 150). The multiple step contacts 116 of the additional groups (e.g., pairs) may extend to each stepped layer 138 at the height of the additional layer 108, respectively.

[0110] The staircase outline of each double stadium 702 may be any one of the aforementioned staircase outlines of the single-step stadium 144 per layer, shown in box 146 in Figures 1, 3A, 3B, 3C, 3D, and 3E. As long as the layer 108 height of one step 114 of the double stadium 702 is the same layer 108 height of another step 114 of the double stadium 702, the staircase outlines of each double stadium 702 in a related group (e.g., a pair) may have the same configuration as one another, or they may have different configurations (e.g., they may be mirrored or mirrored but not the same) as shown in Figure 7.

[0111] Figure 7 shows a specific group (e.g., a pair) of double stadiums 702, where the stadiums are directly adjacent (e.g., the third stadium 128 and the fourth stadium 130 of block 112 (Figure 1)), but in other embodiments, one or more of the stadiums 122 may be sandwiched between the double stadiums 702 of a specific group (e.g., a pair). Such sandwiched stadiums 122 (or stadiums 122) may be one or more single-step, layer-by-layer stadiums 144, one or more multi-step, layer-by-layer stadiums 136 (Figure 1), or one or more double stadiums 702 of different groups (e.g., pairs) of double stadiums 702.

[0112] Therefore, the microelectronic device structure 700 provides at least some conductive structures 106- relating to multiple steps 114- and, thus multiple step contacts 116- in at least some stepped layers 138, where at least one of the multiple steps 114 lies in a different stadium 122 from at least one other of the multiple steps 114, and at least one of the multiple step contacts 116 lies in a different stadium 122 from the stadium 122 to which at least one other of the multiple step contacts 116 lies.

[0113] In any horizontal stadium area of ​​the multiple double stadium 702, regardless of how the individual step contacts 116 of a group (e.g., a pair) of multiple step contacts 116 are spread out, the grouped multiple step contacts 116 can share electrical communication to one of the common contacts 404 that pass through the stack, as schematically shown in Figure 7.

[0114] Referring to Figure 8, in some embodiments, the microelectronic device structure 800 may provide multiple steps 114 and multiple step contacts 116 for each of at least one stepped layer 138 (at least one conductive structure 106) by providing relatively wide and / or relatively long steps 114 for each conductive structure 106 of the stepped layer 138. For example, at least one stepped layer 138 may include relatively wide and / or relatively long steps 114 compared to, for example, a single-step stadium 144 per layer, compared to a step 114 in a stadium 122 that does not provide multiple steps 114 per stepped layer 138. Relatively wide and / or relatively long steps 114 may effectively provide a surface area for multiple steps 114 in a single-step stadium 144 per layer. These relatively wide and / or relatively long steps 114 may each be at one of the different heights of the stepped layers 138 of the stadium 122, the stadium 122 may henceforth be referred to herein as a "stadium of multi-step contacts per layer" 802.

[0115] The stair outline of the multi-step stadium 802 per layer may be any one of the aforementioned stair outlines of the single-step stadium 144 per layer relating to box 146 in Figures 1, 3A, 3B, 3C, 3D, and 3E, but having relatively wider and / or relatively longer steps 114. Thus, for example, the stair outline of box 804 in Figure 8 is substantially equal to the stair outline of the single-step stadium 144 per layer shown in box 146 in Figure 1 (and in Figure 8), but having steps 114 that are relatively twice as wide. Thus, in any of the aforementioned multi-step stadiums 136 per layer, the stair outline shown in box 804 in Figure 8 may alternatively replace any of the aforementioned stair outlines of box 140.

[0116] The multi-step contacts 116 extend to at least several (e.g., each) of each multi-size step 114 in the stadium 802 of multi-step contacts layer by layer. The multi-step contacts 116 in each stepped layer 138 can be electrically connected to the same (e.g., common) of the contacts 404 that have passed through the stack via the path 402 (and, in some embodiments, the junction 406).

[0117] The microelectronic device structure 800 in Figure 8 shows only a single-layer-by-layer multi-step contact stadium 802, providing relatively large steps 114 and multi-step contacts 116 for each step-like layer 138 at the deepest 10 layers 108 height of the stack 102. In other embodiments, however, multiple of the stadiums 122 within a given block 112 (Figure 1) may be configured as layer-by-layer multi-step contact stadiums 802, and these other layer-by-layer multi-step contact stadiums 802 may be formed in the stack 102 (for example, in the intermediate region 150) at other groups of layer 108 heights.

[0118] In some embodiments, all layers 108 and / or all stadiums 122 (Figure 1) of a given block 112 may be associated with multi-step contacts 116 (and, in some embodiments, multi-step 114). For example, referring to Figure 9, each stadium 122 (Figure 1) of block 112 may be configured as one of the layer-by-layer multi-step stadiums 136 having the staircase outline of box 140 in Figures 1, 3A, 3B, 3C, 3D, and 3E, or as a layer-by-layer multi-step contact stadium 802 (Figure 8) having the staircase outline of box 804 in Figure 8.

[0119] Therefore, disclosed is a microelectronic device. The microelectronic device includes a stack structure which includes conductive structures and insulating structures which are sandwiched perpendicularly and arranged in layers. A series of stadiums are located within the stack structure. At least one of the stadiums has a step which is at least partially defined by the conductive structures of the first group of layers. At least one other of the stadiums has an additional step which is at least partially defined by the conductive structures of the second group of layers. The first group of layers is at a lower elevation than the elevation of the second group of layers. Conductive contacts are located within the horizontal area of ​​the stadiums in the series of stadiums. Conductive contacts include pairs of conductive contacts and of which conductive contacts. Each pair of conductive contacts extends from each other to one of the different conductive structures of the first group of layers. The conductive contacts of those conductive contacts extend from each other to one of the different conductive structures of the second group of layers.

[0120] Referring to Figures 10 to 25, the illustrations show various stages forming a microelectronic device, including, for example, the microelectronic device structure 100 in any of Figures 1 and 4 to 6, the microelectronic device structure 700 in Figure 7, the microelectronic device structure 800 in Figure 8, and the microelectronic device structure 900 in Figure 9, where any stair outline shown in box 140 in any of the drawings may be used in place of any other stair outline shown in box 140 or box 804 in Figures 10 to 25, where any stair outline shown in box 146 in any of the drawings may be used in place of any other stair outline shown in box 146 in Figures 10 to 25.

[0121] The stack 1002 (or, as referred herein, the “stack structure” or “layered stack”) is formed on the base structure 110, including areas (for example, a first stadium area 1004, a second stadium area 1006, a third stadium area 1008, and a fourth stadium area 1010) in which a series of stadiums 122 (Figure 1) will be formed. In some embodiments, the stack 1002 is formed to include a vertically alternating sequence of insulating structures 104 and sacrificial structures 1012 arranged in layer 1014. The sacrificial structures 1012 may be formed at an altitude of the stack 1002 in which they will ultimately be replaced by or otherwise converted to conductive structures 106 (for example, Figure 1). In other embodiments, the stack 1002 may be formed to include conductive structures 106 instead of sacrificial structures 1012 without replacement or conversion, so that the stack 1002 may substantially have the material of the stack 102 in Figure 1. Therefore, the stack 1002 is formed to include an insulating structure 104 and "other structures," the other structures may be either a sacrificial structure 1012 or a conductive structure 106.

[0122] To form the stack 1002, the arrangement (e.g., precipitate) of insulating structures 104 may be alternating with the arrangement (e.g., precipitate) of other structures (e.g., sacrificial structures 1012). In some embodiments, the stack 1002 is formed in this stage to include a number of layers 1014 having sacrificial structures 1012 such that a layer 108 (Figure 1) having a conductive structure 106 (Figure 1) exists within the final structure (e.g., microelectronic device structure 100 in any of Figures 1 and 4 to 6, microelectronic device structure 700 in Figure 7, microelectronic device structure 800 in Figure 8, microelectronic device structure 900 in Figure 9).

[0123] One or more hard masks 1016 may also be included on (for example, higher up) the stack 1002 and used in subsequent material removal processes (e.g., etching, patterning).

[0124] Referring to Figure 11, the stack 1002 (and hard mask 1016) is patterned to define the initial stadium opening 1102 in the footprint (e.g., horizontal) areas (e.g., first stadium area 1004, second stadium area 1006, third stadium area 1008, fourth stadium area 1010) of the stadium 122 (Figure 1) that is to be formed. The areas of the stack 1002 at the top 132 (Figure 1) and bridge 134 (Figure 1) do not need to be etched so that they retain the full height of the stack 1002.

[0125] In this specification, the term “stadium opening” (for example, as in the initial stadium opening 1102) means an opening that includes, along the width of its foundation, at least one stepped outline such that the foundation of the stadium opening defines the exposed surface 1104 of the sacrificial structure 1012 at different layer heights 1014.

[0126] Forming the initial stadium opening 1102 defines a staircase outline having one or more staircases (e.g., an ascending staircase 120, a descending staircase 118). The specific staircase outline formed in each initial stadium opening 1102 may be adapted according to the staircase outline of the final stadium 122 to be formed (Figures 1, 7, 8, and 9). In the stadium area, if the final stadium 122 does not include vertical offsets—for example, having the staircase outline of box 140 in Figures 1, 2A, 2B, 2C, 2D, and 9, and the staircase outline of box 146 in Figures 3D and 3E—the staircase outline of the initial stadium opening 1102 may substantially be the staircase outline of the final stadium 122 to be formed (Figures 1, 7, 8, and 9). In the stadium area, if the final stadium 122 is to include a vertical offset 148 (Figure 1)—for example, the staircase outline of box 146 in Figures 1, 3A, 3B, 3C, 7, and 8, and box 804 in Figure 8—then the staircase outline partially defined by the initial stadium opening 1102 may correspond to the staircase outline of the final stadium 122 in this stage, but without the offset 148.

[0127] Each initial stadium opening 1102 may be formed in each stadium area (for example, the first stadium area 1004, the second stadium area 1006, the third stadium area 1008, and the fourth stadium area 1010) at substantially the same uppermost layer 1014 height of the stack 1002.

[0128] Forming each initial stadium opening 1102 may involve a series of material removal (e.g., etching) actions, thereby patterning the hard mask 1016 to define an opening of a first width, which is then etched to a first depth, e.g., a number of depths ("q") (e.g., 5) of layer 1014 that is to be included in the stair outline. The hard mask 1016 may then be trimmed to widen the opening to a second width, which is then patterned to a depth of q-1 (e.g., 4) of layer 1014. The hard mask 1016 may then be trimmed to widen the opening to a third width, which is then patterned to a depth of q-2 (e.g., 3) of layer 1014. This may be repeated until the outlines of the opposite and reflected ascending stair 120 and descending stair 118 are completed.

[0129] In embodiments where the initial stadium opening 1102 is formed to define the stair outline of box 140 in Figure 1, the initial hard mask 1016 patterning and etching action may be substantially equal in width to the width of the stair landing 142 (Figure 1), and this width may be etched to a depth that extends through the sacrificial structure 1012 that first defines the lowest exposed surface 1104 (of step 114 (Figure 1)) of the stairs (e.g., the ascending stairs 120 and the descending stairs 118). For example, the initial width may be etched to a depth of q+1 / 2 of the layer 1014 that is to be included in the stair outline.

[0130] The initial stadium openings 1102 may be formed substantially simultaneously for each stadium area (for example, the first stadium area 1004, the second stadium area 1006, the third stadium area 1008, and the fourth stadium area 1010). In other embodiments, any of the initial stadium openings 1102 may be formed sequentially, entirely, or partially.

[0131] In stadium areas (for example, a first stadium area 1004, a second stadium area 1006) that are to include a vertical offset 148 (Figure 1), such as a single-step stadium 144 with a stair outline of box 146 as shown in any of Figures 1, 3A, 3B, 3C, 7, and 8, a double stadium 702 with a stair outline of box 146 as shown in Figure 7, and a multi-step contact stadium 802 with a stair outline of box 804 as shown in Figure 8, half the width of each stadium may be etched to lower the stair outline by an offset distance of 148 of that half of the stadium. For example, with respect to Figure 12, the right halves of the first stadium area 1004 (Figure 11) and the second stadium area 1006 are etched to lower the ascending stair 120 into the stack 1002 by a vertical offset distance of 148. This vertical offset of half of the stadium defines an offset stadium opening 1202 in the first stadium area 1004 (Figure 11) and the second stadium area 1006.

[0132] In embodiments in which other stadiums 122 to be formed have a staircase outline that does not include a vertical offset 148, the staircase outline formed in the corresponding stadium areas (e.g., the third stadium area 1008, the fourth stadium area 1010) does not need to be altered during the offset (e.g., in the first stadium area 1004 (Figure 11) and the second stadium area 1006).

[0133] In embodiments where the staircase outline of the shallowest stadium 122 of block 112 (Figure 1) includes an offset 148, forming an offset stadium opening 1202 completes the organization of the first stadium 124 as a single-step stadium 144 per layer.

[0134] For stadium areas where the initial stadium opening 1102 and the offset stadium opening 1202 have not yet extended to their final layer height 1014 (e.g., depth) in the stack 1002, these openings may be widened in a series of material removal (e.g., etching) actions.

[0135] For example, the offset stadium opening 1202 in the second stadium area 1006 may be extended deeper into the stack 1002, while the initial stadium openings 1102 in the third stadium area 1008 and the fourth stadium area 1010 may also be extended deeper into the stack 1002. As shown in Figure 13, this expansion may complete the construction of the stadium 122 in the second stadium area 1006 (Figure 12) (for example, forming the second stadium 126), and form the widened partial stadium openings 1302 in the third stadium area 1008 and the fourth stadium area 1010, respectively. The expansion may substantially maintain the stepped outline already defined in an earlier stage, but the stepped outline may be extended to a lower height.

[0136] While widening at least some of the stadium openings (for example, to form the second stadium 126 and the widened partial stadium openings 1302 of the third stadium area 1008 and the fourth stadium area 1010), the already completed stadium 122 of the first stadium 124 may remain unchanged.

[0137] If the staircase outlines have not yet reached their final layer height (e.g., depth) in the stack 1002, the stadium opening expansion continues deeper and deeper into the stack 1002 of each stadium area. Thus, referring to Figure 14, the expansion may continue until the third stadium 128 reaches its final depth, at which stage the fourth stadium area 1010 includes a further widened partial stadium opening 1402. The further widened partial stadium opening 1402 within the fourth stadium area 1010 is then widened to complete the fourth stadium 130, as shown in Figure 15.

[0138] Following the expansion, the stadium 122 substantially defines its final stepped outline having stepped layers 1502 with exposed surfaces 1104 of sacrificial structures 1012, where the stadium 122 ultimately has steps 114 (Figure 1) that are partially defined by conductive structures 106 (Figure 1) of layer 108 (Figure 1).

[0139] Referring to Figure 16, the dielectric material 502 is formed (e.g., deposited) to substantially fill each stadium opening (e.g., stadium groove) above the completed stadium 122. The hard mask 1016 can be reformed above the stack 1002 and the dielectric material 502.

[0140] In embodiments in which stack 1002 is formed to include a sacrificial structure 1012 (rather than a conductive structure 106), the sacrificial structure 1012 may be substantially removed (e.g., excavated) and replaced with the conductive material of the conductive structure 106—or converted to conductive material—in order to form stack 102 having layers 108 of conductive structure 106 and insulating structure 104, as shown in Figure 17. This replacement process then includes step 114 in the stepped layer 138 of conductive structure 106.

[0141] Referring to Figure 18, the hard mask 1016 is patterned to define an opening 1802 in the area where the step contacts 116 (Figure 1) are to be formed. In some embodiments, the opening 1802 defined for step contacts 116 (Figure 1) up to relatively deep stadiums (e.g., third stadium 128 and fourth stadium 130) may be formed relatively wider than the opening 1802 defined for step contacts 116 (Figure 1) up to relatively shallow stadiums 122 (e.g., first stadium 124 and second stadium 126), so that the bottom dimension of the opening 1802 is sufficient to make physical contact with each of those steps 114 and manufacture the step contacts 116, even though the bottom dimension of the opening 1802 tapers, for example, through the stack 102.

[0142] In some embodiments, an opening 1802 formed in the hard mask 1016 is extended downward (e.g., etched) into the dielectric material 502 in a series of etching actions traversing a series of stadium areas (e.g., horizontal areas of stadium 122) until step 114 is reached. For example, the dielectric material 502 may be etched through the opening 1802 to form and complete a contact opening 1902 up to step 114 of the first stadium 124, as shown in Figure 19, while forming an initial partial opening 1904 that terminates in the dielectric material 502 before reaching each of those steps 114 of deeper stadiums 122 (e.g., second stadium 126, third stadium 128, fourth stadium 130). The complete contact opening 1902 exposes a portion of step 114 up to which a step contact 116 (Figure 1) is to be formed. The initial partial opening 1904 does not yet expose a portion of step 114.

[0143] Referring to Figure 20, sacrificial material 2002 is formed in the complete contact opening 1902 (Figure 19) to form the closed contact opening 2004 of the foundation. The sacrificial material 2002 may be formed of and include one or more polymer materials, which may also be byproducts of the etching solution used to form the contact openings (e.g., the complete contact opening 1902 (Figure 19) and the initial partial opening 1904). For example, the etching solution may be introduced (e.g., in gaseous form) into an area spanning the entire structure exposed through the hard mask 1016. By adjusting the composition of the chemical properties of the etching solution (e.g., the relative amounts of chemical species in the chemical properties of the etching solution), the sacrificial material 2002 (e.g., polymer material) may exhibit a lower etching rate compared to the etching rate of the dielectric material 502, and the sacrificial material 2002 may accumulate at the complete contact opening 1902 (Figure 19) to form a base-filled contact opening 2004, while not substantially accumulating at the incomplete contact opening (e.g., at the initial partial opening 1904) (and not substantially inhibiting the continued etching of the dielectric material 502). For example, the etching solution composition may include oxygen (O2) and carbon fluoride (e.g., C x F y ) may contain, and a relatively high oxygen (O2) concentration may result in a relatively low composition of sacrificial material 2002 (e.g., polymer material), a relatively high carbon (C) concentration may result in a relatively high composition of sacrificial material 2002, and a relatively high fluorine (F) concentration may result in a relatively low composition of sacrificial material 2002. Therefore, the flow of O2 and the ratio of carbon (C) and fluorine (F) (e.g., C x F yIn the above, "x" and "y" respectively can be adjusted and / or otherwise adapted to control the relative accumulation of sacrificial material 2002 at the closed contact opening 2004 of the base without significantly suppressing etching of the dielectric material 502 at the still incomplete contact opening (e.g., the initial partial opening 1904). Thus, sacrificial material 2002 can substantially accumulate only at the base of the complete contact opening 1902 (Figure 19), which is substantially defined only in the dielectric material 502—where step 114 is partially exposed—and where it is not within the initial partial opening 1904. The presence of sacrificial material 2002 at the closed contact opening 2004 of the base can suppress etching of the conductive structure 106 during subsequent material removal actions.

[0144] If the opening has not yet reached each of those steps 114, the initial partial opening 1904 is then widened downwards toward each stadium 122. The initial partial opening 1904 may be widened to form a full contact opening 1902 (Figure 19) toward the second stadium 126, as shown in Figure 21, and to form a widened partial opening 2102 toward the other stadiums 122 (for example, in the third stadium 128 and the fourth stadium 130). Sacrificial material 2002 may accumulate again to form a closed contact opening 2004 toward the base of the second stadium 126, without the accumulation of sacrificial material 2002 in the widened partial opening 2102, which is substantially entirely defined in the dielectric material 502. These widening and sacrificial material 2002 formation stages are repeated toward increasingly deeper stadiums 122.

[0145] While it may be explicitly stated and intended that the sacrificial material 2002 substantially forms (e.g., accumulates) only on the exposed portion of the conductive structure 106 of step 114 in the complete contact opening 1902 (Figure 19), in some embodiments of these manufacturing stages, some sacrificial material 2002 may inadvertently accumulate in the partially formed opening, for example, in the further widened partial opening 2202 (Figure 22) in the opening that is not yet completed toward the relatively deeper stadium 122 (e.g., the third stadium 128, the fourth stadium 130). This may result in a manufacturing error (e.g., so-called "insufficient etching") which could lead to the formation of the poorly formed step contact 604 shown in Figure 6. Given that these partial contact openings in the deeper stadiums 122 are exposed to the sacrificial material 2002 more times before the completion of these contact openings, this manufacturing error may be more likely in the deepest stadiums 122 (e.g., the third stadium 128, the fourth stadium 130). However, by forming a multi-step contact 116 (Figure 1) for each stepped layer 138 in one or more of the stadiums 122 (e.g., the deepest stadiums 122) that are most prone to these manufacturing errors, the likelihood that at least one of the multi-step contacts 116 (Figure 1) will be accurately manufactured to provide telecommunications to the stepped layer 138 is significantly increased.

[0146] In the further widened partial opening 2202, which is free from manufacturing errors and not inadvertently blocked by sacrificial material 2002, further expansion of the opening forms a full contact opening 1902 to the remaining stadium 122, as shown in Figure 23.

[0147] Sacrificial material 2002 can be removed (e.g., etched) from the base's blocked contact opening 2004 to complete the formation of the complete contact opening 1902 of the step contacts 116 (Figure 1) up to each stadium 122, as shown in Figure 24, having a portion of each step 114 exposed in the complete contact opening 1902.

[0148] In some embodiments, the hard mask 1016 may be removed in this or a later stage (e.g., etched, flattened).

[0149] In the complete contact opening 1902, the material of the step contact 116 is formed (e.g., deposited) to complete the organization of the step contact 116, as shown in Figure 25.

[0150] The contacts 404 through the stack (Figure 4) may be formed, for example, on the top 132 of the stack 102, and may be formed to connect to conductive features below the stack 102 (e.g., CuA electrical circuit configuration, string driver electrical circuit configuration). The paths 402 (Figure 4) are formed to complete the electrical connections between the step contacts 116 and the contacts 404 through their respective stacks in order to form microelectronic device structures (e.g., microelectronic device structure 100 in Figure 1, microelectronic device structure 700 in Figure 7, microelectronic device structure 800 in Figure 8, microelectronic device structure 900 in Figure 9).

[0151] Therefore, disclosed is a method for forming a microelectronic device. The method comprises forming a layered stack on a base structure. The layered stack comprises a vertically alternating sequence of insulating structures and other structures. Stadiums are formed in the layered stack. Each stadium comprises one or more steps defined at least partially by some horizontal ends of the other structures. At least one dielectric material is formed in grooves lying vertically on top of the stadium. Contact openings are formed through at least one dielectric material. At least one pair of contact openings extends vertically to a common one of the other structures. Conductive contact structures are formed at each contact opening.

[0152] Figure 26 shows a block diagram of system 2600 according to an embodiment of the present disclosure, in which system 2600 includes a memory 2602 which includes an array of vertical strings of memory cells adjacent to a microelectronic device structure (e.g., microelectronic device structure 100 in Figures 1 and 4, Figure 5, and / or Figure 6, microelectronic device structure 700 in Figure 7, microelectronic device structure 800 in Figure 8, and microelectronic device structure 900 in Figure 9). Thus, the architecture and structure of memory 2602 may include one or more device structures according to embodiments of the present disclosure, which may be manufactured according to one or more of the methods described above (see, for example, Figures 10 to 25).

[0153] System 2600 may include a controller 2604 operably coupled to memory 2602. System 2600 may also include another electronic device 2606 and one or more peripheral devices 2608. In some embodiments, the other electronic device 2606 may include one or more microelectronic device structures (e.g., microelectronic device structure 100 in Figures 1 and 4, Figure 5, and / or Figure 6, microelectronic device structure 700 in Figure 7, microelectronic device structure 800 in Figure 8, microelectronic device structure 900 in Figure 9) manufactured according to embodiments of this disclosure and one or more of the methods described above. One or more of the controller 2604, memory 2602, other electronic devices 2606, and peripheral devices 2608 may be in the form of one or more integrated circuits (ICs).

[0154] Bus 2610 provides electrically conductive and operable communication between various components of system 2600. Bus 2610 may include an address bus, a data bus, and a control bus, each independently configured. Alternatively, bus 2610 may use conductive wires to provide one or more of address, data, or control, which may be coordinated by controller 2604. Controller 2604 may take the form of one or more processors.

[0155] Other electronic devices 2606 may include additional memory (for example, having one or more microelectronic device structures (e.g., microelectronic device structure 100 in Figures 1 and 4, Figure 5, and / or Figure 6, microelectronic device structure 700 in Figure 7, microelectronic device structure 800 in Figure 8, and microelectronic device structure 900 in Figure 9) manufactured according to embodiments of the present disclosure and one or more of the methods described above). Other memory structures of memory 2602 and / or other electronic devices 2606 may be configured in architectures other than 3D NAND, such as dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), synchronous graphics random access memory (SGRAM), double data rate dynamic ram (DDR), double data rate SDRAM, and / or magneto-based memory (e.g., spin-transfer torque magneto-RAM (STT-MRAM)).

[0156] The peripheral device 2608 may include a display, imaging device, printing device, wireless device, additional storage memory, and / or control device that can operate in conjunction with the controller 2604.

[0157] System 2600 may include, for example, optical fiber systems or devices, electro-optical systems or devices, optical systems or devices, imaging systems or devices, and information processing systems or devices (for example, wireless systems or devices, telecommunications systems or devices, and computers).

[0158] Accordingly, disclosed is an electronic system comprising a three-dimensional memory device, at least one processor, and at least one peripheral device. The three-dimensional memory device includes a stack structure comprising conductive structures arranged in layers and perpendicularly alternating with insulating structures. A series of stepped stadiums are defined in blocks of the stack structure. Pairs of step contacts extend through a dielectric material covering at least one of the stadiums to each other from among the conductive structures defining at least one step of the at least one stadium. At least one processor is operably communicating with the three-dimensional memory device. At least one peripheral device is operably communicating with at least one processor.

[0159] Non-limiting, exemplary embodiments may include, individually or in combination, the following:

[0160] Embodiment 1: A microelectronic device comprising: a stack structure comprising a vertically alternating sequence of insulating and conductive structures arranged in layers, each layer comprising at least one conductive structure and at least one insulating structure; a stadium within the stack structure, at least one of the stadiums comprising two steps having steps provided by a group of conductive structures; and a step contact extending to the steps of the two steps of at least one of the stadiums, wherein each conductive structure in the group of conductive structures has a plurality of step contacts in contact with it at least one of the steps of the two steps.

[0161] Embodiment 2: The microelectronic device of Embodiment 1, wherein at least one pair of stairs in the stadium are located at the same vertical position relative to each other within the stack structure.

[0162] Embodiment 3: A microelectronic device, one of Embodiments 1 and 2, in which at least one set of two staircases in a stadium reflects each other.

[0163] Embodiment 4: A microelectronic device according to any one of Embodiments 1 to 3, wherein at least one of the two staircases in a stadium includes a first staircase having a negative slope that descends toward a second staircase having a positive slope.

[0164] Embodiment 5: A microelectronic device according to any one of Embodiments 1 to 3, wherein at least one of the two staircases in the stadium includes a first staircase having a positive slope that ascends toward a second staircase having a negative slope.

[0165] Embodiment 6: A microelectronic device according to any one of Embodiments 1 to 3, wherein at least one set of two staircases in a stadium has either a positive or negative gradient.

[0166] Embodiment 7: A microelectronic device from any one of Embodiments 1 to 6, wherein at least one of the other stadiums has only one staircase provided by an additional group of conductive structures.

[0167] Embodiment 8: A microelectronic device from any one of Embodiments 1 to 6, wherein at least one of the other stadiums includes two additional stairs that are offset perpendicularly from each other.

[0168] Embodiment 9: The microelectronic device of Embodiment 8, wherein at least one additional staircase of the stadium includes a first staircase having a negative slope descending toward a second staircase having a positive slope, and the lowest step of the first staircase is vertically higher than the lowest step of the second staircase.

[0169] Embodiment 10: The microelectronic device of Embodiment 8, wherein at least one additional set of stairs in the stadium includes a first set of stairs having a negative slope descending toward a second set of stairs having a positive slope, and the lowest step of the first set of stairs is vertically lower than the lowest step of the second set of stairs.

[0170] Embodiment 11: The microelectronic device of Embodiment 8, wherein at least one additional staircase of the stadium includes a first staircase having a positive slope that ascends toward a second staircase having a negative slope, and the highest step of the first staircase is vertically above the highest step of the second staircase.

[0171] Embodiment 12: The microelectronic device of Embodiment 8, wherein at least one additional staircase of the stadium includes a first staircase having a positive slope that ascends toward a second staircase having a negative slope, and the highest step of the first staircase is vertically lower than the highest step of the second staircase.

[0172] Embodiment 13: A microelectronic device from any one of Embodiments 1 to 12, wherein at least one pair of step contacts sharing electrical communication with one of the conductive structures in a group of conductive structures also shares electrical communication with a conductive routing structure covering a stack structure and with a conductive contact structure extending vertically through the entire stack structure.

[0173] Embodiment 14: The microelectronic device of Embodiment 13, wherein the step contacts of at least one pair of step contacts are located within one common horizontal area of ​​at least one of the stadiums.

[0174] Embodiment 15: The microelectronic device of Embodiment 13, wherein the step contacts of at least one pair of step contacts are each located in a different horizontal area of ​​at least one of the stadiums.

[0175] Embodiment 16: A microelectronic device according to any one of embodiments 13 and 14, wherein the step contacts of at least one pair of step contacts extend to one common step of at least one pair of stairs in a stadium.

[0176] Embodiment 17: A microelectronic device from any one of Embodiments 13 to 16, wherein the conductive contact structure is located within a horizontal area of ​​the top region of a stack structure between horizontally adjacent stadiums.

[0177] Embodiment 18: A microelectronic device of any one of Embodiments 13 to 16, wherein each pair of step contacts shares electrical communication with one of the conductive structures in a group of conductive structures, each pair sharing electrical communication with a different conductive contact structure, and the conductive contact structures extend completely through the stack structure.

[0178] Embodiment 19: A microelectronic device comprising: a stack structure including insulating structures sandwiched perpendicularly between conductive structures and arranged in layers; a series of stadiums within the stack structure, where at least one of the stadiums has a step at least partially defined by the conductive structures of a first group of layers, and at least one other of the stadiums has an additional step at least partially defined by the conductive structures of a second group of layers, and the first group of layers is at a lower elevation than the elevation of the second group of layers; and conductive contacts within the horizontal area of ​​the stadiums in the series of stadiums, the conductive contacts comprising: a pair of conductive contacts where each pair of conductive contacts extends from each other to one different conductive structure of the first group of layers, and conductive contacts among those conductive contacts where each of those conductive contacts extends from each other to one different conductive structure of the second group of layers.

[0179] Embodiment 20: A method for forming a microelectronic device, comprising: forming a layered stack on a base structure, wherein the layered stack comprises a vertically alternating sequence of insulating structures and other structures; forming a stadium in the layered stack, wherein each stadium comprises one or more steps defined at least partially by some horizontal ends of the other structures; forming at least one dielectric material in grooves lying vertically above the stadiums; forming at least one pair of contact openings through at least one dielectric material extending vertically to a common of the other structures; and forming conductive contact structures at each contact opening.

[0180] Embodiment 21: The method of Embodiment 20, wherein forming a stadium in a layered stack includes: defining the staircase outline of the stadium at an upper height of the layered stack; and extending at least some of the staircase outlines of the stadium to a lower height within the layered stack than the height of the staircase outlines of at least some other stadiums in the stadium.

[0181] Embodiment 22: The method of Embodiment 21, wherein defining the stair outline of a stadium at an upper height of a layered stack includes defining at least one of the stair outlines to include a pair of opposite staircases.

[0182] Embodiment 23: The method of Embodiment 22, further comprising the following, before widening at least some of the stair outlines of the stadium: vertically offsetting one of the opposite staircases of a pair of opposite staircases in at least one of the stair outlines.

[0183] Embodiment 24: Any one of Embodiments 20 to 23, wherein each contact opening exposes a surface portion of one of the other structures and forms a contact opening through at least one dielectric material, the method comprising: forming an initial contact opening through an upper elevation of at least one dielectric material; some of the initial contact openings forming some of the contact openings, some of the other initial contact openings terminating in at least one dielectric material; forming a sacrificial material on the surface portion of the other structure exposed by forming some of the initial contact openings; further extending some of the other initial contact openings into at least one dielectric material to form some of the other contact openings; and removing the sacrificial material before forming a conductive contact structure at each contact opening.

[0184] Embodiment 25: Electronic system comprising: a three-dimensional memory device comprising: a stack structure comprising conductive structures arranged alternately and in layers perpendicular to insulating structures; a series of stepped stadiums defined in blocks of the stack structure; pairs of step contacts extending through a dielectric material covering at least one of the stadiums, up to mutually defined conductive structures of at least one step of at least one stadium; at least one processor operably communicating with the three-dimensional memory device; and at least one peripheral device operably communicating with the at least one processor.

[0185] The structures, apparatus (e.g., devices), systems, and methods disclosed are susceptible to various modifications and alternative forms in their embodiments, although specific embodiments are shown as examples in the drawings and described in detail herein. However, this disclosure is not limited to any specific form disclosed. Rather, this disclosure encompasses all modifications, combinations, equivalents, variations, and alternatives that fall within the scope of this disclosure as defined by the appended claims and their legal equivalents below.

Claims

1. A stack structure comprising a vertically alternating sequence of insulating and conductive structures arranged in layers, wherein each layer comprises at least one of the conductive structures and at least one of the insulating structures, The stadium within the stack structure, wherein at least one of the stadiums includes two staircases having steps provided by the group of conductive structures, and each of the conductive structures in the group individually provides a continuous conductive region across the two staircases of at least one of the stadiums, The step contacts extend to the steps of at least one of the two stairs in the stadium, and each conductive structure in the group of conductive structures has a plurality of the step contacts that come into contact with it at least one of the steps of the two stairs. A microelectronic device equipped with the following features.

2. The microelectronic device according to claim 1, wherein at least one of the two staircases in the stadium is located at the same vertical position relative to each other within the stack structure.

3. The microelectronic device according to claim 1, wherein at least one of the two staircases in the stadium reflects each other.

4. The microelectronic device according to claim 1, wherein at least one of the two stairs in the stadium includes a first staircase having a negative slope that descends toward a second staircase having a positive slope.

5. The microelectronic device according to claim 1, wherein at least one of the two staircases in the stadium includes a first staircase having a positive slope that ascends toward a second staircase having a negative slope.

6. The microelectronic device according to claim 1, wherein at least one of the two staircases in the stadium has either a positive or negative gradient.

7. The microelectronic device according to claim 1, wherein at least one of the stadiums has only one staircase provided by an additional group of conductive structures.

8. The microelectronic device according to claim 1, wherein at least one of the stadiums includes two additional steps that are offset perpendicularly from each other.

9. The microelectronic device according to claim 8, wherein at least one of the other two additional staircases in the stadium includes a first staircase having a negative slope descending toward a second staircase having a positive slope, and the lowest step of the first staircase is vertically above the lowest step of the second staircase.

10. The microelectronic device according to claim 8, wherein at least one of the other two additional staircases in the stadium includes a first staircase having a negative slope descending toward a second staircase having a positive slope, and the lowest step of the first staircase is vertically lower than the lowest step of the second staircase.

11. The microelectronic device according to claim 8, wherein at least one of the other two additional staircases in the stadium includes a first staircase having a positive slope that ascends toward a second staircase having a negative slope, and the highest step of the first staircase is vertically above the highest step of the second staircase.

12. The microelectronic device according to claim 8, wherein the two additional stairs of the stadium include a first staircase having a positive slope ascending toward a second staircase having a negative slope, and the highest step of the first staircase is vertically lower than the highest step of the second staircase.

13. The microelectronic device according to any one of claims 1 to 12, wherein at least one pair of step contacts sharing electrical communication with one of the conductive structures in the group of conductive structures also shares electrical communication with a conductive routing structure covering the stack structure and with a conductive contact structure extending vertically through the entire stack structure.

14. The microelectronic device according to claim 13, wherein the step contact of the at least one pair of step contacts is located in the horizontal area of ​​a common stadium of the at least one of the stadiums.

15. The microelectronic device according to claim 13, wherein the step contacts of the at least one pair of step contacts are each located in a horizontal area of ​​a different stadium from the other, of the at least one stadium.

16. The microelectronic device according to claim 13, wherein the step contact of the at least one pair of step contacts extends to a common step of the steps of at least one of the two staircases of the stadium.

17. The microelectronic device according to claim 16, wherein the conductive contact structure is located within a horizontal area of ​​the top region of the stack structure between horizontally adjacent stadiums.

18. The microelectronic device according to claim 16, wherein each pair of the step contacts of at least one pair that share the electrical communication with one of the conductive structures in the group of the conductive structures shares electrical communication with a conductive contact structure different from one another, and the conductive contact structures extend completely through the stack structure.

19. A stacked structure including conductive structures and insulating structures sandwiched perpendicularly and arranged in layers, A series of stadiums within the stack structure, wherein at least one of the stadiums has a step at least partially defined by the conductive structure of the first group of the layers, and at least one other of the stadiums has an additional step at least partially defined by the conductive structure of the second group of the layers, and the layers of the first group are at an altitude lower than the altitude of the layers of the second group, A conductive contact within the horizontal area of ​​one of the aforementioned series of stadiums, Each pair of conductive contacts extends to one different conductive structure of the layer in the first group from each other, and The conductive contacts among the conductive contacts extend from each other to one different conductive structure of the layer in the second group. The conductive contact and Microelectronic devices, including those mentioned above.

20. A method for forming a microelectronic device, The layered stack forms the layered stack on the foundation structure, which includes a vertically alternating sequence of insulating structures and other structures. Each stadium is formed in a layered stack that includes one or more staircases, which are at least partially defined by some of the horizontal ends of other structures. Including the formation of the stadium in the layered stack, The outline of the stairs of the aforementioned stadium is defined at an upper height of the aforementioned layered stack, To extend the staircase outline of at least some of the stadiums to a lower height within the layered stack than the height of the staircase outline of at least some other of the stadiums, Forming at least one dielectric material in a groove lying vertically above the stadium, At least one pair of contact openings forms the contact openings through the at least one dielectric material, extending vertically to a common of the other structures providing a continuous conductive material region, A conductive contact structure is formed at each of the aforementioned contact openings. Methods that include...

21. The method according to claim 20, wherein defining the staircase outline of the stadium at the upper height of the layered stack includes defining at least one of the staircase outlines to include a pair of opposite staircases.

22. The method according to claim 21, further comprising vertically offsetting one of the opposite staircases of the opposite staircase pair in at least one of the staircase outlines before widening at least some of the staircase outlines in the stadium.

23. Each of the aforementioned contact openings exposes a surface portion of one of the other structures and forms the contact opening through the at least one dielectric material, Some of the initial contact openings form some of the contact openings, and some of the other initial contact openings form the initial contact openings through the upper height of the at least one dielectric material, terminating in the at least one dielectric material. Forming a sacrificial material on one of the exposed surface portions of the other structure by forming some of the initial contact openings, Further widening some of the initial contact openings within the at least one dielectric material to form some of the other contact openings, Before forming the conductive contact structure at each of the aforementioned contact openings, the sacrificial material is removed. The method according to any one of claims 20 to 22, including the method described in any one of claims 20 to 22.

24. A stacked structure including insulating structures and conductive structures arranged alternately and in layers perpendicular to each other, A series of stepped stadiums defined in the block of the stack structure, and A pair of step contacts extending through a dielectric material covering at least one of the stadiums, to each other of the conductive structures defining at least one step of at least one stadium, wherein each of the conductive structures individually defines a continuous conductive region across the series of stepped stadiums. A three-dimensional memory device comprising, At least one processor that communicates operably with the three-dimensional memory device, The at least one processor and at least one peripheral device that communicates in an operable manner An electronic system equipped with the following features.

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