Semiconductor equipment

Abstract

To provide a semiconductor device in which reduction of wire bondability is prevented by improving adhesiveness of a sealing resin.SOLUTION: A semiconductor device comprises: a case resin 1 including a frame part 1a defining a space in which a semiconductor chip is disposed, and a bottom part 1b provided at a lower side of the frame part; an external connection terminal including external terminals 3E and 3G which are partially embedded in the frame part, and internal terminals 4E and 4G disposed at the bottom part in a manner to extend from the external terminals into the space; a wire 7 electrically connecting the semiconductor chip with the external terminals; and a sealing resin formed in the space while covering the semiconductor chip, the wire, and the internal terminals. The internal terminal includes: a rectangular connection portion 4a; and step portions 4b which are provided at both opposed ends of the connection portion in parallel in an extension direction of the internal terminal into the space and have top faces lower than a top face of the connection portion. The top face of each of the opposed step portions is partially covered by a vibration suppression section 5 consisting made of the case resin, and the sealing resin is embedded in a groove part 6 where the other top face of the step portion is exposed.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The present invention relates to a semiconductor device, particularly a semiconductor device for power use.

Background Art

[0002] In a semiconductor device for power use such as a power conversion device or a switching device, a circuit board on which semiconductor elements are arranged is housed in a resin case in which external connection terminals are integrally provided by insert molding. External connection terminals including power terminals for power input / output and signal terminals for signal input / output are integrally provided in the case by insert molding. When the semiconductor device operates, the semiconductor elements generate heat. As the operating time of the semiconductor device becomes longer, deterioration such as cracks in the bonding material that bonds the semiconductor elements and power terminals to the circuit board and deformation of the wires bonded to the semiconductor elements occurs. In order to prevent such deterioration, the semiconductor elements inside the case are resin-sealed.

[0003] Since the difference in the linear expansion coefficients between the sealing resin and the case material is large, when repeated stress is generated due to heat cycles caused by the heat generation of the semiconductor elements and changes in the external atmosphere, the sealing resin peels off from the case material. Therefore, the wires bonded to the semiconductor elements are cut, or moisture is absorbed from the gap between the case material and the sealing resin, resulting in a decrease in reliability.

[0004] Patent Document 1 describes improving the adhesion between the case material and the sealing resin by providing grooves on both sides of the external connection portion of the external connection terminal along the periphery of the bottom surface of the case, and preventing a decrease in bonding performance by providing vibration suppression portions within the range of the groove adjacent to the internal connection portion. Patent Document 2 describes improving the adhesion between the external connection terminal and the case resin by providing a stepped portion at the end of the wire connection portion of the external connection terminal to secure the area of ​​the wire connection portion. Patent Document 3 describes preventing the occurrence of a gap below the internal connection portion when the tie bar of an insert-molded lead frame is cut by placing the case material in a recess provided at the tip of the internal connection portion and fixing the internal connection portion. Patent Document 4 describes improving the degree of adhesion between the case material and the internal connection portion and securing the area of ​​the wire connection portion by providing a recess or bend on the back side of the internal connection portion. Patent Document 5 describes preventing the wire connection portion from peeling off between the sealing resin and the external connection terminal and preventing wire breakage by exposing the wire connection portion in a recess of the case material provided at the tip of the internal connection portion.

[0005] Conventionally, to improve the adhesion between the case resin and the sealing resin, the contact surface of the case resin is addressed by applying a coating material or roughening it. However, applying a coating material increases manufacturing costs due to additional material costs and manufacturing processes. Furthermore, depending on the internal shape of the case, applying the coating material may be difficult. In addition, roughening the contact surface requires roughening the inner surface of the molding die by methods such as electrical discharge machining. Wear on the inner surface of the die reduces the surface roughness and deteriorates adhesion. Therefore, management and maintenance of the molding die become necessary, leading to increased manufacturing costs. [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2017-199818 [Patent Document 2] Japanese Patent Publication No. 2000-349219 [Patent Document 3] Japanese Patent Publication No. 2016-111028 [Patent Document 4] Japanese Patent Publication No. 2019-67885 [Patent Document 5] International Publication No. 2015 / 152373 [Overview of the project] [Problems that the invention aims to solve]

[0007] The present invention aims to provide a semiconductor device that can improve the adhesion of the sealing resin to the case and prevent a decrease in wire connectivity to external connection terminals. [Means for solving the problem]

[0008] To achieve the above objective, a first aspect of the present invention is a semiconductor device comprising: (a) a case resin having a frame portion defining a space in which a semiconductor chip is arranged and a bottom portion provided below the frame portion; (b) an external connection terminal having an external terminal partially embedded in the frame portion and an internal terminal provided at the bottom portion so as to extend from the external terminal into the space; (c) a wire for electrically connecting the semiconductor chip and the internal terminal; and (d) a sealing resin formed in the space covering the semiconductor chip, the wire and the internal terminal, wherein the internal terminal has a rectangular connection portion in plan view and stepped portions provided at both opposing ends of the connection portion parallel to the direction in which the internal terminal extends into the space, the upper surface of which is lower than the upper surface of the connection portion, the upper surface of a portion of each of the opposing stepped portions is covered with a vibration suppression portion made of case resin, and the sealing resin is embedded in a first groove portion that exposes the other upper surface of the stepped portion. [Effects of the Invention]

[0009] According to the present invention, it is possible to provide a semiconductor device that can improve the adhesion of the sealing resin to the case and prevent a decrease in the wire connection performance to the external connection terminals. [Brief explanation of the drawing]

[0010] [Figure 1]This is a schematic plan view showing an example of a semiconductor device according to an embodiment of the present invention. [Figure 2] This is a schematic cross-sectional view taken from the direction of line AA in Figure 1. [Figure 3] This is a circuit diagram showing an example of a semiconductor device according to an embodiment of the present invention. [Figure 4] This is a magnified view of section B in Figure 1. [Figure 5] This is a schematic cross-sectional view taken from the direction of the CC line in Figure 4. [Figure 6] This is a schematic cross-sectional view taken from the direction of line DD in Figure 4. [Figure 7] This is a schematic plan view showing another example of a semiconductor device according to an embodiment of the present invention. [Figure 8] This is a schematic cross-sectional view taken from the direction of the EE line in Figure 4. [Figure 9] This is a schematic cross-sectional view taken from the direction of the FF line in Figure 4. [Modes for carrying out the invention]

[0011] The first and second embodiments of the present invention will be described below with reference to the drawings. In the drawings, identical or similar parts are denoted by the same or similar reference numerals, and redundant explanations are omitted. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of the thickness of each layer, etc., may differ from the actual ones. Furthermore, there may be parts where the dimensional relationships and ratios differ between drawings. In addition, the embodiments shown below are illustrative examples of devices and methods for realizing the technical idea of ​​the present invention, and the technical idea of ​​the present invention is not limited to the materials, shapes, structures, arrangements, etc. of the components described below.

[0012] In addition, the definitions of directions such as up and down in the following description are merely for convenience of explanation and do not limit the technical idea of the present invention. For example, the "up" and "down" in the "upper conductive layer" and "lower conductive layer" in the following description are merely for convenience and are not defined with respect to the direction of the earth's gravity. Therefore, if the object is rotated 90° and observed, the up and down are read as being converted to left and right, and if it is rotated 180° and observed, it is a matter of course that the up and down are read as being reversed.

[0013] In the following description, as a representative example of the semiconductor device, a three-phase inverter circuit will be used for explanation. However, the semiconductor device of the present invention is not limited to the three-phase inverter circuit, and may be a power module such as a full-bridge circuit or a half-bridge circuit. Further, as the switching transistor of the inverter circuit, an insulated gate bipolar transistor (IGBT) will be used for explanation, but it is not limited thereto. For example, it may be a bipolar device such as a static induction thyristor (SI thyristor) or a gate turn-off (GTO) thyristor, or may be a MOS field effect transistor (FET), a MISFET, a static induction transistor (SIT), or the like. Further, as the freewheeling diode D of the inverter circuit, a fast recovery diode (FRD), a Schottky barrier diode (SBD), or the like can be adopted.

[0014] (Embodiment) As shown in Figures 1 and 2, the semiconductor device according to an embodiment of the present invention is a semiconductor power module consisting of a three-phase inverter circuit housed in a case resin 1. The case resin 1 has a frame portion 1a that defines the respective spaces where the leg circuits 30u, 30v, and 30w constituting the three-phase inverter circuit are arranged, and a bottom portion 1b provided below the frame portion 1a. The bottom portion 1b extends from the frame portion 1a into the space defined by the frame portion 1a. The case resin 1 is provided with terminals such as external connection terminals (3E, 4E), (3G, 4G), (3F, 4F), (3H, 4H), a positive terminal 15, a negative terminal 16, and an output terminal 17. These terminals are formed by integrally molding a metal lead frame into the case resin 1 by insert molding. External connection terminals (3E, 4E) have an external terminal 3E embedded and fixed in the frame portion 1a, and an internal terminal 4E extending from the external terminal 3E into the space defined by the frame portion 1a and positioned at the bottom portion 1b. External connection terminals (3G, 4G) have an external terminal 3G embedded and fixed in the frame portion 1a, and an internal terminal 4G extending from the external terminal 3G into the space defined by the frame portion 1a and positioned at the bottom portion 1b. External connection terminals (3F, 4H) have an external terminal 3F embedded and fixed in the frame portion 1a, and an internal terminal 4F extending from the external terminal 3F and positioned at the bottom portion 1b. External connection terminals (3H, 4H) have an external terminal 3H embedded and fixed in the frame portion 1a, and an internal terminal 4H extending from the external terminal 3H and positioned at the bottom portion 1b.

[0015] The case resin 1 is fixed to the cooling plate 21 by adhesive 20. The case resin 1 is made of, for example, an insulating thermoplastic resin. Suitable thermoplastic resins include polyphenylene sulfide (PPS) resin, polybutylene terephthalate (PBT) resin, polybutylene succinate (PBS) resin, polyamide (PA) resin, and acrylonitrile butadiene styrene (ABS) resin.

[0016] Each of the leg circuits 30u, 30v, and 30w includes semiconductor chips 2a and 2b mounted on an insulating circuit board 10. As shown in FIG. 2, each of the insulating circuit boards 10 has an insulating board 11, conductor layers 12a, 12b, and 12c patterned on the upper surface of the insulating board 11, and a conductor layer 13 provided on the lower surface of the insulating board 11. As shown in FIG. 1, the semiconductor chip 2a is disposed on the conductor layer 12a, and the semiconductor chip 2b is disposed on the conductor layer 12b. The insulating circuit board 10 is joined to the cooling plate 21 via the conductor layer 13 by a joining material such as solder. The insulating circuit board 10 can employ, for example, a direct copper bonding (DCB) board in which copper is eutectically bonded to the surface of a ceramic board, an active metal brazing (AMB) board in which metal is disposed on the surface of a ceramic board by the AMB method, etc. The material of the ceramic board can employ, for example, silicon nitride (Si3N4), aluminum nitride (AlN), alumina (Al2O3), etc.

[0017] As shown in FIG. 2, in the space defined by the frame portion 1a of the case resin 1, a sealing resin 9 (not shown in FIG. 1) is formed so as to cover the insulating circuit board 10 on which the semiconductor chips 2a, 2b, etc. are mounted, the wire 7, and the internal terminals 4G, 4E, 4F, 4H. Although an epoxy resin is used as the sealing resin 9, it is not limited thereto. For example, a thermoplastic resin different from the case resin 1, which has excellent insulation and adhesion, such as a silicone resin, a urethane resin, a polyimide resin, a polyamide resin, a polyamideimide resin, etc. can be employed.

[0018] In each of the leg circuits 30u, 30v, and 30w, as shown in Figure 3, for example, semiconductor chip 2a constitutes the upper arm and semiconductor chip 2b constitutes the lower arm. Semiconductor chips 2a and 2b have a switching transistor T made of IGBT and a freewheeling diode D connected in reverse to the switching transistor T. The cathode electrode K of the freewheeling diode D is electrically connected to the collector electrode C of the switching transistor T. The anode electrode A of the freewheeling diode D is electrically connected to the emitter electrode E of the switching transistor T. The collector electrode C of semiconductor chip 2a is electrically connected to the positive terminal 15. The emitter electrode E of semiconductor chip 2b is electrically connected to the negative terminal 16. The emitter electrode E of semiconductor chip 2a and the collector electrode C of semiconductor chip 2b are electrically connected to the output terminal 17.

[0019] As shown in Figure 1, the gate electrode G of the switching transistor T of semiconductor chip 2a is electrically connected to the internal terminal 4G via wire 7. The auxiliary emitter electrode (not shown) electrically connected to the emitter electrode E of semiconductor chip 2a is electrically connected to the internal terminal 4E via wire 7. The gate electrode G of the switching transistor T of semiconductor chip 2b is electrically connected to the internal terminal 4H via wire 7. The auxiliary emitter electrode (not shown) electrically connected to the emitter electrode E of semiconductor chip 2b is electrically connected to the internal terminal 4F via wire 7. A resistive element may be added to the gate electrode G to adjust the switching speed and loss. The auxiliary emitter electrode is an auxiliary electrode for detecting the voltage on the emitter electrode side.

[0020] In each of the leg circuits 30u, 30v, and 30w, as shown in Figure 3, the connection node between the emitter electrode E of semiconductor chip 2a and the collector electrode C of semiconductor chip 2b is electrically connected to the output terminal 17. For example, when the semiconductor device according to the embodiment is in operation, the positive electrode P and negative electrode N of an external DC power supply (not shown) are connected to the positive electrode terminal 15 and negative electrode terminal 16 of each of the leg circuits 30u, 30v, and 30w. For each of the leg circuits 30u, 30v, and 30w, a pulse signal is input to the gate electrode G from the control circuit (not shown) via external terminals 3G and 3H, and a reference signal is input to the emitter electrode E via external terminals 3E and 3F. As a result, for example, U-phase AC power is output from the output terminal 17 of the leg circuit 30u, V-phase AC power is output from the output terminal 17 of the leg circuit 30v, and W-phase AC power is output from the output terminal 17 of the leg circuit 30w, supplying three-phase AC power to a load 50 such as a motor.

[0021] Figure 4 is an enlarged view of section B shown in Figure 1, and shows the configuration of the external connection terminals (3E, 4E) and (3G, 4G) integrally molded with the case resin 1. In Figure 4, the sealing resin 9 is omitted from the drawing. Figure 5 is a schematic cross-sectional view taken perpendicularly from the CC line in Figure 4, which passes through the joint end of the wire 7, and Figure 6 is a schematic cross-sectional view taken perpendicularly from the DD line in Figure 4, avoiding the joint end of the wire 7. The external connection terminals (3F, 4F) and (3H, 4H) have a similar configuration. As shown in Figures 4 to 6, the internal terminals 4E and 4G of the external connection terminals (3E, 4E) and (3G, 4G) are each composed of a connection portion 4a and a stepped portion 4b. The connection portion 4a is rectangular in plan view. The stepped portions 4b are provided at opposite ends of the connection portion 4a, parallel to the direction in which the internal terminal 4E extends from the external terminal 3E into the space where the semiconductor chips 2a and 2b are arranged. The stepped portion 4b has a width Ws, and its upper surface is lower than the upper surface of the connecting portion 4a by a depth Ds. The upper surface of the connecting portion 4a is a flat surface at substantially the same height level as the upper surface of the bottom portion 1b.

[0022] As shown in Figure 4, grooves (first grooves) 6 are provided on the frame portion 1a side and on the tip side of the internal terminals 4E and 4G, between the bottom portion 1b and the connection portion 4a, exposing the upper surface of the stepped portion 4b. The grooves 6 are provided, for example, with a length Lc on the frame portion 1a side and a length Lt on the tip side of the internal terminals 4E and 4G. As shown in Figure 6, sealing resin 9 is embedded in the upper surface of the stepped portion 4b exposed in the grooves 6. For example, the PPS resin used for the case resin 1 and the epoxy resin used for the sealing resin 9 have different coefficients of thermal expansion and also have poor adhesion. In conventional semiconductor devices, repeated stress due to heat generation from the semiconductor chip makes it easy for the sealing resin made of epoxy resin to peel off from the case resin made of PPS resin. As a result, wire breakage of the connection between the semiconductor chip and the external connection terminal and moisture absorption from the gap between the case resin and the sealing resin are more likely to occur. In the semiconductor device according to this embodiment, a groove 6 is provided in the bottom 1b of the case resin 1, and sealing resin 9 is embedded in the groove 6, which exposes the upper surface of the stepped portion 4b. Therefore, the sealing resin 9 comes into contact with the metal surface of the stepped portion 4b. The adhesion between the sealing resin 9 and the stepped portion 4b, which is made of metal, is better than that between the case resin 1 and the stepped portion 4b. Therefore, the adhesion between the sealing resin 9 and the case resin 1 can be improved. Furthermore, since the sealing resin 9 is embedded in the groove 6, the adhesion can be further improved by the anchoring effect.

[0023] Furthermore, as shown in Figure 4, a vibration suppression section 5 is defined between the grooves 6, covering the upper surface of the stepped section 4b with the case resin 1. The vibration suppression section 5 is provided with a length Lv. As shown in Figure 5, the connection section 4a of the internal terminals 4E and 4G has its stepped sections 4b fixed at both ends by vibration suppression sections 5 defined at the bottom 1b of the case resin 1. Since the wire 7 is joined to the upper surface of the connection section 4a by ultrasonic bonding, there is concern that the bonding performance of the wire may decrease due to the vibration of the ultrasonic waves applied during bonding. In the semiconductor device according to this embodiment, vibration of the connection section 4a during ultrasonic bonding is suppressed by fixing the connection section 4a via the vibration suppression section 5 provided on the stepped section 4b of the internal terminals 4E and 4G. As shown in Figure 4, in order to suppress vibration more effectively, it is preferable to join the wire 7 such that the joining end of the wire 7 is enclosed within the bonding region 8 defined by the opposing vibration suppression sections 5. In a plan view, the bonding region 8 has the same length Lv as the vibration suppression portion 5 in the extension direction from the external terminals 3E and 3G into the space defined by the frame portion 1a. The length Lv of the bonding region 8 is longer than the length Lb of the bonding end of the wire 7. In this way, by enclosing the bonding end of the wire 7 within the bonding region 8, it is possible to suppress the longitudinal and transverse vibrations of the ultrasonic waves applied during wire bonding of the wire 7.

[0024] In the above description, a groove 6 is provided in the bottom 1b of the case resin 1 to improve the adhesion between the sealing resin 9 and the case resin 1. However, a groove may also be provided in the frame portion 1a. For example, Figure 7 is an enlarged view corresponding to portion B shown in Figure 1, Figure 8 is a schematic cross-sectional view taken perpendicularly from the EE line in Figure 7, and Figure 9 is a schematic cross-sectional view taken perpendicularly from the FF line in Figure 7. As shown in Figures 7 to 9, a groove (second groove) 6a is provided in the side wall of the frame portion 1a of the case resin 1. The metal surfaces of the external terminals 3E and 3G are exposed in the groove 6a, and the sealing resin 9 embedded in the groove 6a comes into contact with the metal surfaces. Therefore, the adhesion between the sealing resin 9 and the case resin 1 can be improved. Furthermore, since the sealing resin 9 is embedded in the groove 6a, the adhesion can be further improved by the anchoring effect. Note that insert molding is performed multiple times, for example, twice, to form the groove 6a in the side wall of the frame portion 1a. In the primary insert molding process, only the portion corresponding to the frame portion 1a into which the lead frame for the external connection terminals is embedded is insert molded, and grooves 6a are provided on the side walls of the portion corresponding to the frame portion 1a. Then, in the secondary insert molding process, the remaining portion including the bottom portion 1b is insert molded to form the case resin 1.

[0025] (Other embodiments) Although the present invention has been described by the embodiments disclosed above, the descriptions and drawings that constitute part of this disclosure should not be understood as limiting the present invention. It should be understood that various alternative embodiments, examples, and operational techniques will become apparent to those skilled in the art from the disclosure of the specification and drawings of the present invention. Furthermore, it goes without saying that the present invention includes various embodiments not described herein, such as configurations that arbitrarily apply the configurations described in the above embodiments and each of the modifications. Therefore, the technical scope of the present invention is determined solely by the inventive features relating to the claims that are reasonable from the above illustrative description. [Explanation of symbols]

[0026] 1 case resin 1a Frame 1b bottom 2a, 2b Semiconductor chips (3E,4E), (3F,4F), (3G,4G), (3H,4H) External connection terminal 3E, 3F, 3G, 3H external terminal 4a Connection part 4b Stepped section 4E, 4F, 4G, 4H internal terminals 5 Vibration suppressor 6, 6a Groove 7 wires 8 Joint area 9 Sealing resin 10 Insulated circuit board 11 Insulating board 12a, 12b, 12c, 13 Conductor layers 15 Positive terminal 16 Negative terminal 17 Output terminals 20 Adhesives 21 Cooling plate 30u, 30v, 30w Reg circuit 50 load

Claims

1. A case resin having a frame portion that defines the space in which a semiconductor chip is arranged, and a bottom portion provided below the frame portion, An external connection terminal having an external terminal partially embedded in the frame and an internal terminal positioned at the bottom so as to extend from the external terminal into the space, A wire electrically connecting the semiconductor chip and the internal terminal, The semiconductor chip, the wire and the internal terminal are covered by a sealing resin formed in the space. Equipped with, The internal terminal has a rectangular connecting portion in plan view, and stepped portions provided at both opposing ends of the connecting portion parallel to the direction in which the internal terminal extends into the space, the upper surface of which is lower than the upper surface of the connecting portion. The upper surfaces of a portion of each of the opposing stepped portions are covered with vibration-dampening portions made of the case resin. A semiconductor device characterized in that the sealing resin is embedded in the first groove that exposes the other upper surface of the stepped portion.

2. The semiconductor device according to claim 1, characterized in that the joined end of the wire above the connecting portion is contained within a joining region defined by the opposing vibration suppression portion.

3. The semiconductor device according to claim 1 or 2, characterized in that the frame portion is provided with a second groove portion into which the sealing resin is embedded, exposing a part of the surface of the external terminal.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that the first groove is provided separately from the vibration suppression portion in the stretching direction.

Images