Semiconductor equipment

Abstract

A semiconductor device (10) according to the present invention is a field-effect transistor comprising a gate electrode (110) located between a source electrode (108) and a drain electrode (109), a carrier traveling between the source electrode and the drain electrode, wherein the field-effect transistor also comprises a channel control layer (104) located between the gate electrode and a channel (103) in which the carrier travels, a recess is disposed in at least a source-electrode-side part of a surface of the channel control layer that is in contact with the gate electrode, and part of the gate electrode fills the recess.　The present invention thereby makes it possible to provide a semiconductor device having exceptional high-frequency characteristics.

Description

Technical Field

[0001] The present invention relates to a semiconductor device having a field effect transistor structure.

Background Art

[0002] Regarding the technology using terahertz waves in the electromagnetic wave frequency band of 0.3 to 3 THz, new applications such as high-speed wireless communication exceeding 100 Gbps, non-destructive internal inspection by three-dimensional imaging, component analysis using electromagnetic wave absorption, and atmospheric sensing from space are being explored and realized.

[0003] In order to realize applications using terahertz waves, better high-frequency characteristics are required for the electronic devices constituting the applications. As an electronic device having good high-frequency characteristics, a field effect transistor made of a compound semiconductor having a physically high electron mobility is used. For the further development of terahertz wave technology in the future, a field effect transistor having better high-frequency characteristics is required.

[0004] A field effect transistor is composed of a semiconductor (channel) layer, a gate electrode formed on the semiconductor (channel) layer, source electrodes formed on both horizontal sides of the gate electrode, and a drain electrode. In a field effect transistor, when a potential is applied to the gate electrode, carriers (electrons) traveling through the channel layer between the source electrode and the drain electrode are modulated corresponding to the intensity of the applied potential.

[0005] In order to improve the high-frequency characteristics of a field effect transistor, it is necessary to increase the modulation speed in the channel layer. Indicators showing the high-frequency characteristics of this field effect transistor are the cutoff frequency (ft) and the maximum operating frequency (fmax). Among these, from the viewpoint of amplification in an analog electronic circuit, improvement of fmax is important. fmax indicates the frequency at which the power gain of the field effect transistor becomes 1.

[0006] In a field-effect transistor, shortening the gate electrode length is important to improve the fmax.

[0007] Furthermore, in a field-effect transistor, applying a high bias to the drain electrode generates hot electrons in the channel layer between the gate and drain electrodes. This generates electron-hole pairs, increasing the drain conductance. As a result, fmax deteriorates. Therefore, reducing the drain conductance is also important in order to improve fmax.

[0008] Another field-effect transistor that improves high-frequency characteristics is the high-electron-mobility field-effect transistor (HEMT). HEMTs consist of semiconductor layers such as a buffer layer, channel layer, barrier layer, and cap layer on a semiconductor substrate.

[0009] In a HEMT, carriers are supplied from the δ-doped layer formed in the barrier layer to the channel layer, forming a two-dimensional electron gas and creating a conduction channel between the source electrode and the drain electrode. When a potential is applied to the gate electrode, the concentration of the two-dimensional electron gas is modulated in accordance with the intensity of the applied potential, and electrons move through the conduction channel between the source electrode and the drain electrode.

[0010] Furthermore, in HEMTs, the channel layer where a two-dimensional electron gas is formed and carriers travel is spatially separated from the electron supply layer where impurities are introduced. As a result, in HEMTs, scattering due to impurities is suppressed in the conduction channel, thereby improving electron mobility and enhancing high-frequency characteristics.

[0011] Therefore, in order to improve fmax in HEMTs, it is important to shorten the gate electrode length, reduce the drain conductance, and apply a high-mobility material to the channel layer.

[0012] In a field-effect transistor including a HEMT, shortening of the gate length has been realized as a scaling technology.

[0013] Also, in order to apply a high-mobility channel layer in a HEMT, as shown in FIG. 8, a first channel layer 803 made of InGaAs with an In composition x of x ≤ 0.8, a second channel layer 804 made of InGaAs with an In composition x of 0.8 < x ≤ 1 or InAs, a third channel layer 805 made of InGaAs with a composition x of x ≤ 0.8, a spacer layer 806 made of InAlAs, an electron supply layer 807, and a barrier layer 808 are formed in this order (for example, Patent Document 1).

[0014] Also, in order to reduce the drain conductance, as shown in FIG. 9, a structure (asymmetric recess structure) 912 having a space without a cap layer 906 is formed asymmetrically such that the distance between the gate electrode 914 and the drain electrode 908 is longer than the distance between the gate electrode 914 and the source electrode 907 (Patent Document 2). In addition, it includes a substrate 901, a buffer layer 902, a channel layer 903, a barrier layer 904, an electron supply layer 905, a first insulating layer 909, an opening 911 for forming an asymmetric recess, a second insulating layer 913, and a passivation layer 921.

[0015] Similarly, as shown in FIG. 10, an asymmetric recess structure 1012 / 1013 in which the cap layer 1018 is removed is disclosed such that the distance between the gate electrode 1011 and the drain electrode 1010 is longer than the distance between the gate electrode 1011 and the source electrode 1009 (Patent Document 3). In addition, it includes a substrate 1001, a buffer layer 1002, a channel layer 1003, a barrier layer 1004, a passivation layer 1005, an electron supply layer 1008, an insulating film 1014, and an opening 1015.

[0016] These asymmetric recess structures intentionally induce carrier depletion in the drain electrode region, thereby suppressing the generation of hot electrons when a high drain bias is applied. As a result, drain conductance can be reduced, and fmax can be improved. [Prior art documents] [Patent Documents]

[0017] [Patent Document 1] Patent No. 5525013 [Patent Document 2] Patent No. 6810014 [Patent Document 3] Patent No. 5662547 [Overview of the project] [Problems that the invention aims to solve]

[0018] However, in field-effect transistors, shortening the length of the gate electrode (gate length) can lead to short-channel effects such as a decrease in threshold voltage, which poses a problem.

[0019] Furthermore, in configurations using a high-mobility channel layer, the band gap in high-mobility channel materials such as InAs is small, resulting in significant hot electron generation in the channel layer between the gate and drain electrodes when a high bias is applied to the drain electrode. This degrades the fmax.

[0020] Furthermore, in a configuration with an asymmetric recess structure, electrons are not induced in the barrier layer near the space without a cap layer in the drain electrode region. As a result, the length of the barrier layer where electrons are not induced increases, significantly increasing the drain resistance. When the drain resistance increases, ft deteriorates, and consequently, fmax deteriorates significantly.

[0021] Thus, even if the drain conductance is reduced by forming a long space without a cap layer in the drain electrode side region, the drain resistance increases so as to cancel out the effect of improving the fmax. As a result, even if an asymmetric recess structure is applied, there is a certain limit to the fmax improvement effect, and a sufficient effect cannot be obtained.

Means for Solving the Problems

[0022] In order to solve the problems as described above, a semiconductor device according to the present invention includes a gate electrode between a source electrode and a drain electrode, and is a field effect transistor in which carriers travel between the source electrode and the drain electrode. A channel control layer is provided between the channel through which the carriers travel and the gate electrode. In the channel control layer, a recess is disposed at least in a part on the source electrode side of a surface in contact with the gate electrode, and a part of the gate electrode is filled in the recess. The channel control layer comprises a first channel control layer disposed on the channel side and a second channel control layer disposed on the gate electrode side, wherein the band gap of the first channel control layer is greater than the band gap of the second channel control layer, and the depth of the recess is greater than or equal to the thickness of the second channel control layer and less than the thickness of the channel control layer. It is characterized by the above.

Effect of the Invention

[0023] According to the present invention, a semiconductor device having excellent high-frequency characteristics can be provided.

Brief Description of the Drawings

[0024] [Figure 1] FIG. 1 is a schematic cross-sectional view showing the configuration of a semiconductor device according to a first embodiment of the present invention. [Figure 2] FIG. 2 is a schematic cross-sectional view showing the configuration of a semiconductor device according to a second embodiment of the present invention. [Figure 3] FIG. 3 is a schematic cross-sectional view showing the configuration of a semiconductor device according to a third embodiment of the present invention. [Figure 4] FIG. 4 is a schematic cross-sectional view showing the configuration of a semiconductor device according to a fourth embodiment of the present invention. [Figure 5] FIG. 5 is a schematic cross-sectional view showing the configuration of a semiconductor device according to a fifth embodiment of the present invention. [Figure 6]Figure 6 is a schematic cross-sectional view showing an example of the configuration of a semiconductor device according to the fifth embodiment of the present invention. [Figure 7] Figure 7 is a schematic cross-sectional view showing an example of the configuration of a semiconductor device according to an embodiment of the present invention. [Figure 8] Figure 8 is a schematic cross-sectional view showing an example of the layer configuration of a conventional semiconductor device. [Figure 9] Figure 9 is a schematic cross-sectional view showing an example of a conventional semiconductor device configuration. [Figure 10] Figure 10 is a schematic cross-sectional view showing an example of a conventional semiconductor device configuration. [Modes for carrying out the invention]

[0025] <First Embodiment> A semiconductor device according to the first embodiment of the present invention will be described with reference to Figure 1.

[0026] <Configuration of semiconductor device> As shown in Figure 1, the semiconductor device 10 according to this embodiment comprises, in order from the substrate 101 side, a buffer layer 102, a channel layer 103, a barrier layer (hereinafter also referred to as the "channel control layer") 104, and cap layers 106 and 107, with a δ-doped layer 105 provided within the barrier layer 104.

[0027] Furthermore, the cap layers 106 and 107 are equipped with an ohmic electrode, which is a source electrode 108, and a drain electrode 109.

[0028] Furthermore, a gate electrode 110 is provided on the barrier layer 104 between the source electrode 108 and the drain electrode 109. Here, an example is shown where the gate electrode 110 is positioned near the center between the source electrode 108 and the drain electrode 109, but it is not limited to this position and may be positioned at any position between the source electrode 108 and the drain electrode 109.

[0029] Furthermore, the barrier layer 104 has a recess in a part of its surface (one region), and the gate electrode 110 is formed on the surface of the barrier layer 104 including the recess. In other words, the barrier layer 104 has a recess in a part of the surface (one region) that is in contact with the gate electrode 110. As a result, the barrier layer 104 directly beneath the gate electrode 110 is thin in a predetermined region (one region) and thick in other regions.

[0030] Here, the portion consisting of the gate electrode 110 and the barrier layer 104 (recess) in a predetermined region (one region) is called the "barrier recess" 111 (dotted rectangle in the figure).

[0031] Here, in the region where the barrier layer 104 and the gate electrode 110 are in contact, the barrier recess 111, or recess, is located at the end on the source electrode 108 side. In this case, the recess only needs to be located at least a part of the barrier recess 111 that is closer to the source electrode 108 than the center.

[0032] In this way, a barrier recess 111 is formed in the barrier layer 104 to which the gate electrode 110 makes contact, with a portion of the gate electrode 110 filling into a recess in the barrier layer 104.

[0033] The structure including this barrier recess 111 is fabricated by forming a recess in a predetermined area on the surface of the barrier layer 104 by etching, and then forming the gate electrode 110.

[0034] As an example of a semiconductor device according to this embodiment, an InP-based HEMT will be described. Here, InP-based HEMTs are generally often used in HEMTs for high-frequency applications.

[0035] In an InP-based HEMT, the buffer layer 102 is a buffer region that is formed when crystal growth occurs on the semiconductor (InP) substrate 101. Undoped InAlAs is commonly used as the material, and its thickness is approximately 10 to 1000 nm.

[0036] The channel layer 103 functions as a channel through which carriers travel between the source electrode 108 and the drain electrode 109, and is a region where carriers are modulated by the electric field from the gate electrode 110. The higher the electron mobility in the channel layer 103, the higher the high-frequency performance can be. Undoped InAs is used as the material. In x Ga 1-x Materials such as As and InSb can be used. Furthermore, composite channel structures with different compositions can also be applied. The total thickness of the channel layer 103 is approximately 3 to 20 nm.

[0037] The barrier layer (channel control layer) 104 is the region for forming a Schottky junction with the gate electrode 110. InP is used as the material. Other materials that have a band gap larger than the band gap of the channel layer and can form a sufficiently high Schottky barrier with respect to the gate electrode 110, such as InAlAs and InxGa1-xAs, can also be used. A composite barrier structure with different compositions can also be applied. The total thickness of the barrier layer 104 is set to approximately 1 / 4 to 1 / 5 or less of the gate length. For example, if the gate length is 50 nm, the thickness of the barrier layer 104 is 10 nm to 12.5 nm.

[0038] The δ-doped layer 105 is formed in a sheet-like manner to supply carriers in the undoped barrier layer 104. The dopant is an n-type doping impurity such as Si. The δ-doped layer 105 within the barrier layer 104 is generally formed around the middle of the barrier layer 104's thickness (described later).

[0039] The cap layers 106 and 107 are formed to achieve a low-resistance ohmic junction with the source electrode 108 and drain electrode 109, respectively, without annealing. n-type InP is used as the material. Other materials such as InAlAs and InGaAs can also be used. The thickness of the cap layers 106 and 107 is set to achieve sufficiently low contact resistance and structurally reduce external parasitic capacitance, for example, 5 to 20 nm.

[0040] The source electrode 108 and drain electrode 109, which are ohmic electrodes, are formed to conduct carriers such as electrons to the channel layer 103 via the cap layers 106 and 107 and the barrier layer 104, and have a metal multilayer structure. A Ti / Pt / Au multilayer structure is used for the metal multilayer structure. Other materials such as Mo, W, and WSi may also be used for the multilayer structure.

[0041] The gate electrode 110 is formed to modulate electrons in the channel layer 103 by an electric field through the barrier layer 104, and, like the source electrode 108 and drain electrode 109, has a metal multilayer structure. A Ti / Pt / Au multilayer structure is used for the metal multilayer structure. Other multilayer structures such as Mo, W, and WSi may also be used.

[0042] Furthermore, the length of the gate electrode 110 (gate length) is set to approximately 4 to 5 times the thickness of the barrier layer 104.

[0043] The barrier recess 111 is located on the source electrode 108 side of the gate electrode 110. The length of the barrier recess 111 is approximately 20-50% of the gate length. For example, if the gate length is approximately 50 nm, the length of the barrier recess 111 is 10-25 nm.

[0044] Furthermore, the depth of the recess in the barrier recess 111 should be less than the thickness of the barrier layer 104. For example, if the thickness of the barrier layer 104 is about 10 nm, the depth of the recess in the barrier recess 111 can be set to 2 to 8 nm.

[0045] <Effects> In this embodiment, the barrier recess structure shortens the distance between the gate electrode and the channel layer (the thickness of the barrier layer), thereby suppressing short-channel effects such as a decrease in threshold voltage.

[0046] Furthermore, since a thicker barrier layer is formed at the drain electrode end of the gate electrode, the electric field strength near the drain electrode end of the gate electrode is reduced, and the electric field applied to electrons traveling through the channel layer in the gate region is suppressed. As a result, the generation of hot electrons is suppressed, and the drain conductance can be reduced.

[0047] Furthermore, in this embodiment, drain conductance can be reduced by ensuring a sufficient cap layer region (area) in the drain electrode side region, for example, by using a configuration without an asymmetric recess structure. In this configuration, electrons are sufficiently induced in the barrier layer of the drain electrode side region, thus avoiding an increase in drain resistance. In this way, drain conductance can be reduced without increasing drain resistance, thus improving fmax.

[0048] Naturally, even in configurations where an asymmetric recess structure is applied, the drain conductance can be further reduced and the fmax can be improved.

[0049] Thus, in HEMT structures with shortened gate lengths and high-mobility channels, fmax can be improved by reducing drain conductance.

[0050] According to the semiconductor device of this embodiment, the increase in drain conductance due to hot electron generation can be suppressed without increasing the drain resistance, and a field-effect transistor with good high-frequency characteristics can be realized.

[0051] <Second Embodiment> A semiconductor device according to a second embodiment of the present invention will be described with reference to Figure 2.

[0052] <Configuration of semiconductor device> In the semiconductor device 20 according to this embodiment, as shown in Figure 2, the depth of the recess in the barrier recess 211 is greater than the position (depth) of the δ-doped layer 105 within the barrier layer 104. The other configurations are the same as in the first embodiment.

[0053] In conventional HEMT structures, applying a high-mobility channel to the channel layer tends to result in a higher threshold voltage, depending on the density of the induced electron gas. A high threshold voltage necessitates applying a high reverse bias to the gate electrode when turning off the HEMT, thus imposing constraints on the circuit's bias design.

[0054] According to the semiconductor device of this embodiment, in addition to the effects of the first embodiment, a high fmax can be achieved by using a high-mobility channel and the threshold voltage can be reduced, making it easy to design the bias of the circuit.

[0055] <Third Embodiment> A semiconductor device according to a third embodiment of the present invention will be described with reference to Figure 3.

[0056] <Configuration of semiconductor device> In the semiconductor device 30 according to this embodiment, as shown in Figure 3, the barrier layer 304 is composed of different materials on the electrode side (surface side) and the channel layer side. Hereinafter, the barrier layer 304_1 on the channel layer side will be referred to as the "channel layer side barrier layer," and the barrier layer 304_2 on the electrode side (surface side) will be referred to as the "electrode side barrier layer." The other configurations are the same as in the first embodiment.

[0057] Here, the depth of the recess in the barrier recess 311 is greater than or equal to the thickness of the electrode-side barrier layer 304_2, but less than the total thickness of the barrier layer (the sum of the thickness of the channel-side barrier layer 304_1 and the electrode-side barrier layer 304_2).

[0058] The channel-side barrier layer 304_1 is made of a material with a wider band gap than the electrode-side barrier layer 304_2, and can be made of materials such as InAlAs, InP, or InAlP. This effectively shortens the distance between the gate electrode 310 and the channel layer 103.

[0059] Furthermore, the electrode-side barrier layer 304_2 is made of a material with a small energy difference from the conduction band edge of the cap layers 106 and 107, such as InGaAs or InAs. This reduces the energy difference from the conduction band edge of the cap layers 106 and 107, thereby reducing ohmic resistance.

[0060] Here, the δ-doped layer 305 may be placed at the boundary between the channel-side barrier layer 304_1 and the electrode-side barrier layer 304_2, or it may be placed in the electrode-side barrier layer 304_2, or it may be placed in the channel-side barrier layer 304_1.

[0061] According to the semiconductor device of this embodiment, in addition to the effects of the first embodiment, the distance between the gate electrode and the channel layer can be effectively shortened, thereby suppressing short-channel effects such as a decrease in threshold voltage. Furthermore, the drain resistance can be reduced by reducing the ohmic resistance, which further improves ft and, consequently, fmax.

[0062] <Fourth Embodiment> A semiconductor device according to a fourth embodiment of the present invention will be described with reference to Figure 4.

[0063] <Configuration of semiconductor device> In the semiconductor device 40 according to this embodiment, as shown in Figure 4, a high dielectric material 412 is selectively provided between the gate electrode 410 and the barrier layer 104 in the barrier recess portion 411. The other configurations are the same as in the first embodiment.

[0064] Here, the high dielectric material 412 can be, for example, Al2O3, HfO2, ZrO2, HfSiO4, etc. The thickness of the high dielectric material 412 is 20-50% of the depth of the recess in the barrier recess portion 411.

[0065] According to the semiconductor device of this embodiment, in addition to the effects of the first embodiment, leakage current can be reduced even if the distance between the gate electrode and the channel layer is shortened, because an insulating high-dielectric material is arranged.

[0066] <Fifth Embodiment> A semiconductor device according to a fifth embodiment of the present invention will be described with reference to Figure 5.

[0067] <Configuration of semiconductor device> As shown in Figure 5, the semiconductor device 50 according to this embodiment is provided with a barrier recess 511 over the entire area of ​​the gate electrode 510.

[0068] In detail, the recess of the barrier recess 511 has a certain depth in a predetermined region on the source electrode 108 side of the gate electrode 510, and gradually becomes shallower towards the end on the drain electrode 109 side of the gate electrode 510.

[0069] Here, the configuration of the recess in the barrier recess 511 is not limited to this, and it may also be configured to become continuously shallower from the end of the barrier recess 511 on the source electrode 108 side to the end on the drain electrode 109 side.

[0070] In other words, in the barrier recess 511, the thickness of the barrier layer 504 directly beneath the gate electrode 510 increases continuously from the end on the source electrode 108 side to the end on the drain electrode 109 side.

[0071] According to the semiconductor device of this embodiment, in addition to the effects of the first embodiment, the electric field strength at the drain electrode end of the gate electrode can be easily mitigated by optimizing the shape of the recess in the barrier recess (depth from the source electrode end to the drain electrode end). This further improves ft, and consequently improves fmax.

[0072] Furthermore, in the semiconductor device according to this embodiment, as shown in Figure 6, the recess of the barrier recess portion 611 may have a sloping structure in which the recess becomes linearly shallower from the end on the source electrode 108 side to the end on the drain electrode 109 side.

[0073] In the embodiments of the present invention, an example using HEMT as the semiconductor device is shown, but the invention is not limited to this and can be applied to field-effect transistors such as MOSFETs (Metal-oxide-semiconductor field-effect transistors) and MISFETs (Metal-Insulator-Semiconductor FETs).

[0074] For example, as shown in Figure 7, the MOSFET 70 comprises a Si substrate 701, a p-type semiconductor (Si) layer 702, an n-type source region 703, an n-type drain region 704, an oxide film (insulating film or channel control layer) 705, a source electrode 706, a drain electrode 707, and a gate electrode 708. An inversion layer (channel) 709 is also formed, and electrons travel as carriers.

[0075] In the MOSFET 70, the oxide film (insulating film) 705 has a recess in a part of its surface (one region), and the gate electrode 708 is formed on the surface of the oxide film 705 including the recess. As a result, the oxide film 705 directly beneath the gate electrode 708 is thin in a predetermined region (one region) and thick in other regions. Here, the portion consisting of the gate electrode 708 and the oxide film 705 in the predetermined region (one region) is the barrier recess 711 (dotted rectangle in the figure). The barrier recess 711 is located on the source electrode 706 side of the gate electrode 708.

[0076] Here, an example using a p-type semiconductor layer, an n-type source region, and an n-type drain region is shown, but an n-type semiconductor layer, a p-type source region, and a p-type drain region may also be used. In this case, holes act as carriers.

[0077] Based on the above, in the semiconductor device according to the embodiment of the present invention, in the layer disposed between the region (channel) on which carriers travel between the source electrode and the drain electrode and the gate electrode, a recess is provided at least on a part of the interface with the gate electrode on the source electrode side.

[0078] This makes it possible to suppress the increase in drain conductance due to hot electron generation without increasing the drain resistance, thereby realizing a field-effect transistor with good high-frequency characteristics.

[0079] In the embodiments of the present invention, examples of the structure, dimensions, materials, etc., of each component in the configuration and manufacturing method of the semiconductor device are shown, but the invention is not limited to these examples. Any configuration that performs the function and provides the desired effect of the semiconductor device is acceptable. [Industrial applicability]

[0080] The present invention relates to a semiconductor device having a field-effect transistor structure and can be applied to technologies using terahertz waves, such as high-speed wireless communication, non-destructive internal inspection, material analysis, and atmospheric sensing. [Explanation of Symbols]

[0081] 10 Semiconductor Devices 103 channels (layers) 104 Channel control layer (barrier layer) 108 Source Electrode 109 Drain electrode 110 Guard Station

Claims

1. A field-effect transistor comprising a gate electrode between a source electrode and a drain electrode, wherein carriers travel between the source electrode and the drain electrode, A channel control layer is provided between the channel on which the carrier travels and the gate electrode. In the channel control layer, a recess is provided on at least a portion of the surface in contact with the gate electrode on the source electrode side. A portion of the gate electrode is filled into the recess. The channel control layer comprises a first channel control layer located on the channel side and a second channel control layer located on the gate electrode side. The band gap of the first channel control layer is larger than the band gap of the second channel control layer. The depth of the recess is greater than or equal to the thickness of the second channel control layer and less than the thickness of the channel control layer. A semiconductor device characterized by the following features.

2. In the channel control layer, the recess becomes shallower from the source electrode end towards the drain electrode end. The semiconductor device according to feature 1.

3. In order, the channel layer that functions as the channel, The channel control layer is provided, The channel control layer is sequentially provided with a first cap layer and the source electrode on one region of the channel control layer. The channel control layer is then further provided with a second cap layer and the drain electrode, in order above the other regions of the channel control layer. The channel layer is composed of a first semiconductor, The channel control layer is composed of a second semiconductor having a larger band gap than the first semiconductor. The semiconductor device according to claim 1 or 2.

4. The channel control layer has a δ-doped layer, The recess is located deeper than the position of the δ-doped layer from the surface in contact with the gate electrode. The semiconductor device according to claim 3.

5. A high dielectric material is placed at the boundary between the channel control layer and the gate electrode in the recess. The semiconductor device according to claim 3.

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