Quantum devices and methods for manufacturing quantum devices

Abstract

This quantum device comprises a higher-order topological insulator layer and a superconductor layer. The higher-order topological insulator layer has: a first surface and a second surface which are parallel to each other; a third surface intersecting the second surface and positioned closer to the first surface than to the second surface; and a fourth surface intersecting the third surface and parallel to the first surface and the second surface. The superconductor layer is formed on a line of intersection between a plane including the third surface and the first surface.

Description

[Technical Field]

[0001] This disclosure relates to quantum devices and methods for manufacturing quantum devices. [Background technology]

[0002] Research is being conducted on quantum computing devices using Majorana particles. A structure combining a two-dimensional topological insulator and an s-wave superconductor has been proposed as a structure for generating Majorana particles. As the two-dimensional topological insulator, a monolayer of WTe2, a layered material of transition metal ditellide, is being used. Furthermore, research is also being conducted on higher-order topological insulator layers composed of multilayer WTe2. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-96107 [Patent Document 2] Special Publication No. 2020-511780 [Patent Document 3] Japanese Patent Publication No. 2013-247267 [Patent Document 4] U.S. Patent Application No. 2021 / 0257536 [Patent Document 5] U.S. Patent Application No. 2019 / 0013457 [Non-patent literature]

[0004] [Non-Patent Document 1] Z. Wang, et al., Phys. Rev. Lett. 123, 186401 (2019) [Non-Patent Document 2] Y.-B. Choi et al., Nat. Mater. 19, 974 (2020) [Overview of the project] [Problems that the invention aims to solve]

[0005] In the research on conventional higher-order topological insulator layers, the focus has been on Majorana particles that appear in one-dimensional conduction channels (hinge helical channels) formed on the edges of cuboid-shaped higher-order topological insulator layers. However, when actually forming a higher-order topological insulator layer, the atomic arrangement on the edges is more likely to be disordered compared to that inside or on the surfaces. Therefore, the Majorana particles that appear on the edges may become unstable.

[0006] An object of the present disclosure is to provide a quantum device capable of obtaining stable Majorana particles and a method for manufacturing the quantum device.

Means for Solving the Problem

[0007] According to one aspect of the present disclosure, there is provided a quantum device having a higher-order topological insulator layer and a superconductor layer. The higher-order topological insulator layer has a first surface and a second surface parallel to each other, a third surface intersecting the second surface and located on the first surface side of the second surface, and a fourth surface intersecting the third surface and parallel to the first surface and the second surface. The superconductor layer is formed on the intersection line between the plane including the third surface and the first surface. [[ID=​​​​​​​​​​​​​​​​​​​​​​ [Figure 5] Figure 5 is a bottom view showing the higher-order topological insulator layer and the superconductor layer in the first embodiment. [Figure 6] Figure 6 is a cross-sectional view (part 1) showing a method for manufacturing the quantum device 1 according to the first embodiment. [Figure 7] Figure 7 is a cross-sectional view (part 2) showing a method for manufacturing the quantum device 1 according to the first embodiment. [Figure 8] Figure 8 is a cross-sectional view (part 3) showing a method for manufacturing the quantum device 1 according to the first embodiment. [Figure 9] Figure 9 is a cross-sectional view (part 4) showing a method for manufacturing the quantum device 1 according to the first embodiment. [Figure 10] Figure 10 is a cross-sectional view (part 5) showing a method for manufacturing the quantum device 1 according to the first embodiment. [Figure 11] Figure 11 is a diagram (part 1) showing the model used in calculations for a one-dimensional conduction channel. [Figure 12] Figure 12 is a diagram (part 2) showing the model used in calculations for a one-dimensional conduction channel. [Figure 13] Figure 13 is a diagram (part 1) showing the calculation results for a higher-order topological insulator layer. [Figure 14] Figure 14 is a diagram (part 2) showing the calculation results for the higher-order topological insulating layer. [Figure 15] Figure 15 is a plan view showing a quantum device according to the second embodiment. [Figure 16] Figure 16 is a cross-sectional view showing a quantum device according to the second embodiment. [Figure 17] Figure 17 is a cross-sectional view showing a quantum device according to the third embodiment. [Figure 18] Figure 18 is a perspective view showing a higher-order topological insulator layer in the fourth embodiment. [Figure 19] Figure 19 is a bottom view showing the higher-order topological insulator layer and the superconductor layer in the fourth embodiment. [Modes for carrying out the invention]

[0010] Embodiments of this disclosure will be described in detail below with reference to the attached drawings. In this specification and drawings, components having substantially the same functional configuration will be denoted by the same reference numerals to avoid redundant explanations. In this disclosure, the X1-X2 direction, Y1-Y2 direction, and Z1-Z2 direction are mutually orthogonal directions. A plane including the X1-X2 direction and the Y1-Y2 direction is described as the XY plane, a plane including the Y1-Y2 direction and the Z1-Z2 direction is described as the YZ plane, and a plane including the Z1-Z2 direction and the X1-X2 direction is described as the ZX plane. For convenience, the Z1-Z2 direction is considered the up and down direction, with the Z1 side being the upper side and the Z2 side being the lower side. Furthermore, a plan view means viewing the object from the Z1 side, and a planar shape means the shape of the object as viewed from the Z1 side.

[0011] (First Embodiment) A first embodiment will be described. The first embodiment relates to a quantum device. Figure 1 is a plan view showing a quantum device according to the first embodiment. Figures 2 and 3 are cross-sectional views showing the quantum device according to the first embodiment. Figure 4 is a perspective view showing a higher-order topological insulator layer in the first embodiment. Figure 5 is a bottom view showing the higher-order topological insulator layer and the superconductor layer in the first embodiment. In Figure 1, the protective layer is seen through. Figure 2 corresponds to a cross-sectional view along the line II-II in Figure 1. Figure 3 corresponds to a cross-sectional view along the line III-III in Figure 1.

[0012] The quantum device 1 according to the first embodiment mainly comprises a substrate 300, a superconducting layer 200, and a higher-order topological insulator layer 100.

[0013] The substrate 300 has, for example, a silicon (Si) substrate 310 and an insulating film 320. The insulating film 320 is formed on the silicon substrate 310. The insulating film 320 is, for example, a silicon oxide film. The substrate 300 is a so-called oxide film-coated substrate. The shape of the substrate 300 is, for example, a rectangular parallelepiped with two planes parallel to the XY plane, two planes parallel to the YZ plane, and two planes parallel to the ZX plane, with the X1-X2 direction being the longitudinal direction and the Y1-Y2 direction being the short direction.

[0014] The superconducting layer 200 is provided on the insulating film 320. The shape of the superconducting layer 200 is, for example, a rectangular parallelepiped with two planes parallel to the XY plane, two planes parallel to the YZ plane, and two planes parallel to the ZX plane, with the X1-X2 direction being the longitudinal direction and the Y1-Y2 direction being the short direction. The superconducting layer 200 is, for example, an aluminum (Al) layer or a niobium (Nb) layer.

[0015] The higher-order topological insulator layer 100 has a first surface 111, a second surface 112, and a fourth surface 114 parallel to the XY plane, a third surface 113, a fifth surface 115, and a sixth surface 116 parallel to the YZ plane, and a seventh surface 117 and an eighth surface 118 parallel to the ZX plane. The higher-order topological insulator layer 100 is a multilayer WTe2 (tungsten ditelluride) layer. The a-axis of WTe2 is parallel to the Y1-Y2 direction, the b-axis is parallel to the X1-X2 direction, and the c-axis is parallel to the Z1-Z2 direction. Here, the a-axis, b-axis, and c-axis are defined as shown in Figure 1(a) of Non-Patent Literature 2.

[0016] The shapes of the first face 111, the second face 112, and the fourth face 114 are rectangles with two sides parallel to the X1-X2 direction and two sides parallel to the Y1-Y2 direction. The X2 side of the first face 111 and the X2 side of the second face 112 are in the same position in the X1-X2 direction. The Y1 side of the first face 111 and the Y1 side of the second face 112 are in the same position in the Y1-Y2 direction, and the Y2 side of the first face 111 and the Y2 side of the second face 112 are in the same position in the Y1-Y2 direction. The X1 side of the first face 111 and the X1 side of the fourth face 114 are in the same position in the X1-X2 direction. The edge on the Y1 side of the first face 111 and the edge on the Y1 side of the fourth face 114 are in the same position in the Y1-Y2 direction, and the edge on the Y2 side of the first face 111 and the edge on the Y2 side of the fourth face 114 are in the same position in the Y1-Y2 direction. In the Z1-Z2 direction, the fourth face 114 is closer to the first face 111 than to the second face 112, and closer to the second face 112 than to the first face 111. In other words, the fourth face 114 is located closer to the first face 111 than to the second face 112.

[0017] The shapes of the third face 113, the fifth face 115, and the sixth face 116 are rectangles having two sides parallel to the Y1-Y2 direction and two sides parallel to the Z1-Z2 direction. The third face 113 intersects with the second face 112 and the fourth face 114. The third face 113 intersects with the second face 112 and the fourth face 114, for example, at a right angle. The fifth face 115 intersects with the first face 111 and the second face 112. The fifth face 115 intersects with the first face 111 and the second face 112, for example, at a right angle. The sixth face 116 intersects with the first face 111 and the fourth face 114. The sixth face 116 intersects with the first face 111 and the fourth face 114, for example, at a right angle.

[0018] The shapes of faces 7117 and 8118 are hexagons with three sides parallel to the Z1-Z2 direction and three sides parallel to the X1-X2 direction. Both faces 7117 and 8118 intersect with faces 111, 212, 313, 414, 5115, and 6116. Both faces 7117 and 8118 intersect with faces 111, 212, 313, 414, 5115, and 6116, for example, at a right angle. Face 7117 is on the Y1 side of face 8118.

[0019] Thus, the higher-order topological insulator layer 100 has a three-dimensional shape such that a step is formed in a rectangular parallelepiped. In the higher-order topological insulator layer 100, one-dimensional conduction channels are formed at edges 121, 122, and 123, which are shown by thick lines in Figure 4. Specifically, one-dimensional conduction channels are formed at edge 121, which corresponds to the intersection of the first face 111 and the fifth face 115; at edge 122, which corresponds to the intersection of the fourth face 114 and the sixth face 116; and at edge 123, which corresponds to the intersection of the second face 112 and the third face 113. Furthermore, in the higher-order topological insulator layer 100, a one-dimensional conduction channel is also formed at the intersection 124 between the plane containing the third face 113 and the first face 111.

[0020] The higher-order topological insulator layer 100 is provided above the substrate 300 such that its first surface 111 is in contact with the upper surface of the superconductor layer 200. The seventh surface 117 is on the Y1 side of the plane on the Y1 side of the superconductor layer 200, and the eighth surface 118 is on the Y2 side of the plane on the Y2 side of the superconductor layer 200. Also, the fifth surface 115 is on the X1 side of the plane on the X2 side of the superconductor layer 200, and the sixth surface 116 is on the Y2 side of the plane on the Y1 side of the superconductor layer 200. The superconductor layer 200 is close to the intersection line 124. In other words, the intersection line 124 is within the range of the proximity effect of the superconductor layer 200. To put it another way, the superconductor layer 200 is formed on the intersection line 124 between the plane containing the third surface 113 and the first surface 111. Furthermore, when viewed from a direction perpendicular to the first surface 111, the intersection line 124 has a portion that extends beyond the superconducting layer 200.

[0021] A protective layer 131 is formed covering the surface of the higher-order topological insulator layer 100. The protective layer 131 is, for example, a native oxide film of WTe2.

[0022] In this embodiment, a one-dimensional conduction channel is generated at the intersection line 124 between the plane containing the third surface 113 of the higher-order topological insulator layer 100 and the first surface 111. Furthermore, because the superconductor layer 200 is in close proximity to the intersection line 124, Majorana particles 11 appear at the intersection line 124. For example, Majorana particles 11 appear in the portion of the intersection line 124 that extends beyond the superconductor layer 200.

[0023] One-dimensional conduction channels are also formed on edges 121, 122, and 123, but the arrangement of atoms on edges 121, 122, and 123 is prone to disorder. In contrast, since the intersection line 124 is located inside the first surface 111, the arrangement of atoms on the intersection line 124 is stable. Therefore, according to the first embodiment, stable Majorana particles can be obtained.

[0024] Next, a method for manufacturing the quantum device 1 according to the first embodiment will be described. Figures 6 to 10 are cross-sectional views showing the method for manufacturing the quantum device 1 according to the first embodiment.

[0025] First, as shown in Figure 6, a substrate 300 is prepared, and a superconducting layer 200 is formed on the insulating film 320 of the substrate 300. The superconducting layer 200 can be formed, for example, by a lift-off method using a mask. Examples of mask materials include polymethyl methacrylate (PMMA).

[0026] Next, a higher-order topological insulator layer 100A is provided on the superconductor layer 200. The higher-order topological insulator layer 100A will later become the higher-order topological insulator layer 100. The higher-order topological insulator layer 100A can be provided on the superconductor layer 200, for example, as follows.

[0027] First, a single crystal of WTe2 is prepared by reacting tungsten (W) and tellurium (Te) in a vacuum-sealed tube. Next, the WTe2 single crystal is thinned by repeatedly cleaving it using adhesive tape. As a result of thinning, multiple single crystals dispersed in an island-like manner are obtained from a single single crystal. Subsequently, these multiple single crystals are pressed onto a silicon substrate with an oxide film (different from substrate 300) and heated. As a result, a sample is obtained in which multiple micron-sized single crystals are scattered on the silicon substrate with an oxide film. Then, from among the multiple single crystals, one suitable for forming the higher-order topological insulator layer 100 in terms of thickness and planar shape is selected as the higher-order topological insulator layer 100A. Subsequently, the higher-order topological insulator layer 100A is attached to a polymer dome tool with an adhesive layer and lifted. The polymer dome tool with an adhesive layer is made, for example, by dropping a droplet of polydimethylsiloxane (PDMS) onto a glass substrate to form a dome shape, and then attaching a polymer film on top of it. A polymer film is, for example, a polycarbonate (PC) film.

[0028] Next, the higher-order topological insulator layer 100A, which is bonded to the polymer dome tool with an adhesive layer, is pressed onto the superconductor layer 200, and the polymer film is dissolved by heating. If the polymer film is a PC film, for example, the heating temperature is 180°C. As a result, the higher-order topological insulator layer 100A is provided on the superconductor layer 200 together with the polymer film. After that, the polymer film is removed. If the polymer film is a PC film, for example, the polymer film can be removed by dissolving it with chloroform.

[0029] The higher-order topological insulator layer 100A may be formed directly, for example, by molecular beam epitaxy (MBE) or pulse laser deposition (PLD). In this case, for example, a contact mask or the like may be used to ensure that the higher-order topological insulator layer 100A is formed only at the desired location.

[0030] After providing a higher-order topological insulator layer 100A on the superconductor layer 200, an electron beam resist film 50 covering the higher-order topological insulator layer 100A and the superconductor layer 200 is formed on the insulating film 320, as shown in Figure 7. The material for the electron beam resist film 50 is, for example, ZEP-520A from Nippon Zeon Co., Ltd. or XR-1541 from Dow Corning. The electron beam resist film 50 can be formed, for example, by a spin coating method.

[0031] Next, as shown in Figure 8, an opening 51 is formed in the electron beam resist film 50 by exposure and development using an electron beam lithography apparatus, exposing the region in which the fourth surface 114 will be formed.

[0032] Subsequently, as shown in Figure 9, milling with argon (Ar) molecules is performed using a reactive ion etching apparatus to form the third surface 113, the fourth surface 114, and the sixth surface 116 on the higher-order topological insulator layer 100A. The remaining portion of the higher-order topological insulator layer 100A becomes the second surface 112. As a result, the higher-order topological insulator layer 100 is obtained from the higher-order topological insulator layer 100A. During milling, recesses may be formed in the superconductor layer 200 and the substrate 300.

[0033] Next, as shown in Figure 10, the electron beam resist film 50 is removed and a protective layer 131 is formed on the surface of the higher-order topological insulator layer 100. The protective layer 131 can be formed, for example, by natural oxidation. If the sixth surface 116 is not planar in the process shown in Figure 9, the sixth surface 116 may be made planar by processing using another mask after the electron beam resist film 50.

[0034] In this way, the quantum device 1 according to the first embodiment can be manufactured.

[0035] Here, we will explain the calculations performed by the inventors of the present invention for a one-dimensional conduction channel of WTe2. In these calculations, the Hamiltonian H(k) of formula (1) is used (see Non-Patent Documents 1 and 2). Here, m1, m2, m3, ν a ν b νc , λ b , λ c , γ x , γ z and β a are parameters specific to the substance, and μi, τi, and σi are 2×2 Pauli matrices.

[0036]

Number

[0037] Then, as shown in FIG. 11, the Hamiltonian H(k) is made finite-sized to the size where the number of sites in the direction parallel to the b-axis of WTe2 is N<00000o9>and the number of sites in the direction parallel to the c-axis is N c (see Equation 2).

[0038]

Number

[0039] Next, the matrix H lattice (k a ) in Equation (2) is diagonalized. At this time, m1, m2, m3, ν a , ν b , ν c , λ b , λ c , γ x , γ z and β a are substituted with the parameters specific to WTe2. In this way, 8×N a ×N b ×N c eigenvalues E n (k a ) and eigenvectors Ψ n (k a ) are obtained for the wave number k

[0040] After that, the eigenenergy (eigenvalue E n (k a )) is plotted against the wave number k a It should be noted that there may be some inaccuracies in the translation due to the complexity and potential ambiguity of the original text, especially in the context of specific physical and mathematical notations. It is recommended to cross-reference with the original text and relevant knowledge for a more accurate understanding.Plotting it as a function of E yields the energy dispersion of the entire system. Furthermore, the energy dispersion is linear with respect to wavenumber (E n (k a )∝k a The square of the absolute value of the eigenvector corresponding to state n such that (|Ψ) n (k a )| 2 By plotting the contour lines of WTe2, we can determine where the electrons are located.

[0041] The calculation results for the higher-order topological insulator layer 100 are shown in Figures 13 and 14. Figures 13 and 14 show that brighter areas indicate a higher likelihood of electron presence. In this calculation, as shown in Figure 12, the number of sites N corresponds to the distance between the third surface 113 and the fifth surface 115. b1 Let 50 be the number of sites N, which corresponds to the distance between the third surface 113 and the sixth surface 116. b2 Let 50 be the number of sites N, which corresponds to the distance between the first surface 111 and the second surface 112. c1 Let 5 be the number of sites N, which corresponds to the distance between the first surface 111 and the fourth surface 114. c2 We set this to 2. As shown in Figure 13, electrons are likely to be present not only in the parts corresponding to edge 121 and edge 122, but also in the parts corresponding to edge 123 and intersection line 124, as shown in Figure 14. From these calculation results, it can be seen that a one-dimensional conduction channel is formed at intersection line 124.

[0042] (Second Embodiment) A second embodiment will now be described. The second embodiment differs from the first embodiment mainly in the configuration between the substrate 300 and the superconducting layer 200. Figure 15 is a plan view showing the quantum device according to the second embodiment. Figure 16 is a cross-sectional view showing the quantum device according to the second embodiment. In Figure 15, the protective layer is visible through the device. Figure 16 corresponds to a cross-sectional view along the line XVI-XVI in Figure 15.

[0043] In the quantum device 2 according to the second embodiment, a hexagonal boron nitride (h-BN) layer 400 is provided on the insulating film 320 of the substrate 300, and a superconductor layer 200 and a higher-order topological insulator layer 100 are provided on the hexagonal boron nitride layer 400. The hexagonal boron nitride layer 400 can be fabricated, for example, from a single crystal of h-BN by the same method as the higher-order topological insulator layer 100A in the first embodiment. The hexagonal boron nitride layer 400 may also be fabricated by chemical vapor deposition (CVD).

[0044] The other configurations are the same as in the first embodiment.

[0045] The same effects as the first embodiment can be obtained with the second embodiment. Furthermore, according to the second embodiment, since a hexagonal boron nitride layer 400 is provided, the electron transport characteristics of the higher-order topological insulator layer 100 can be improved.

[0046] (Third embodiment) A third embodiment will now be described. The third embodiment differs from the first embodiment mainly in the configuration of the protective layer. Figure 17 is a cross-sectional view showing a quantum device according to the third embodiment.

[0047] The quantum device 3 according to the third embodiment has a protective layer 132 instead of protective layer 131. Also, the electron beam resist film 50 used during the manufacturing process of the first embodiment remains without being removed. The protective layer 132 has a portion that fills the inside of the opening 51 and a portion that is on top of the electron beam resist film 50. The protective layer 131 is, for example, a parerin layer.

[0048] The other configurations are the same as in the first embodiment.

[0049] The same effects as the first embodiment can be obtained with the third embodiment. Furthermore, even if the electron beam resist film 50 is difficult to remove, it does not need to be removed. Therefore, damage associated with the removal of the electron beam resist film 50 can be avoided.

[0050] (Fourth Embodiment) A fourth embodiment will now be described. The fourth embodiment differs from the first embodiment mainly in the configuration of the higher-order topological insulator layer. Figure 18 is a perspective view showing the higher-order topological insulator layer in the fourth embodiment. Figure 19 is a bottom view showing the higher-order topological insulator layer and the superconductor layer in the fourth embodiment.

[0051] In the fourth embodiment, the higher-order topological insulator layer 100 has multiple sets of second surfaces 112, third surfaces 113, and fourth surfaces 114, in this case three sets. Therefore, there are multiple intersection lines 124 between the plane including the third surface and the first surface, in this case three. The superconducting layer 200 is adjacent to each of the intersection lines 124.

[0052] The other configurations are the same as in the first embodiment.

[0053] The same effects as the first embodiment can be obtained with the fourth embodiment. Furthermore, in the fourth embodiment, multiple one-dimensional conduction channels can be created on one of the first surfaces 111 of the higher-order topological insulator layer 100. Therefore, a large number of Majorana particles 11 can be generated. For this reason, the fourth embodiment is suitable for increasing the bit count and density of qubits.

[0054] Furthermore, it is not necessary for a single superconducting layer 200 to be in close proximity to all intersection lines 124; the superconducting layers adjacent to each intersection line 124 may be independent of each other and spaced apart. For example, three superconducting layers 200 may be provided.

[0055] The material of the higher-order topological insulator layer 100 is not limited to WTe2. For example, the material of the higher-order topological insulator layer 100 may be MoTe2 or Bi. When the higher-order topological insulator layer 100 is a multilayer MoTe2 layer, it is preferable that the intersection line 124 is parallel to the a-axis of MoTe2. When the higher-order topological insulator layer 100 is a multilayer Bi layer, it is preferable that the intersection line 124 is parallel to the

[0111] axis of Bi.

[0056] Although preferred embodiments have been described in detail above, the invention is not limited to the embodiments described above, and various modifications and substitutions can be made to the embodiments described above without departing from the scope of the claims. [Explanation of symbols]

[0057] 1, 2, 3: Quantum devices 11: Majorana particles 100, 100A: Higher-order topological insulating layer 121, 122, 123: edges 124: Intersection line 200: Superconductor layer 300: Circuit board 400: Hexagonal boron nitride layer

Claims

1. A higher-order topological insulating layer, A superconducting layer, It has, The aforementioned higher-order topological insulating layer is The first and second faces are parallel to each other, A third surface intersects with the second surface and is located closer to the first surface than the second surface, A fourth surface intersects with the third surface and is parallel to the first and second surfaces, It has, The quantum device is characterized in that the superconducting layer is formed on the intersection line between the plane including the third plane and the first plane.

2. The quantum device according to claim 1, characterized in that, when viewed from a direction perpendicular to the first surface, the intersection line has a portion that extends beyond the superconducting layer.

3. The quantum device according to claim 1 or 2, characterized in that the third surface intersects the second surface at a right angle.

4. The quantum device according to claim 1 or 2, characterized in that the fourth surface intersects the third surface at a right angle.

5. The aforementioned higher-order topological insulating layer has multiple sets of the second, third, and fourth surfaces, The quantum device according to claim 1 or 2, characterized in that the superconducting layer is close to the intersection line between the first surface and a plane containing each of the plurality of third surfaces.

6. The aforementioned higher-order topological insulator layer is multilayer WTe ２ Layer or multilayer MoTe ２ A quantum device according to claim 1 or 2, characterized by including a layer.

7. By processing a higher-order topological insulator layer having a first surface, A second surface parallel to the first surface, A third surface intersects with the second surface and is located closer to the first surface than the second surface, A fourth surface intersects with the third surface and is parallel to the first and second surfaces, The process of forming, A step of forming a superconducting layer on the intersection line of the plane including the third plane and the first plane, A method for manufacturing a quantum device, characterized by having the following features.

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