Chip carrier and chip processing method

Abstract

To provide a technology capable of stably holding a lateral surface of a chip when the chip electrostatically attracted to a chip carrier is separated from the chip carrier.SOLUTION: A chip carrier comprises a carrier substrate, a plurality of electrodes, and an operation terminal. The carrier substrate has a front surface having a plurality of attraction parts each being in contact with a chip to electrostatically attract the chip, and a rear surface opposite to the front surface. The plurality of electrodes are provided on the carrier substrate to individually generate an attraction force for electrostatically attracting the chip for each attraction part. The operation terminal is provided on the carrier substrate so as to be connected with an attraction force control part that controls the attraction force. The front surface of the carrier substrate has a recessed part recessed more than the attraction part on a circumferential edge of each of the plurality of attraction parts.SELECTED DRAWING: Figure 9

Description

Technical Field

[0001] The present disclosure relates to a chip carrier and a chip processing method.

Background Art

[0002] The substrate carrier described in Patent Document 1 includes a doped semiconductor substrate, a plurality of electrostatic field generation circuits that generate an electrostatic field, and a charging interface. Each electrostatic field generation circuit includes a positive electrode, a negative electrode, and a bias electrode. The charging interface turns on or off the electrostatic field by charging or discharging each electrostatic field generation circuit.

[0003] The substrate carrier described in Patent Document 2 includes an electrical insulating layer and an electrode portion embedded inside the electrical insulating layer. A part of the electrode portion is exposed on the back surface of the substrate carrier and functions as a connection terminal connected to each switch of the voltage control unit.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0005] One aspect of the present disclosure provides a technique capable of stably holding the side surface of a chip when separating the chip electrostatically adsorbed to a chip carrier from the chip carrier.

Means for Solving the Problems

[0006] A chip carrier according to one aspect of the present disclosure is The chip carrier comprises an insulating carrier substrate having a surface with multiple adsorption portions that contact a chip and electrostatically adsorb the chip, and a back surface facing the opposite direction from the surface; a plurality of electrodes embedded inside the carrier substrate, each generating an adsorption force for electrostatically adsorbing the chip; and an operating terminal provided on the carrier substrate and connected to an adsorption force control unit that controls the adsorption force. The surface of the carrier substrate has recesses at the periphery of each of the plurality of adsorption portions that are recessed more than the adsorption portion. The chip carrier has through holes in the adsorption portions that penetrate the carrier substrate from the surface to the back surface. The electrodes are arranged to surround the through holes.

Effects of the Invention

[0007] According to one aspect of this disclosure, the side surface of a chip can be stably held when separating a chip electrostatically attached to a chip carrier from the chip carrier. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 is a plan view showing an example of a second chip processing system. [Figure 2] Figure 2(A) is a cross-sectional view showing an example of a chip mounted on a frame via tape, Figure 2(B) is a cross-sectional view showing an example of a chip carrier, and Figure 2(C) is a cross-sectional view showing an example of a chip electrostatically attached to a chip carrier. [Figure 3] Figure 3 is a plan view showing an example of an adsorption area and recess on the surface of a carrier substrate. [Figure 4] Figure 4 is a plan view showing modified examples of the adsorption portion and recess on the surface of the carrier substrate. [Figure 5] Figure 5 is a cross-sectional view showing an example of a chip array device. [Figure 6] Figure 6 is a plan view showing an example of the first chip processing system. [Figure 7] Figure 7(A) is a cross-sectional view showing an example of a device substrate, Figure 7(B) is a cross-sectional view showing an example of a chip after the protective film has been removed, and Figure 7(C) is a cross-sectional view showing an example of a substrate with a chip attached. [Figure 8] Figure 8 is a cross-sectional view showing an example of a tip cleaning device. [Figure 9] Figure 9 is a cross-sectional view showing an example of a chip bonding apparatus. [Figure 10] Figure 10 is a cross-sectional view showing an example of a gas supply pipe. [Figure 11] Figure 11(A) is a cross-sectional view showing an example of the operation of the first contact position adjustment unit, Figure 11(B) is a cross-sectional view showing an example of the operation following Figure 11(A), and Figure 11(C) is a cross-sectional view showing an example of the operation following Figure 11(B). [Modes for carrying out the invention]

[0009] Embodiments of this disclosure will be described below with reference to the drawings. In each drawing, the same or corresponding components are denoted by the same reference numerals, and their descriptions may be omitted. In this specification, the X-axis, Y-axis, and Z-axis directions are perpendicular to each other. The X-axis and Y-axis directions are horizontal, and the Z-axis direction is vertical.

[0010] An example of the second chip processing system 201 will be described with reference to Figures 1 to 5. As shown in Figures 2(A) to 2(C), the second chip processing system 201 transfers the chips CP mounted on the frame FR via tape TP from tape TP to the chip carrier 10. This rearranges the chips CP.

[0011] The processing by the second chip processing system 201 is performed before the processing by the first chip processing system 101, which will be described later. The first chip processing system 101 mounts the chip CP onto the device substrate W. As a result, the first device Wb on the device substrate W and the second device CPb on the chip CP are electrically connected (see Figure 7(C)).

[0012] In this embodiment, the first chip processing system 101 and the second chip processing system 201 are provided separately, but they may be provided as an integrated unit. For example, the chip arrangement device 230 of the second chip processing system 201 may be incorporated into the first chip processing system 101.

[0013] Multiple chips CP, as shown in Figure 2(A), are fed into the second chip processing system 201. The multiple chips CP are adhered to a tape TP, and the outer circumference of the tape TP is mounted on a frame FR. The multiple chips CP are arranged in the opening of the frame FR. The multiple chips CP are obtained by dicing the substrate, that is, by dividing the substrate into individual pieces.

[0014] Chip CP has a lower base substrate CPa and a second device CPb formed on the lower base substrate CPa. The lower base substrate CPa is, for example, a silicon wafer, a compound semiconductor wafer, or a glass substrate. The second device CPb includes semiconductor elements, circuits, terminals, etc. The second device CPb is disposed on the side opposite to the tape TP with respect to the lower base substrate CPa.

[0015] The second device CPb is covered with a protective film PF before the substrate is diced. The protective film PF protects the second device CPb, for example, when dicing the substrate. The protective film PF is singulated together with the substrate. The protective film PF is not particularly limited, but is preferably water-soluble. After dicing, the protective film PF can be removed by supplying pure water or the like to the water-soluble protective film PF.

[0016] The chip carrier 10 shown in FIG. 2(B) is carried into the second chip processing system 201. The chip carrier 10 electrostatically adsorbs and transports a plurality of chips CP. The plurality of chips CP are transported together with the chip carrier 10. The chip carrier 10 includes a carrier substrate 20, a plurality of electrodes 30, and a plurality of operation terminals 40.

[0017] The carrier substrate 20 has a front surface 21 and a back surface 22 opposite to the front surface 21. The front surface 21 of the carrier substrate 20 has a plurality of adsorption portions 21a that contact the chip CP and electrostatically adsorb the chip CP. The carrier substrate 20 insulates the plurality of electrodes 30 and maintains the charges supplied to each electrode 30.

[0018] A capacitor (not shown) may be provided on the carrier substrate 20. The capacitor accumulates the charges supplied to each electrode 30. The charges may be either positive charges or negative charges. The capacitor may recover the charges discharged from each electrode 30. The capacitor is connected to each electrode 30 via, for example, the operation terminal 40.

[0019] Charge may be supplied to each electrode 30 from outside the carrier substrate 20. Furthermore, charge may be discharged from each electrode 30 to the outside of the carrier substrate 20.

[0020] Multiple electrodes 30 are provided on the carrier substrate 20, and each electrode individually generates an adsorption force for electrostatically adsorbing the chip CP to each adsorption section 21a. An electrode 30 is provided for each adsorption section 21a. The electrodes 30 may be either unipolar or bipolar. The electrodes 30 are exposed on the surface 21 of the carrier substrate 20, but they do not have to be exposed and may be embedded inside the carrier substrate 20.

[0021] The operating terminal 40 is provided on the carrier substrate 20 and is connected to the second suction force control unit 239 (see Figure 5) or the first suction force control unit 139 (see Figures 9 and 11). Hereinafter, the first suction force control unit 139 and the second suction force control unit 239 may be collectively referred to as suction force control units 139 and 239.

[0022] The adsorption force control units 139 and 239 control the adsorption force by controlling the charge accumulated on the electrode 30. For example, the adsorption force control units 139 and 239 control the generation or disappearance of the adsorption force by controlling the supply or discharge of charge to the electrode 30. The adsorption force is either the Coulomb force or the Johnson-Rabec force.

[0023] The accumulation of charge on the electrode 30 generates an adsorption force. Subsequently, even after the connection between the operating terminal 40 and the second adsorption force control unit 239 is released, the operating terminal 40 maintains the state in which charge is accumulated on the electrode 30, thus maintaining the state in which an adsorption force is generated. Therefore, multiple chips CP can be transported together with the chip carrier 10.

[0024] As the charge is discharged from electrode 30, the adsorption force disappears. Subsequently, it becomes possible to separate the chip CP from the chip carrier 10. Since the generation and disappearance of the adsorption force are controlled by the supply and discharge of charge, the work efficiency of transferring the chip CP can be improved compared to when adhesive is applied and removed.

[0025] The operation terminal 40 is exposed on the back surface 22 of the carrier substrate 20 and is connected to the suction force control units 139 and 239 by wire. Alternatively, the operation terminal 40 and the suction force control units 139 and 239 may be connected wirelessly. Furthermore, the operation terminal 40 may be exposed on the front surface 21 or side surface of the carrier substrate 20.

[0026] An operating terminal 40 is provided individually for each suction unit 21a. Alternatively, one operating terminal 40 may be provided that is common to multiple suction units 21a. It is sufficient that the suction force control units 139 and 239 can individually control the suction force for each suction unit 21a.

[0027] Incidentally, the surface 21 of the carrier substrate 20 has recesses 21b that are recessed more deeply than the adsorption parts 21a at the periphery of each of the multiple adsorption parts 21a. As a result, as will be described in more detail later, as shown in Figure 9, the side holding head 133a inserted into the recesses 21b can hold the side surface CPe of the chip CP over its entire vertical direction. Therefore, the side surface CPe of the chip CP can be held stably, and the chip CP can be prevented from falling. In addition to the side surface CPe of the chip CP, the bottom surface (second surface CPd) of the chip CP may also be supported.

[0028] The chip carrier 10 may have a through-hole 50 in the suction part 21a that penetrates the carrier substrate 20 from the front surface 21 to the back surface 22. As a result, as will be described in more detail later, as shown in Figure 9 or Figure 11, a push pin 136 can be inserted into the through-hole 50 and the chip CP can be pushed with the push pin 136 to assist in separating the chip CP. Alternatively, as shown in Figure 10, gas can be supplied from the gas supply pipe 137 to the through-hole 50 and the chip CP can be pushed with the gas pressure to assist in separating the chip CP.

[0029] The electrodes 30 may be arranged to surround the through-hole 50. One electrode 30 may be arranged in a ring around the through-hole 50, or multiple electrodes 30 may be arranged at intervals around the through-hole 50. There may be three or more electrodes 30. By arranging the electrodes 30 to surround the through-hole 50, the chip CP can be stably electrostatically attracted to the adsorption part 21a.

[0030] As shown in Figure 3, the recesses 21b are formed in a mesh-like structure, and the adsorption portions 21a may be arranged in an island-like manner within the mesh of the recesses 21b. This makes it easier to discharge the cleaning solution from the recesses 21b when supplying cleaning solution to the chip CP for purposes such as removing the protective film PF, as will be described in more detail later, as shown in Figure 8.

[0031] The recess 21b extends to the periphery of the surface 21 of the carrier substrate 20 to facilitate the discharge of the cleaning fluid outside the carrier substrate 20. The depth of the recess 21b is generally uniform, but it may become deeper from the center of the surface 21 of the carrier substrate 20 towards the periphery. In the latter case, gravity can be used to discharge the cleaning fluid.

[0032] The suction portion 21a may be smaller than the chip CP. Compared to the case where the suction portion 21a is the same size as the chip CP, the positioning accuracy of the chip CP can be relaxed when rearranging multiple chip CPs on the chip carrier 10. If the suction portion 21a is smaller than the chip CP, even if the chip CP is slightly misaligned, the chip CP will extend beyond the suction portion 21a. Therefore, the side surface CPe of the chip CP can be held over its entire vertical direction.

[0033] The recess 21b may be formed over the entire periphery of the suction portion 21a, as shown in Figure 3, or it may be formed only on a part of the periphery of the suction portion 21a, as shown in Figure 4. In the latter case as well, the side retaining head 133a inserted into the recess 21b can hold the side CPe of the chip CP over its entire vertical direction, thereby stably holding the side CPe of the chip CP.

[0034] As shown in Figure 1, the second chip processing system 201 includes, for example, a second loading / unloading station 210, a second processing station 220, and a second control device 290. The second loading / unloading station 210 and the second processing station 220 are arranged in this order, from the negative X-axis side to the positive X-axis side.

[0035] The second loading / unloading station 210 is equipped with a mounting table 211. Cassettes C1 to C4 are placed on the mounting table 211. Cassette C1 contains a chip carrier 10. Cassette C2 contains a chip carrier 10 with multiple chips CP electrostatically attached. Cassette C3 contains multiple chips CP mounted on a frame FR via tape TP. Cassette C4 contains a used frame FR. A used frame FR is the frame FR that remains after multiple chips CP have been peeled off from tape TP. Chips CP may remain on the used frame FR.

[0036] The second loading / unloading station 210 comprises a third transport area 212, a third carrier transport arm 213, and a frame transport arm 214. The third transport area 212 is adjacent to the mounting table 211. The third carrier transport arm 213 holds and transports the chip carrier 10 in the third transport area 212. The frame transport arm 214 holds and transports the frame FR in the third transport area 212. The third carrier transport arm 213 and the frame transport arm 214 are capable of movement in the horizontal direction (both in the X-axis and Y-axis directions) and the vertical direction, as well as rotation around the vertical axis, respectively.

[0037] The second loading / unloading station 210 has a drive unit (not shown) for moving or rotating the third carrier transport arm 213 and the frame transport arm 214. The third carrier transport arm 213 and the frame transport arm 214 may be mounted on the same Y-axis slider and moved simultaneously in the Y-axis direction, or they may be mounted on different Y-axis sliders and moved independently in the Y-axis direction. When the third carrier transport arm 213 and the frame transport arm 214 are mounted on the same Y-axis slider, they may be stacked in the Z-axis direction. When the third carrier transport arm 213 and the frame transport arm 214 are mounted on different Y-axis sliders, the multiple Y-axis sliders are arranged offset in the Z-axis direction.

[0038] The third carrier transport arm 213 removes the chip carrier 10 from cassette C1 and transports it to the chip arrangement device 230. The third carrier transport arm 213 also removes the chip carrier 10, with multiple chips CP electrostatically attached, from the chip arrangement device 230 and stores it in cassette C2. The third carrier transport arm 213 that removes the chip carrier 10 from cassette C1 and the third carrier transport arm 213 that stores the chip carrier 10 in cassette C2 may be provided separately.

[0039] The frame transport arm 214 removes multiple chips CP along with the frame FR from the cassette C3 and transports them to the chip arrangement device 230. The frame transport arm 214 also removes the used frame FR from the chip arrangement device 230 and stores it in the cassette C4. The frame transport arm 214 that removes the frame FR from the cassette C3 and the frame transport arm 214 that stores the frame FR in the cassette C4 may be provided separately.

[0040] The second processing station 220 includes a chip arrangement device 230. The chip arrangement device 230 is adjacent to the third transport area 212. The chip arrangement device 230 rearranges the chips CP, which are mounted on the frame FR via tape TP, by transferring them from tape TP to the chip carrier 10. As shown in Figure 5, the chip arrangement device 230 includes, for example, a second carrier holding unit 231, a frame holding unit 232, and a chip transfer unit 233.

[0041] The second carrier holding unit 231 holds the chip carrier 10. The second carrier holding unit 231 holds the carrier substrate 20 horizontally from below, for example, with the surface 21 of the carrier substrate 20 facing upward. The second carrier holding unit 231 is capable of movement in the horizontal direction (both in the X-axis and Y-axis directions or only in the X-axis direction) and rotation around the vertical axis.

[0042] The frame holding unit 232 holds the frame FR with multiple chips CP mounted on it via tape TP. The frame holding unit 232 holds the frame FR horizontally from below, for example. The frame holding unit 232 is capable of movement in the horizontal direction (both in the X-axis and Y-axis directions or in the X-axis direction only) and rotation around the vertical axis.

[0043] The chip transfer unit 233 transfers chips CP from the tape TP provided at the opening of the frame FR held by the frame holding unit 232 to the chip carrier 10 held by the second carrier holding unit 231. The chip transfer unit 233 includes a collet 233a for holding chips CP and a collet moving mechanism 233b (see Figure 1) for moving the collet 233a. The collet 233a vacuum-suctions the chips CP. The collet 233a can move horizontally (in both the X-axis and Y-axis directions) and vertically, and can rotate about the vertical axis.

[0044] The collet 233a holds the chip CP from the side opposite to the tape TP. The chip CP has a first surface CPc and a second surface CPd that contacts the tape TP in the opposite direction to the first surface CPc. A protective film PF is pre-formed on the first surface CPc, and the collet 233a holds the chip CP via the protective film PF. This prevents contact between the chip CP and the collet 233a, and prevents contact damage to the chip CP. This is particularly effective when the first surface CPc of the chip CP includes a second device CPb.

[0045] With the collet 233a holding the chip CP from above, the collet moving mechanism 233b moves the collet 233a upward, thereby separating the chip CP from the tape TP. Subsequently, the collet moving mechanism 233b moves the collet 233a horizontally and then downward, placing the chip CP onto the chip carrier 10.

[0046] The chip CP is placed on the chip carrier 10 without being inverted. The second surface CPd of the chip CP contacts the adsorption portion 21a on the surface 21 of the carrier substrate 20. The adsorption portion 21a may be smaller than the second surface CPd of the chip CP, and the second surface CPd of the chip CP may extend beyond the adsorption portion 21a.

[0047] The chip arrangement device 230 may have push pins 236. The push pins 236 push up the chips CP from below via the tape TP. The collet 233a attracts the chips CP pushed up by the push pins 236. By pushing the chips CP to be separated higher than the surrounding chips CP, contact between the surrounding chips CP and the collet 233a can be suppressed.

[0048] The chip arrangement device 230 may have an expandable section, although it is not shown in the figure. The expandable section widens the spacing between adjacent chips CP by radially expanding the tape TP. This prevents adjacent chips CP from rubbing against each other.

[0049] The second carrier holding unit 231 is provided with, for example, a second contact terminal 238 and a second suction force control unit 239. The second contact terminal 238 contacts the operation terminal 40 of the chip carrier 10. Multiple second contact terminals 238 are provided corresponding to multiple operation terminals 40. The second suction force control unit 239 is connected to the operation terminal 40 of the chip carrier 10 via the second contact terminal 238 provided on the second carrier holding unit 231. The operation terminal 40 receives control signals transmitted from the second suction force control unit 239. The second suction force control unit 239 may be provided outside the second carrier holding unit 231, or it may be part of the second control device 290.

[0050] The second adsorption force control unit 239 controls the adsorption force while connected to the operating terminal 40 of the chip carrier 10. The second adsorption force control unit 239 controls the charge accumulated on the electrode 30. The second adsorption force control unit 239 generates an adsorption force by controlling the supply of charge to the electrode 30. The timing of supplying charge to the electrode 30 may differ for each adsorption unit 21a, or it may be the same for multiple adsorption units 21a.

[0051] Even after the chip arrangement device 230 transfers the chips CP from the tape TP to the chip carrier 10, the connection between the operation terminal 40 and the second suction force control unit 239 is released, but the operation terminal 40 maintains a state in which charge is accumulated on the electrode 30, and maintains a state in which suction force is generated. Therefore, multiple chips CP can be transported together with the chip carrier 10.

[0052] The second control device 290 is, for example, a computer and comprises a CPU (Central Processing Unit) 291 and a storage medium 292 such as memory. The storage medium 292 stores programs that control various processes executed in the second chip processing system 201. The second control device 290 controls the operation of the second chip processing system 201 by causing the CPU 291 to execute the programs stored in the storage medium 292.

[0053] Next, an example of a chip processing method using the second chip processing system 201 will be described. The following chip processing method is performed under the control of the second control device 290.

[0054] First, the third carrier transport arm 213 of the second loading / unloading station 210 removes the chip carrier 10 from the cassette C1 and transports it to the chip arrangement device 230. Once the second carrier holding unit 231 of the chip arrangement device 230 holds the chip carrier 10, the third carrier transport arm 213 exits the chip arrangement device 230.

[0055] Furthermore, the frame transport arm 214 of the second loading / unloading station 210 removes multiple chips CP along with the frame FR from the cassette C3 and transports them to the chip arrangement device 230. When the frame holding section 232 of the chip arrangement device 230 holds the frame FR, the frame transport arm 214 exits the chip arrangement device 230.

[0056] Next, the chip arrangement device 230 transfers the chips CP mounted on the frame FR via tape TP from tape TP to chip carrier 10 and rearranges the chips CP. The chip carrier 10 electrostatically attracts multiple chips CP.

[0057] Next, the third carrier transport arm 213 removes the chip carrier 10, which has multiple chips CP electrostatically attached to it, from the chip arrangement device 230 and stores it in the cassette C2. After that, the multiple chips CP, still electrostatically attached to the chip carrier 10, are supplied to the first chip processing system 101.

[0058] Furthermore, the frame transport arm 214 removes the used frame FR from the chip arrangement device 230 and stores it in the cassette C4. The frame FR is then reused.

[0059] An example of the first chip processing system 101 will be described with reference to Figures 6 to 10. As shown in Figures 7(A) to 7(C), the first chip processing system 101 separates the chip CP from the chip carrier 10 and mounts the separated chip CP onto the device substrate W to manufacture a substrate CW with a chip.

[0060] The device substrate W shown in Figure 7(A) is fed into the first chip processing system 101. The device substrate W has a base substrate Wa and a plurality of first devices Wb formed on the base substrate Wa. The base substrate Wa is, for example, a silicon wafer, a compound semiconductor wafer, or a glass substrate. The first devices Wb include semiconductor elements, circuits, or terminals. A plurality of first devices Wb are formed on the main surface Wc of the device substrate W.

[0061] The first chip processing system 101 may be loaded with the chip carrier 10 shown in Figure 7(B), but in this embodiment, the chip carrier 10 shown in Figure 2(B) is loaded. The chip carrier 10 electrostatically holds a plurality of chips CP. Each chip CP has a second device CPb on its first surface CPc that is electrically connected to a first device Wb.

[0062] The first surface CPc of the chip CP does not necessarily have to be covered with a protective film PF at the time of delivery, as shown in Figure 7(B). However, in this embodiment, it is covered with a protective film PF as shown in Figure 2(B). The protective film PF can protect the first surface CPc of the chip CP until just before mounting the chip CP, suppressing particle adhesion and scratching.

[0063] As shown in Figure 6, the first chip processing system 101 includes, for example, a first loading / unloading station 110, a first processing station 120, and a first control device 190. The first loading / unloading station 110 and the first processing station 120 are arranged in this order, from the negative X-axis side to the positive X-axis side.

[0064] The first loading / unloading station 110 is equipped with a mounting table 111. Cassettes C5 to C8 are placed on the mounting table 111. Cassette C5 contains the chip carrier 10 before the chip CP is separated. Cassette C6 contains the chip carrier 10 after the chip CP has been separated. Cassette C7 contains the device board W before the chip CP is mounted. Cassette C8 contains the device board W after the chip CP has been mounted.

[0065] The first loading / unloading station 110 comprises a second transport area 112, a second carrier transport arm 113, and a second substrate transport arm 114. The second transport area 112 is adjacent to the mounting table 111. The second carrier transport arm 113 holds and transports the chip carrier 10 in the second transport area 112. The second substrate transport arm 114 holds and transports the device substrate W in the second transport area 112. The second carrier transport arm 113 and the second substrate transport arm 114 are capable of movement in the horizontal direction (both in the X-axis and Y-axis directions) and the vertical direction, as well as rotation around the vertical axis.

[0066] The first loading / unloading station 110 has a drive unit (not shown) for moving or rotating the second carrier transport arm 113 and the second substrate transport arm 114. The second carrier transport arm 113 and the second substrate transport arm 114 may be mounted on the same Y-axis slider and moved simultaneously in the Y-axis direction, or they may be mounted on different Y-axis sliders and moved independently in the Y-axis direction. When the second carrier transport arm 113 and the second substrate transport arm 114 are mounted on the same Y-axis slider, they are stacked in the Z-axis direction. When the second carrier transport arm 113 and the second substrate transport arm 114 are mounted on different Y-axis sliders, the multiple Y-axis sliders are arranged offset in the Z-axis direction.

[0067] The second carrier transport arm 113 removes the chip carrier 10 from cassette C5 before separating the chip CP and transports it to the transition device 115. The second carrier transport arm 113 also removes the chip carrier 10 after separating the chip CP from the transition device 115 and stores it in cassette C6. The second carrier transport arm 113 that removes the chip carrier 10 from cassette C5 and the second carrier transport arm 113 that stores the chip carrier 10 in cassette C6 may be provided separately.

[0068] The second board transport arm 114 removes the device board W, before the chip CP is mounted, from the cassette C7 and transports it to the transition device 116. The second board transport arm 114 also removes the device board W, after the chip CP has been mounted, from the transition device 116 and stores it in the cassette C8. The second board transport arm 114 that removes the device board W from the cassette C7 and the second board transport arm 114 that stores the device board W in the cassette C8 may be provided separately.

[0069] The first loading / unloading station 110 includes transition devices 115 and 116. The transition devices 115 and 116 are positioned between the second transport area 112 of the first loading / unloading station 110 and the first transport area 122 of the first processing station 120, and are adjacent to both transport areas. The transition devices 115 and 116 may be stacked vertically to reduce the footprint of the first loading / unloading station 110.

[0070] The transition device 115 is used to place the chip carrier 10 before the chip CP is separated. The transition device 115 may also be used to place the chip carrier 10 after the chip CP has been separated. Separate transition devices 115 may be provided for before and after the separation of the chip CP, and multiple transition devices 115 may be provided for each stage.

[0071] The device substrate W before the chip CP is mounted is placed on the transition device 116. The device substrate W after the chip CP is mounted may also be placed on the transition device 116. Separate transition devices 116 may be provided for before and after the chip CP is mounted, and multiple transition devices 116 may be provided for each stage.

[0072] The first processing station 120 comprises a first transport area 122, a first carrier transport arm 123, and a first substrate transport arm 124. The first transport area 122 extends in the X-axis direction. The first carrier transport arm 123 holds and transports the chip carrier 10 in the first transport area 122. The first substrate transport arm 124 holds and transports the device substrate W in the first transport area 122. The first carrier transport arm 123 and the first substrate transport arm 124 are capable of movement in the horizontal direction (both in the X-axis and Y-axis directions) and the vertical direction, as well as rotation around the vertical axis.

[0073] The first processing station 120 has a drive unit (not shown) for moving or rotating the first carrier transport arm 123 and the first substrate transport arm 124. The first carrier transport arm 123 and the first substrate transport arm 124 may be mounted on the same X-axis slider and moved simultaneously in the X-axis direction, or they may be mounted on different X-axis sliders and moved independently in the X-axis direction. When the first carrier transport arm 123 and the first substrate transport arm 124 are mounted on the same X-axis slider, they are stacked in the Z-axis direction. When the first carrier transport arm 123 and the first substrate transport arm 124 are mounted on different X-axis sliders, the multiple X-axis sliders are arranged offset in the Z-axis direction.

[0074] The first carrier transport arm 123 removes the chip carrier 10 before the chip CP is separated from the transition device 115 and transports it to the chip bonding device 130 via the chip cleaning device 125. The first carrier transport arm 123 also removes the chip carrier 10 after the chip CP has been separated from the chip bonding device 130 and transports it to the transition device 115. The first carrier transport arm 123 that transports the chip carrier 10 before the chip CP is separated and the first carrier transport arm 123 that transports the chip carrier 10 after the chip CP has been separated may be provided separately.

[0075] The first substrate transport arm 124 removes the device substrate W before the chip CP is mounted from the transition device 116 and transports it to the chip bonding device 130 via the surface modification device 126 and the substrate cleaning device 127. The first substrate transport arm 124 also removes the device substrate W after the chip CP has been mounted from the chip bonding device 130 and transports it to the transition device 116. The first substrate transport arm 124 that transports the device substrate W before the chip CP is mounted and the first substrate transport arm 124 that transports the device substrate W after the chip CP has been mounted may be provided separately.

[0076] The first processing station 120 includes a chip cleaning device 125, a surface modification device 126, a substrate cleaning device 127, and a chip bonding device 130. The chip cleaning device 125, the surface modification device 126, the substrate cleaning device 127, and the chip bonding device 130 are adjacent to the first transport area 122 and are arranged on the positive or negative Y-axis side of the first transport area 122.

[0077] The chip cleaning device 125 cleans multiple chips CP that are electrostatically adsorbed to the chip carrier 10. After cleaning the chips CP, the chips CP can be bonded to the device substrate W to suppress the inclusion of foreign matter. The chip cleaning device 125 may also remove the protective film PF by supplying a cleaning solution to the chips CP. If the protective film PF is water-soluble, pure water such as DIW (deionized water) is supplied as the cleaning solution.

[0078] As shown in Figure 8, the chip cleaning device 125 includes, for example, a carrier holding unit 141, a rotation drive unit 142, a nozzle 143, and a cup 144. The carrier holding unit 141 holds the carrier substrate 20 horizontally from below with its surface 21 facing upward. The rotation drive unit 142 rotates the carrier substrate 20 together with the carrier holding unit 141. The nozzle 143 supplies cleaning fluid to multiple chips CP. The nozzle 143 may move in a direction perpendicular to the rotation centerline of the carrier holding unit 141. The cup 144 collects the cleaning fluid. The cleaning fluid collected in the cup 144 is discharged from the inside of the cup 144 to the outside by a drain unit (not shown).

[0079] According to this embodiment, as shown in Figure 3, the recesses 21b are formed in a mesh-like structure, and the adsorption portions 21a are arranged in an island-like manner within the mesh of the recesses 21b. This makes it easier to discharge the cleaning liquid from the recesses 21b when supplying the cleaning liquid to the chip CP. The recesses 21b extend to the periphery of the surface 21 of the carrier substrate 20 so that the cleaning liquid can be easily discharged outside the carrier substrate 20. The depth of the recesses 21b is uniform overall, but it may become deeper from the center of the surface 21 of the carrier substrate 20 towards the periphery. In the latter case, gravity can be used to discharge the cleaning liquid.

[0080] The tip cleaning device 125 may also have a cleaning head (not shown). The cleaning head is a brush or sponge, and scrubs multiple tips CP. The cleaning head may also apply ultrasonic waves to the liquid film formed between the multiple tips CP. The liquid film is formed when the nozzle 143 supplies cleaning fluid.

[0081] The surface modification apparatus 126 performs plasma treatment on the main surface Wc of the device substrate W. In the surface modification apparatus 126, for example, oxygen gas, which is the treatment gas, is excited and plasma-generated under reduced pressure and then ionized. The main surface Wc of the device substrate W is modified by irradiation of the oxygen ions with the main surface Wc. The treatment gas is not limited to oxygen gas; for example, nitrogen gas may also be used.

[0082] The substrate cleaning apparatus 127 cleans the main surface Wc of the device substrate W. For example, the substrate cleaning apparatus 127 rotates the device substrate W, which is held in a spin chuck, while supplying pure water (e.g., deionized water) onto the device substrate W. The pure water spreads across the entire main surface Wc by centrifugal force, cleaning the main surface Wc. The pure water imparts OH groups to the pre-modified main surface Wc. The hydrogen bonding between the OH groups allows the device substrate W and the chip CP to be bonded together.

[0083] The chip bonding apparatus 130 bonds the chip CP to the device substrate W. Specifically, the chip bonding apparatus 130 separates the chip CP from the chip carrier 10 and mounts the separated chip CP onto the device substrate W. The first device Wb on the device substrate W and the second device CPb on the chip CP are electrically connected. As shown in Figure 9, the chip bonding apparatus 130 includes, for example, a first carrier holding unit 131, a substrate holding unit 132, a pickup unit 133, and a mounting unit 134.

[0084] The first carrier holding unit 131 holds the chip carrier 10. The first carrier holding unit 131 holds the carrier substrate 20 horizontally from below, for example, with the surface 21 of the carrier substrate 20 facing upwards. The first carrier holding unit 131 is capable of movement in the horizontal direction (both in the X-axis and Y-axis directions) and rotation around the vertical axis.

[0085] The chip carrier 10 electrostatically attracts the chip CP. When the chip CP is electrostatically attracted, the attraction force can be eliminated by discharging the electric charge. Unlike when the chip CP is fixed with adhesive, there is no need to remove the adhesive. Therefore, the workability of transferring the chip CP from the chip carrier 10 to the device substrate W can be improved.

[0086] The substrate holding portion 132 holds the device substrate W. The substrate holding portion 132 holds the device substrate W horizontally from below, for example, with the main surface Wc of the device substrate W facing upwards. The substrate holding portion 132 is capable of movement in the horizontal direction (both in the X-axis and Y-axis directions) and rotation around the vertical axis.

[0087] The pickup unit 133 separates the chip CP from the chip carrier 10 held by the first carrier holding unit 131. The pickup unit 133 includes a side holding head 133a that holds the side surface CPe of the chip CP, and a first head moving mechanism 133b (see Figure 6) that moves the side holding head 133a. The side holding head 133a is capable of movement in the horizontal direction (both in the X-axis and Y-axis directions) and the vertical direction, as well as rotation around the vertical axis. In addition to the side surface CPe of the chip CP, the side holding head 133a may also support the bottom surface (second surface CPd) of the chip CP.

[0088] The side-holding head 133a holds the side CPe of the chip CP. For example, the side-holding head 133a has a pair of openable and closable claws, and holds the chip CP by gripping it with the pair of claws. Alternatively, the side-holding head 133a may use vacuum suction to hold the side CPe of the chip CP.

[0089] The side-holding head 133a does not hold the first surface CPc of the chip CP, but instead forms a gap between itself and the first surface CPc. This suppresses particle adhesion and scratching on the first surface CPc, even when the protective film PF is removed and the first surface CPc is exposed.

[0090] The side-holding head 133a is inserted into a recess 21b formed on the surface 21 of the carrier substrate 20. At this time, the pair of claws are open so as not to touch the chip CP. Subsequently, the pair of claws close to hold the chip CP in place.

[0091] The side-holding head 133a is inserted into the recess 21b, thereby holding the side CPe of the chip CP across its entire vertical surface. This allows for stable holding of the side CPe of the chip CP, preventing the chip CP from falling.

[0092] Subsequently, the first head movement mechanism 133b moves the side-holding head 133a upward. The side-holding head 133a is then removed from the recess 21b of the carrier substrate 20. As a result, the chip CP is separated from the chip carrier 10.

[0093] Subsequently, the chip CP is transferred from the side holding head 133a to the suction head 134a. The suction head 134a holds the second surface CPd of the chip CP by suction. After being separated from the chip carrier 10, the chip CP is inverted and then brought into contact with the device substrate W.

[0094] The mounting unit 134 mounts the chip CP, which has been separated from the chip carrier 10 by the pickup unit 133, onto the device substrate W held by the substrate holding unit 132. The mounting unit 134 includes a suction head 134a that adsorbs and holds the second surface CPd of the chip CP, and a second head moving mechanism 134b (see Figure 6) that moves the suction head 134a.

[0095] The suction head 134a is capable of moving horizontally (in both the X-axis and Y-axis directions) and vertically, as well as rotating about the horizontal axis (i.e., inverting upside down). The suction head 134a picks up the chip CP from above and then moves downwards in that state to mount the chip CP onto the main surface Wc of the device substrate W.

[0096] In this embodiment, the suction head 134a of the mounting unit 134 directly receives the chip CP from the side holding head 133a of the pickup unit 133, but it may also receive it via a transport unit (not shown). The transport unit transports the chip CP from the pickup unit 133 to the mounting unit 134. The transport unit may also invert the chip CP.

[0097] The chip bonding device 130 may have a push pin 136. The push pin 136 is inserted into the through hole 50 of the chip carrier 10 and assists in separating the chip CP by pushing it. The first carrier holding part 131 has a communication hole 131a that communicates with the through hole 50 of the chip carrier 10. The push pin 136 is waiting in the communication hole 131a and is inserted into the through hole 50 from the communication hole 131a to push the chip CP. When the push pin 136 pushes the chip CP, the pair of claws that constitute the side holding head 133a are waiting beside the chip CP. After the push pin 136 pushes the chip CP, the pair of claws close and hold the chip CP in place.

[0098] The chip bonding device 130 may have a gas supply pipe 137 instead of the push pins 136, as shown in Figure 10. The gas supply pipe 137 supplies gas to the through-hole 50 of the chip carrier 10 and assists in separating the chips CP by pushing them with gas pressure. The first carrier holding part 131 has a communication hole 131a that communicates with the through-hole 50 of the chip carrier 10. The gas supply pipe 137 supplies gas to the through-hole 50 through the communication hole 131a.

[0099] The gas supply pipe 137 has multiple individual pipes 137a that supply gas individually to multiple through holes 50. Each of the multiple individual pipes 137a is provided with an on-off valve 137b. By individually controlling the multiple on-off valves 137b when separating multiple chip CPs, the separation of each chip CP can be assisted.

[0100] The first carrier holding unit 131 is provided with, for example, a first contact terminal 138 and a first suction force control unit 139. The first contact terminal 138 contacts the operation terminal 40 of the chip carrier 10. Multiple first contact terminals 138 are provided corresponding to multiple operation terminals 40. The first suction force control unit 139 is connected to the operation terminal 40 of the chip carrier 10 via the first contact terminal 138 provided on the first carrier holding unit 131. The operation terminal 40 receives control signals transmitted from the first suction force control unit 139. Note that the first suction force control unit 139 may be provided outside the first carrier holding unit 131, or may be part of the first control device 190.

[0101] The first adsorption force control unit 139 controls the adsorption force while connected to the operating terminal 40 of the chip carrier 10. The first adsorption force control unit 139 controls the charge accumulated on the electrode 30. The first adsorption force control unit 139 controls the discharge of charge from the electrode 30, thereby eliminating the adsorption force.

[0102] The first adsorption force control unit 139 controls the removal of the adsorption force on the chip CP that is to be separated from the chip carrier 10, while maintaining the adsorption force on the remaining chip CPs. The timing of supplying charge to the electrode 30 differs for each adsorption unit 21a. This allows the remaining chip CPs to be electrostatically adsorbed to the chip carrier 10 when one chip CP is separated from the chip carrier 10, preventing the remaining chip CPs from falling due to contact with the side holding head 133a.

[0103] As shown in Figure 11, the chip bonding device 130 may include a first contact position adjustment unit 135 that moves the chip carrier 10 relative to the first carrier holding unit 131, thereby sequentially bringing multiple operating terminals 40 into contact with a single first contact terminal 138. This can accommodate multiple chip carriers 10 with different pitches of operating terminals 40. The first contact position adjustment unit 135 moves the chip carrier 10, but it may also move the first carrier holding unit 131. A push pin 136 is inserted into the through hole 50 of the chip carrier 10, but a gas supply pipe 137 may be used to supply gas.

[0104] Although not shown in the figures, the chip arrangement device 230 may also include a second contact position adjustment unit that moves the chip carrier 10 relative to the second carrier holding unit 231, thereby sequentially bringing multiple operation terminals 40 into contact with a single second contact terminal 238. The second contact position adjustment unit moves the chip carrier 10, but it may also move the second carrier holding unit 231.

[0105] The first control device 190 (see Figure 6) is, for example, a computer and comprises a CPU (Central Processing Unit) 191 and a storage medium 192 such as memory. The storage medium 192 stores programs that control various processes executed in the first chip processing system 101. The first control device 190 controls the operation of the first chip processing system 101 by causing the CPU 191 to execute the programs stored in the storage medium 192.

[0106] Next, an example of a chip processing method using the first chip processing system 101 will be described. The following chip processing method is carried out under the control of the first control device 190.

[0107] First, the second carrier transport arm 113 of the first loading / unloading station 110 removes the chip carrier 10, before the chip CP is separated, from the cassette C5 and transports it to the transition device 115. Next, the first carrier transport arm 123 of the first processing station 120 removes the chip carrier 10, before the chip CP is separated, from the transition device 115 and transports it to the chip cleaning device 125. Then, the chip cleaning device 125 removes the protective film PF by cleaning multiple chip CPs. After that, the first carrier transport arm 123 removes the chip carrier 10, before the chip CP is separated, from the chip cleaning device 125 and transports it to the chip bonding device 130.

[0108] In parallel with the above process, the following process is performed. First, the second substrate transport arm 114 of the first loading / unloading station 110 removes the device substrate W before the chip CP is mounted from the cassette C7 and transports it to the transition device 116. Next, the first substrate transport arm 124 of the first processing station 120 removes the device substrate W before the chip CP is mounted from the transition device 116 and transports it to the surface modification device 126. Next, the surface modification device 126 performs plasma treatment on the main surface Wc of the device substrate W. After that, the first substrate transport arm 124 removes the device substrate W from the surface modification device 126 and transports it to the substrate cleaning device 127. Next, the substrate cleaning device 127 cleans the main surface Wc of the device substrate W. After that, the first substrate transport arm 124 removes the device substrate W from the substrate cleaning device 127 and transports it to the chip bonding device 130.

[0109] Next, the chip bonding apparatus 130 separates the chip CP from the chip carrier 10 and mounts the separated chip CP onto the device substrate W, thereby manufacturing the chip-equipped substrate CW shown in Figure 7(C). The first device Wb of the device substrate W and the second device CPb of the chip CP are electrically connected.

[0110] Subsequently, the first substrate transport arm 124 removes the device substrate W, after the chip CP has been mounted, from the chip bonding device 130 and transports it to the transition device 116. Next, the second substrate transport arm 114 of the first loading / unloading station 110 removes the device substrate W, after the chip CP has been mounted, from the transition device 116 and stores it in the cassette C8.

[0111] Next, the first carrier transport arm 123 removes the chip carrier 10, after the chip CP has been separated, from the chip bonding device 130 and transports it to the transition device 115. Then, the second carrier transport arm 113 of the first loading / unloading station 110 removes the device substrate W, after the chip CP has been separated, from the transition device 115 and stores it in the cassette C6.

[0112] The following additional information is disclosed regarding the above embodiment. [Note 1] A chip arrangement device for arranging multiple chips on a chip carrier having multiple adsorption parts on its surface for electrostatically adsorbing chips, A second carrier holding section for holding the chip carrier, A frame holding unit that holds the frame with multiple chips attached to the frame via tape, A chip transfer unit transfers the chip from the tape provided in the opening of the frame held by the frame holding unit to the chip carrier held by the second carrier holding unit, A chip array device equipped with the following features.

[0113] [Note 2] The chip has a first surface and a second surface that contacts the tape in the opposite direction to the first surface. A protective film is pre-formed on the first surface of the chip. The chip arrangement apparatus according to Appendix 1, wherein the chip transfer unit comprises a collet that holds the chip via the protective film and a collet moving mechanism that moves the collet.

[0114] [Note 3] The chip carrier comprises a carrier substrate having the front surface and a back surface facing the opposite direction to the front surface, a plurality of electrodes provided on the carrier substrate that individually generate an adsorption force for electrostatically adsorbing the chip to each adsorption portion, and an operating terminal provided on the carrier substrate and connected to a second adsorption force control unit that controls the adsorption force, The chip arrangement apparatus according to Appendix 1 or 2, comprising the second adsorption force control unit.

[0115] [Note 4] The second carrier holding portion is provided with a second contact terminal that contacts the operating terminal, The chip arrangement apparatus described in Appendix 3, wherein the second suction force control unit is connected to the operation terminal via the second contact terminal.

[0116] [Note 5] The chip arrangement apparatus according to Appendix 4, further comprising a second contact position adjustment unit that moves the chip carrier relative to the second carrier holding unit, thereby sequentially bringing a plurality of operation terminals into contact with one of the second contact terminals.

[0117] [Note 6] A chip processing method comprising arranging a plurality of chips on a chip carrier having a plurality of adsorption portions on its surface for electrostatically adsorbing chips, The chip carrier is held in the second carrier holding section, The frame is held by the frame holding part with multiple chips attached to the frame via tape, Transferring the chip from the tape provided in the opening of the frame held by the frame holding portion to the chip carrier held by the second carrier holding portion, A chip processing method having the following characteristics.

[0118] The embodiments of the chip carrier and chip processing method described above have been explained, but this disclosure is not limited to the embodiments described above. Various changes, modifications, substitutions, additions, deletions, and combinations are possible within the scope of the claims. These also naturally fall within the technical scope of this disclosure. [Explanation of symbols]

[0119] 10 Chip Carriers 20 Carrier board 21 Surface 21a Adsorption part 21b Recess 22 Back side 30 electrodes 40 Operation terminal

Claims

1. An insulating carrier substrate having a surface having multiple adsorption portions that contact a chip and electrostatically adsorb the chip, and a back surface facing the opposite direction from the surface, A plurality of electrodes embedded inside the carrier substrate, which individually generate an adsorption force for electrostatically adsorbing the chip to each adsorption portion, An operating terminal provided on the carrier substrate and connected to an adsorption force control unit that controls the adsorption force, Equipped with, The surface of the carrier substrate has recesses at the periphery of each of the plurality of adsorption portions that are recessed more than the adsorption portion. The carrier substrate is provided with a through hole that penetrates from the front surface to the back surface in the adsorption portion. The electrode is a chip carrier arranged to surround the through hole.

2. The chip carrier according to claim 1, wherein the recess is formed in a mesh-like manner, and the adsorption portions are arranged in an island-like manner in the mesh of the recess.

3. The chip carrier according to claim 1 or 2, wherein the adsorption portion is smaller than the chip.

4. Transporting a plurality of chips together with a chip carrier, with the plurality of chips electrostatically attached to the chip carrier described in any one of claims 1 to 3, The side-holding head, which holds the side of the chip, is inserted into the recess on the surface of the carrier substrate so as not to touch the chip. The side of the chip is held by the side holding head inserted into the recess, By removing the side holding head from the recess, the chip is separated from the surface of the carrier substrate, A chip processing method having the following characteristics.

5. The chip processing method according to claim 4, comprising inserting a push pin into the through hole and pressing the chip with the push pin.

6. The chip processing method according to claim 4, comprising supplying gas to the through hole and pressing the chip with the pressure of the gas.

7. The chip processing method according to any one of claims 4 to 6, wherein the adsorption force control unit eliminates the adsorption force on the chips that are to be separated from the carrier substrate, and maintains the adsorption force on the remaining chips.

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