Photoelectric conversion devices and equipment

Abstract

To improve the accuracy of AD conversion.SOLUTION: A photoelectric conversion device comprises: a plurality of pixel circuits; a plurality of AD conversion circuits that AD-convert analog signals read out from the plurality of pixel circuits in an AD-conversion period to generate digital data; a plurality of memory circuits that store the digital data generated by the plurality of AD conversion circuits; a plurality of output circuits respectively connected with two or more memory circuits among the plurality of memory circuits; and a scanning circuit that selects any one of the plurality of output circuits and selects any one of two or more memory circuits connected with the selected output circuit to read out the digital data stored in the selected memory circuit to an output line. The scanning circuit, when the length of the AD conversion period is defined as T, does not change the selection of the output circuit from among the plurality of output circuits during an inhibition period that at least includes a period from the lapse of 0.35T to the lapse of 0.65T from the start of the AD conversion period.SELECTED DRAWING: Figure 7

Description

Technical Field

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[0001] The present invention relates to a photoelectric conversion device and equipment.

Background Art

[0002] Various techniques for rapidly reading data from a photoelectric conversion device have been proposed. Patent Document 1 proposes a photoelectric conversion device including an AD conversion circuit and a memory circuit for each pixel column. While digital data is being read from the memory circuit, the analog signal from the next pixel row is AD-converted, thereby accelerating data reading. Further, the plurality of memory circuits are divided into a plurality of blocks, and two or more memory circuits included in each block are connected to a common output circuit. The horizontal scanning circuit reads digital data from the selected memory circuit to a data output line by selecting any one of the plurality of output circuits and then selecting any one of the two or more memory circuits connected to the selected output circuit.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the photoelectric conversion device described in Patent Document 1, when changing the selection state of the output circuit, two or more memory circuits are connected to or disconnected from the data output line. The power supply fluctuations caused by this change in the connection state may affect the AD conversion operation. The present invention aims to improve the accuracy of AD conversion.

Means for Solving the Problems

[0005] In view of the above issues, the present invention provides a plurality of pixel circuits, a plurality of AD conversion circuits that generate digital data by performing AD conversion on analog signals read from the plurality of pixel circuits during an AD conversion period, a plurality of memory circuits that store the digital data generated by the plurality of AD conversion circuits, a plurality of output circuits each connected to two or more of the plurality of memory circuits, and a scanning circuit that reads the digital data stored in the selected memory circuit to an output line by selecting one of the plurality of output circuits and one of the two or more memory circuits connected to the selected output circuit, wherein the scanning circuit changes the selection of an output circuit from the plurality of output circuits during a prohibition period that includes at least a period from 0.35T to 0.65T after the start of the AD conversion period, with the length of the AD conversion period being T. Instead, the scanning circuit changes the selection of an output circuit from the plurality of output circuits during a period within the AD conversion period that is not included in the prohibited period. A photoelectric conversion device is provided. [Effects of the Invention]

[0006] The above method improves the accuracy of AD conversion. [Brief explanation of the drawing]

[0007] [Figure 1] A block diagram showing an example configuration of the imaging device according to the first embodiment. [Figure 2] A block diagram showing an example configuration of the photoelectric conversion device according to the first embodiment. [Figure 3] An equivalent circuit diagram showing an example configuration of the pixel circuit and column circuit of the first embodiment. [Figure 4] A block diagram showing an example configuration of the memory block and its surrounding circuitry according to the first embodiment. [Figure 5] A timing diagram showing an overview of the operation example of the photoelectric converter of the first embodiment. [Figure 6] A timing diagram showing details of an example of operation of the photoelectric converter according to the first embodiment. [Figure 7] A timing diagram showing details of an example of operation of the photoelectric converter according to the first embodiment. [Figure 8]A block diagram showing an example configuration of the photoelectric conversion device according to the second embodiment. [Figure 9] A timing diagram showing details of an example of operation of the photoelectric converter of the second embodiment. [Figure 10] A timing diagram showing details of an example of operation of the photoelectric converter according to the first embodiment. [Figure 11] A block diagram showing an example configuration of another embodiment. [Modes for carrying out the invention]

[0008] The embodiments will be described in detail below with reference to the attached drawings. Note that the following embodiments do not limit the invention as defined in the claims. While the embodiments describe multiple features, not all of these features are essential to the invention, and the features may be combined in any way. Furthermore, in the attached drawings, identical or similar configurations are given the same reference numerals, and redundant descriptions are omitted.

[0009] The photoelectric conversion device described below may be an image sensor that performs imaging (e.g., a CMOS image sensor). However, it is not limited to image sensors that perform imaging, and can be applied to other examples. For example, distance measuring devices (devices for distance measurement using focus detection or TOF (Time of Flight)), photometric devices (devices for measuring the amount of incident light, etc.).

[0010] <First Embodiment> Referring to Figure 1, an example of the configuration of the imaging device 100 according to the first embodiment will be described. The imaging device 100 includes, for example, the components shown in Figure 1. The photoelectric converter 101 has a pixel region in which multiple pixel circuits are arranged in two dimensions and is capable of outputting imaging signal data corresponding to incident light. The detailed configuration of the photoelectric converter 101 will be described later. The overall control circuit 102 controls the operation of each component of the imaging device 100. It also performs signal processing such as development and compression on the imaging signal data to generate images for recording and playback. The input device 103 receives inputs from an external source, such as a user, to the overall control circuit 102, such as instructions to execute shooting and settings for the drive mode of the imaging device 100.

[0011] The timing generation circuit 104 generates timing signals to drive the photoelectric converter 101 and the signal processing circuit 107 according to the control signal from the overall control circuit 102. The imaging lens 105 forms an optical image of the subject on the photoelectric converter 101. The imaging lens 105 may or may not be detachable from the main body of the imaging device 100. The lens drive mechanism 106 drives the imaging lens 105 and specifically performs focus control, zoom control, aperture control, etc., according to the control signal from the overall control circuit 102. The signal processing circuit 107 performs signal processing such as correction on the imaging signal data output from the photoelectric converter 101.

[0012] The display device 108 displays information such as the image to be reproduced and the drive mode setting of the imaging device 100. The recording device 109 has a recording medium (not shown) and records image data for recording. A semiconductor memory such as flash memory is used as the recording medium. The recording medium may or may not be detachable from the recording device 109.

[0013] Referring to FIG. 2, a configuration example of the above-described photoelectric conversion device 101 will be described. In the pixel region 200, a plurality of pixel circuits 201 are arranged in a matrix. In the present embodiment, for simplicity of explanation, an example of having pixel circuits 201 of 10 rows × 16 columns is shown, but the number of rows and columns of the pixel circuits 201 is not limited to this. The pixel circuit 201 includes a photoelectric conversion unit and can output an analog signal corresponding to incident light as a pixel signal. Further, the pixel circuit 201 can output an analog signal in a reset state. Among the pixel region 200, the pixel circuits 201 included in the top row and the leftmost two columns (the shaded portion in FIG. 2) are shielded OB (optical black) pixel circuits 201a. The output of the OB pixel circuit 201a is used for signal correction of other pixel circuits 201.

[0014] The vertical scanning circuit 202 controls the read timing of pixel signals for the pixel region 200 in row units. A plurality of column circuits 203 are provided corresponding to the plurality of pixel columns in the pixel region 200. In the example of FIG. 2, 16 column circuits 203 are provided corresponding to 16 pixel columns, and the pixel columns and the column circuits 203 correspond one-to-one. The column circuit 203 includes an AD (analog-digital) conversion circuit. The AD conversion circuit generates digital data by AD-converting the analog signals read from the pixel circuits 201 of each pixel column. A counter circuit 204 is provided commonly for the plurality of column circuits 203. The count signal output from the counter circuit 204 is referred to by the AD conversion circuit of the column circuit 203 and used for AD conversion.

[0015] Multiple memory circuits 205 are provided to correspond to multiple column circuits 203. In the example in Figure 2, there is a one-to-one correspondence between the column circuits 203 and the memory circuits 205. The memory circuits 205 temporarily store the digital data generated by the AD conversion circuits of the column circuits 203. By providing memory circuits 205 to correspond to the column circuits 203, it becomes possible to output digital data from the memory circuits 205 in parallel with the AD conversion operation of the pixel signals in the column circuits 203. Multiple memory circuits 205 are divided into multiple memory blocks 206. In the example in Figure 2, one memory block 206 is composed of four columns of memory circuits 205.

[0016] Each of the multiple memory blocks 206 is provided with a block digital output line 207. Signal data held in the memory circuit 205 is output via the block digital output line 207 of the corresponding memory block 206. Each of the multiple block digital output lines 207 is provided with an output circuit 208. The output circuit 208 is provided between the block digital output line 207 and the common digital output line 209 and is used to control the electrical connection state between the common digital output line 209 and the block digital output line 207 on a memory block 206 basis. One output circuit 208 is connected via the block digital output line 207 to two or more (four in the example of Figure 2) memory circuits 205 included in the corresponding memory block 206. Digital data is output to the outside of the photoelectric converter 101 via the common digital output line 209. The horizontal scanning circuit 210 controls the electrical connection state between the common digital output line 209 and the block digital output line 207 by the output circuit 208, and the output timing of each memory circuit 205.

[0017] Referring to FIG. 3, a circuit configuration example of the pixel circuit 201 and the column circuit 203 will be described. The pixel circuit 201 includes a photodiode PD. The photodiode PD functions as a photoelectric conversion unit and can accumulate charges according to incident light. Further, the pixel circuit 201 includes a transfer transistor M1, a reset transistor M2, a floating diffusion FD, an amplification transistor M3, and a selection transistor M4. The floating diffusion FD can operate as a charge holding unit. Control signals are input from the vertical scanning circuit 202 to the gates of the transistors M1 to M4, respectively. The transistors M1 to M4 are in an on state while the control signals are at a high level and in an off state while the control signals are at a low level. Each control signal is commonly input in units of pixel rows in the pixel region 200, and the pixel circuits 201 arranged in the same pixel row are simultaneously driven by the common control signal.

[0018] The transfer transistor M1 is controlled by a control signal PTX. During the period when the transfer transistor M1 is in an on state, the charges accumulated in the photodiode PD are transferred to the floating diffusion FD. The reset transistor M2 is controlled by a control signal PRES. When the reset transistor M2 is in an on state, the potential of the floating diffusion FD is reset by the power supply potential VDD. Further, by setting the control signal PRES and the control signal PTX to be in an on state simultaneously, the accumulated charges in the photodiode PD can be reset. The selection transistor M4 is controlled by a control signal PSEL. The signal voltage amplified and converted by the amplification transistor M3 according to the charge amount of the floating diffusion FD is transmitted as a pixel signal to the vertical signal line VL during the period when the amplification transistor M3 is in an on state.

[0019] The column circuit 203 includes an AD conversion circuit. In the example in Figure 3, an example is shown in which a slope-type AD conversion circuit is used as the AD conversion circuit. Alternatively, other AD conversion circuits such as successive approximation types may be used. The AD conversion circuit includes a comparator 301 and latch circuits 302 and 303. The signal voltage input from the pixel circuit 201 via the vertical output line VL is input to the comparator 301. The comparator 301 compares the input signal Vin with the reference signal RAMP and outputs the comparison result as a comparison signal COMP. The reference signal RAMP is a ramp voltage generated by a ramp generation circuit (not shown) and is supplied in common to the comparator 301 of each column. The comparator 301 compares the magnitude of the input signal Vin with the reference voltage RAMP. The comparator 301 outputs a low level as the comparison signal COMP if the input signal Vin is lower than the reference signal Ramp, and a high level if the input signal Vin is higher than the reference signal RAMP.

[0020] Latch circuits 302 and 303 receive a comparison signal COMP and multi-bit data representing the count value supplied from the counter circuit 204. Furthermore, latch circuit 302 receives a selection signal SEL_N. While the selection signal SEL_N is high, latch circuit 302 accepts the comparison signal COMP. When the comparison signal COMP switches from high to low, latch circuit 302 latches each bit of the count value input from the counter circuit 204 as signal data. Similarly, latch circuit 303 receives a selection signal SEL_S. While the selection signal SEL_S is high, latch circuit 303 accepts the comparison signal COMP. When the comparison signal COMP switches from high to low, latch circuit 303 latches each bit of the count value input from the counter circuit 204 as signal data. In the example shown in Figure 3, the count circuit 13 outputs n bits of data as a count value, and the latch circuits 302 and 303 are configured to each latch n bits of data. Alternatively, the number of bits of data that can be latched may differ between latch circuit 302 and latch circuit 303.

[0021] Referring to Figure 4, an example configuration from the memory circuit 205 to the common digital output line 209 will be explained. In the example in Figure 4, each memory block 206 has a memory circuit 205 for 4 pixel columns. When referring to a specific one of several column circuits 203, the subscript x is added and it is represented as column circuit 203_x. When referring to a specific one of several memory circuits 205, the subscript x is added and it is represented as memory circuit 205_x. When referring to a specific one of several memory blocks 206, the subscript i is added and it is represented as memory block 206_i. When referring to a specific one of several block digital output lines 207, the subscript i is added and it is represented as block digital output line 207_i. When referring to a specific one of several output circuits 208, the subscript i is added and it is represented as output circuit 208_i. The subscript x indicates that it is the element corresponding to the x-th pixel column, and it is an integer between 1 and the number of pixel columns. The subscript i indicates that it corresponds to the i-th memory block, and is an integer between 1 and (number of pixel rows / 4).

[0022] The memory circuit 205_x holds each bit data output by the latch circuits 302 and 303 of the column circuit 203_x according to the memory transfer signal MTX, which is given to each pixel column in common. The column selection circuit 400_x is connected to the output terminal of the memory circuit 205_x. The column selection circuit 400_x connects the memory circuit 205_x to the block digital output line 207_i according to the read signal READ_x input from the horizontal scanning circuit 210 for each column. The block digital output line 207_i is provided for each memory block 206_i and can transmit each bit data from the connected digital memory.

[0023] The output circuit 208i connects the block digital output line 207_i to the common digital output line 209 while the block selection signal BSEL_i, input from the horizontal scanning circuit 210 for each memory block, is at a high level. The common digital output line 209 is provided in common to multiple memory blocks 206 and can transmit the bit data of each memory block 206_i connected via the output circuit 208_i.

[0024] Referring to Figures 5 and 6, an example of the operation of reading digital data from the photoelectric converter 101 will be described. Figure 5 shows the temporal order of operations for a specific pixel row (hereinafter referred to as row y) and the pixel rows before and after it. Processing for one pixel row includes a data generation operation that generates digital data corresponding to the analog signal read from the pixel circuit 201, and a data output operation that outputs the generated digital data to the outside. In the data generation operation, digital data is generated in parallel for multiple pixel circuits 201 included in the same pixel row. In the data output operation, digital data is output sequentially for multiple pixel circuits 201 included in the same pixel row. The photoelectric converter 101 is configured such that the data generation operation for row y and the data output operation for row y-1 are temporally superimposed. Furthermore, the photoelectric converter 101 is configured such that the data generation operation for row y+1 and the data output operation for row y are temporally superimposed.

[0025] Referring to Figure 6, the data generation operation, including AD conversion of the pixel signal, and the data output operation from the memory circuit 205 are described in detail. The data generation operation for the y-th row pixel circuit 201 is shown from time T00 to T10, and the data output operation for the y-th row pixel circuit 201 from the memory circuit 205 is shown from time T11 to T14. From time T00 to T10, the data output operation for the y-1-th row pixel circuit 201 is performed in parallel with the data generation operation for the y-th row pixel circuit 201. Also, from time T11 to T14, the data output operation for the y-th row pixel circuit 201 is performed in parallel with the data generation operation for the y+1-th row pixel circuit 201. The control signals PSEL, PRES, and PTX switch levels at different timings for each pixel row. Therefore, the control signals supplied to the pixel circuit 201 of each pixel row are distinguished by adding a subscript. For example, the control signal PSEL supplied to the y-th row pixel circuit 201 is represented as PSEL_y.

[0026] The data generation operation for the y-th row pixel circuit 201 is initiated at time T00 when the control signal PSEL_y is switched to a high level. This turns on the selection transistor M4 of the y-th row pixel circuit 201, and connects the amplification transistor M3 to the vertical output line VL.

[0027] At time T01, the control signal PRES_y switches to a low level, causing the reset transistor M2 to switch to the off state and releasing the reset of the floating diffusion FD. Subsequently, at time T02, after a predetermined time has elapsed, the AD conversion operation for the pixel reset level begins. The interval between times T01 and T02 is set to a length that is expected to allow the voltage of the vertical output line VL to stabilize after the reset is released.

[0028] The AD conversion operation begins when the ramp signal RAMP is supplied to the comparator 301 of the AD conversion circuit. The ramp signal RAMP is a signal whose voltage level changes at a constant rate over time. As soon as the supply of the ramp signal RAMP begins, the counter circuit 204 starts counting from time T02 and counts the time while the ramp signal RAMP is being supplied. As soon as the supply of the ramp signal RAMP begins and the counter circuit 204 starts counting, the selection signal SEL_N switches to a high level. This causes the latch circuit 302 to start accepting the input of the comparison signal COMP.

[0029] The comparator 301 compares the magnitude of the input voltage Vin, which is input via the vertical output line VL, with the voltage level of the ramp signal RAMP. At this time, the input voltage Vin is stable at a voltage level based on the reset level of the floating diffusion FD of the pixel circuit 201. The input voltage Vin at this point is the analog signal read from the pixel circuit 201, which is in a reset state. This analog signal will be referred to as the N signal below. As the voltage level of the ramp signal RAMP decreases over time and falls below the input voltage Vin, the comparator signal COMP switches to a low level. This time is denoted as T03. In response to the change in the comparator signal COMP to a low level, the latch circuit 302 latches each bit data of the count value from the counter circuit 204. The digital data latched at this time represents the N signal read from the pixel circuit 201. Hereinafter, the digital data representing the N signal will be referred to as the N signal data.

[0030] At time T04, the supply of the ramp signal RAMP to the comparator 301 of the AD conversion circuit ends. This terminates the AD conversion operation of the N signal of the pixel circuit 201. As the supply of the ramp signal RAMP to the comparator 301 of the AD conversion circuit ends, the selection signal SEL_N switches to a low level. This stops the latch circuit 302 from accepting the comparison signal COMP. Also, as the supply of the ramp signal RAMP to the comparator 301 of the AD conversion circuit ends, the counter circuit 204 stops counting. The ramp signal RAMP and the counter circuit 204 are reset before the next AD conversion operation.

[0031] At time T05, the control signal PTX_y switches to a high level and remains high until time T06. This transfers the signal charge accumulated in the photodiode PD to the floating diffusion FD. The photodiode PD has accumulated charge corresponding to the amount of light incident on the pixel circuit 201 (specifically, its photodiode PD) since the end of the previous readout. The potential of the floating diffusion FD fluctuates according to the amount of charge transferred from the photodiode PD. Accordingly, the input voltage Vin changes to a voltage level based on the potential of the floating diffusion FD. At this point, the input voltage Vin is the analog signal read out from the pixel circuit 201, which has accumulated charge corresponding to the incident light. This analog signal will be referred to as the S signal below. The S signal has a value obtained by superimposing the optical signal level on the reset level of the pixel circuit 201. When no light is incident on the photodiode (for example, for the OB pixel circuit 201a), the S signal is approximately equal to the N signal, as shown by the dashed line in Figure 6.

[0032] At time T06, the control signal PTX_y is switched to a low level. This terminates the transfer of signal charge from the photodiode PD. Simultaneously, the AD conversion operation for the input voltage Vin is restarted. The AD conversion operation that starts at time T06 is the same as the AD conversion operation that started at time T02 described above. However, in this AD conversion operation, the selection signal SEL_S is switched to a high level at the start of the AD conversion operation in order to hold the result in the latch circuit 302. T07a represents the time when the comparison signal COMP inverts when no light is incident on the photodiode PD (for example, for the OB pixel circuit 201a). T07b represents the time when the comparison signal COMP inverts when some amount of light is incident. The latched digital data at this time represents the S signal read out from the pixel circuit 201. Hereinafter, the digital data representing the S signal will be referred to as S signal data.

[0033] At time T08, the supply of the ramp signal RAMP to the comparator 301 of the AD conversion circuit ends. This terminates the AD conversion operation of the S signal of the pixel circuit 201. As the supply of the ramp signal RAMP to the comparator 301 of the AD conversion circuit ends, the selection signal SEL_S switches to a low level. This stops the latch circuit 303 from accepting the comparison signal COMP. Also, as the supply of the ramp signal RAMP to the comparator 301 of the AD conversion circuit ends, the counter circuit 204 stops counting. The ramp signal RAMP and the counter circuit 204 are reset before the next AD conversion operation.

[0034] At time T09, the control signal PRES_y is switched to a high level. This causes the reset transistor M2 to switch to the ON state, initiating the reset of the floating diffusion FD. At time T10, the control signal PSEL_y is switched to a low level. This causes the selection transistor M4 of the y-th row pixel circuit 201 to switch to the OFF state, and the connection of the amplification transistor M3 to the vertical output line VL is released. As described above, the data generation operation for the y-th row pixel circuit 201 ends when the control signal PSEL_y is switched to a low level.

[0035] After the AD conversion operation for the S signal is completed, at any time between T08 and T11, the memory transfer signal MTX supplied to the memory circuit 205 is temporarily switched to a high level (between T09 and T10 in the example in Figure 6). As a result, the N signal data latched in the latch circuit 302 and the S signal data latched in the latch circuit 303 are stored in the memory circuit 205. Hereafter, the N signal data and S signal data together will be referred to as signal data.

[0036] After the signal data for the y-th row pixel circuit 201 is stored in the memory circuit 205, the data output operation for the y-th row pixel circuit 201 starts at time T11. Specifically, the digital data stored in the memory circuit 205 is output to the outside of the photoelectric converter 101 (for example, the signal processing circuit 107 in Figure 1) via the common digital output line 209.

[0037] Between times TB1 and TB2, the block selection signal BSEL_1 is at a high level. This selects memory block 206_1, and the block digital output line 207_1 is connected to the common digital output line 209. While the block selection signal BSEL_1 is at a high level, read signals READ_1 to READ_4 are sent sequentially, and memory circuits 205_1 to 205_4 are selected in order. As memory circuits 205_1 to 205_4 are sequentially connected to the block digital output line 207_1, the signal data stored in memory circuits 205_1 to 205_4 is output sequentially from the common digital output line 209.

[0038] Similarly, between times TB2 and TB3, memory block 206_2 is selected, and the signal data stored in memory circuits 205_5 to 205_8 is output sequentially from the common digital output line 209. Between times TB3 and TB4, memory block 206_3 is selected, and the signal data stored in memory circuits 205_9 to 205_12 is output sequentially from the common digital output line 209. Between times TB4 and TB5, memory block 206_4 is selected, and the signal data stored in memory circuits 205_13 to 205_16 is output sequentially from the common digital output line 209. Once the digital data has been read from all memory circuits 205, the data output operation for the y-th row pixel circuit 201 is completed.

[0039] The signal data output to the outside of the photoelectric converter 101 is processed by the signal processing circuit 107. For example, the signal processing circuit 107 removes noise components contained in the S signal data by subtracting the N signal data from the S signal data, and extracts components corresponding to the incident light. The subtraction function may be performed by a circuit provided in the photoelectric converter 101.

[0040] The operation of the horizontal scanning circuit 210 will be described in detail with reference to Figure 7. Figure 7 is a diagram that focuses on some signals and some periods of the timing diagram in Figure 6. As described above, the horizontal scanning circuit 210 selects a specific output circuit 208 from among multiple output circuits 208 by supplying a control signal BSEL to multiple output circuits 208.

[0041] When a specific output circuit 208 is selected, the block digital output line 207 and the common digital output line 209 connected to that output circuit 208 are connected. When the selection of a specific output circuit 208 is deselected, the block digital output line 207 and the common digital output line 209 connected to that output circuit 208 are disconnected. Such changes in connection states cause power fluctuations in the column circuit 203 and vertical output line VL via the power supply wiring. If such power fluctuations occur near the inversion of the output of the comparator 301 during AD conversion (i.e., the determination of the bit value of the digital data), errors will occur in the value obtained by AD conversion. Signals with relatively small values, such as the N signal and the S signal from the OB pixel circuit 201a, are particularly susceptible to the effects of such power fluctuations.

[0042] Therefore, the horizontal scanning circuit 210 of this embodiment operates in such a way that it does not change the selection of an output circuit from the multiple output circuits 208 near the point where the output of the comparator 301 is inverted during the AD conversion operation for the N signal. Changing the selection of an output circuit 208 includes selecting a new output circuit 208 and deselecting an output circuit 208. Selecting a new output circuit 208 is done by switching the control signal BSEL supplied to the output circuit 208 to a high level. Deselecting an output circuit 208 is done by switching the control signal BSEL supplied to the output circuit 208 to a low level. The period during which the selection of an output circuit 208 from the multiple output circuits 208 is not changed is called the prohibition period. That is, the horizontal scanning circuit 210 does not change the selection of an output circuit 208 during the prohibition period, but changes the selection of an output circuit 208 during other periods.

[0043] First, let's explain the prohibition period for AD conversion operation on the N signal. The period during which AD conversion operation is performed on the N signal is denoted as AD conversion period 1. The prohibition period included in AD conversion period 1 is denoted as prohibition period 1. As mentioned above, AD conversion period 1 may be the period during which the ramp signal is changing in order to perform AD conversion operation. The photoelectric converter 101 is designed so that the time at which the output of comparator 301 inverts during AD conversion operation on the N signal is located in the middle of AD conversion period 1. Therefore, prohibition period 1 includes time TC4, which is in the middle of AD conversion period 1 (times T02 to T04). Also, the time at which the output of comparator 301 inverts changes depending on the actual value of the N signal. Therefore, prohibition period 1 has a certain length.

[0044] The midpoint of Prohibition Period 1 may coincide with the midpoint (time TC4) of AD Conversion Period 1 (times T02 to T04), or it may be offset from it. Let T be the length of AD Conversion Period 1. The length of Prohibition Period 1 may be, for example, 30% of T or 50% of T. If the length of Prohibition Period 1 is 30% of T, Prohibition Period 1 may be the period from 0.35T to 0.65T after the start of AD Conversion Period 1. If the length of Prohibition Period 1 is 50% of T, Prohibition Period 1 may be the period from 0.25T to 0.75T after the start of AD Conversion Period 1.

[0045] The longer the prohibition period 1, the higher the probability that the time when the output of comparator 301 inverts will be included in prohibition period 1. On the other hand, the longer the prohibition period 1, the longer the period during which the selection of output circuit 208 is restricted. Therefore, the length of prohibition period 1 is designed considering the trade-off between these two factors. Prohibition period 1 may be shorter than or the same as AD conversion period 1.

[0046] In the example in Figure 7, the horizontal scanning circuit 210 selects output circuit 208_1 at time T00 by switching the control signal BSEL_1 to a high level. Subsequently, at time TC2, the horizontal scanning circuit 210 deselects output circuit 208_1 by switching the control signal BSEL_1 to a low level, and selects output circuit 208_2 by switching the control signal BSEL_2 to a high level. Then, at time TC3, prohibition period 1 begins, so the horizontal scanning circuit 210 does not change the selection of output circuit 208. Specifically, the horizontal scanning circuit 210 maintains the state in which output circuit 208_2 is selected.

[0047] At time TC4, the prohibition period 1 ends. Subsequently, at time T04, the horizontal scanning circuit 210 deselects output circuit 208_2 by switching the control signal BSEL_2 to a low level, and selects output circuit 208_3 by switching the control signal BSEL_3 to a high level. In the example above, time T03, when the N signal data is finalized, is included in prohibition period 1.

[0048] Next, we will explain the prohibition period for AD conversion operation on the S signal. The period during which AD conversion operation is performed on the S signal will be referred to as AD conversion period 2. The prohibition period included in AD conversion period 2 will be referred to as prohibition period 2. As mentioned above, AD conversion period 2 may also be the period during which the ramp signal is changing in order to perform AD conversion operation.

[0049] As mentioned above, if the value of the analog signal being converted via AD is large, it is less susceptible to power supply fluctuations. Therefore, a prohibition period 2 is set in the first half of AD conversion period 2. The length of prohibition period 2 may be the same as the length of prohibition period 1. Also, the length from the start of AD conversion period 2 to the start of prohibition period 2 may be the same as the length from the start of AD conversion period 1 to the start of prohibition period 1. If the length of AD conversion period 1 is T, the length of prohibition period 2 may be, for example, 30% of T or 50% of T. If the length of prohibition period 1 is 30% of T, prohibition period 2 may be the period from 0.35T elapsed to 0.65T elapsed from the start of AD conversion period 2. If the length of prohibition period 2 is 50% of T, prohibition period 2 may be the period from 0.25T elapsed to 0.75T elapsed from the start of AD conversion period 2.

[0050] In the example shown in Figure 7, the horizontal scanning circuit 210 deselects output circuit 208_3 at time TC5 by switching the control signal BSEL_3 to a low level. Also at time TC5, the horizontal scanning circuit 210 selects output circuit 208_4 by switching the control signal BSEL_4 to a high level. Subsequently, since the prohibition period 2 begins at time TC6, the horizontal scanning circuit 210 does not change the selection of output circuit 208. Specifically, the horizontal scanning circuit 210 maintains the state in which output circuit 208_4 is selected.

[0051] At time TC7, the prohibition period 2 ends. Subsequently, at time TC8, the horizontal scanning circuit 210 deselects the output circuit 208_4 by switching the control signal BSEL_4 to a low level. In the example above, time T07a, when the S signal data for the OB pixel circuit 201a is determined, is included in the prohibition period 2.

[0052] The selection of the output circuit 208 may be changed so that the effect of power supply fluctuations on the AD conversion operation is similar for the N signal and the S signal. For example, the time from the start of AD conversion period 1 until the last change in the selection of the output circuit 208 between the start of prohibition period 1 (TC2-T02) may be equal to the time from the start of AD conversion period 2 until the last change in the selection of the output circuit 208 between the start of prohibition period 2 (TC5-T06).

[0053] As described above, according to this embodiment, the impact of changing the selection of the output circuit 208 on AD conversion can be reduced. This improves the accuracy of AD conversion.

[0054] Alternatively, the timing of the change of the comparison signal COMP to a low level in the AD conversion of the N signal may be controlled by having the comparator 301 hold an offset prior to the AD conversion period 1. This operation is also called auto-zero operation. For example, in the configuration shown in Figure 2 of Japanese Patent Application Publication No. 2021-64859, an offset may be assigned to multiple comparators 301 by the operation from time t1 to t12 shown in Figure 3 of the same publication, and the offset may be held. In this case, in the AD conversion of the N signal, the timing of the change of the comparison signal COMP to a low level is typically set near the middle of the AD conversion period 1. For this reason, as in this embodiment, the prohibition period 1 is set near the middle of the AD conversion period 1 (the period from 0.35T elapsed from the start to 0.65T elapsed, where T is the length of the AD conversion period). This makes it easier to obtain the effects of this embodiment. Furthermore, by setting the prohibition period 1 to the period from 0.25T to 0.75T after the start of the AD conversion period 1, it is possible to make it less likely for the operation of changing the selection of the output circuit from the multiple output circuits 208 to coincide with the timing of the change of the comparison signal COMP to a low level.

[0055] <Second Embodiment> The first embodiment describes the case in which the photoelectric converter 101 operates in an operating mode in which data is read from all memory circuits 205. This operating mode is called the full memory mode. In the second embodiment, the photoelectric converter 101 can operate in an operating mode in which data is read from only some of the memory circuits 205, instead of or in addition to the full memory mode. This operating mode in which a small number of output circuits 208 are selected is called the partial memory mode. For example, the photoelectric converter 101 operates in partial memory mode when reading signals from adjacent pixel rows by binning, or when reading signals from only some of the pixel rows (i.e., in the case of crop reading).

[0056] In the following section, as an example of partial memory mode, we will describe a case in which pixel signals are read out only from the 10 x 4 pixel circuit 201 included in region 800 of Figure 8, out of the multiple pixel circuits 201, by crop reading. Figure 8 is a diagram in which region 800 is added to the photoelectric converter 101 shown in Figure 2. In this example, only the memory circuits 205 corresponding to the pixel circuits 201 included in region 800 (specifically, memory circuits 205_1 to 205_4) are used, and the other memory circuits 205 (specifically, memory circuits 205_5 to 205_16) are not used.

[0057] The operation of the photoelectric converter 101 in full memory mode is the same as that described in Figure 6. The operation of the photoelectric converter 101 in partial memory mode will be described with reference to Figure 9. The explanation of the parts common to Figure 6 will be omitted. In this example, the memory circuits 205 included in memory blocks 206_2 to 206_4 are not selected. Therefore, the horizontal scanning circuit 210 maintains the control signals BSEL_2 to BSEL_4 and READ_5 to READ_16 at a low level. In partial memory mode, the number of times the selection of the output circuit 208 is changed is less than in full memory mode. Therefore, the prohibition period during which the selection of the output circuit 208 is prohibited can be made longer.

[0058] The operation of the horizontal scanning circuit 210 will be described in detail with reference to Figure 10. Figure 10 is a diagram that focuses on some signals and some periods in the timing diagram of Figure 9. The start of the prohibition period 1 in partial memory mode may be at the same timing as the start of the prohibition period 1 in full memory mode. On the other hand, the end of the prohibition period 1 in partial memory mode may be at a later timing than the end of the prohibition period 1 in full memory mode. That is, the prohibition period 1 in partial memory mode is longer than the prohibition period 1 in full memory mode. The prohibition period 1 in partial memory mode may continue until the end of the AD conversion period 1.

[0059] The start of prohibition period 2 in partial memory mode may be at the same time as the start of prohibition period 2 in full memory mode. On the other hand, the end of prohibition period 2 in partial memory mode may be at a later time than the end of prohibition period 2 in full memory mode. That is, prohibition period 2 in partial memory mode is longer than prohibition period 2 in full memory mode. Prohibition period 2 in partial memory mode may continue until the end of AD conversion period 2. In the example in Figure 10, output circuit 208_1 is selected before prohibition period 1. Output circuit 208_1 may be selected for other periods, for example, the period shown by the dashed line in Figure 9.

[0060] <Other Embodiments> With reference to Figure 11(a), embodiments of the device 1100 equipped with a semiconductor device 1103 will be described in detail. The semiconductor device 1103 may be a photoelectric converter of any of the embodiments described above. The semiconductor device 1103 may include a semiconductor device 1101 and a package 1102 that houses the semiconductor device 1101. The package 1102 may include a substrate on which the semiconductor device 1101 is fixed and a cover made of glass or the like that faces the semiconductor device 1101. The package 1102 may further include bonding members such as bonding wires or bumps that connect terminals provided on the substrate and terminals (bonding pads) provided on the semiconductor device 1101.

[0061] The device 1100 may include at least one of the following: an optical device 1104, a control device 1105, a processing device 1106, a display device 1107, a storage device 1108, and a mechanical device 1109. The optical device 1104 is, for example, a lens, a shutter, or a mirror. The control device 1105 controls the semiconductor device 1103. The control device 1105 is, for example, a semiconductor device such as an FPGA (Field Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit).

[0062] The processing unit 1106 processes the signals output from the semiconductor device 1103. The processing unit 1106 is a semiconductor device such as a CPU (Central Processing Unit) or ASIC for configuring an AFE (Analog Front End) or DFE (Digital Front End). The display device 1107 is an EL (Electro-Luminescence) display device or liquid crystal display device that displays the information (image) obtained by the semiconductor device 1103. The storage device 1108 is a magnetic device or semiconductor device that stores the information (image) obtained by the semiconductor device 1103. The storage device 1108 is a volatile memory such as SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory), or a non-volatile memory such as flash memory or a hard disk drive.

[0063] The mechanical device 1109 has movable parts or propulsion parts such as a motor or engine. The device 1100 displays signals output from the semiconductor device 1103 on the display device 1107 or transmits them to the outside using a communication device (not shown) provided by the device 1100. For this purpose, the device 1100 may further include a storage device 1108 and a processing device 1106, separate from the memory circuits and arithmetic circuits of the semiconductor device 1103. The mechanical device 1109 may be controlled based on signals output from the semiconductor device 1103.

[0064] Furthermore, the device 1100 is suitable for electronic devices such as information terminals with shooting capabilities (e.g., smartphones and wearable devices) and cameras (e.g., interchangeable lens cameras, compact cameras, video cameras, and surveillance cameras). In a camera, the mechanical device 1109 may drive components of the optical device 1104 for zooming, focusing, and shutter operation. Alternatively, the mechanical device 1109 in a camera may move the semiconductor device 1103 for vibration damping.

[0065] Furthermore, the device 1100 may be a transport device such as a vehicle, ship, or aircraft. The mechanical device 1109 in the transport device may be used as a mobile device. The device 1100 as a transport device may transport the semiconductor device 1103, or it may assist and / or automate driving (piloting) by imaging. The processing device 1106 for assisting and / or automating driving (piloting) may perform processing to operate the mechanical device 1109 as a mobile device based on information obtained from the semiconductor device 1103. Alternatively, the device 1100 may be a medical device such as an endoscope, a measuring instrument such as an analytical distance sensor, an analytical instrument such as an electron microscope, or an office machine such as a copier.

[0066] Embodiments relating to the imaging system and the moving object will be described using Figures 11(b) and 11(c). Figure 11(b) shows an example of an imaging system 1110 relating to an in-vehicle camera. The imaging system 1110 has a photoelectric converter 1111. The photoelectric converter 1111 may be any of the photoelectric converters in the embodiments described above. The imaging system 1110 has an image processing unit 1112, which is an image processing unit that performs image processing on a plurality of image data acquired by the photoelectric converter 1111. The imaging system 1110 also has a parallax acquisition unit 1113, which is an image processing unit that calculates parallax (phase difference of parallax images) from a plurality of image data acquired by the photoelectric converter 1111. Furthermore, the imaging system 1110 has a distance acquisition unit 1114, which is an image processing unit that calculates the distance to an object based on the calculated parallax, and a collision determination unit 1115, which is an image processing unit that determines whether or not there is a possibility of collision based on the calculated distance. Here, the parallax acquisition unit 1113 and the distance acquisition unit 1114 are examples of information acquisition units that acquire information such as distance information to an object. That is, distance information refers to information such as parallax, defocus amount, and distance to an object. The collision determination unit 1115 may use any of this distance information to determine the possibility of a collision. The various processing units described above may be implemented by specially designed hardware, or by general-purpose hardware that performs calculations based on software modules. Furthermore, the processing units may be implemented by FPGAs, ASICs, etc., or by a combination thereof.

[0067] The imaging system 1110 is connected to the vehicle information acquisition device 1116 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The imaging system 1110 is also connected to the control ECU 1117, which is a control device that outputs a control signal to generate braking force on the vehicle based on the judgment result of the collision judgment unit 1115. In other words, the control ECU 1117 is an example of a mobile body control unit that controls a moving object based on distance information. The imaging system 1110 is also connected to the warning device 1118, which issues a warning to the driver based on the judgment result of the collision judgment unit 1115. For example, if the collision judgment unit 1115 determines that there is a high probability of collision, the control ECU 1117 performs vehicle control to avoid a collision or mitigate damage by applying the brakes, releasing the accelerator, or suppressing engine output. The warning device 1118 warns the user by sounding an alarm, displaying warning information on a screen such as a car navigation system, or vibrating the seat belt or steering wheel.

[0068] In this embodiment, the imaging system 1110 captures images of the area around the vehicle, for example, the front or rear. Figure 11(c) shows the imaging system 1110 when capturing images of the area in front of the vehicle (imaging range 1119). The vehicle information acquisition device 1116 sends an instruction to the imaging system 1110 to operate and perform imaging.

[0069] The above explanation described an example of control to prevent collisions with other vehicles, but it can also be applied to control systems that automatically follow other vehicles, or control systems that automatically stay within their lanes. Furthermore, the imaging system can be applied not only to vehicles such as automobiles, but also to mobile objects (transportation equipment) such as ships, aircraft, or industrial robots. The moving parts in mobile objects (transportation equipment) are various moving parts such as engines, motors, wheels, and propellers. In addition, it can be applied not only to mobile objects, but also to a wide range of devices that utilize object recognition, such as intelligent transportation systems (ITS).

[0070] The invention is not limited to the embodiments described above, and various modifications and variations are possible without departing from the spirit and scope of the invention. Accordingly, claims are attached to disclose the scope of the invention. [Explanation of symbols]

[0071] 101 Photoelectric converter, 203 Column circuit, 205 Memory circuit, 208 Output circuit, 210 Horizontal scanning circuit

Claims

1. Multiple pixel circuits, Multiple AD conversion circuits generate digital data by performing AD conversion on analog signals read from the multiple pixel circuits during the AD conversion period. Multiple memory circuits for storing the digital data generated by the multiple AD conversion circuits, Multiple output circuits, each connected to two or more of the aforementioned multiple memory circuits, The system includes a scanning circuit that selects one of the plurality of output circuits and one of two or more memory circuits connected to the selected output circuit, thereby reading the digital data stored in the selected memory circuit to an output line. The scanning circuit does not change the selection of the output circuit from the plurality of output circuits during a prohibition period that includes at least the period from 0.35T to 0.65T after the start of the AD conversion period, where T is the length of the AD conversion period. The scanning circuit is a photoelectric converter that changes the selection of an output circuit from the plurality of output circuits during a period of the AD conversion period that is not included in the prohibited period.

2. Multiple pixel circuits, Multiple AD conversion circuits generate digital data by performing AD conversion on analog signals read from the multiple pixel circuits during the AD conversion period. Multiple memory circuits for storing the digital data generated by the multiple AD conversion circuits, Multiple output circuits, each connected to two or more of the aforementioned multiple memory circuits, The system includes a scanning circuit that selects one of the plurality of output circuits and one of two or more memory circuits connected to the selected output circuit, thereby reading the digital data stored in the selected memory circuit to an output line. The scanning circuit does not change the selection of the output circuit from the plurality of output circuits during a prohibition period that includes at least the period from 0.35T to 0.65T after the start of the AD conversion period, where T is the length of the AD conversion period. The scanning circuit is a photoelectric converter that changes the selection of an output circuit from the plurality of output circuits during the period from the start of the AD conversion period to the start of the prohibition period.

3. The photoelectric converter according to claim 1 or 2, wherein the length of the prohibition period is shorter than the length of the AD conversion period.

4. Multiple pixel circuits, Multiple AD conversion circuits generate digital data by performing AD conversion on analog signals read from the multiple pixel circuits during the AD conversion period. Multiple memory circuits for storing the digital data generated by the multiple AD conversion circuits, Multiple output circuits, each connected to two or more of the aforementioned multiple memory circuits, The system includes a scanning circuit that selects one of the plurality of output circuits and one of two or more memory circuits connected to the selected output circuit, thereby reading the digital data stored in the selected memory circuit to an output line. The scanning circuit does not change the selection of the output circuit from the plurality of output circuits during a prohibition period that includes at least the period from 0.35T to 0.65T after the start of the AD conversion period, where T is the length of the AD conversion period. A photoelectric converter in which the length of the aforementioned prohibition period is shorter than the length of the aforementioned AD conversion period.

5. The aforementioned multiple A / D conversion circuits are, During the first AD conversion period, the first analog signal read from the plurality of pixel circuits in the reset state is converted using AD conversion. During the second AD conversion period, the second analog signal read out from the plurality of pixel circuits, which have accumulated charge corresponding to the incident light, is AD converted. The AD conversion period is the first AD conversion period, The photoelectric converter according to any one of claims 1 to 4, wherein the scanning circuit does not change the selection of an output circuit from the plurality of output circuits during a first prohibition period which includes at least a period from 0.35T to 0.65T after the start of the first AD conversion period, with length T being the length of the first AD conversion period.

6. The photoelectric converter according to claim 5, wherein the scanning circuit does not change the selection of an output circuit from the plurality of output circuits during a second prohibition period which includes at least a period from 0.35T to 0.65T after the start of the second AD conversion period, with length T being the length of the first AD conversion period.

7. The photoelectric converter according to claim 6, wherein the time from the start of the first AD conversion period until the last change in the selection of an output circuit from the plurality of output circuits, between the start of the first prohibition period, is equal to the time from the start of the second AD conversion period until the last change in the selection of an output circuit from the plurality of output circuits, between the start of the second prohibition period.

8. The photoelectric conversion device can operate in a first operating mode and a second operating mode in which the number of selected output circuits from the plurality of output circuits is smaller than in the first operating mode. The photoelectric converter according to claim 6 or 7, wherein in the second operating mode, the first prohibition period continues until the end of the first AD conversion period, and the second prohibition period continues until the end of the second AD conversion period.

9. The photoelectric converter according to any one of claims 1 to 8, wherein the prohibition period includes at least the period from 0.25T elapsed to 0.75T elapsed from the start of the AD conversion period.

10. The AD conversion circuit includes a comparator that receives a lamp signal and outputs a signal indicating the result of comparing the lamp signal with the analog signal. The photoelectric converter according to any one of claims 1 to 9, wherein the AD conversion period is the period from the start of a change in the voltage level of the lamp signal to the end of the change.

11. The photoelectric converter according to claim 10, wherein the comparator holds an offset prior to the AD conversion period.

12. A photoelectric conversion device according to any one of claims 1 to 11, Optical device corresponding to the aforementioned photoelectric converter, A control device for controlling the aforementioned photoelectric converter, A processing device that processes the signal output from the aforementioned photoelectric converter, A display device that displays information obtained by the aforementioned photoelectric converter. A storage device for storing information obtained by the aforementioned photoelectric converter, and An apparatus comprising at least one of the following: a mechanical device that operates based on information obtained from the photoelectric converter; and a device.

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