Substrates for semiconductor devices and semiconductor devices

Abstract

A substrate for a semiconductor device is provided which is provided with restricting portions at appropriate locations, which allows the structure of each portion of the semiconductor device to be optimized and allows the semiconductor device to be manufactured efficiently. [Solution] A substrate for a semiconductor device has at least a metal portion that will become an electrode portion formed on a mother substrate. A restricting portion that restricts a semiconductor element is provided on the mother substrate. The restricting portion has an overhanging portion. The overhanging portion is not formed on the side of the restricting portion that faces the semiconductor element.

Description

Technical Field

[0004] , , , , , , , , , , , , , ,

[0003]

[0001] The present invention relates to a substrate for a semiconductor device used for manufacturing a semiconductor device in a form in which a metal part such as an electrode is exposed at the bottom.

Background Art

[0002] In a conventional semiconductor device in which a semiconductor element is mounted on a substrate, the semiconductor element and a metal terminal for external connection are connected by wiring, and then the entire substrate including the semiconductor element is covered with a protective material such as resin, there is a limit to miniaturization due to its structure. On the other hand, a semiconductor device in which a metal part serving as a semiconductor element mounting part or an electrode part is formed, a semiconductor element is mounted on this metal part, and after processing such as wiring, the surface side of the metal part having the semiconductor element and wiring is sealed with a sealing material such as resin, and the metal part is partially exposed at the bottom has the advantages that its height can be reduced to save space, and heat generated in the semiconductor element can be released to the outside through the exposed metal part, and it is excellent in terms of heat dissipation, and is being increasingly used in the field of ultra-small semiconductor devices such as chip size.

[0003] Such semiconductor devices are mainly manufactured through a manufacturing process in which metal parts serving as semiconductor element mounting parts and electrode parts are integrally formed by plating (electroforming) on a conductive mother substrate for the desired number of semiconductor devices, the surface side of the metal part on which the semiconductor element is mounted and processed such as wiring is sealed with a sealing material, and then only the mother substrate is removed and a large number of semiconductor devices in an integrated state are individually cut. As an example of such a manufacturing method of a semiconductor device, there are those disclosed in JP-A-2002-9196 and JP-A-2004-214265.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Summary of the Invention

[0005] Conventional semiconductor device manufacturing methods have the configuration shown in the aforementioned patent document. In forming the metal part on the matrix substrate, a resist layer is formed in advance to correspond to the formation position of the metal part on the matrix substrate, so that the metal part is formed in the appropriate position by electroplating. A metal such as nickel, which is suitable for formation by plating, is used for this metal part, and the surface of the metal part is generally gold-plated or silver-plated to improve conductivity and the bonding of wiring wires. The resist layer also plays a role in preventing the plating from adhering to areas other than where it is needed. After removing this resist layer with a solvent or the like, the matrix substrate and the metal part formed on its surface are supplied as a semiconductor device substrate. Using this semiconductor device substrate, semiconductor elements are mounted, wired, and sealed with a sealing material are performed in the actual semiconductor device manufacturing process.

[0006] In recent years, there has been an increasing demand for lower profile semiconductor devices manufactured using the above-mentioned semiconductor device substrates, in order to further miniaturize the electronic devices in which these semiconductor devices are used. However, with conventional structures, there are limitations to how thin the metal parts that make up the semiconductor device mounting area and electrode area can be made in order to prevent the semiconductor device mounting area and electrode area from falling off the semiconductor device. Furthermore, the semiconductor device itself needs to maintain a certain thickness to provide the required strength, making further thinning and lower profile difficult. Although a structure without a semiconductor device mounting area can be considered, this would inevitably lead to misalignment of the semiconductor device during mounting.

[0007] The present invention has been made to solve the aforementioned problems, and aims to provide a semiconductor device substrate and a method for manufacturing the substrate, as well as a semiconductor device manufactured using this semiconductor device substrate and a method for manufacturing the same, which enable the optimization of the structure of each part of the resulting semiconductor device by providing restrictive parts at appropriate locations, and enable the efficient manufacture of semiconductor devices. [Means for solving the problem]

[0008] The semiconductor device substrate disclosed in the present invention is a semiconductor device substrate in which at least one metal portion 11 that will become an electrode portion 11b is formed on a master substrate 10, and a restricting portion 11a that restricts the semiconductor element 14 is provided on the master substrate 10.

[0009] As described above, according to the disclosure of the present invention, by providing a restricting portion 11a for restricting the semiconductor element 14 on the matrix substrate 10, it is possible to prevent misalignment of the semiconductor element 14 when mounting the semiconductor element 14 during the manufacturing of a semiconductor device using a semiconductor device substrate.

[0010] Furthermore, in the semiconductor device substrate disclosed in the present invention, the restricting portion 11a is provided by forming a through hole 11e in the metal portion 11. The shape of the through hole 11e is such that it can accommodate a semiconductor element 14.

[0011] As described above, according to the disclosure of the present invention, the restricting portion 11a is provided by forming a through hole 11e in the metal portion 11. By making the shape (size) of the through hole 11e large enough to accommodate the semiconductor element 14, when the semiconductor element 14 is placed in the through hole 11e (restricting portion 11a) during semiconductor device manufacturing, not only is it possible to prevent misalignment of the semiconductor element 14, but the placement position can be lowered compared to when it is mounted on the upper surface of the semiconductor element mounting portion as in the conventional method. As a result, the height of the upper surface of the semiconductor element 11 and the wires that connect the electrode portion 11b and the semiconductor element 14 are also lowered, allowing for the manufacture of a semiconductor device with a reduced thickness, thus achieving a lower profile semiconductor device. Furthermore, as the position of the semiconductor element 14 is lowered, the upper surfaces of the semiconductor element 14 and the electrode portion 11b to which the wires 15 connect are closer together, so the wire length can also be shortened, reducing the amount of wire 15 used and lowering costs. It is preferable that the shape of the through hole 11e be the same as that of the semiconductor element 14.

[0012] Furthermore, the semiconductor device substrate disclosed in the present invention is configured such that the height dimension of the restricting portion 11a is set to be greater than or equal to the thickness dimension of the semiconductor element 14.

[0013] As described above, according to the disclosure of the present invention, by setting the height dimension of the restricting portion 11a to be greater than or equal to the thickness dimension of the semiconductor element 14, the entire side surface of the semiconductor element 14 housed during semiconductor device manufacturing can be restricted by the restricting portion 11a, thereby preventing misalignment of the semiconductor element 14. Furthermore, if the restricting portion 11a consists of a through hole 11e, and the depth dimension of the through hole 11e is set to be greater than or equal to the thickness dimension of the semiconductor element 14, the entire side surface of the semiconductor element 14 will be surrounded and restricted by the restricting portion 11a, thereby more reliably preventing misalignment of the semiconductor element 14.

[0014] Furthermore, the present invention relates to a method for manufacturing a semiconductor device substrate, in which a metal portion 11 that serves as an electrode portion 11b and a restricting portion 11a that restricts a semiconductor element 14 is provided on a master substrate 10, and comprises the steps of forming a first resist layer 12 on the master substrate 10 corresponding to the formation position of the metal portion 11, and forming the metal portion 11 in an exposed area on the surface of the master substrate 10 that is not covered by the first resist layer 12, thereby obtaining a metal portion 11 of a predetermined shape by setting the first resist layer 12.

[0015] Thus, according to the disclosure of the present invention, by setting the first resist layer 12 in the formation of the metal portion 11, the metal portion 11 which will become the electrode portion 11b and the restricting portion 11a can be accurately and easily arranged and formed on the master substrate 10.

[0016] Furthermore, in the method for manufacturing a semiconductor device substrate according to the disclosure of the present invention, the first resist layer 12 is formed at the location where the semiconductor element 14 is to be placed, and after the formation of the metal portion 11 is completed, the first resist layer 12 is finally removed, thereby creating through holes 11e in the area where the first resist layer 12 was located at the semiconductor element placement location.

[0017] As described above, according to the disclosure of the present invention, by arranging the first resist layer 12 in the area where the semiconductor element 14 will be placed, and creating through holes 11e in the finally formed metal portion 11 corresponding to the shape of the first resist layer 12 at the semiconductor element placement position, when manufacturing a semiconductor device using the obtained semiconductor device substrate, the semiconductor element 14 can be placed in the through holes 11e, and the entire side surface of the semiconductor element can be controlled.

[0018] Furthermore, in the method for manufacturing a semiconductor device substrate according to the disclosure of the present invention, a first resist layer 12 is formed on a matrix substrate 10, a second resist layer 16 is formed on at least the first resist layer 12, and a metal portion 11 is formed with a thickness exceeding that of the first resist layer 12 but not exceeding that of the second resist layer 16, thereby forming a substantially overhanging portion 11c that extends toward the first resist layer 12 at the upper edge of the metal portion 11 closer to the first resist layer 12.

[0019] As described above, according to the disclosure of the present invention, in the case of the metal portion 11 constituting the semiconductor device, an overhang 11c is formed on the upper edge of the metal portion 11 closer to the first resist layer 12. When the semiconductor device is manufactured using the obtained semiconductor device substrate, the sealing material 19 hardens with the overhang 11c positioned in a recessed manner. Due to this gripping effect, when the master substrate 10 is peeled off and removed from the semiconductor device, the metal portion 11 remains securely on the sealing material 19 side and is not pulled off together with the master substrate 10. This effectively prevents displacement or loss of the metal portion 11, improving the yield during the manufacturing process. On the other hand, since no overhang 11c is formed on the upper edge of the metal portion 11 closer to the second resist layer 16, the semiconductor element 14 can be smoothly placed in the through hole 11e.

[0020] In addition, the semiconductor device according to the disclosure of the present invention has an electrode portion 11b that is electrically connected to the semiconductor element 14. In the semiconductor device in which the semiconductor element 14 is mounted, the electrical connection between the semiconductor element 14 and the electrode portion 11b, and the sealing with the sealing material 19 are performed, and the back surface side of the electrode portion 11b is exposed at the bottom of the device, a restricting portion 11a for restricting the semiconductor element 14 is provided.

[0021] Thus, according to the disclosure of the present invention, by providing the restricting portion 11a for restricting the semiconductor element 14, the semiconductor element 14 can be restricted by the restricting portion 11a, and the positional deviation of the semiconductor element 14 can be prevented.

[0022] In addition, the semiconductor device according to the disclosure of the present invention is such that the restricting portion 11a is provided at a position directly below the loop top 15' of the wire 15 that joins the semiconductor element 14 and the electrode portion 11b.

[0023] Thus, according to the disclosure of the present invention, by arranging the restricting portion 11a so as to overlap with the position directly below the loop top 15' of the wire 15, the positional deviation of the semiconductor element 14 by the restricting portion 11a can be prevented. Moreover, since the restricting portion 11a and the wire 15 can be in the most distant positional relationship, contact between the restricting portion 11a and the wire 15 can be prevented as much as possible. [[ID=*********]]

Brief Description of the Drawings

[0024] [Figure 1] It is an enlarged view of the main part of the substrate for a semiconductor device according to the first embodiment of the present invention. [Figure 2] It is an explanatory diagram of the process in the manufacturing method of the substrate for a semiconductor device according to the first embodiment of the present invention. [Figure 3] It is an explanatory diagram of the process in the manufacturing method of the substrate for a semiconductor device according to the first embodiment of the present invention. [Figure 4] It is an explanatory diagram of the process in the manufacturing method of the substrate for a semiconductor device according to the first embodiment of the present invention. [Figure 5] It is an explanatory diagram of the process in the manufacturing method of the substrate for a semiconductor device according to the first embodiment of the present invention. [Figure 6] These are a cross-sectional view and a bottom view of a semiconductor device according to the first embodiment of the present invention. [Figure 7] These are a cross-sectional view and a bottom view of another embodiment of the semiconductor device according to the first embodiment of the present invention. [Figure 8] These are a cross-sectional view and a bottom view of a semiconductor device according to a second embodiment of the present invention. [Figure 9] These are a cross-sectional view and a bottom view of a semiconductor device according to a third embodiment of the present invention. [Figure 10] These are a cross-sectional view and a bottom view of a semiconductor device according to the fourth embodiment of the present invention. [Figure 11] These are a cross-sectional view and a bottom view of a semiconductor device according to a fifth embodiment of the present invention. [Figure 12] These are a cross-sectional view and a bottom view of another embodiment of the semiconductor device according to the fifth embodiment of the present invention. [Figure 13] These are a cross-sectional view and a bottom view of a semiconductor device according to the sixth embodiment of the present invention. [Figure 14] This is an explanatory diagram of the arrangement of the regulating part and semiconductor element according to the present invention. [Modes for carrying out the invention]

[0025] (First Embodiment) Hereinafter, a semiconductor device substrate according to the first embodiment of the present invention will be described with reference to Figures 1 to 7. In each of the above figures, the semiconductor device substrate 1 according to this embodiment comprises a master substrate 10 made of a conductive material, a metal portion 11 formed on the master substrate 10 which will be at least an electrode portion 11b of a semiconductor device 70 manufactured using this substrate, and a surface metal layer 13 formed on the surface of the metal portion 11 by plating.

[0026] As shown in Figure 6, the semiconductor device 70 manufactured using this semiconductor device substrate 1 comprises, in addition to the metal portion 11 and surface metal layer 13 obtained from the semiconductor device substrate 1, a semiconductor element 14 that is electrically connected to the electrode portion 11b of the metal portion 11, a wire 15 that joins the semiconductor element 14 and the electrode portion 11b, and a sealing material 19 that covers and seals the surface side of the metal portion 11 including the semiconductor element 14 and the wire 15.

[0027] In this semiconductor device 70, the back side of the metal part 11 is exposed at the bottom as an electrode or heat dissipation pad (see Figure 6(B)), and the back side of this exposed metal part 11 and the back side of the sealing material 19 that appears as part of the device exterior are located on approximately the same plane. On each surface of the semiconductor device 70 other than the bottom, only the sealing material 19 that forms the device exterior is exposed.

[0028] The semiconductor device substrate 1 is manufactured by first forming a second resist layer 16 on a matrix substrate 10, following a first resist layer 12, so that the area where the metal part 11 is to be placed is exposed, then forming the metal part 11 by plating, and finally forming a surface metal layer 13 on the surface of the metal part 11 by plating, after which removing the first resist layer 12 and the second resist layer 16.

[0029] Furthermore, when manufacturing a semiconductor device using this semiconductor device substrate 1, semiconductor elements 14 are mounted and wired onto the semiconductor device substrate 1, and then sealed with a sealing material 19. After sealing, the master substrate 10 is removed from the semiconductor device portion to obtain the semiconductor device 70.

[0030] The master substrate 10 is formed from a conductive metal plate (approximately 0.1 mm thick) such as stainless steel (SUS430, etc.), aluminum, or copper, and forms a key part of the semiconductor device substrate 1 until it is removed during the semiconductor device manufacturing process. At each stage of the semiconductor device substrate manufacturing process, a first resist layer 12 and a metal part 11 are formed on the surface side, and a resist layer 18 is placed on the back side. When forming the metal part 11, current is passed through the master substrate 10, so that the metal part 11 is formed by electroplating in the electrically conductive parts (exposed areas) on the surface of the master substrate 10 that are not covered by the first resist layer 12. Also, when electroplating is performed on the surface metal layer 13, current is passed through the master substrate 10.

[0031] On the other hand, in the semiconductor device manufacturing process using the semiconductor device substrate 1, the surface side of the metal part 11 on the master substrate 10 is covered with a sealing material 19 (see Figure 5(B)). Once sufficient strength is obtained without supporting the metal part 11 and the sealing material 19 with the master substrate 10, the master substrate 10 is removed (see Figure 5(C)). If the master substrate 10 is stainless steel, it is removed by physically peeling it off from the semiconductor device side by applying force. If the master substrate 10 is copper or the like, an etching method is used to dissolve and remove it using a chemical solution. In the case of etching, an etching solution is used that has selective etching properties such that the master substrate 10 is dissolved but the nickel or other material of the metal part 11 is not affected. Once the master substrate 10 is removed, the bottom of the semiconductor device is exposed with the back surfaces of the metal part 11 (electrode part 11b) and the sealing material 19 on the same plane.

[0032] The metal portion 11 is made of nickel, copper, or a nickel alloy such as nickel-cobalt, which is suitable for electroplating, and is formed by electroplating on the portion exposed from the first resist layer 12 on the master substrate 10. In the semiconductor device substrate 1, the metal portion 11 is formed on the surface of the master substrate 10 in a form in which one or more electrode portions 11b are arranged as a single unit, with the number of such portions equal to the number of semiconductor devices to be manufactured being arranged in a line.

[0033] The metal portion 11 is formed with a thickness exceeding the thickness of the first resist layer 12 (for example, a thickness of approximately 60-80 μm), and has a roughly overhanging portion 11c at its upper edge that extends toward the surface of the first resist layer 12. The overhanging portion 11c is obtained by continuing electroplating after the metal portion 11 has been formed to the thickness of the first resist layer 12 during electroplating, allowing the growth of the metal portion to progress not only in the thickness direction but also in other directions not restricted by the first resist layer 12, resulting in a shape that extends toward the first resist layer 12 from the upper end of the metal portion 11 beyond the first resist layer 12. This overhanging portion 11c is then sandwiched and fixed by the sealing material 19 (anchor effect) when the sealing material 19 is applied.

[0034] In addition, a restricting portion 11a is provided as a metal portion 11 for restricting the semiconductor element 14 during semiconductor device manufacturing. Specifically, the restricting portion 11a is formed by creating a through hole 11e in the metal portion 11 where the semiconductor element 14 is to be placed. This restricting portion 11a is created by forming the first resist layer 12, then placing the second resist layer 16 in the area corresponding to the restricting portion 11a, and then removing the first resist layer 12 and the second resist layer 16 in that area to create the through hole 11e, which is the restricting portion 11a. The thickness is such that it maintains the strength necessary to restrict the semiconductor element 14. The semiconductor element 14 can be restricted by this restricting portion 11a, and displacement of the semiconductor element 14 can be prevented when mounting the semiconductor element 14. The back surface of this restricting portion 11a is also exposed on the same plane as the back surface of the sealing material 19, similar to the electrode portion 11b.

[0035] The metal part 11 is mostly formed of nickel or nickel alloys suitable for electroplating, but a thin film 11d of a metal with better solder wettability than the main material such as nickel, such as gold, silver, tin, palladium, or solder, is provided on the back side of the metal part 11 to allow for proper soldering when mounting semiconductor devices. The thickness of this thin film 11d is preferably about 0.01 to 1 μm.

[0036] When forming the metal part 11, a thin film 11d is first formed on the part of the matrix substrate 10 where the first resist layer 12 is absent (exposed area) by plating or the like, and then the main material part such as nickel is further formed on this thin film 11d by plating or the like (see Figure 4(B)). This thin film 11d can also be given the function of preventing corrosion and deterioration of the metal part 11 by etching solution when the matrix substrate 10 is removed by etching.

[0037] Furthermore, when the purpose is to prevent soldering, the formation of the thin film on the back side of the metal part 11 is not limited to before the main material part of the metal part 11 is formed by plating, but may also be performed after the semiconductor device 70 is completed, by forming a thin film on the back side of the metal part 11 exposed from the sealing material 19.

[0038] The first resist layer 12 is made of an insulating material that has dissolution resistance to the plating solution used for electroplating the metal part 11 and plating the surface metal layer 13. It is arranged on the master substrate 10 in a manner that exposes the predetermined placement area of ​​the metal part 11, and is removed after the formation of the metal part 11 and the surface metal layer 13 (see Figure 4(C)).

[0039] This first resist layer 12 is disposed on the master substrate 10 prior to the formation of the metal part 11. Specifically, an alkali-developable photosensitive resist material is tightly disposed on the master substrate 10 to a predetermined thickness, for example, about 50 μm. A mask film 50 with a predetermined pattern corresponding to the position of the metal part 11 of the semiconductor device 70 is placed on top, and the resist is cured by exposure with ultraviolet irradiation (see Figure 2(C)), followed by development to remove the resist material from the unirradiated areas, etc., so that the area where the metal part 11 is to be placed is exposed.

[0040] Furthermore, the second resist layer 16 is formed of an insulating material that has dissolution resistance to the plating solution, similar to the first resist layer 12. It is positioned after the first resist layer 12 is formed, corresponding to the predetermined restricting portion 11a of the metal part 11, and is removed after the metal part 11 and the surface metal layer 13 are formed. As with the first resist layer 12, an alkali-developable photosensitive resist material can be used for this second resist layer 16. This resist material is formed on the surface of the matrix substrate 10 and the first resist layer 12 to a predetermined thickness, for example, a thickness of more than approximately 30 μm. When a mask film 51 with a predetermined pattern corresponding to the placement position of the restricting portion 11a of the metal part 11 is placed on top and the resist is cured by exposure with ultraviolet irradiation, a fixed second resist layer 16 is formed on the matrix substrate 10 and the first resist layer 12. These first resist layer 12 and second resist layer 16 prevent electroplating from progressing in the portion corresponding to the restricted portion 11a of the metal part 11, thus providing a restricted portion 11a of the missing part of the metal part 11, i.e., the through hole 11e.

[0041] Furthermore, the first resist layer 12 and the second resist layer 16 are not limited to photosensitive resists. They can also be formed by applying a coating that does not deteriorate in response to the plating solution and provides a high-strength coating film, using electrodeposition coating or the like, to the required coating thickness so that the areas where the metal parts 11 are placed on the matrix substrate 10 are exposed.

[0042] On the other hand, separate from the first resist layer 12 and the second resist layer 16 on the surface side, a resist layer 18 is also formed on the back side of the matrix substrate 10 (see Figure 2). The resist layer 18 on the back side can be formed by heat-pressing a resist material that is resistant to plating solutions in the cured state and can be easily dissolved and removed when no longer needed, such as an alkali-developable photosensitive film resist with a thickness of approximately 50 μm, and then cured and formed over the entire back surface by exposure by ultraviolet irradiation without a mask. Note that the resist layer 18 is not limited to resist; for example, it could be a cover film, or any material that has insulating properties.

[0043] The surface metal layer 13 is formed as a plating film made of gold, silver, palladium, etc., which has excellent bonding properties with gold wires, etc., that make up the wiring wires 15. This surface metal layer 13 is formed on the surface of the metal part 11 by plating each master substrate 10, with a predetermined thickness, for example, about 0.1 to 1 μm in the case of gold plating, and about 1 to 10 μm in the case of silver plating. When plating this surface metal layer 13, the back side of the master substrate 10 is covered with a resist layer 18, so no plating adhesion occurs (see Figure 4(B)). When plating this surface metal layer 13, a different plating solution is used from the one used for plating the metal part 11, and a plating solution corresponding to the metal to be plated is used.

[0044] When forming the plating of this surface metal layer 13, if the metal part 11 is nickel, the plating does not adhere well. Therefore, it is generally desirable to apply a base plating (copper strike, nickel strike, silver strike, or gold strike) to the surface of the metal part 11 before plating the surface metal layer 13 to improve the adhesion of the surface metal layer 13 to the metal part 11.

[0045] The semiconductor element 14 is a so-called chip on which a fine electronic circuit is formed. Wires 15 made of conductive wires such as gold and copper are bonded to electrodes provided on the surface of the semiconductor element 14 and to electrode portions 11b of the metal portion 11, respectively, thereby electrically connecting the semiconductor element 14 and the electrode portion 11b.

[0046] At this time, the semiconductor element 14 is restricted by the restricting portion 11a, thus preventing misalignment of the semiconductor element. Moreover, the restricting portion 11a can be obtained by forming a through hole 11e in the metal portion 11, and if the semiconductor element 14 is placed within this through hole 11e, the semiconductor element 14 will be placed surrounded by the restricting portion 11a, thus more reliably preventing misalignment of the semiconductor element 14. Furthermore, compared to the conventional method of mounting on the upper surface of the semiconductor element mounting portion, the placement position can be lowered, and since the upper surface of the semiconductor element 14 and the wires 15 to which it is joined are also lowered, the thickness of the semiconductor device 70 can be reduced during manufacturing, achieving a lower profile semiconductor device 70. In addition, because the position of the semiconductor element 14 is lowered, the upper surfaces of the semiconductor element 14 and the electrode portion 11b to which the wires 15 join are closer together, the length of the wires 15 can also be shortened, reducing the amount of wires 15 used and lowering costs. Note that when the semiconductor element 14 is placed within the through hole 11e, the back surface of the semiconductor element 14 will also be exposed from the bottom of the semiconductor device 70.

[0047] The sealing material 19 is a thermosetting epoxy resin or the like with high physical strength, and seals the semiconductor element 14 and wire 15 on the surface side of the metal part 11, thereby protecting the structurally weak parts of the semiconductor element 14 and wire 15 from the outside. If the semiconductor element 14 is a light-emitting element such as an LED, a light-transmitting material is used.

[0048] The sealing process using this sealing material 19 is performed on the semiconductor device substrate 1. The area on the surface side of the master substrate 10 that will become a semiconductor device, including the metal part 11, is covered with a mold that will serve as the upper mold. The sealing material 19 is then pressed between the mold and the master substrate 10, and the sealing is completed by hardening the sealing material 19. However, in the sealing process, the semiconductor element mounting area 11a and multiple electrode parts 11b that will become a single semiconductor device are sealed uniformly while remaining in an aligned state, so the semiconductor device is in a state where many are connected via the sealing material 19.

[0049] This sealing material 19 has sufficient physical strength and adequately protects the interior as part of the exterior of the semiconductor device 70. Even when the matrix substrate 10 is physically removed by applying force, such as by peeling it away from the semiconductor device, it maintains its integrated state with the metal part 11 without cracking or other damage.

[0050] Next, we will describe each step in the manufacturing process of a semiconductor device substrate and the manufacturing process of a semiconductor device using the semiconductor device substrate according to this embodiment.

[0051] As part of the manufacturing process for semiconductor device substrates, first, a master substrate 10 is prepared (Figure 2(A)), and a first resist layer 12 is placed on the master substrate 10 corresponding to the areas where the metal parts 11 are not to be placed. Specifically, a photosensitive resist material 12a is placed on the surface side of the master substrate 10 so as to correspond to the shape and height (for example, about 50 μm) of the metal parts 11 to be formed (see Figure 2(B)). A mask film 50 with a predetermined pattern corresponding to the placement positions of the metal parts 11 is placed on the photosensitive resist material 12a, and curing is performed by exposure with ultraviolet irradiation (see Figure 2(C)), development is performed to remove the resist material from the unirradiated areas, etc., to form a first resist layer 12 in which the placement areas of the metal parts 11 are exposed (see Figure 3(A)). In addition, a photosensitive resist material is placed on the back side of the master substrate 10 in the same way as on the front side, and a resist layer 18 is formed over the entire back surface by exposure and other treatments on the entire surface of this resist material (see Figure 2(C)).

[0052] After forming the first resist layer 12, a second resist layer 16 is placed on top of the first resist layer 12, which has been formed to a predetermined thickness, corresponding to the restricting portion 11a in the metal portion 11. Specifically, a photosensitive resist material 16a is placed in close contact with the surface side of the matrix substrate 10 and the first resist layer 12, to a predetermined thickness (for example, about 30 μm) that is greater than the height (depth) of the restricting portion 11a having the through-hole 11e (see Figure 3(B)). A mask film 51 with a predetermined pattern corresponding to the placement position of the restricting portion 11a (through-hole 11e) is placed on this photosensitive resist material, and processes such as exposure by ultraviolet irradiation (see Figure 3(C)) and development to remove the resist agent from the unirradiated areas are performed to form a second resist layer 16 corresponding to the location where the restricting portion 11a (through-hole 11e) will be created (see Figure 4(A)). The through-hole 11e is provided by forming the first resist layer 12 and the second resist layer 16, but it can also be provided by forming only the second resist layer 16. Specifically, in the process of forming the first resist layer 12, the photosensitive resist material 12a at the location where the through-hole 11e will be created is not exposed, and in the process of forming the second resist layer 16, the photosensitive resist material 16a at the location where the through-hole 11e will be created is exposed and developed to create the through-hole 11e. Furthermore, if the size of the through-hole 11e is sufficiently larger than the amount of the restricting portion 11a protruding toward the first resist layer 12, the second resist layer 16 may be omitted, and only the first resist layer 12 may be formed at the location where the through-hole 11e will be created.

[0053] Once the resist layers 12 and 16, which have resistance to dissolution in the plating solution used for plating the metal part 11, are formed, the exposed areas on the surface of the master substrate 10 that are not covered by the first resist layer 12 and the second resist layer 16 are subjected to surface oxide film removal or surface activation treatment as needed. Specifically, depending on the materials of the master substrate 10 and the metal part 11 (thin film 11d), degreasing, acid immersion, chemical etching, electrolytic treatment, strike plating, etc., are selected and performed. Chemical etching dissolves the master substrate 10 itself and removes the oxide film (inert film) from its surface, resulting in a rough surface.

[0054] Subsequently, a thin gold film 11d for improving solder wettability is formed on this exposed portion by plating, for example, with a thickness of 0.01 to 1 μm (see Figure 4(B)). Then, nickel is laminated on this thin film 11d by electroplating to form the metal part 11 (see Figure 4(B)).

[0055] In the process of forming the metal part 11, the metal part 11 is formed to a thickness that exceeds the thickness of the first resist layer 12 but does not exceed the upper surface of the second resist layer 16, and has a portion that is in contact with the side surface of the second resist layer 16, while a roughly overhanging portion 11c is formed on the upper edge of the metal part 11 closer to the first resist layer 12, and the metal part 11 is not formed in the area where the second resist layer 16 is located. The metal part 11 is formed on the surface of the matrix substrate 10 in a form in which one or more electrode portions 11b are arranged as a single unit, with the number of portions equal to the number of semiconductor devices to be manufactured being arranged in a line.

[0056] Once a metal part 11 of the desired thickness and shape is obtained, a surface metal layer 13 is formed on the surface of the metal part 11 by immersion in the plating bath for each master substrate 10, to a predetermined thickness, for example, approximately 0.1 to 0.5 μm in the case of silver plating (see Figure 4(B)). The first resist layer 12 and the second resist layer 16 have sufficient resistance to the plating solution used in the plating bath, so no deterioration occurs, maintaining their function as resist layers and preventing plating from adhering to areas other than where it is needed. Furthermore, during the plating of this surface metal layer 13, the back side of the master substrate 10 is covered with the resist layer 18, so no plating adheres to that side.

[0057] After forming the surface metal layer 13, the first resist layer 12 on the surface side of the matrix substrate 10, the second resist layer 16, and the resist layer 18 on the back side are removed (dissolved and removed by swelling) (see Figure 4(C)) to complete the semiconductor device substrate 1. At this time, by removing the second resist layer 16 and the first resist layer 12 formed beneath it, a restricting portion 11a with through holes 11e is revealed.

[0058] Next, the manufacturing of a semiconductor device using the obtained semiconductor device substrate 1 will be described. First, a semiconductor element 14 is inserted and mounted in the through hole 11e of the semiconductor device substrate 1, and the semiconductor element 14 is fixed in place by the restricting portion 11a. Then, a wire 15 such as a gold wire is joined to the electrodes on the surface of the semiconductor element 14 and the corresponding electrode portions 11b, thereby electrically connecting the semiconductor element 14 and the electrode portions 11b (see Figure 5(A)). This electrical connection by wiring is performed using an ultrasonic bonding device or the like. Since a surface metal layer 13 is formed on the surface of the electrode portions 11b, the bonding with the wire 15 can be made secure, and the reliability of the connection can be increased. When connecting the semiconductor element 14 and the electrode portions 11b with the wire 15, there is a risk that the semiconductor element 14 may fall off from its placement location. To prevent this, it is advisable to apply a temporary adhesive (die attach film, resin film, resin paste, etc.) in advance to the back surface of the semiconductor element 14 or to the placement location of the semiconductor element 14.

[0059] Once the connection between the semiconductor element 14 and each electrode portion 11b is complete, the area on the surface side of the master substrate 10 that will become a semiconductor device, including the metal portion 11, is sealed with a sealing material 19 such as a thermosetting epoxy resin, thereby protecting the semiconductor element 14 and wires 15 from the outside (see Figure 5(B)). Specifically, the surface side of the master substrate 10 is mounted on a mold that will become the upper mold, and the master substrate 10 acts as the lower mold while epoxy resin, which will become the sealing material 19, is injected into the mold. As a result, on the master substrate 10, multiple electrode portions 11b that will become a single semiconductor device are uniformly sealed in an aligned state, and multiple semiconductor devices appear connected together.

[0060] Once the semiconductor device with multiple connected components is obtained, the master substrate 10 is removed, and the back side of the metal part 11 and the back side of the semiconductor element 14 are exposed at the bottom of each semiconductor device (see Figure 5(C)). To remove the master substrate 10, which is made of stainless steel, a method is used in which the master substrate 10 is physically peeled off from the semiconductor device. By using stainless steel, which has excellent strength and peelability, for the master substrate 10, the master substrate 10 can be quickly separated and removed by peeling it off from the semiconductor device.

[0061] In addition, another method for removing the master substrate 10 is to etch (dissolve) it. In this etching method, an etching solution is used that has selective etching properties such that the master substrate 10 is dissolved but the thin film 11d and the material of the metal part 11 are not affected. When removing by dissolution, excessive force is not applied to the semiconductor device, so the probability of adverse effects associated with the removal of the master substrate 10 can be reduced.

[0062] At the bottom of the semiconductor device after the master substrate 10 has been removed, the back side of the exposed metal part 11 and the back side of the sealing material 19 are located on approximately the same plane. After the master substrate 10 is removed, if the numerous connected semiconductor devices are separated one by one, a complete semiconductor device 70 is obtained.

[0063] Inside the resulting semiconductor device 70, the upper edge of the metal part 11 is formed as an overhang portion 11c, which protrudes in a roughly eaves-like shape. In the sealed state with the sealing material 19, this overhang portion 11c is surrounded and fixed by the sealing material 19. As a result, the overhang portion 11 bites into the sealing material 19, which is tightly bonded and firmly integrated with the resin, and acts as a resistor against external forces applied to the metal part 11. For example, when stainless steel or the like is used for the master substrate 10 and the master substrate 10 is physically peeled off from the semiconductor device side, even if an external force is applied to the back side of the metal part 11 that attempts to separate it from the device exterior, the overhang portion 11 prevents the movement of the metal part 11, eliminating displacement of the metal part 11 relative to other parts. This improves the yield during manufacturing, increases the strength of the semiconductor device, and enhances durability during use and the reliability of the semiconductor device's operation.

[0064] As described above, the semiconductor device substrate 1 according to this embodiment has a restricting portion 11a on the master substrate 10, which prevents misalignment of the semiconductor element 14 when manufacturing a semiconductor device 70 using this semiconductor device substrate 1. Furthermore, since the restricting portion 11a is a through-hole 11e of a size that allows the semiconductor element 14 to be inserted and restricted during the semiconductor device manufacturing process, when manufacturing a semiconductor device 70 using this semiconductor device substrate 1, the mounting position of the semiconductor element 14 can be lowered compared to when it is mounted on the upper surface of the semiconductor element mounting portion as in the conventional method. As a result, the height of the upper surface of the semiconductor element 14 and the wire 15 that connects the electrode portion 11b and the semiconductor element 14 are also reduced, allowing for the manufacture of a thinner semiconductor device 70, thus achieving a lower profile semiconductor device 70. In addition, as the position of the semiconductor element 14 is lowered and the upper surfaces of the semiconductor element 14 and the electrode portion 11b to which the wire 15 connects are closer to each other, the wire length can also be shortened, reducing the amount of wire used and contributing to cost reduction.

[0065] In this embodiment, the semiconductor device substrate 1 has a straight through-hole 11e, but it may also be tapered. If the tapered through-hole widens toward the surface side of the matrix substrate (the back side of the semiconductor device), it is possible to create a structure in which the semiconductor element is less likely to fall out after being inserted into the through-hole during the manufacturing of the semiconductor device. Alternatively, if the tapered through-hole narrows toward the surface side of the matrix substrate (the back side of the semiconductor device), it is possible to create a structure in which the semiconductor element is easier to insert into the through-hole during the manufacturing of the semiconductor device.

[0066] Furthermore, as shown in Figure 7, the semiconductor element 14 can also be positioned in the middle (wall) of a tapered through-hole 11e that narrows toward the surface side of the matrix substrate 10 (the back side of the semiconductor device 71). This structure also makes it possible to prevent misalignment of the semiconductor element 14 and to achieve a lower profile semiconductor device. This tapered through-hole 11e can be easily obtained by forming the first resist layer 12 and the second resist layer 16 to correspond to the desired tapered shape. In the semiconductor device 71 shown in Figure 7, the semiconductor element 14 is exposed from its bottom, but by sealing the space surrounded by the bottom of the semiconductor element 14 and the inner wall of the tapered through-hole with a sealing material 19, it is also possible to have a configuration in which the semiconductor element 14 is not exposed from the bottom of the semiconductor device (a configuration in which the back surface of the semiconductor element 14 is covered with the sealing material 19).

[0067] (Second Embodiment) The semiconductor device substrate according to the second embodiment comprises a matrix substrate 10, an electrode portion 11b, and a restricting portion 11a, similar to the first embodiment. Figure 8 shows a semiconductor device 72 manufactured using a semiconductor device substrate with this configuration. As shown in Figure 8, the height of the restricting portion 11a (depth of the through hole 11e) is set to be greater than or equal to the thickness of the semiconductor element 14.

[0068] In this way, by setting the height dimension of the restricting portion 11a to be greater than or equal to the thickness dimension of the semiconductor element 14, the entire side surface of the semiconductor element 14 can be restricted by the restricting portion 11a, thereby preventing misalignment of the semiconductor element 14. Furthermore, if the restricting portion 11a consists of a through hole 11e, the entire side surface of the semiconductor element 14 will be covered and restricted by the restricting portion 11a, thus preventing misalignment of the semiconductor element 14 more reliably. In addition, since the side surface of the semiconductor element 14 is positioned opposite the restricting portion 11a, heat dissipation can be improved.

[0069] Furthermore, to obtain a regulating portion 11a (through-hole 11e) of a desired height (depth), it can be easily obtained by adjusting the thickness of the first resist layer 12 and / or the second resist layer 16 formed on the matrix substrate 10 during the process of forming the first resist layer 12 and the second resist layer 16 in the manufacturing process of the semiconductor device substrate in the first embodiment (see Figures 2(B) to 4(A)), that is, by setting the thickness of the first resist layer 12 and / or the second resist layer 16 to be greater than or equal to the thickness of the semiconductor element 14.

[0070] (Third embodiment) In the semiconductor device substrate described above, the electrode portion 11b and the restricting portion 11a are provided separately on the master substrate 10, and in the semiconductor device manufacturing process using this semiconductor device substrate, the semiconductor element 14 is mounted so as to be restricted by the restricting portion 11a. However, in the semiconductor device substrate according to the third embodiment, the electrode portion 11b also serves as the restricting portion 11a.

[0071] The semiconductor device substrate according to this embodiment comprises a master substrate 10 and electrode portions 11b, similar to the above embodiment, but differs in that the electrode portions 11b also serve as the restricting portions 11a in the above embodiment. The spaces between each electrode portion 11b correspond to through holes 11e, and semiconductor elements 14 are arranged between these electrode portions 11b. These electrode portions 11 are the planned locations for the placement of semiconductor elements 14 in a later semiconductor device manufacturing process, and are formed on the master substrate 10 with a spacing greater than or equal to the outer diameter of the semiconductor elements 14. Figure 9 shows a semiconductor device 73 manufactured using a semiconductor device substrate with this configuration.

[0072] In this configuration, the electrode portion 11b also serves as the restricting portion 11a, which eliminates the need to form the restricting portion compared to a configuration where the electrode portion and the restricting portion are formed separately. This allows for a more compact semiconductor device. Furthermore, by eliminating the need to form the restricting portion, it becomes possible to increase the number of semiconductor devices formed on the matrix substrate 10 by the amount of the restricting portion's area, thereby reducing costs.

[0073] The manufacturing process for the semiconductor device substrate according to this embodiment can be described by omitting the formation of the resist pattern corresponding to the restricting portion 11a in the process of forming the first resist layer 12 (and the second resist layer 16) on the master substrate 10 in the manufacturing process for the semiconductor device substrate according to the first embodiment. Other aspects are the same as in the first embodiment. Furthermore, the subsequent manufacturing process for a semiconductor device using the semiconductor device substrate is also the same as in the first embodiment.

[0074] (Fourth Embodiment) The semiconductor device substrate according to the fourth embodiment comprises a matrix substrate 10, an electrode portion 11b, and a restricting portion 11a, similar to the above embodiment. Figure 10 shows a semiconductor device 74 manufactured using a semiconductor device substrate with this configuration. The restricting portion 11a is positioned to overlap directly below the loop top portion 15' of the wire 15. In other words, the restricting portion 11a and the loop top portion 15' of the wire 15 are located on a straight line in the height direction of the semiconductor device (semiconductor device substrate). Here, the loop top portion 15' refers to the highest point of the wire 14 that connects the electrode of the semiconductor element 14 and the metal electrode portion 11b.

[0075] In this way, by positioning the restricting portion 11a directly below the loop top portion 15' of the wire 15, misalignment of the semiconductor element 14 can be prevented, and contact between the restricting portion 11a and the wire 15 can be prevented as much as possible.

[0076] Furthermore, a semiconductor device substrate with the above configuration can be easily obtained by adjusting the shape and thickness of the first resist layer 12 and / or second resist layer 16 corresponding to the placement area of ​​the semiconductor element 14 on the matrix substrate 10 during the manufacturing process of the semiconductor device substrate in the first embodiment described above.

[0077] (Fifth embodiment) The semiconductor device substrate according to the fifth embodiment comprises a matrix substrate 10, an electrode portion 11b, and a restricting portion 11a. A through hole 11e is formed as the restricting portion 11a, and a recess 11f is provided so as to overlap the through hole 11e. The bottom surface (bottom area) of this recess 11f is larger than the opening (opening area) of the through hole 11e. Figure 11 shows a semiconductor device 75 manufactured using a semiconductor device substrate with the above configuration.

[0078] In this configuration, by providing a recess 11f that overlaps with the through-hole 11e, it is possible to prevent misalignment of the semiconductor element 14 due to the inner surface of the recess 11f and to reduce the height of the semiconductor device. Moreover, by arranging the semiconductor element 14 on the bottom surface of the recess 11f so as to cover the through-hole 11e, the semiconductor element 14 can be positioned in a recessed location from the bottom of the semiconductor device 70 (the back surface of the sealing material 19), thereby protecting the semiconductor element 14 from external forces.

[0079] Furthermore, a semiconductor device substrate with the above configuration can be easily obtained by adjusting the shape and thickness of the first resist layer 12 and / or second resist layer 16 corresponding to the restricting portion 11a (through hole 11e) formed on the matrix substrate 10 during the manufacturing process of the semiconductor device substrate in the first embodiment described above.

[0080] At the bottom of the semiconductor device 75, the back surface of the semiconductor element 14 is exposed through the through-hole 11e. However, as in the first embodiment described above, by sealing the through-hole 11e with a sealing material 19, the semiconductor device 76 can be configured such that the semiconductor element 14 is not exposed from the bottom (the back surface of the semiconductor element 14 is covered with the sealing material 19), as shown in Figure 12.

[0081] (Sixth Embodiment) The semiconductor device substrate according to the sixth embodiment comprises a matrix substrate 10 and an electrode portion 11b, the electrode portion 11b also serving as a restricting portion 11a (the space between the electrode portions 11 corresponds to a through hole 11e), and an extension portion 20 is integrally provided on the upper part of the electrode portion 11b. Figure 13 shows a semiconductor device 77 manufactured using a semiconductor device substrate with the above configuration. The extension portion 20 is provided so as to extend toward the semiconductor element 14, and the extension portion 20 and the electrodes of the semiconductor element 14 are electrically connected.

[0082] In this configuration, the extension portion 20 is provided above the electrode portion 11b (regulating portion 11a). This allows the electrode portion 11b (regulating portion 11a) to regulate the side surface of the semiconductor element 14, as well as the extension portion 20 to regulate the top surface of the semiconductor element 14. Therefore, positional deviations from each surface of the semiconductor element 14 can be suppressed.

[0083] To obtain a semiconductor device substrate with the above configuration, in the manufacturing process of the semiconductor device substrate in the first embodiment, electrode portions 11b (regulating portions 11a) are formed on the master substrate 10, semiconductor elements 14 are placed between the electrode portions 11b, and then, in order to form the extension portion 20, a resist layer is formed so that the upper surface of the electrode portions 11b (regulating portions 11a) and the upper surface of the semiconductor elements 14 are exposed, and then it is plated.

[0084] In the above embodiment, as shown in Figure 14(A), the protruding portion 11c is not formed on the upper edge of the side of the restricting portion 11a facing the semiconductor element 14 (the side in contact with the side surface of the second resist layer 16). However, as shown in Figure 14(B), the protruding portion 11c may also be formed on the side of the restricting portion 11a facing the semiconductor element 14. In this case, the formation of the second resist layer 16, which was formed on the first resist layer 12, is omitted. That is, as shown in Figure 3(A), after forming the first resist layer 12 on the master substrate 10, plating is performed until the thickness exceeds that of the first resist layer 12 without forming the second resist layer 16. Alternatively, the upper edge of the metal portion 11 (restricting portion 11a, electrode portion 11b) may be made straight without forming the protruding portion 11c (see Figure 14(C)). In this case, as shown in Figure 3(A), after forming the first resist layer 12 on the master substrate 10, plating is performed so as not to exceed the thickness of the first resist layer 12.

[0085] Furthermore, in the above embodiment, when forming the first resist layer 12 and the second resist layer 16, the photosensitive resist material 12a is placed and exposed and developed before the photosensitive resist material 16a is placed. However, it is also possible to place the photosensitive resist material 12a and expose it, then place the photosensitive resist material 16a without developing it, expose it, and then develop the photosensitive resist material 12a and the photosensitive resist material 16a together. In addition, when forming the first resist layer 12 and the second resist layer 16, exposure is performed using mask films 50 and 51, but exposure may also be performed using a direct writing device.

[0086] Furthermore, in the above embodiment, when the semiconductor element 14 is disposed in the through hole 11e, there may be a gap between the inner surface of the through hole 11e and the outer surface of the semiconductor element 14, or there may be no gap between the inner surface of the through hole 11e and the outer surface of the semiconductor element 14, and the restricting portion 11a and the semiconductor element 14 may be disposed in close contact.

[0087] Alternatively, to provide grounding, the regulating section 11a may be used as a grounding electrode, and the ground wire may be connected to the regulating section 11a. [Explanation of symbols]

[0088] 1. Substrate for semiconductor device 10 Master board 11 Metal parts 11a Regulatory Department 11b Electrode section 11c Overhang 11d thin film 11e Through hole 11f recess 12. First resist layer 12a Resist material 13 Surface metal layer 14 Semiconductor devices 15 wires 16. Second Resist Layer 16a Resist material 18 Resist Layers 19. Sealing material 20 Extension section 70-77 Semiconductor equipment

Claims

1. In a semiconductor device substrate in which at least a metal portion that will serve as an electrode portion is formed on a matrix substrate, The aforementioned matrix substrate is provided with a mounting area for semiconductor elements and a restricting section for restricting the placement of the semiconductor elements. The upper edge of the regulating portion has a protruding portion, The aforementioned protruding portion is not formed on the side of the restricting portion that faces the mounting area of ​​the semiconductor element. A substrate for a semiconductor device, characterized in that the height of the restricting portion is higher than the height of the semiconductor element mounted in the mounting area.

2. In the semiconductor substrate according to claim 1, A substrate for a semiconductor device, characterized in that the regulating portion also serves as the electrode portion.

3. In a semiconductor device in which a semiconductor element and an electrode portion electrically connected to the semiconductor element are sealed with a sealing material, and the back sides of the semiconductor element and the electrode portion are exposed at the bottom of the device, A regulating unit is provided to regulate the aforementioned semiconductor element, The upper edge of the regulating portion has a protruding portion, The aforementioned protruding portion is not formed on the side of the restricting portion facing the semiconductor element. A semiconductor device characterized in that the height of the restricting portion is greater than the height of the semiconductor element.

4. In the semiconductor device described in claim 3, A semiconductor device characterized in that the regulating portion also serves as the electrode portion.

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