Increasing the dynamic range of digital pixels by utilizing polling during integration.

Abstract

A digital circuit is provided that periodically reads at least one bit of a digital counter associated with a pixel of an image sensor. When the read bit of a particular digital counter decreases during a subsequent reading, the digital circuit increments an overflow counter associated with the particular digital counter. The value of each of the overflow counters of the digital circuit is used together with the corresponding value of the digital counter to generate pixel values ​​for a frame (also referred to as an image).

Description

[Technical Field]

[0001] This disclosure generally relates to digital image sensors, and more specifically, to improving the dynamic range of digital image sensors. [Background technology]

[0002] Modern digital image sensors often include an integrated-then-read mode, where the sensor is triggered while idle. When operating in integrated-then-read mode, the image sensor does not fully utilize its output bandwidth, which is often idle.

[0003] Digital image sensors are susceptible to saturation and noise if they are not polled (i.e., read out or reset) frequently enough. For example, pixels often include a digital counter to track the intensity of light received by the pixel. The digital counter may contain N bits, and if the amount of light received by the pixel exceeds the capacity of the digital counter, it can be rolled over (i.e., reset to a lower value). This introduces uncertainty into the resulting image. [Overview of the project]

[0004] In a typical embodiment, the disclosure provides a system and method for more fully utilizing the bandwidth of a digital image sensor by periodically reading the status of a pixel's digital counter, which is stored either on-chip or off-chip, in order to extend the pixel's dynamic range.

[0005] In one embodiment, a digital circuit periodically reads at least one bit of a digital counter associated with a pixel of an image sensor. When the read bit of a particular digital counter decreases between subsequent reads, the digital circuit increments an overflow counter associated with that particular digital counter. At the end of each frame, the values ​​of each overflow counter of the digital circuit are used together with the corresponding values ​​of the digital counters to generate the pixel values ​​of the frame (also referred to as an image).

[0006] The aspects and embodiments of this disclosure generally relate to read-out integrated circuits (ROICs) of focal plane arrays (FPAs), which include two-dimensional arrays of pixels (also referred to as detector elements). Unlike conventional ROICs, the imaging system described herein includes digital circuitry for interface with a digital counter in the ROIC. Instead of including a higher-bit digital counter, the digital circuitry allows for extending the dynamic range of the pixels (i.e., extending beyond the limit bits of the digital counter) by tracking when the digital counter rolls over.

[0007] According to one embodiment, a method is provided that is performed using a digital circuit to increase the dynamic range of a video frame. The method includes the step of storing an overflow counter associated with each of a plurality of digital counters of an imaging system. Each of the digital counters is associated with and communicates with each of the pixels of the imaging system, and each of the digital counters is configured to store a digital counter value based on a signal received from each of the pixels. For each of the plurality of digital counters, the method periodically reads at least one bit of the digital counter value over a plurality of iterations, compares the at least one bit of the digital counter value from one of the plurality of iterations to a previous iteration of the plurality of iterations, and increments the associated overflow counter of the digital circuit if the value represented by the at least one bit of the digital counter value decreases from the previous iteration to the one iteration. The method also converts and outputs the digital counter values ​​from the plurality of digital counters and at least one of the associated overflow counters as at least one pixel value of the video frame.

[0008] Alternatively or additionally, at least one bit is smaller than all bits of the digital counter value.

[0009] Alternatively or additionally, the at least one bit may be only the most significant bit of the digital counter value.

[0010] Alternatively or additionally, the method further stores the charge generated by each of the multiple pixels in one of a plurality of charge storage devices associated with that pixel. The method periodically determines whether the accumulated charge in each charge storage device exceeds a predetermined threshold. In response to the determination that the accumulated charge in each charge storage device exceeds the predetermined threshold, the method reduces the charge stored in each charge storage device by a predetermined charge reduction amount and increments one of a plurality of digital counter values ​​stored in the digital counter and associated with each of the pixels.

[0011] Alternatively or additionally, each of the pixels further includes a photodetector configured to generate the charge in response to light striking the pixel. Based on the intensity of the light striking the photodetector of at least one of the pixels, the method determines the duration of the period over which the digital circuit reads at least one bit of the digital counter value over a plurality of iterations.

[0012] Alternatively or additionally, the duration of the period is determined based on the intensity of the light hitting the photodetector of the pixel receiving the highest intensity light among the pixels.

[0013] Alternatively or additionally, the method periodically converts the residual charge in each of the plurality of pixels, in each of the plurality of electrostatic storage devices, into an analog signal. The method also uses one of a plurality of analog-to-digital converters to convert the analog signal from each pixel into a corresponding digital binary value, each of the plurality of analog-to-digital converters having an input and an output, and each of the plurality of analog-to-digital converters is coupled via its input to one of the plurality of pixels and the corresponding electrostatic storage device. Each digital binary value is additionally used to convert at least one of the plurality of digital counters and the associated overflow counter into the at least one pixel value of the video frame.

[0014] In another embodiment, a digital circuit is provided for increasing the dynamic range of a video frame. The digital circuit stores an overflow counter associated with each of a plurality of digital counters of an imaging system. Each of the digital counters is associated with and communicates with each of the pixels of the imaging system, and each of the digital counters is configured to store a digital counter value based on a signal received from each of the pixels. For each of the plurality of digital counters, the circuit periodically reads at least one bit of the digital counter value over a plurality of iterations, and compares the at least one bit of the digital counter value from one of the plurality of iterations to a previous iteration of the plurality of iterations. Then, if the value represented by the at least one bit of the digital counter value decreases from the previous iteration to the current iteration, the associated overflow counter is incremented.

[0015] Alternatively or additionally, at least one bit is smaller than all bits of the digital counter value.

[0016] Alternatively or additionally, the at least one bit may be only the most significant bit of the digital counter value.

[0017] Alternatively or additionally, each of the pixels further includes a photodetector configured to generate an electric charge in response to light striking the pixel. The duration of the period during which the digital circuit reads at least one bit of the digital counter value over a plurality of iterations is determined based on the intensity of the light striking at least one of the pixels' photodetectors.

[0018] Alternatively or additionally, the duration of the period is determined based on the intensity of the light hitting the photodetector of the pixel receiving the highest intensity light among the pixels.

[0019] In another embodiment, an imaging system is provided comprising an array of pixels, a plurality of digital counters, and a digital circuit. Each of the pixels is an electrostatic storage device configured to store charge from a photocurrent, and coupled to the electrostatic storage device and configured to convert the charge into an analog quantization event signal. A plurality of digital counters correspond to the array of pixels, each of which is associated with and communicates with one of the pixels, and each of which stores a digital counter value in response to receiving the analog quantization event signal from one of the pixels. A digital circuit stores an overflow counter associated with each of the plurality of digital counters. For each of the plurality of digital counters, the digital circuit periodically reads at least one bit of the digital counter value over a plurality of iterations, compares the at least one bit of the digital counter value from one of the plurality of iterations to a previous iteration, and increments the associated overflow counter if the value represented by the at least one bit of the digital counter value decreases from the previous iteration to the one iteration.

[0020] Alternatively or additionally, at least one bit is smaller than all bits of the digital counter value.

[0021] Alternatively or additionally, the at least one bit may be only the most significant bit of the digital counter value.

[0022] Alternatively or additionally, each of the pixels further includes a photodetector configured to generate the charge in response to light striking the pixel. The duration of the period during which the digital circuit reads at least one bit of the digital counter value over a plurality of iterations is determined based on the intensity of the light striking at least one of the pixels' photodetectors.

[0023] Alternatively or additionally, the duration of the period is determined based on the intensity of the light impinging on the photodetector of the pixel receiving the light of the highest intensity among the pixels.

[0024] Alternatively or additionally, the system further includes a digital formatter configured to convert a digital counter value from at least one of the plurality of digital counters and the associated overflow counter into at least one pixel value of a video frame.

[0025] Alternatively or additionally, the system also includes a plurality of analog-to-digital converters, each having an input and an output. Each of the plurality of analog-to-digital converters is coupled to the electrical storage device associated with at least one of the pixels via the input and is configured to convert the residual charge in each electrical storage device into a digital binary value. The digital formatter additionally utilizes the digital binary value from at least one of the plurality of analog-to-digital converters in the conversion of the digital counter value from at least one of the plurality of digital counters and the associated overflow counter into the at least one pixel value of the video frame.

[0026] Alternatively or additionally, each of the pixels further includes a photodetector configured to generate the photocurrent in response to light impinging on the photodetector. The digital counter value corresponds to the intensity of the light impinging on each one of the photodetectors of the pixels.

[0027] Although numerous features relating to embodiments of the present invention are described herein, the features described with respect to a given embodiment can also be used in connection with other embodiments. The following description and the accompanying drawings disclose specific exemplary embodiments of the present invention. However, these embodiments merely illustrate some of the various ways in which the principles of the present invention can be used. Other objects, advantages, and novel features in accordance with aspects of the present invention will become apparent from the following detailed description when considered in conjunction with the drawings.

Brief Description of the Drawings

[0028] The accompanying drawings are not necessarily to scale, but show various aspects of the present invention, and like reference numerals are used to indicate the same or similar parts in the various views. [Figure 1] FIG. 1 is a block diagram of an imaging system. [Figure 2] FIG. 2 is a block diagram of a method for generating pixel values using the imaging system. [Figure 3] FIG. 3 shows an exemplary output over time of the imaging system for the method of FIG. 2. [Figure 4] FIG. 4 is a plot of the standard pixel in the imaging system of FIG. 1 and time for the pixel with respect to the pixel value. [[ID=二十]] [Figure 5] FIG. 5 is a block diagram of the imaging system of FIG. 1 additionally including an analog-to-digital converter. [Figure 6] FIG. 6 is a block diagram of a method for increasing the dynamic range of a frame.

[0029] The present invention will now be described in detail with reference to the drawings. In the drawings, each element with a reference number is the same as any other element with the same reference number, regardless of any letter designation following the reference number. In this text, a reference number followed by a specific letter designation refers to the specific element associated with that number and letter designation, while a reference number without a specific letter designation refers to all elements with the same reference number, regardless of any letter designation following the reference number in the drawings. [Modes for carrying out the invention]

[0030] Referring to Figure 1, a general embodiment of the imaging system 100 is shown, which includes a photodetector 105, incident light 110, a capacitor 115, a bias circuit 120, a comparator 125, a charge removal circuit 135, multiple digital counters 145, a tri-state gate 150, a data outline 180, multiple pixels 190 (also referred to as detector elements or pixels) in an array 195, and a digital circuit 210. Each digital counter 145 is associated with and communicates with each of the pixels 190. Each digital counter 145 increments and stores a digital counter value. Each pixel 190 includes a quantization circuit (also referred to as an electrical storage device) coupled to a capacitor 115, and is configured to convert charge into an analog quantized event signal. Each digital counter 145 stores a digital counter value in response to the reception of an analog quantization event signal from the pixel associated with the digital counter 145.

[0031] The digital circuit 210 stores an overflow counter associated with each of the multiple digital counters in memory 230 (e.g., a non-temporary computer-readable medium). In particular, the digital circuit 210 periodically reads at least one bit of the value for each of the digital counters 145 over multiple iterations. The digital circuit 210 compares the bit of the digital counter value from one iteration to the previous iteration. When the bit value of a particular digital counter 145 decreases from the previous iteration to the current iteration, the digital circuit 210 increments the associated overflow counter.

[0032] In one embodiment, the digital circuit 210 reads only a portion of the bits of each digital counter. That is, the value of each digital counter 145 may be a digital binary value (i.e., a value represented by multiple bits), and the digital circuit 210 can read only a few bits representing the digital counter value of each digital counter 145. For example, the digital circuit 210 can read only the most significant bit of each digital counter 145. By reading only a portion of the bits representing each digital counter value, the digital counter values ​​can be read more frequently (i.e., at a higher frequency) by the digital circuit, reducing the possibility of aliasing occurring (as will be explained in more detail below).

[0033] Each pixel 190 includes an electrical storage device for accumulating charge from the photocurrent. In one embodiment, pixel 190 includes a photodetector (also called a photodiode) 105 that generates a photocurrent based on the flux of light 110 received by the photodetector 105. The charge is stored in a capacitor 115 (also called a capacitive element) that effectively integrates the charge over an integration time interval to generate a voltage corresponding to the intensity of the flux of light 110. The photodetector 105 receives a voltage V biasIt can be coupled to the capacitor 115 via a bias circuit 120 (such as a MOS transistor or a direct injection gate) that is biased using the above.

[0034] The charge removal circuit 135 includes a circuit that can reset the voltage of the capacitor 115 to its initial state, as well as a circuit that can transfer charge or voltage to the data outline 180 (also referred to as column or row wires) for transfer to the output of the array 195. As described below, such voltage or charge can be digitized by the circuit associated with the focal plane array 195, resulting in binary values ​​(e.g., at least one value for each pixel 190 of the focal plane array 195). Thus, the focal plane array 195 can be used to convert a two-dimensional pattern of light beams into a two-dimensional array of binary values. The resulting array is often referred to as a digital image or frame.

[0035] Array 195 can be configured as a two-dimensional (2D) array organized by columns and rows. The array 195 of digital pixels 190 can be embodied as a readout integrated circuit (ROIC) of a focal plane array. When array 195 is embodied as an ROIC, the digital circuit 210 may be located separately from the ROIC, reducing the cost and complexity of the ROIC. For example, the digital circuit 210 can be embodied as a field-programmable gate array (FPGA) or ASCIIS communicatively coupled to the ROIC. The digital circuit 210, being a separate digital structure, improves area efficiency and cost, and allows for better utilization of output bandwidth. By using a separate structure for the digital circuit 210 (e.g., FPGA), it is also possible to use an existing (e.g., off-shelf) ROIC.

[0036] The digital circuit 210 may include any suitable device, such as a processor (e.g., a CPU), programmable circuitry, integrated circuits, memory and I / O circuits, application-specific integrated circuits, microcontrollers, complex programmable logic devices, their programmable circuits, etc. The digital circuit 210 may also include a non-temporary computer-readable medium, such as random-access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), or any other suitable medium, etc.

[0037] In one embodiment, the digital circuit 210 utilizes commercially available (commercial-off-the-shelf, CTOS) memory for implementation. The power requirements of the digital circuit 210 may be negated by the existing serialization link of the array 195, which exists when the array 195 is embodied as an ROIC. In addition, in the integrated system during reading, the bandwidth of the ROIC is typically available for use by the digital circuit 210, because the bandwidth is not used when no data (such as frames or images) is being transmitted.

[0038] When Array 195 is implemented as ROIC, the ROIC can be optimized for polling by staggering the row connections to the bus, thereby activating multiple rows on the existing bus. This technique can alleviate the timing requirements for reading the most significant bit of the pixel array, enabling higher polling speeds.

[0039] As shown in the embodiment of Figure 1, the digital circuit 210 may be a physical structure separate from the array 195. For example, the digital circuit 210 can be implemented using an FPGA that includes a digital memory 230 for storing at least one digital counter value and an overflow counter. The digital circuit 210 may have the same logic configuration as the array 195 (e.g., 1920 × 1080 memory elements) or a different logic configuration.

[0040] In an integrated-while-read architecture, the digital circuit 210 may include two sets of memory locations for each pixel 190: a first location for storing the current overflow counter value 256 associated with the pixel 190, and a second location for storing the previous overflow counter value 256 associated with the pixel 190.

[0041] As will be explained in more detail below, the effective amount of charge accumulated by the pixel 190 over the integration interval is increased by the addition of a digital counter 145 (also referred to as a digital count circuit). In some embodiments, each pixel 190 is given its own digital counter 145 (referred to as the associated digital counter). As will be explained, the circuit contained in each pixel allows a predetermined amount of charge to be removed from the capacitor 115 of each pixel 190, and correspondingly, the value of the associated digital counter to be increased by one count. Thus, over the elapsed time of the integration interval, (1) the capacitor 115 of the pixel 190 integrates the photocharge, (2) the circuit within the pixel removes a predetermined amount of charge, and (3) the digital counter 145 associated with the pixel 190 counts the number of charge removed. In this way, the effective amount of charge accumulated by the pixel 190 over the integration interval can be increased because the associated digital counter 145 effectively expands the capacitance of the capacitor 115.

[0042] The digital counter 145 may be comprised of multiple digital memory elements coupled to the array 195 of pixels 190. The type of digital counter 145 used to record charge rejection may be any logical variation, including binary, Gray code, linear feedback shift register (LFSR), or any other digital counting circuit capable of counting charge rejection. Furthermore, since the relative sign of charge rejection can be positive or negative with respect to the circuit's ground, charge rejection can in some cases be considered a charge addition.

[0043] Moving to Figure 2, a flowchart of method 300 for generating a value for pixel 190 in the frame is shown. In process block 302, the photocurrent from photodetector 105 is integrated into capacitor 115. In decision block 304, a continuous check is performed to determine whether capacitor 115 has reached its capacity for charge accumulation. If capacitor 115 has not reached its capacity, the process returns to process block 302, and capacitor 115 continues to accumulate charge. If capacitor 115 has reached its capacity, the process moves to process block 306. In process block 306, capacitor 115 is reset to allow for the accumulation of additional charge. In process block 308, the associated digital counter 145 (i.e., the digital counter 145 associated with pixel 190) is incremented, and the process returns to process block 302.

[0044] In the decision block 310, a check is performed to determine whether it is time to poll the relevant digital counter 145. For example, the digital counter 145 associated with pixel 190 may be polled at a given frequency, and the clock may be checked to determine whether enough time has elapsed since the last poll so that it is time to perform an additional poll. If it is not time to poll the digital counter 145, the process returns to the decision block 310 until it is time to poll the relevant digital counter 145. If it is time to poll the relevant digital counter 145, the process moves to the process block 312. In the process block 312 of the embodiment shown in Figure 2, the MSB (or a number of bits smaller than all bits) of the relevant digital counter 145 is polled and sent to the digital circuit 210.

[0045] In decision block 314, a check is performed to determine whether the previously polled MSB of the associated digital counter 145 is greater than the most recently polled MSB of the associated digital counter 145. If not, the process returns to decision block 310. If it is ("yes"), the process moves to process block 316. In process block 316, the digital circuit 210 increments the overflow counter 316 associated with the pixel 190.

[0046] In the decision block 320, a check is performed to determine whether it is time to capture a frame (also referred to as an image). For example, a frame may be captured at a specific frequency, or an image capture command may be generated based on the exposure settings. If so ("yes"), the process moves to process step 322. In process step 322, the value of the relevant digital counter 145 and the digitized residue from the capacitor 115 of the pixel 190 are read. In process step 324, the value of the relevant digital counter 145, the value of the digitized residue from the capacitor 115, and the value of the overflow counter are combined to generate the value of the pixel 190. By performing this process for all pixels 190 in the array 195, a frame with an improved dynamic range is generated.

[0047] Referring to Figure 3, an exemplary relationship between the values ​​of capacitor 115, associated digital counter 145, and overflow counter is shown against time. In the illustrated example, the photocurrent on photodetector 105 is accumulated and stored in capacitor 115. The charge 250 stored by capacitor 115 (also called the residue) is reset when filled, and as a result, the residue 250 appears as a sawtooth plot in Figure 3. When the residue 250 is reset (represented in Figure 3 by the residue 250 decreasing from a maximum to a minimum), the digital counter value 252 of the associated digital counter 145 is incremented.

[0048] The increment of the digital counter value 252 is represented in Figure 3 by a stair step pattern and counter bits. In Figure 3, the digital counter value 252 is represented by four counter bits, including the least significant bit (LSB) and the most significant bit (MSB) 254. Although the digital counter value 252 is represented by four bits in Figure 3, this is merely an example, and the digital counter value 252 may be represented by any number of bits.

[0049] When the digital counter value 252 exceeds the maximum value represented by the counter bits, the digital counter value 252 rolls over and is reset to the minimum value. For example, in the case of 4 bits, the maximum value is 15 and the minimum value is zero. When the digital counter value 252 is incremented from 15, the digital counter value 252 is reset to zero instead of reaching 16. This is represented by the step-by-step pattern in Figure 3, which transitions from the maximum value to the minimum value. When this rollover of the digital counter value 254 occurs, the overflow counter value 256 is incremented. The rollover of the digital counter value 252 can be detected by periodically polling the MSB 254 of the digital counter value 252. If the MSB 254 decreases during polling, this can be used as an indicator that the MSB 254 has rolled over.

[0050] In Figure 3, when a frame end (shown by a dashed line) occurs and a frame is generated, the digital counter value 256 and the remainder 250 from the photodetector 105 are read out and combined with the overflow counter value 256 to determine the value of pixel 190. For example, the pixel value may be defined as follows: Pix Val =Overflow Val × (2 num_bits -1) + DigCounter Val +Res / Mag Res Here, Pix Val is the pixel value, Overflow Val is the overflow value 256, DigCounter Val is the digital counter value 252, num_bits is the number of bits of the digital counter value 254, Res is the remainder 250, and Mag Res is the maximum value of the remainder before the remainder is reset.

[0051] In one embodiment, the imaging system 100 may additionally include a digital formatter for converting the digital counter value 252 from at least one of a plurality of digital counters 145 and associated overflow counters to at least one pixel 190 of a frame. The digital formatter may be off-chip (i.e., separate) computer hardware or on-chip (i.e., included) as part of the digital circuit 210.

[0052] The frequency at which the digital circuit 210 reads and / or stores each bit of the digital counter value 252 can be determined based on the intensity of the light 110 impinging on at least one of the photodetectors 105 of the pixel 190. For example, if at least one of the pixels 190 is receiving bright light, the read frequency at which the digital circuit 210 reads the bits of the digital counter value 252 can be increased to avoid aliasing. Aliasing occurs when the read frequency is not fast enough to account for the change in bits of the digital counter. For example, in FIG. 3, aliasing occurs when the MSB 254 of the digital counter 145 switches from "0" to "1" and back to "0" during polling by the digital circuit 210 and only "0" is seen. That is, aliasing occurs when the digital circuit 210 misses the digital counter 145 flipping one of its MSBs 254 from "0" to "1" and back to "0" and instead only sees "0" and it is "0" during polling.

[0053] Moving on to Figure 4, a plot of pixel value 258 versus pixel 190 over time is shown. The dashed line represents the maximum pixel value 258 for pixel 190 without using the digital circuit 210. For such pixel 190, the maximum pixel value 258 is capped out by the capacity of pixel 190 and / or the number of bits in the digital counter 145. The solid line in Figure 4 shows the pixel value for pixel 190, including the digital counter 145 and using the digital circuit 210 to maintain the overflow counter as described above. As shown, the pixel value 258 represented by the solid line is not limited in the same way as the pixel value 258 represented by the dashed line. Instead, the pixel value 258 represented by the dashed line continues to increase over time.

[0054] In the embodiment shown in Figure 5, each pixel 190 includes a capacitor 115 for accumulating photocharge to generate a voltage, a comparator 125 for detecting when the voltage exceeds a reference voltage, a charge removal circuit 135 for removing a predetermined fixed amount of charge from the capacitor 115, and a digital counter 145 that increments each time charge is removed from the capacitor 115. Reset logic 140 supplies a clock-type signal to the charge removal circuit 135, triggering the charge removal circuit to remove a predetermined amount of charge from the capacitor 115 in response to a signal from the comparator 125 indicating that the voltage across the capacitor has exceeded the reference voltage. With each charge removal / reset event, the digital counter 145 is incremented. The value of the digital counter 145 can be read via a tristate gate 150 on the data outline 180. Several other means of transmitting the value of the digital counter 145 to a set of outputs exist as alternatives to the tristate gate 150 (e.g., the value may be shifted out).

[0055] In array 195, the size of the capacitor may be relatively small (e.g., 1 femtofarad or 10 femtofarads), and the number of counter bits may be a number of bits (e.g., 16 bits) that results in a large range of count values. Accordingly, the voltage range of capacitor 115 may be relatively small (e.g., 250 millivolts). In this configuration, the digital counter 145 can operate as an analog-to-digital converter (ADC). Charge removal from capacitor 115 can be reset back to a first voltage using a simple device such as a MOSFET. Charge removal may also be a more complex circuit that removes an amount of charge that changes the capacitor voltage from a first value to a second value.

[0056] The aforementioned digital formatter may additionally utilize a digital binary value from at least one of several analog-to-digital converters in the conversion of (1) a digital counter value 252 from at least one of several digital counters, and (2) the value of the associated overflow counter, to a pixel value.

[0057] Buffer 345 may be coupled between column read-out line 335 and ADC 340. Voltage transfer can be replaced with charge transfer, and such transfer does not substantially affect the overall function or operation of the invention.

[0058] As described above, the pixels in the analog array 195 may be arranged in columns and rows. In one example, each column of pixels is coupled to a corresponding column-based ADC 340 that digitizes the residual voltage 250. However, it will be understood that different circuit topologies can be used to perform the functions described above, and furthermore, the ADC 340 may be time-shared between different columns (for example, one of the ADC 340s can be used for multiple different pixel columns or rows). The ADC 340 may be located on the ROIC.

[0059] Referring to Figure 6, a method 500 for increasing the dynamic range of an image is shown. In process block 502, the digital circuit 210 stores the overflow counter 145 associated with each of the multiple digital counters of the imaging system 100. In process block 506, for each digital counter 145, bits of the digital counter value 252 are read out as the previous value.

[0060] In process block 508, after a certain period, the bits of each digital counter are read out as current values. In decision block 512, the bits of the digital counter value 252 from the current iteration (i.e., the current value) are compared with the previous iteration (i.e., the previous value). If the value represented by the bits of the digital counter value decreases during the subsequent iteration (i.e., the current value is less than the previous value), the associated overflow counter value 256 is incremented in process block 514. If the value does not decrease during the subsequent iteration or after process block 514, a check is performed in decision block 516 to determine whether the end of the frame has been reached. For example, the check may be performed to determine whether a frame readout signal has been received, or whether the timing to output the frame (e.g., determined by the frame frequency) has been reached. If so ("yes"), the process proceeds to block 520. In process block 520, a pixel value is generated for each pixel 190 and output to form a frame. For each pixel 190, the pixel value is generated based on both the digital counter value 252 from the digital counter 145 associated with the pixel 190, and the associated overflow counter. If the end of the frame is not reached in the decision block 516, the process returns to the process block 508.

[0061] All scopes and ratio limits disclosed in the specification and claims can be combined in any way. Unless otherwise specified, a reference to "one" ("a", "an", and / or "the") may include one or more items. Similarly, a reference to a singular item may include multiple items.

[0062] While the present invention has been shown and described in relation to certain embodiments, equivalent changes and modifications will be made by those skilled in the art by reading and understanding this specification and the accompanying drawings. In particular, with respect to the various functions performed by the elements described above (components, assemblies, devices, compositions, objects, etc.), the terminology used to describe such elements (including references to “means”) is intended to correspond to any element performing a particular function of the described element (i.e., functionally equivalent), even if it is not structurally equivalent to a disclosed structure performing that function in the exemplary embodiments of the present invention shown herein, unless otherwise indicated. In addition, while certain features of the present invention have been described above in relation to only one or more of the exemplary embodiments, such features can be combined with one or more other features of other embodiments so as to be desirable and advantageous for any given or particular application.

Claims

1. A method performed using digital circuitry to increase the dynamic range of a video frame, wherein the method is: This step involves storing the overflow counter value associated with each of the multiple digital counters in the imaging system. Each of the aforementioned digital counters is associated with and communicates with one of the multiple pixels of the imaging system. Each of the aforementioned pixels includes a photodetector configured to generate an electric charge in response to light impacting the pixel, Each of the aforementioned digital counters is configured to store a digital counter value based on a signal received from each of the aforementioned pixels. For each of the aforementioned multiple digital counters, Over multiple iterations, at least one bit of the digital counter value is read periodically. Compare at least one bit of the digital counter value from one of the plurality of iterations with a previous iteration from the plurality of iterations. Steps and When the value represented by at least one bit of the digital counter value decreases from the previous iteration to the current iteration, The steps include incrementing the associated overflow counter of the digital circuit, The steps include converting and outputting, as at least one pixel value of the video frame, at least one of the plurality of digital counters, and the digital counter value from the overflow counter associated with the digital counter, It includes, and further, The step is to determine the duration of the period during which the digital circuit reads the at least one bit of the digital counter value over the plurality of iterations, based on the intensity of light striking at least one of the pixels of the photodetector. The duration of the aforementioned period is determined based on the intensity of the light hitting the photodetector of the pixel receiving the highest intensity light among the pixels. Steps and For each of the multiple pixels, the step of storing the charge generated by the pixel in one of the multiple electrical storage devices associated with that pixel, The process involves continuously checking whether the accumulated charge in each electrical storage device exceeds a predetermined threshold, In response to the determination that the accumulated charge in each of the aforementioned electrical storage devices exceeds a predetermined threshold, The charge stored in each of the aforementioned electrical storage devices is reduced by a predetermined charge reduction amount, and, The digital counter values ​​stored in the digital counter and associated with each of the pixels are incremented. Steps and It includes, and further, The steps include periodically converting the residual charge in each of the aforementioned electrical storage devices into an analog signal, This step involves using one of several analog-to-digital converters to convert the analog signal from each pixel into its respective digital binary value. Each of the aforementioned plurality of analog-to-digital converters has an input and an output. Each of the plurality of analog-to-digital converters is coupled via an input to one of the corresponding electrostatic storage devices among the plurality of pixels. Steps include, Each of the aforementioned digital binary values ​​is additionally used when converting at least one of the plurality of digital counters and the overflow counter associated with said digital counter to the at least one pixel value of the video frame. method.

2. The number of bits in the at least one bit is smaller than the total number of bits in the digital counter value. The method according to claim 1.

3. The at least one bit is only the most significant bit of the digital counter value. The method according to claim 2.

4. A digital circuit for increasing the dynamic range of a video frame, wherein the digital circuit comprises: Store the overflow counter value associated with each of the multiple digital counters in the imaging system. Each of the aforementioned digital counters is associated with and communicates with one of the multiple pixels of the imaging system. Each of the aforementioned pixels includes a photodetector configured to generate an electric charge in response to light impacting the pixel, Each of the aforementioned digital counters is configured to store a digital counter value based on a signal received from each of the aforementioned pixels. For each of the aforementioned multiple digital counters, Over multiple iterations, at least one bit of the digital counter value is read periodically. Compare at least one bit of the digital counter value from one of the plurality of iterations with a previous iteration from the plurality of iterations. It is configured in such a way, and, When the value represented by at least one bit of the digital counter value decreases from the previous iteration to the current iteration, the associated overflow counter is incremented. It is configured in such a way, The duration of the period during which the digital circuit reads at least one bit of the digital counter value over the plurality of iterations is determined based on the intensity of light striking at least one of the pixels, the photodetector. The duration of the aforementioned period is determined based on the intensity of the light hitting the photodetector of the pixel receiving the highest intensity light among the pixels. The digital counter values ​​from at least one of the plurality of digital counters and the overflow counter associated with that digital counter are converted to at least one pixel value of the video frame, and further, For each of the aforementioned plurality of pixels, the charge generated by the pixel is stored in one of the plurality of electrical storage devices associated with that pixel. The system continuously checks whether the accumulated charge in each electrical storage device exceeds a predetermined threshold. In response to a determination that the accumulated charge in each of the aforementioned electrical storage devices exceeds a predetermined threshold, the charge stored in each of the aforementioned electrical storage devices is reduced by a predetermined charge reduction amount. The digital counter values ​​stored in the digital counter and associated with each of the pixels are incremented. It is configured in such a way, and furthermore, Includes multiple analog-to-digital converters, Each of the aforementioned plurality of analog-to-digital converters has an input and an output, Each of the plurality of analog-to-digital converters is configured to be coupled via the input to the electrical storage device relating to at least one of the pixels, and to convert the residual charge in each of the electrical storage devices into a digital binary value, and The digital circuit is configured to additionally utilize the digital binary value from at least one of the plurality of analog-to-digital converters in the conversion of the digital counter value from at least one of the plurality of digital counters and an overflow counter associated with the digital counter to the at least one pixel value of the video frame. Digital circuits.

5. The number of bits in the at least one bit is smaller than the total number of bits in the digital counter value. The digital circuit according to claim 4.

6. The at least one bit is only the most significant bit of the digital counter value. The digital circuit according to claim 5.

7. An imaging system, It is an array of pixels, and each of the pixels is A photodetector configured to generate a photocurrent in response to light colliding with the aforementioned pixel, An electrical storage device configured to store charge from the aforementioned photocurrent, and A quantization circuit coupled to the electrical storage device and configured to convert the charge into an analog quantization event signal, An array of pixels including, A plurality of digital counters corresponding to the array of pixels, Each of the aforementioned digital counters is associated with and communicates with each of the aforementioned pixels, Each of the digital counters stores a digital counter value in response to the reception of the analog quantization event signal from each of the pixels. Multiple digital counters are configured in such a way, It is a digital circuit, The overflow counter value associated with each of the plurality of digital counters is stored, and for each of the plurality of counters, Over multiple iterations, at least one bit of the digital counter value is read periodically. Compare at least one bit of the digital counter value from one of the plurality of iterations with a previous iteration from the plurality of iterations, and When the value represented by at least one bit of the digital counter value decreases from the previous iteration to the current iteration, the associated overflow counter is incremented, and further, The duration of the period during which the digital circuit reads at least one bit of the digital counter value over the plurality of iterations is determined based on the intensity of light striking at least one of the pixels, the photodetector. The duration of the aforementioned period is determined based on the intensity of the light hitting the photodetector of the pixel receiving the highest intensity light among the pixels. At least one of the plurality of digital counters, and the digital counter value from the overflow counter associated with the digital counter, Converted to at least one pixel value of the video frame, For each of the aforementioned pixels, the charge generated by the pixel is stored in one of a plurality of electrical storage devices associated with that pixel. The system continuously checks whether the accumulated charge in each electrical storage device exceeds a predetermined threshold. In response to a determination that the accumulated charge in each of the aforementioned electrical storage devices exceeds a predetermined threshold, the charge stored in each of the aforementioned electrical storage devices is reduced by a predetermined charge reduction amount. The digital counter values ​​stored in the digital counter and associated with each of the pixels are incremented. A digital circuit is configured in such a way, and furthermore, Includes multiple analog-to-digital converters, Each of the aforementioned plurality of analog-to-digital converters has an input and an output, Each of the plurality of analog-to-digital converters is configured to be coupled via the input to the electrical storage device relating to at least one of the pixels, and to convert the residual charge in each of the electrical storage devices into a digital binary value, and The digital circuit is configured to additionally utilize the digital binary value from at least one of the plurality of analog-to-digital converters in the conversion of the digital counter value from at least one of the plurality of digital counters and an overflow counter associated with the digital counter to the at least one pixel value of the video frame. Imaging system.

8. The number of bits in the at least one bit is smaller than the total number of bits in the digital counter value. The imaging system according to claim 7.

9. The at least one bit is only the most significant bit of the digital counter value. The imaging system according to claim 8.

10. The imaging system further includes: The system includes at least one of the aforementioned plurality of digital counters, and a digital formatter configured to convert the digital counter values ​​from the digital counter and associated overflow counters into at least one pixel value of a video frame. The imaging system according to any one of claims 7 to 9.

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