Photoelectric conversion devices and equipment

Abstract

To provide a technique advantageous for preventing an increase in the number of wires while dealing with acceleration of read-out of pixel signals.SOLUTION: A photoelectric conversion device comprises: at least two pixels; and a processing circuit including at least two comparison circuits that each perform a first operation to compare pixel signals from the at least two pixels with a threshold, at least two holding circuits that hold results of the first operations, and at least two setting units. Each of the at least two holding circuits holds the result of the first operation performed by the corresponding comparison circuit of the at least two comparison circuits. The results of the first operations are transferred from the at least two holding circuits to the corresponding setting unit of the at least two setting units through a common signal line. Each of the at least two setting units sets an operating state of the processing circuit according to the results of the first operations.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a photoelectric conversion device and an apparatus using the photoelectric conversion device.

Background Art

[0002] There is a technique of arranging analog-to-digital (AD) converters for each column of pixels arranged in a matrix and performing AD conversion using a ramp signal. Patent Document 1 discloses an imaging device that performs AD conversion using two ramp signals having different voltage changes with respect to time.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] When simultaneously reading signals from a plurality of pixels for high-speed AD conversion, using two ramp signals may lead to a further increase in the number of wirings. An object of the present invention is to provide a technique advantageous for suppressing an increase in the number of wirings while coping with high-speed reading of pixel signals.

Means for Solving the Problems

[0005] One aspect of the present invention is a processing circuit comprising at least two pixels, at least two comparison circuits each performing a first operation comparing pixel signals from the at least two pixels with a threshold, at least two holding circuits for holding the results of the first operation, and at least two setting units, wherein each of the at least two holding circuits holds the result of the first operation of the corresponding comparison circuit among the at least two comparison circuits, the result of the first operation is transferred from the at least two holding circuits to the corresponding setting unit among the at least two setting units via a common signal line, and each of the at least two setting units sets the operating state of the processing circuit according to the result of the first operation. [Effects of the Invention]

[0006] According to the present invention, it is possible to provide a technology that is advantageous in suppressing an increase in the number of wires while accommodating faster readout of pixel signals. [Brief explanation of the drawing]

[0007] [Figure 1] A schematic diagram of the photoelectric conversion device according to Example 1. [Figure 2] An example of an AD converter using two ramp signals. [Figure 3] A diagram explaining AD conversion. [Figure 4] A diagram explaining AD conversion. [Figure 5] A diagram illustrating the AD conversion according to Example 1. [Figure 6] Comparative example of a photoelectric conversion device. [Figure 7] A schematic diagram of the photoelectric conversion device according to Example 2. [Figure 8] A schematic diagram of the photoelectric conversion device according to Example 3. [Figure 9] A diagram illustrating the AD conversion according to Example 3. [Figure 10] An example of applying the photoelectric conversion device according to the embodiment to a device. [Modes for carrying out the invention]

[0008] The embodiments will be described in detail below with reference to the attached drawings. Note that the following embodiments do not limit the invention as defined in the claims. While the embodiments describe multiple features, not all of these features are essential to the invention, and the features may be combined in any way. Furthermore, in the attached drawings, identical or similar configurations are given the same reference numerals, and redundant descriptions are omitted.

[0009] In the embodiments described below, the imaging device will be the primary focus as an example of a photoelectric conversion device. However, each embodiment is not limited to an imaging device and can be applied to other examples of photoelectric conversion devices. Examples include distance measuring devices (devices for distance measurement using focus detection or TOF (Time of Flight)) and photometric devices (devices for measuring the amount of incident light).

[0010] Furthermore, in the following embodiments, connections between circuit elements may be described. In this case, even if another element is interposed between the elements of interest, unless otherwise specified, the elements of interest will be treated as connected. For example, suppose element A is connected to one node of a capacitive element C having multiple nodes, and element B is connected to the other node. Even in such a case, elements A and B will be treated as connected unless otherwise specified.

[0011] Furthermore, while this specification describes amplifiers that output an amplified signal from an input signal, amplification is not necessarily limited to increasing the signal amplitude. In other words, amplification is a concept that includes signal attenuation, and the amplification factor of the amplifier may be less than 1. Also, while this specification describes analog-to-digital converters (AD converters) that convert analog signals to digital signals, the conversion rate from analog to digital signals can be treated as the amplification factor. That is, in AD conversion of analog signals of the same signal level, if a digital signal with a larger value is generated compared to when a digital signal with a smaller value is generated, it can be said that the amplification factor of the AD converter is high.

[0012] (Embodiment 1) Prior to describing Embodiment 1, an AD conversion using two ramp signals, each with a different rate of change in voltage, as reference signals that change at different rates of change in time, will be explained using an example in Figure 2. A ramp signal is a reference signal whose voltage value changes over time. The change referred to here is not limited to a slope-like form, but also includes, for example, a step-like form in which the voltage value changes. In other words, it includes forms in which either an increase or decrease in voltage value is constantly ongoing, or forms in which either an increase or decrease in voltage value, and a cessation of voltage value change, are continuously repeated.

[0013] The photoelectric converter includes a pixel 100, a pixel array 110 in which the pixels 100 are arranged in a matrix, a pixel scanning unit 120, and a vertical signal line 130. Furthermore, the analog-to-digital (AD) conversion configuration includes a comparison circuit 140, a lamp generator 150, a judgment result transfer line 210, a judgment circuit 300, and a counter 360. It may also have an output unit including a horizontal scanning circuit 400 and an output circuit 500 to output the AD-converted data. The pixel 100 includes a photoelectric conversion unit containing a photoelectric conversion element, a floating diffusion that converts the charge accumulated in response to light incident on the photoelectric conversion element into a potential, a transfer transistor that transfers the converted potential to the vertical signal line 130, and an amplification transistor.

[0014] The comparison circuit 140 includes a comparator 160, a switching unit 170, and a selection unit 200. The switching unit 170 includes a switch 180 and a switch 190. The selection unit 200 includes a logic circuit 250. The determination circuit 300 includes a holding circuit 320, a pulse generator 330, and a memory 340. The horizontal scanning circuit 400 includes a horizontal transfer selection switch 420, a transfer memory 430, and a logic circuit 440. The ramp generator 150 outputs two ramp signals, rampL and ramppH, whose voltages change at different rates and have different slopes.

[0015] The counter 360 counts the clock and outputs a count signal cnt corresponding to the counted count value. Also, a control signal s2 and a control signal s3 are input to a selection unit 200 that selects either a ramp signal rampL or a ramp signal rampH during AD conversion. A control signal s1 for controlling the holding circuit 320 is input to the determination circuit 300, and a transfer signal ATX, a transfer signal BTX, and a horizontal selection signal for controlling the transfer memory 430 are supplied to the horizontal scanning circuit 400. The output of the comparator 160 is output to the determination circuit 300 via a comparator output line 310. The output of the memory 340 is output to an AD result output line 410.

[0016] Next, using FIG. 3, the AD conversion operation performed in the example of FIG. 2 when the pixel signal output from the pixel 100 to the vertical signal line 130 is at a level corresponding to low brightness will be described. The potential of the reset level of the pixel is AD-converted between time t0 and time t2. By this AD change, a signal of the noise level can be obtained. First, the pixel 100 is set to the reset state.

[0017] [[ID=?]] First, at time t0, the control signal s2 is controlled to the H level and s3 is controlled to the L level. When the control signal s2 becomes the H level, the selection unit 200 becomes in a selectable state by the control signal s3, and when the control signal s3 becomes the L level, the switching unit 170 controls the switch 180 to be on and the switch 190 to be off. By the control of the switching unit 170 by the selection unit 200, the ramp rampL is selected. As a result, the ramp signal rampL is input to the positive input terminal of the comparator 160.

[0018] It seems there is a typo in your original text where the line with tag has no content in the Japanese part. I translated it as it is but it might be an error in the original. If you have any further clarifications or corrections, feel free to let me know.At this time, pixel 100 is reset, and the potential of the vertical signal line 130 is at a level corresponding to the reset level of pixel 100. That is, the potential of the vertical signal line 130 indicates the noise level. At this time, since the potential of the positive input terminal of the comparator 160 > the potential of the negative input terminal, the output of the comparator 160 becomes the H level. After time t0, the potential of the ramp signal rampL decreases, and the count signal cnt counts up. At time t1, when the ramp signal rampL falls below the potential of the vertical signal line 130, the output of the comparator 160 transitions from the H level to the L level, and the pulse generator 330 receiving the output of the comparator 160 generates a short one-shot pulse and supplies it to the memory 340.

[0019] By the one-shot pulse, the value of the count signal cnt of the counter 360 at time t1 is written into the memory 340. In this embodiment, the relationship between the ramp signal rampL and the potential of the vertical signal line 130 has been described as the output of the comparator 160 transitioning when the ramp signal rampL falls below the potential of the vertical signal line 130. However, it is also possible to reverse the change of the ramp signal rampL so that the output of the comparator 160 transitions when the potential of the vertical signal line 130 is exceeded. For example, there is a configuration in which an amplifier that inversely amplifies the signal of the vertical signal line 130 is provided, and the output of this amplifier is given to the comparator 160. In the case of this configuration, due to the inverse amplification by the amplifier, the signal input to the comparator 160 has a larger voltage value as the light incident on the pixel increases. In such a case, the ramp signals rampL and rampH can be signals that change so that the voltage value increases with the passage of time.

[0020] The count signal cnt written to memory 340 is a count value corresponding to the magnitude of the analog signal. This count value becomes the data of the AD conversion result by the ramp signal rampL relative to the reset level. At time t2, the ramp signal rampL and the count signal cnt are reset, and the output of comparator 160 returns from L level to H level. The AD conversion result data written at t1 is written to the selected transfer memory 430 from memory 340 by the logic circuit 440, which receives the transfer signal BTX at time t2. In addition, the horizontal transfer selection switch 420 is controlled by the horizontal selection signal to select the transfer memory 430, and the selected data is transferred to the output circuit 500.

[0021] Subsequently, at time t3, the control signal s3 switches to the H level. This causes the selection unit 200 to control the switching unit 170, turning off switch 180 and turning on switch 190. As a result, the ramp signal rampH is input to the forward input terminal of comparator 160 via switch 190. From time t3 onward, the potential of the ramp signal rampH decreases, during which time counter 360 counts up and outputs the count value as the count signal cnt. At time t4, when the ramp signal rampH falls below the potential of the vertical signal line 130, the output of comparator 160 transitions to the L level, causing pulse generator 330 to generate a one-shot pulse. The one-shot pulse is supplied to memory 340. Due to this operation, at time t4, the count signal cnt is written to memory 340.

[0022] The count signal cnt written to memory 340 is a count value corresponding to the magnitude of the analog signal. This count value becomes the AD conversion result of the ramp signal rampH relative to the reset level. At time t5, the control signal s3 becomes L level, the ramp signal rampH and the count signal cnt are reset, and the output of comparator 160 returns from L level to H level. At time t5, the written AD conversion result is written from memory 340 to the selected transfer memory 430 by the logic circuit 440, which has received the transfer signal BTX. In addition, the horizontal transfer selection switch 420 is controlled by the horizontal selection signal to select the transfer memory 430, and the selected data is transferred to the output circuit 500. At time t5, as the control signal s3 returns to L level, the ramp signal rampL is once again input to the forward input of comparator 160.

[0023] At time t6, in pixel 100, a pixel signal corresponding to the charge accumulated in the photoelectric conversion element of the photoelectric conversion unit, such as a photodiode, in response to incident light is transferred to the vertical signal line 130. At this time, the potential of the vertical signal line 130 is set to a level equivalent to a low-luminance light signal. At this timing, the potential of the ramp signal rampL is lowered to a predetermined reference potential to determine the level of the vertical signal line 130. In this embodiment, the ramp signal can be selected depending on whether it is greater than or less than the reference potential (threshold). It is preferable that this threshold voltage has an amplitude smaller than the target voltage value reached at time t11 by the ramp signal rampL, whose potential changes from time t9 in the AD conversion of the pixel signal described later.

[0024] In this specification, amplitude is defined as the absolute value of the difference between the reference voltage value and the changed voltage value. In other words, a voltage with an amplitude smaller than the target voltage value of the ramp signal rampL is, in this embodiment, a voltage with a voltage value greater than the target voltage value of the ramp signal rampL. By setting the threshold in this way, it is possible to ensure AD conversion accuracy for pixel signals at levels near the target voltage value of the ramp signal rampL. If the threshold is set to the same value as the target voltage value of the ramp signal rampL, the ramp signal rampL may be selected when determining the level of the vertical signal line 130. However, in subsequent AD conversion, if the amplitude of the vertical signal line 130 increases due to external noise or fluctuations in the power supply voltage, it may exceed the target voltage value of the ramp signal rampL.

[0025] In this case, the output of comparator 160 will not change, making it difficult to perform AD conversion correctly. By setting a threshold voltage with an amplitude smaller than the target voltage value of ramp signal rampL, it is possible to determine whether to use the ramp signal rampH for signal levels on the vertical signal line 130 near the target voltage value of ramp signal rampL. This makes it possible to perform AD conversion appropriately even for signals at levels near the target voltage value of ramp signal rampL.

[0026] In Figure 2, since the incident light is low brightness, the potential of the vertical signal line 130 exceeds the reference potential determined by the ramp signal rampL, and the output of the comparator 160 becomes L level. At this time, the control signal s1 is set to H level during the period from time t6 to t7, thereby enabling writing to the holding circuit 320, and the L level, which is the result of the comparator 160's determination, is written to the holding circuit 320.

[0027] During the period from time t7 to t8, the logic circuit 440, which receives the transfer signal ATX, writes the judgment result to the transfer memory 430. At time t8, the ramp signal rampL is returned to its starting level, causing the output of the comparator 160 to return to the H level.

[0028] Then, by setting the control signal s2 to an L level at time t9, the selection unit 200 can be set to a state where it is controlled by the output of the holding circuit 320. At this time, the judgment result written to the holding circuit 320 can be reflected to the selection unit 200. An L level is written to the holding circuit 320 during the period from time t6 to t7. The selection unit 200 controls the switching unit 170 in response to the L level signal from the holding circuit 320, setting switch 180 to ON and switch 190 to OFF. As a result, the forward input terminal of the comparator 160 can be set to receive the ramp signal rampL. At this time, the selection unit 200 functions as a setting unit that selects the ramp signal and supplies it to the comparator to set the operating state of the AD conversion.

[0029] From time t9 onwards, AD conversion of the pixel signal corresponding to low-luminance incident light is performed. From time t9, the potential of the ramp signal rampL decreases, and the count signal cnt counts up. At time t10, the potential of the ramp signal rampL falls below the potential of the vertical signal line 130. At time t10, the comparator output transitions to the L level, and the AD conversion result by the ramp signal rampL for the signal level is written to memory 340. At time t11, the ramp signal rampL and the count signal cnt are reset.

[0030] From time t11 onward, the AD conversion result written to memory 340 at t10 is written to transfer memory 430, which is selected by logic circuit 440 upon receiving the transfer signal BTX. The judgment result with the reference signal and the AD conversion result of the pixel signal, which were previously written to transfer memory 430, are selected by the horizontal transfer selection switch 420 via the horizontal selection signal and horizontally transferred to output circuit 500. In output circuit 500, processing such as "SN processing," which subtracts noise level data from the pixel signal data, is performed on the AD conversion result horizontally transferred from transfer memory 430. After processing, a signal is output from output circuit 500. At this time, the output circuit can apply different processing to the AD conversion result depending on the judgment result. This point will be described later.

[0031] As described above, when the signal level of the pixel signal on the vertical signal line 130 is equivalent to low brightness, selecting and using a ramp signal rampL with a smaller slope reduces random noise due to quantization errors, etc., making it possible to perform high-precision AD conversion.

[0032] Next, using Figure 4, we will explain the AD conversion operation performed in Figure 2 when the signal level output from pixel 100 to the vertical signal line 130 is high brightness. The operation is the same as in Figure 3 up to the point where the noise level up to time t6 is converted using AD. At time t6, the pixel signal corresponding to the charge accumulated in the photoelectric conversion unit in response to the incident light at pixel 100 is transferred to the vertical signal line 130. At this time, the potential of the vertical signal line 130 becomes a level equivalent to a high brightness light signal. At this timing, the potential of the ramp signal rampL is lowered to a predetermined reference potential to determine the level of the vertical signal line 130. In this embodiment, the ramp signal can be selected depending on whether it is greater than or less than the reference potential.

[0033] In Figure 4, since the incident light is of high brightness, the reference potential determined by the ramp signal rampL exceeds the potential of the vertical signal line 130, and the output of the comparator 160 remains at the H level without changing. At this time, the control signal s1 is set to the H level during the period from time t6 to t7, thereby enabling writing to the holding circuit 320, and the H level, which is the result of the comparator 160's determination, is written to the holding circuit 320.

[0034] During the period from time t6, the signal level of the vertical signal line 130 is compared with a reference potential to determine the ramp signal used when performing AD conversion of the pixel signal. The result written to the holding circuit 320 changes according to this determination. At time t8, the transfer signal ATX falls, and the determination result is stored in the transfer memory 430. At time t9, by setting the control signal s2 to the L level, the selection unit 200 can be put into a state where it is controlled by the output of the holding circuit 320. The holding circuit 320 has an H level written to it. In response to the H level signal from the holding circuit 320, the selection unit 200 controls the switching unit 170, controlling switch 180 to the OFF state and switch 190 to the ON state. As a result, the ramp signal rampH can be input to the forward input terminal of the comparator 160.

[0035] From time t9, AD conversion is performed using the ramp signal rampH. At time t10, the ramp signal rampH falls below the potential of the vertical signal line, so the comparator output of comparator 160 transitions from H level to L level, and pulse generator 330 generates a one-shot pulse in response to the transition of the comparator 160's output. The value of the count signal cnt of counter 360 is written to memory 340 by the one-shot pulse. From time t11 onward, the AD conversion result written to memory 340 at time t10 is written to transfer memory 430 selected using the BTX signal and logic circuit 440. The judgment result with respect to the reference potential and the AD conversion result written to transfer memory 430 may be horizontally transferred to output circuit 500 when the horizontal transfer selection switch 420 is selected by the horizontal selection signal.

[0036] At this time, the output circuit 500 may perform "SN processing" in accordance with the determination result of the holding circuit 320, which involves subtracting noise level data from the data corresponding to the pixel signal. Furthermore, the signal may be output after processing such as applying a gain according to the ratio of the slopes of the ramp signal rampL and ramppH. It is also possible to perform processing such as correcting offset differences caused by differences in the start timing and propagation delay of the operation between the ramp signal rampL and the ramp signal ramppH.

[0037] As described above, when the signal level of the vertical signal line 130 is equivalent to high brightness, a ramp signal rampH with a larger slope is selected and used. This increases random noise in AD conversion due to quantization errors, etc., but the optical shot noise appearing on the vertical signal line 130 side becomes dominant, minimizing the impact on the total random noise while shortening the readout time.

[0038] Next, this embodiment will be explained with reference to Figure 1. Here, we will explain the differences from Figure 2. In the example of the photoelectric converter in Figure 1, in order to read signals from pixels 100 at high speed, the pixel array 110 is configured to simultaneously read pixels 100 arranged in two rows. For this purpose, two first comparison circuits 140-1 and a second comparison circuit 140-2 and two first determination circuits 300-1 and a second determination circuit 300-2 are stacked vertically in the column direction. Here, we will explain an example of reading two rows simultaneously, but the number of rows, columns, and the number of pixels read simultaneously are not limited.

[0039] In the following, when describing items with the same name but assigned numbers such as "First" and "Second," the numbers "First" and "Second" may be omitted. Similarly, when describing items with sub-numbers such as "300-1" and "300-1," the sub-numbers "-1" and "-2" in the reference number may be omitted.

[0040] The first judgment circuit 300-1 and the second judgment circuit 300-2 are equipped with the first serial transfer switch 350-1 and the second serial transfer switch 350-2. The judgment result transfer line 210 is used in common by the two judgment circuits 300 and the two comparison circuits 140; in other words, the judgment result transfer line 210 is shared by multiple judgment circuits 300 and comparison circuits 140. The two selection units 200 each have a memory 215. Transfer signals ATX1, ATX2, BTX1 and BTX2 are input to the horizontal scanning circuit 400. Transfer signal ATX1 is also input to the first comparison circuit 140-1 and the first judgment circuit 300-1. Transfer signal ATX2 is input to the second comparison circuit 140-2 and the second judgment circuit 300-2.

[0041] Serial transfer switches 350-1 and 350-2 connect the outputs of holding circuits 320-1 and 320-2 to the judgment result transfer line 210, respectively. Switches 350-1 and 350-2 are controlled by transfer signals ATX1 and ATX2, respectively. Memory 215-1 of the first selection unit 200-1 takes the judgment result transfer line 210 as input and stores the level of the judgment result transfer line 210 by latching it with the falling edge of transfer signal ATX1. Memory 215-2 of the second selection unit 200-2 takes the judgment result transfer line 210 as input and stores the level of the judgment result transfer line 210 by latching it with the falling edge of transfer signal ATX2. Reading from each memory 215 can be controlled by the logic circuit 250.

[0042] The first comparison circuit 140-1, the second comparison circuit 140-2, the first determination circuit 300-1, and the second determination circuit 300-2 can each be called a circuit block. The determination result transfer line 210 is shared among the circuit blocks. The determination result transfer line 210 is also connected to the input of the transfer memory 430 of the horizontal scanning circuit 400. The signal from the determination result transfer line 210 is stored in one of the transfer memories 430-1 to 430-4 selected by the transfer signal ATX1 or transfer signal ATX2 and the logic circuit 440. The system also has an output section including the horizontal scanning circuit 400 and the output circuit 500 to output the AD-converted data. In this embodiment, the determination circuit and the comparison circuit can be described as processing circuits that process pixel signals.

[0043] Next, the operation of this embodiment will be explained with reference to Figure 5. Here, as explained in Figure 3, the operation when the incident light is low brightness will be described. The operation from time t0 to t2 is the same as in Figure 3, an AD conversion period for the reset level by the lamp signal ramnpL. The difference is that for two pixels, AD conversion is performed simultaneously using the first comparator circuit 140-1 and the first decision circuit 300-1, and the second comparator circuit 140-2 and the second decision circuit 300-2, respectively.

[0044] At time t2, the vertical signal line potentials for the outputs from each of the two pixels and the AD conversion results by rampL are transferred to transfer memories 430-5 and 430-7 using transfer signals BTX1 and BTX2 and stored. AD conversion to the reset level using the ramp signal rampH is performed during the period from time t3 to time t5, and the respective AD conversion results are transferred to transfer memories 430-6 and 430-8 at time t5 using transfer signals BTX1 and BTX2. The data of the determination result with respect to the reference potential and the AD conversion result stored in transfer memory 430 are transferred to the output circuit 500 by a horizontal selection signal. At this time, according to the determination result of the holding circuit 320, the output circuit 500 may perform "SN processing" by subtracting noise level data from the data corresponding to the pixel signal. Furthermore, the signal may be output after processing such as applying a gain according to the ratio of the slopes of the ramp signal rampL and rampH.

[0045] The period from time t6 to time t8 is the period during which the level of the pixel signal is compared with the magnitude of the reference signal and the determination result is written to the first holding circuit 320-1 and the second holding circuit 320-2, as explained in Figure 3. At this time, the signal levels of the two pixels are compared with the reference potential and determined. From time t7 to t8, the determination results held in the first holding circuit 320-1 and the second holding circuit 320-2 are sequentially transferred to the determination result transfer line 210. In this embodiment, an example is described in which one of two ramp signals is selected according to the reference potential, as in the example in Figure 3, but there may be two or more reference potentials and three or more types of ramp signal slopes may be provided.

[0046] Between t7 and t8, the transfer signals ATX1 and ATX2 sequentially become high. The judgment results held in the holding circuits 320-1 and 320-2 are sequentially transferred to the judgment result transfer line 210 in accordance with the transfer signals ATX1 and ATX2 becoming high and the serial transfer switches 350-1 and 350-2 being controlled to turn on sequentially. The judgment results are sequentially transferred from the two judgment circuits 300 to the two comparison circuits 140 via the judgment result transfer line 210, which is wired in common.

[0047] The transferred judgment results are first stored in memory 215-1 and transfer memories 430-1 and 430-2 on the falling edge of transfer signal ATX1 during the period from time t7 to t8. Next, on the falling edge of ATX2, they are stored in memory 215-2 and transfer memories 430-3 and 430-4. Here, an example is given using the falling edges of transfer signals ATX1 and ATX2 for storage, but depending on the circuit configuration, the rising edge can also be used. Also, since transfer signals ATX1 and ATX2 use the same judgment result transfer line 210, the timing of when they become high level is staggered so that the serial transfer switch 350 is not turned on at the same time.

[0048] Logic circuits 250-1 and 250-2 control the switching unit 170 according to the judgment results stored in memories 215-1 and 215-2 to select a lamp signal. The selected lamp signal is input to the comparator. In this explanation, AD conversion was described using two pixels as an example. As shown in Figure 1, a comparator circuit and a judgment circuit are provided for each of the two pixels, so that an appropriate lamp signal can be selected and set for each of the two pixels according to the level of incident light.

[0049] In this embodiment, an example of controlling the serial transfer switch 350 using transfer signals ATX1 and ATX2 has been described. However, the configuration is not limited to this one, as long as the judgment result data can be sequentially transferred and stored in the memory 215 and transfer memory 430 corresponding to the judgment result. By performing such serial transfer of the judgment result, it is possible to reduce the number of judgment result transfer lines 210 when multiple comparison circuits and judgment circuits are provided to speed up the reading of pixel signals.

[0050] The period from time t9 is the period during which the pixel signals from two pixels are AD-converted using the ramp signal rampL selected based on the determination result. The determination circuit and the comparison circuit can be described as processing circuits that include AD conversion processing of pixel signals. As described above, in this embodiment, a ramp signal can be selected from among multiple ramp signals whose voltages change at different rates over time, according to the magnitude of the pixel signal. As a result, the operating state of the processing circuit including the comparison circuit can be changed. The AD-converted data can be transferred to and stored in transfer memories 430-5 and 430-7 by transfer signals BTX1 and BTX2. Subsequently, the data stored in transfer memory 430 can be output to output circuit 500.

[0051] In addition to the high-speed operation of reading signals from pixels, reducing the pixel size also narrows the pitch width between rows. Therefore, by forming circuits by sharing the pitch across multiple rows, the reduction in signal lines is advantageous in multi-stage circuits, especially in terms of securing layout area.

[0052] Furthermore, in this embodiment, instead of transferring multiple simultaneously determined judgment results all at once using the transfer signal ATX, they are transferred separately to transfer signals ATX1 and ATX2 at different timings. By performing memory write operations at different transfer timings, the peak power generated during memory write timing can be distributed. This reduces voltage fluctuations caused by peak currents in the commonly wired power and ground connections. In addition, it is possible to suppress image quality degradation.

[0053] (Embodiment 2) Next, Embodiment 2 will be described. Prior to describing this embodiment, an example of simultaneously performing AD conversion of signals from four pixels 100 will be explained with reference to Figure 6. Figure 6 shows a schematic diagram of a multi-stage stacking circuit. Here, the operation will be explained using a four-stage stacking example in which AD conversion is performed by circuits arranged in blocks within a single column, simultaneously reading the pixels 100 arranged in four rows. In this example as well, the AD conversion is performed by ramp signals with two different time change rates. In a pixel array 110 in which multiple pixels are arranged in a matrix, the pixel signals from four rows selected by the pixel scanning unit 120 are supplied to four comparator circuits 140 via vertical signal lines 130.

[0054] There are four comparison circuits: the first comparison circuit 140-1 through the fourth comparison circuit 140-4. The ramp signal rampL and ramp signal rampH from the ramp generator 150 are connected to each of the comparison circuits 140. Similarly, four judgment circuits 300-1 through 300-4 are provided, as there are as many judgment circuits 300 as there are pixels 100 to read simultaneously. A counter 360 is connected to each judgment circuit 300 for AD conversion.

[0055] From the four comparison circuits 140, the judgment result transfer line 210 and the comparator output line 310, which are outputs of the holding circuit 320, are connected to the four judgment circuits 300, respectively. Furthermore, the AD result output line 410 and the judgment result transfer line 210 are connected between the four judgment circuits 300-1 to 300-4 and the horizontal scanning circuit 400. The horizontal scanning circuit 400 sequentially transfers the received AD conversion results and judgment results horizontally to the output circuit 500. The output circuit 500 can perform data processing according to the judgment results. The processed signal can be output externally.

[0056] Here, simultaneous reading from four pixels requires four comparator circuits and four judgment circuits. Therefore, a total of eight wires—four judgment result transfer lines 210 and four comparator output lines 310—are wired to each column between the comparator and judgment circuits. Additionally, a total of eight wires—four judgment result transfer lines 210 and four AD result output lines 410—are wired to each column between the four judgment circuits and the horizontal scanning circuit. This explanation uses the simultaneous reading of four pixels as an example. For simultaneous reading of eight pixels, a total of 16 wires are wired within each column, and the number of wires within a column increases in proportion to the number of pixels being read simultaneously.

[0057] Figure 7 is a schematic diagram of the multi-stage circuit of this embodiment. It is an example of a four-stage stack, the same as in Figure 6. The differences from the example in Figure 6 will be explained. In this embodiment, by serially transferring the judgment results, the judgment result transfer line 210 connecting the four first comparator circuits 140-1 to the fourth comparator circuit 140-4 and the four first judgment circuits 300-1 to the fourth judgment circuit 300-4 can be reduced to one line. In addition, the comparator output line 310 can be reduced to four lines. A total of five wires are wired in one row. Furthermore, the connection lines between the four judgment circuits 300 and the horizontal scanning circuit 400 consist of one judgment result transfer line 210 and four AD result output lines, for a total of five wires, wired in one row. Therefore, the amount of wiring in a row is reduced compared to the total of eight wires in the conventional example.

[0058] In this example, we used simultaneous reading of 4 pixels, but with simultaneous reading of 8 pixels, a total of 9 wires would be routed within the row, a reduction from the 16 wires in the conventional example. Thus, the greater the number of pixels read simultaneously, the greater the effect of reducing the number of wires within the row in this embodiment.

[0059] (Embodiment 3) The photoelectric converter of this embodiment will be described with reference to Figure 8. The photoelectric converter includes the pixel array 110 shown in Embodiment 1. In this configuration, the vertical signal line 130 of the pixel array 110 is connected to one electrode of the input capacitor 132 in the column amplifier 131. The other electrode of the input capacitor 132 is connected to the amplifier 134 and the feedback capacitor 133 of the amplifier 134. A selection unit 200 is also arranged in the column amplifier 131, and the selection unit 200 includes a memory 215 and a logic circuit 250, similar to Embodiment 1. The selection unit 200 switches the capacitance value of the feedback capacitor 133, which determines the amplification factor of the amplifier 134, using switches 180 and 190 of the switching unit 170. The selection unit 200 functions as a setting unit for setting the amplification factor. In this embodiment, the amplifier 134 is an inverting amplifier.

[0060] Amplifier 134 inverts and amplifies the vertical signal potential from the vertical signal line 130 and outputs it as an image signal 135. The potential of the image signal 135 is shown by the image signal potential (dashed line). The image signal 135 is input to the comparator circuit 140. In this embodiment, the comparator circuit 140 compares the lamp signal rampH generated by the lamp generator 150 with the image signal 135. The comparison result is input from the comparator circuit 140 to the judgment circuit 300 via the comparator output line 310. The column amplifier 131 including amplifier 134, the comparator circuit 140 and the judgment circuit 300 can be described as a processing circuit that includes AD conversion processing of the pixel signal. The other configurations are the same as in Embodiment 1.

[0061] Next, the operation of this embodiment will be explained with reference to Figure 9. Here, we will explain the AD conversion operation performed in Figure 8 when the signal level of the image signal output from pixel 100 to the vertical signal line 130 is high brightness. Between time t0 and time t2, the potential of the pixel's reset level is converted using AD. This AD conversion allows us to obtain data corresponding to the noise level signal. Initially, pixel 100 is in a reset state.

[0062] In this embodiment, the column amplifier's amplification factor is set to 4 times to amplify the reset level potential. First, at time t0, the feedback capacitor 133 that determines the column amplifier's amplification factor is selected by the selection unit 200 to have an amplification factor of 4 times. At this time, the pixel 100 is reset, and the potential of the vertical signal line 130 is at a level equivalent to the reset level of the pixel 100. That is, the potential of the vertical signal line 130 indicates the noise level.

[0063] The vertical signal line 130 is input to the amplifier 134, which is an inverting amplifier, via the input capacitor 132. The image signal 135, which is the output signal of the amplifier 134, is connected to the forward input terminal of the comparator 160. The ramp signal rampH is input to the inverting input terminal of the comparator 160. At time t0, the potential of the forward input terminal of the comparator 160 is higher than the potential of the inverting input terminal, so the output of the comparator 160 is at the H level. After time t0, the potential of the ramp signal rampH increases with time. At this time, the count signal cnt counts up along with the increase in the ramp signal rampH. At time t1, when the ramp signal rampH exceeds the potential of the image signal 135, the output of the comparator 160 transitions from the H level to the L level, and the pulse generator 330, which receives the output of the comparator 160, generates a short-time one-shot pulse and supplies it to the memory 340.

[0064] A one-shot pulse writes the value of the count signal cnt of counter 360 at time t1 to memory 340. In this embodiment, the relationship between the potential of the ramp signal rampH and the potential of the image signal 135 was explained as the output of comparator 160 transitioning when the ramp signal rampH exceeds the potential of the image signal 135. However, the change in the ramp signal rampH can also be reversed so that the output of comparator 160 transitions when it falls below the potential of the image signal 135.

[0065] For example, amplifier 134 can be a non-inverting amplifier, and the image signal from the vertical signal line 130 can be input to the non-inverting amplifier. The output of this amplifier can then be fed to comparator 160. In this configuration, due to the non-inverting amplification by the amplifier, the voltage value of the signal input to comparator 160 decreases as more light enters the pixel. In such a case, the ramp signal rampH can be a signal that changes so that its voltage value decreases over time.

[0066] The count signal cnt written to memory 340 is a count value corresponding to the magnitude of the analog value of the image signal 135. This count value becomes the AD conversion result data by ramp signal rampH to a reset level amplified by column amplifier 131 at a gain of 4. At time t2, the ramp signal rampH and count signal cnt are reset, and the output of comparator 160 returns from L level to H level. Also at time t2, the written AD conversion result data is written from memory 340 to the selected transfer memory 430 by logic circuit 440, which receives the transfer signal BTX. Furthermore, the horizontal transfer selection switch 420 is controlled by the horizontal selection signal to select the transfer memory 430, and the selected data is transferred to output circuit 500.

[0067] At time t3, in pixel 100, a pixel signal corresponding to the charge accumulated in the photoelectric conversion element of the photoelectric conversion unit, such as a photodiode, in response to incident light is transferred to the vertical signal line 130. In this embodiment, the operation is described assuming the pixel signal is at a high brightness level. Therefore, the potential of the vertical signal line 130 is at a level equivalent to a high brightness light signal. The pixel signal is amplified by the column amplifier 131 and input to the comparator circuit 140. Assume that the amplification factor of the column amplifier is set to 4 at time t3.

[0068] At time t4, the potential of the ramp signal rampH is increased to a predetermined reference potential shown by the solid line, and a determination operation is performed to compare it with the potential of the image signal 135 shown by the dashed line. In this embodiment, the amplification factor of the column amplifier 131 can be selected depending on whether it is greater than or less than the reference potential (threshold). It is preferable that this threshold voltage has an amplitude smaller than the target voltage value reached at time t9 in the AD conversion of the pixel signal described later, where the potential of the ramp signal rampH changes from time t7. According to this embodiment, the operating state of the processing circuit, including the amplification factor of the column amplifier, can be changed.

[0069] In this specification, amplitude is defined as the absolute value of the difference between the reference voltage value and the changed voltage value. In other words, a voltage with an amplitude smaller than the target voltage value of the ramp signal rampH is a voltage with a voltage value smaller than the target voltage value of the ramp signal rampH in this embodiment. By setting the threshold in this way, it is possible to ensure AD conversion accuracy for pixel signals at levels near the target voltage value of the ramp signal rampH.

[0070] If the threshold voltage is set to the same value as the target voltage of the ramp signal rampH, then during subsequent AD conversion, if the amplitude of the image signal 135 increases due to external noise or fluctuations in the power supply voltage, it may exceed the target voltage of the ramp signal rampH. In this case, the output of the comparator 160 will not change, making it difficult to perform AD conversion correctly. By setting the threshold voltage to a voltage with a smaller amplitude than the target voltage of the ramp signal rampH, it is preferable to change the column amplifier amplification factor to 1x for signal levels of the image signal 135 near the target voltage of the ramp signal rampH and make a determination. This allows for appropriate AD conversion even for signals at levels near the target voltage of the ramp signal rampH.

[0071] In the example in Figure 9, because the incident light is high brightness, the potential of the image signal 135 exceeds the reference potential determined by the lamp signal rampH, and the output of the comparator 160 becomes H level. At this time, by setting the control signal s1 to H level during the period from time t4 to t5, the holding circuit 320 is made writable, and the H level, which is the result of the comparator 160's determination, is written to the holding circuit 320.

[0072] During the period from time t4 to t5, an H level is written to the holding circuit 320. The values ​​written to the two holding circuits 320 are transferred sequentially to the memory 215 of the selection unit 200 by the transfer signals ATX1 and ATX2 between time t5 and t6. Then, by setting the control signal s2 to an L level at time t6, the selection unit 200 can be put into a state where it is controlled by the output of the holding circuit 320. In this example, the incident light was set to high brightness, so switch 180 is turned on and switch 190 is turned off. As a result, the amplification factor of the column amplifier 131 is changed from 4 times to 1 time.

[0073] Furthermore, during the period from time t5 to t6, the logic circuit 440, upon receiving the transfer signal ATX1 or ATX2, writes the determination result to the transfer memory 430.

[0074] In this embodiment, the amplification ratios of the column amplifier 131 are given as examples of 4x and 1x, but the amplification ratio is not limited to these. Multiple thresholds may be provided, and the amplification ratio selected from multiple amplification ratios may be set. In this embodiment, the amplification ratio of the column amplifier 131 is changed to 1, so the forward input terminal of the comparator 160 can be set to receive an image signal 135, which is the pixel signal from the vertical signal line 130 inverted and amplified by an amplification ratio of 1. Furthermore, as shown in Figure 8, a comparison circuit and a judgment circuit are provided for each of the two pixels, so that an appropriate amplification ratio of the column amplifier can be selected and set for each of the two pixels according to the level of incident light.

[0075] From time t7 onwards, AD conversion of the pixel signal corresponding to high-luminance incident light is performed. From time t7, the potential of the ramp signal rampH increases, and the count signal cnt counts up. At time t8, the potential of the ramp signal rampH exceeds the potential of the image signal 135. At time t8, the comparator output transitions to the L level, and the AD conversion result of the ramp signal rampH relative to the signal level is written to memory 340. At time t9, the ramp signal rampL and the count signal cnt are reset. From time t9 onwards, the information written to memory 340 is processed in the same manner as in Example 1.

[0076] <Examples of application of photoelectric converters to equipment> The following describes a device 1000 that includes a semiconductor device 1100, which includes a package 1020 on which a semiconductor chip 1110, including a semiconductor integrated circuit, is mounted, as shown in Figure 10. The semiconductor chip 1110 is housed in the package 1020 and mounted on the device 1000. In the configuration shown in Figure 10, the semiconductor chip 1110 includes a photoelectric converter according to the above embodiment. The semiconductor device 1100 may include a package 1020 that includes a base 1010 on which the semiconductor chip 1110 is fixed, and a light-transmitting member 1030 such as glass facing the semiconductor chip 1110. The package 1020 may have connecting members such as wires or bumps that connect inner leads provided on the base 1010 to terminals such as pad electrodes provided on the semiconductor chip 1110.

[0077] The device 1000 may include at least one of the following: an optical device 1040, a control device 1050, a processing device 1060, a display device 1070, a storage device 1080, and a mechanical device 1090. The optical device 1040 is, for example, a lens, a shutter, or a mirror. The control device 1050 controls the semiconductor chip 1110. The control device 1050 is, for example, a semiconductor device such as an ASIC.

[0078] The processing unit 1060 processes the output signal from the photoelectric converter included in the semiconductor chip 1110. The processing unit 1060 is a semiconductor device such as a CPU or ASIC for configuring the AFE analog front end or DFE digital front end. For example, it may generate an image based on the imaging signal when an event is detected. The display device 1070 is an EL display device or liquid crystal display device that displays the information image obtained from the semiconductor chip 1110. The storage device 1080 is a magnetic device or semiconductor device that stores the information image obtained from the semiconductor chip 1110. The storage device 1080 is a volatile memory such as SRAM or DRAM, or a non-volatile memory such as flash memory or a hard disk drive.

[0079] The mechanical device 1090 has movable parts or propulsion parts such as a motor or engine. In the device 1000, signals output from the semiconductor chip 1110 are displayed on the display device 1070 or transmitted to the outside by a communication device (not shown) provided in the device 1000. For this purpose, the device 1000 may further include a storage device 1080 and a processing device 1060, separate from the memory circuits and arithmetic circuits of the semiconductor chip 1110. The mechanical device 1090 may be controlled based on signals output from the semiconductor chip 1110.

[0080] The device 1000 is suitable for electronic devices such as information terminals with shooting capabilities, such as smartphones and wearable devices, and cameras, such as interchangeable lens cameras, compact cameras, video cameras, and surveillance cameras. In a camera, the mechanical device 1090 may be a device that can drive components of the optical device 1040 for zooming, focusing, and shutter operation. Alternatively, the mechanical device 1090 in a camera may be a device that can move the optical device 1040 for vibration damping.

[0081] Furthermore, the device 1000 may be a transport device such as a vehicle or a ship. The mechanical device 1090 in the transport device may be used as a mobile device. The device 1000 as a transport device is suitable for transporting semiconductor chips 1110 or for assisting and / or automating driving operations through its imaging function. The processing device 1060 for assisting and / or automating driving operations can perform processing to operate the mechanical device 1090 as a mobile device based on information obtained from the semiconductor chip 1110. Alternatively, the device 1000 may be a medical device such as an endoscope, a measuring instrument such as a distance sensor, an analytical instrument such as an electron microscope, an office machine such as a copier, or an industrial machine such as a robot.

[0082] (Other embodiments) The disclosures herein include the following photoelectric converters and devices using photoelectric converters. (Item 1) At least two pixels, The processing circuit comprises at least two comparison circuits, each performing a first operation to compare pixel signals from at least two pixels with a threshold; at least two holding circuits for holding the results of the first operation; and at least two setting units. Each of the at least two holding circuits holds the result of the first operation of the corresponding comparison circuit among the at least two comparison circuits. The result of the first operation is transferred from the at least two holding circuits to the corresponding setting unit among the at least two setting units via a common signal line. Each of the at least two setting units sets the operating state of the processing circuit according to the result of the first operation. A photoelectric conversion device characterized by the following features. (Item 2) The setting of the operating state includes setting a reference signal selected from among a plurality of reference signals whose voltages change at different rates over time, The at least two comparison circuits perform a second operation, comparing the pixel signal with the selected reference signal. A photoelectric conversion device as described in item 1, characterized by the features described herein. (Item 3) The photoelectric conversion device according to item 1 or 2, characterized in that the at least two pixels are arranged in different rows in a pixel array in which a plurality of pixels are arranged in a matrix. (Item 4) The photoelectric converter according to item 3, characterized in that the number of distinct rows is 2, 4, or 8. (Item 5) The photoelectric converter according to any one of items 1 to 4, characterized in that the results of the first operation held in the at least two holding circuits are sequentially transferred to the signal line. (Item 6) The system further comprises a counter and a memory that holds the count value of the counter, The photoelectric converter according to item 2, characterized in that, in the second operation, the count value counted during the period until the selected reference signal exceeds or falls below the magnitude of the pixel signal is stored in the memory. (Item 7) The photoelectric converter according to any one of items 1 to 6, further comprising an output unit, wherein the result of the first operation is supplied to the output unit via the signal line. (Item 8) The processing circuit further includes an amplifier that amplifies the pixel signal at a set amplification factor. The photoelectric converter according to item 1, characterized in that the setting of the operating state includes setting the amplification factor. (Item 9) The photoelectric conversion device according to item 8, characterized in that the at least two comparison circuits perform a second operation of comparing the pixel signal with a reference signal whose voltage changes over time. (Item 10) The photoelectric conversion device according to item 8 or 9, characterized in that the at least two pixels are arranged in different rows in a pixel array in which a plurality of pixels are arranged in a matrix. (Item 11) The photoelectric converter according to item 10, characterized in that the number of distinct rows is 2, 4, or 8. (Item 12) The photoelectric converter according to any one of items 8 to 11, characterized in that the results of the first operation held in the at least two holding circuits are sequentially transferred to the signal line. (Item 13) The system further comprises a counter and a memory that holds the count value of the counter, The photoelectric converter according to item 9, characterized in that, in the second operation, the count value counted during the period until the reference signal exceeds or falls below the magnitude of the pixel signal is stored in the memory. (Item 14) The photoelectric converter according to any one of items 8 to 13, further comprising an output unit, wherein the result of the first operation is supplied to the output unit via the signal line. (Item 15) A photoelectric converter described in any one of items 1 to 14, The apparatus is characterized by comprising a processing device for processing the output signal from the aforementioned photoelectric converter.

[0083] The invention is not limited to the embodiments described above, and various modifications and variations are possible without departing from the spirit and scope of the invention. Accordingly, claims are attached to disclose the scope of the invention. [Explanation of Symbols]

[0084] 100: Pixel, 110: Pixel array, 120: Pixel scanning unit, 130: Vertical signal line, 131: Column amplifier, 132: Input capacitance, 133: Feedback capacitance, 134: Amplifier, 135: Image signal, 140: Comparator circuit, 150: Lamp generator, 160: Comparator, 170: Switching unit, 180: Switch, 190: Switch, 200: Selection unit, 210: Judgment result transfer line, 215: Memory, 250: Logic circuit, 300: Judgment circuit, 310: Comparator output line, 320: Hold circuit, 330: Pulse generator, 340: Memory, 350: Serial transfer switch, 360: Counter, 400: Horizontal scanning circuit, 410: AD result output line, 420: Horizontal transfer selection switch, 430: Transfer memory, 440: Logic circuit, 500: Output circuit

Claims

1. At least two pixels, The processing circuit comprises at least two comparison circuits, each performing a first operation to compare pixel signals from at least two pixels with a threshold; at least two holding circuits for holding the results of the first operation; and at least two setting units. Each of the at least two holding circuits holds the result of the first operation of the corresponding comparison circuit among the at least two comparison circuits. The result of the first operation is transmitted from the at least two holding circuits to the corresponding setting unit among the at least two setting units via a common signal line. Each of the at least two setting units sets the operating state of the processing circuit according to the result of the first operation. A photoelectric conversion device characterized by the following features.

2. The setting of the operating state includes setting a reference signal selected from among a plurality of reference signals whose voltages change at different rates over time, The at least two comparison circuits perform a second operation, comparing the pixel signal with the selected reference signal. The photoelectric conversion device according to feature 1.

3. The photoelectric conversion device according to claim 1, characterized in that the at least two pixels are arranged in different rows in a pixel array in which a plurality of pixels are arranged in a matrix.

4. The photoelectric conversion device according to claim 2, characterized in that the number of distinct rows is 2, 4, or 8.

5. The photoelectric converter according to claim 1, characterized in that the results of the first operation held in the at least two holding circuits are sequentially transferred to the signal line.

6. The system further comprises a counter and a memory that holds the count value of the counter, The photoelectric converter according to claim 2, characterized in that, in the second operation, the count value counted during the period until the selected reference signal exceeds or falls below the magnitude of the pixel signal is stored in the memory.

7. The photoelectric conversion device according to claim 1, further comprising an output unit, wherein the result of the first operation is supplied to the output unit via the signal line.

8. The processing circuit further includes an amplifier that amplifies the pixel signal at a set amplification factor. The photoelectric converter according to claim 1, characterized in that the setting of the operating state includes setting the amplification factor.

9. The photoelectric conversion device according to claim 8, characterized in that the at least two comparison circuits perform a second operation of comparing the pixel signal with a reference signal whose voltage changes over time.

10. The photoelectric conversion device according to claim 8, characterized in that the at least two pixels are arranged in different rows in a pixel array in which a plurality of pixels are arranged in a matrix.

11. The photoelectric conversion device according to claim 10, characterized in that the number of different rows is 2, 4, or 8.

12. The photoelectric converter according to claim 8, characterized in that the results of the first operation held in the at least two holding circuits are sequentially transferred to the signal line.

13. The system further comprises a counter and a memory that holds the count value of the counter, The photoelectric converter according to claim 9, characterized in that, in the second operation, the count value counted during the period until the reference signal exceeds or falls below the magnitude of the pixel signal is stored in the memory.

14. The photoelectric conversion device according to claim 8, further comprising an output unit, wherein the result of the first operation is supplied to the output unit via the signal line.

15. A photoelectric conversion device according to any one of claims 1 to 14, The apparatus is characterized by comprising a processing device for processing the output signal from the aforementioned photoelectric converter.

Images