Imaging device

Abstract

To provide an imaging device that is integrated three-dimensionally.SOLUTION: An imaging device includes a first layer including a first transistor containing metal oxide in a channel formation region, a first insulating layer, and a second insulating layer, and a second layer including a photodiode. With a conductor penetrating the first insulating layer and the second insulating layer, a conductive layer in contact with the metal oxide and one of a cathode and an anode of the photodiode are in electric connection.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One aspect of the present invention relates to an imaging device.

[0002] Furthermore, one aspect of the present invention is not limited to the above-mentioned technical field. One aspect of the technical field relates to a product, method, or method of manufacture. Or, the present invention. One aspect of this is a process, machine, manufacture, or composition. This relates to matter. Therefore, the invention disclosed more specifically in this specification One aspect of the technical field is semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, and lighting devices. A device, an energy storage device, a memory device, an imaging device, a method of operating them, or a method of manufacturing them. This can be given as an example.

[0003] In this specification, a semiconductor device refers to a device that can function by utilizing semiconductor properties. This refers to the general term. Transistors and semiconductor circuits are forms of semiconductor devices. Also, memory devices, Display devices, imaging devices, and electronic devices may include semiconductor devices. [Background technology]

[0004] Oxide semiconductors are attracting attention as semiconductor materials applicable to transistors. For example, acid Using zinc oxide or In-Ga-Zn oxide semiconductors as the oxide semiconductor, the transient A technique for producing the material has been disclosed (see Patent Documents 1 and 2).

[0005] Furthermore, an imaging device that uses an oxide semiconductor transistor as part of the pixel circuit is particularly useful. This is disclosed in Document 3. [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2007-123861 [Patent Document 2] Japanese Patent Publication No. 2007-96055 [Patent Document 3] Japanese Patent Publication No. 2011-119711 [Overview of the project] [Problems that the invention aims to solve]

[0007] In semiconductor integrated circuits, while density and capacity are increasing, there is also a demand for miniaturization, and two-dimensional There is a shift from integration to three-dimensional integration. In three-dimensional integration, the manufacturing process is complex. Although it can sometimes become messy, the increased freedom in materials and design rules for each layer is a significant advantage. This method enables the fabrication of high-performance semiconductor integrated circuits that are difficult to manufacture through dimensional integration alone.

[0008] The pixel circuit of the imaging device comprises a photoelectric conversion element and a transistor that controls the photoelectric conversion element. It possesses. The photoelectric conversion element requires high light sensitivity, and the transistor has an off-current. Furthermore, low noise characteristics are required. Photoelectric conversion elements and transistors are 3D By integrating the components in a specific way and using manufacturing processes that are appropriate for each component, a higher quality can be achieved. It is possible to fabricate image sensors with specific functions.

[0009] For example, a photodiode with a silicon substrate as the photoelectric conversion layer has high light sensitivity and is used in imaging devices. While suitable, transistors formed on the same silicon substrate have a relatively large off-current. It had a title.

[0010] Therefore, one aspect of the present invention aims to provide a three-dimensional integrated imaging device. It is one of the following. Alternatively, a photodiode and oxide semiconductor using a silicon substrate are used. One of the objectives is to provide an imaging device having a transistor. One of the objectives is to provide an imaging device that can capture images with minimal noise. One of its objectives is to provide an imaging device with high resolution. Alternatively, it can provide imaging with a high aperture ratio. One of the objectives is to provide an imaging device that can be used over a wide temperature range. One of the objectives is to provide an apparatus, or to provide a highly reliable imaging apparatus. One of the objectives is to provide a novel imaging device or the like.

[0011] Furthermore, the description of these problems does not preclude the existence of other problems. The approach does not need to solve all of these problems. This will become clear from the description in the specification, drawings, claims, etc., and the specification, drawings It is possible to extract other issues from the descriptions in the surfaces, claims, etc. [Means for solving the problem]

[0012] One aspect of the present invention comprises a first layer and a second layer, wherein the first layer has a channel-forming region. A first transistor having a metal oxide, a first insulating layer, and a second insulating layer, Transistor 1 is provided between the first insulating layer and the second insulating layer, and the first transistor The sta has a first conductive layer in contact with a metal oxide, and the second layer has a photodiode. The first conductive layer and either the cathode or anode of the photodiode are separated by the first insulating layer. The imaging device is electrically connected via a conductor that penetrates the second insulating layer.

[0013] Furthermore, in the above embodiment, even if the photodiode is provided on a single-crystal silicon substrate good.

[0014] Furthermore, in the above embodiment, a third layer is provided, and the third layer has silicon in the channel formation region. It has a second transistor, a third insulating layer, and a fourth insulating layer, and a first transistor The first transistor and the second transistor are positioned so that their gate surfaces face each other. A second conductive layer is provided such that it has a region embedded in the third insulating layer, and the second transient The source, drain, or gate of the conductor, and the second conductive layer, and the conductor that penetrates the fourth insulating layer. Electrically connected via, a third on the light-receiving side of the photodiode on the single-crystal silicon substrate. A conductive layer is provided, and the second conductive layer and the third conductive layer are the first to third insulating layers and They may be electrically connected via a conductor that penetrates the single-crystal silicon substrate.

[0015] Furthermore, in the above embodiment, the first conductive layer and the cathode or anode of the photodiode. One of the two is that electricity is transmitted through a conductor that penetrates the first insulating layer, the metal oxide, and the second insulating layer. It may be connected electrically.

[0016] Furthermore, in the above embodiment, the first layer comprises a first transistor and a second transistor, It has a third transistor, a fourth transistor, a first wire, and a second wire. The first transistor is provided in the pixel circuit, and the second transistor is provided in the row driver. The third transistor is provided in the column driver, and the fourth transistor is in the analog switch. The second to fourth transistors are provided in such a configuration that they have a metal oxide in the channel formation region. good.

[0017] Furthermore, in the above embodiment, the A / D converter is included, and the analog switch has a first wiring and Electrically connected, the analog switch is electrically connected to the second wiring, and the first wiring is The first wire is electrically connected to the pixel circuit, and the second wire is electrically connected to the A / D converter. Even if an A / D converter has a transistor that uses silicon in the channel formation region good.

[0018] Furthermore, in the above embodiment, the metal oxide is In, Zn, and M (where M is Al, Ga, Y) It may have Sn) and .

[0019] Furthermore, a module having an imaging device and a lens according to one aspect of the present invention is also according to one aspect of the present invention. be.

[0020] Furthermore, an electronic device having an imaging device and a display device according to one aspect of the present invention is also according to one aspect of the present invention. be. [Effects of the Invention]

[0021] By using one aspect of the present invention, a three-dimensional integrated imaging device can be provided. Alternatively, photodiodes using silicon substrates and transients using oxide semiconductors An imaging device with a st is provided. Or, an imaging device that captures images with low noise is provided. We can provide an imaging device that can do the following. Or, we can provide an imaging device with high resolution. It is possible to provide an imaging device with a high aperture ratio. Alternatively, it is possible to provide a wide temperature An imaging device usable within a certain range can be provided. Or, a reliable imaging device can be provided. We can provide equipment. Alternatively, we can provide novel imaging devices, etc.

[0022] Furthermore, one aspect of the present invention is not limited to these effects. For example, one aspect of the present invention In some cases, or depending on the circumstances, it may have effects other than those listed above. Yes. Or, for example, one aspect of the present invention may, depending on the circumstances, These effects may not always be present. [Brief explanation of the drawing]

[0023] [Figure 1] Diagrams and circuit diagrams illustrating the pixels of an imaging device. [Figure 2] A diagram illustrating the pixel circuit. [Figure 3] A diagram showing the 1 / f noise characteristics of an OS transistor. [Figure 4] A diagram illustrating the configuration of a photoelectric conversion element. [Figure 5] A diagram illustrating the connection configuration between a photoelectric conversion element and a transistor. [Figure 6] A diagram illustrating the connection configuration between a photoelectric conversion element and a transistor. [Figure 7] A diagram illustrating the connection configuration between a photoelectric conversion element and a transistor. [Figure 8] A diagram illustrating the pixels of an imaging device. [Figure 9] A diagram illustrating the pixels of an imaging device. [Figure 10] A diagram illustrating the peripheral circuitry of the imaging device. [Figure 11] A block diagram of the image sensor, a block diagram of the A / D converter, and a diagram showing the connection configuration between the image sensor and the A / D converter. [Figure 12] A diagram showing the configuration of a shift register. [Figure 13] A diagram illustrating the pixel circuit. [Figure 14] A timing chart illustrating the operation of the pixel circuit. [Figure 15]A diagram illustrating the pixel circuit. [Figure 16] Top view and cross-sectional view illustrating a transistor. [Figure 17] Top view and cross-sectional view illustrating a transistor. [Figure 18] A diagram illustrating the cross-section of a transistor in the channel width direction. [Figure 19] A diagram illustrating the cross-section of a transistor along its channel length. [Figure 20] Top view and cross-sectional view illustrating the semiconductor layer. [Figure 21] Top view and cross-sectional view illustrating a transistor. [Figure 22] Top view and cross-sectional view illustrating a transistor. [Figure 23] A diagram illustrating the cross-section of a transistor in the channel width direction. [Figure 24] A diagram illustrating the cross-section of a transistor along its channel length. [Figure 25] Top view and cross-sectional view illustrating a transistor. [Figure 26] Top view and cross-sectional view illustrating a transistor. [Figure 27] Top view and cross-sectional view illustrating a transistor. [Figure 28] Top view and cross-sectional view illustrating a transistor. [Figure 29] Top view and cross-sectional view illustrating a transistor. [Figure 30] A top view illustrating a transistor. [Figure 31] A diagram illustrating the range of atomic ratios in oxide semiconductors. [Figure 32] A diagram illustrating the crystal structure of InMZnO4. [Figure 33] Band diagram of a stacked oxide semiconductor structure. [Figure 34] Figures illustrating the XRD structural analysis of CAAC-OS and single-crystal oxide semiconductors, as well as a figure showing the limited-field electron diffraction pattern of CAAC-OS. [Figure 35]Cross-sectional TEM images of CAAC-OS, as well as planar TEM images and their image analysis results. [Figure 36] Figure showing the electron diffraction pattern of nc-OS, and a cross-sectional TEM image of nc-OS. [Figure 37] Cross-sectional TEM image of an a-like OS. [Figure 38] A diagram showing the changes in the crystalline structure of In-Ga-Zn oxide due to electron irradiation. [Figure 39] Perspective and cross-sectional views of the package containing the imaging device. [Figure 40] Perspective and cross-sectional views of the package containing the imaging device. [Figure 41] A diagram illustrating electronic devices. [Modes for carrying out the invention]

[0024] Embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. Without departing from the spirit and scope of the present invention, its form and details may be changed in various ways. Those skilled in the art will readily understand that further improvements are possible. Therefore, the present invention can be implemented as follows: The description of the form is not to be interpreted as being limited to the content of the description. Furthermore, the structure of the invention described below In this context, the same reference numeral is used for identical parts or parts having similar functions across different drawings. It is used in this way, and the explanation of its repetition may be omitted. Note that the same elements that make up the figure Matching may be omitted or modified as appropriate between different drawings.

[0025] The ordinal numbers "1st" and "2nd" are used for convenience only and do not necessarily indicate the order of processes or layering. It does not indicate order. Therefore, for example, "the first" could be "the second" or "the third." It can be explained by substituting it as appropriate. Also, ordinal numbers as described in this specification, etc. The ordinal numbers used to specify one aspect of the present invention may not always coincide.

[0026] For example, in this specification, etc., if it is explicitly stated that X and Y are connected The cases are when X and Y are electrically connected and when X and Y are functionally connected. The cases disclosed in this specification, etc., include the case where X and Y are directly connected. Therefore, the connection relationships are not limited to those shown in the diagram or text. In addition to the connection relationships shown in the diagram or text, other connections may also be included as described in the diagram or text. do.

[0027] Here, X and Y are the object (e.g., device, element, circuit, wiring, electrode, terminal, conductive film, layer). (etc.)

[0028] One example of a case where X and Y are directly connected is when an electrical connection between X and Y is possible. Elements such as switches, transistors, capacitive elements, inductors, resistive elements, and dies. If the diode, display element, light-emitting element, load, etc. are not connected between X and Y and elements that enable electrical connection between X and Y (e.g., switches, transistors, capacitors). Without the need for elements such as components, inductors, resistors, diodes, display elements, light-emitting elements, loads, etc. This is the case when X and Y are connected.

[0029] One example of a case where X and Y are electrically connected is the ability to make an electrical connection between X and Y possible. Elements such as switches, transistors, capacitive elements, inductors, resistive elements, and dies. One or more devices (such as diodes, display elements, light-emitting elements, and loads) are connected between X and Y. Yes, it is possible. Furthermore, a switch has the function of being controlled to be on or off. In other words, a switch The switch can be in a conductive (on) or non-conductive (off) state, allowing current to flow. It has a function to control whether or not current flows. Alternatively, the switch selects the path through which current flows. It has a function to switch between them. Furthermore, if X and Y are electrically connected, X and This includes cases where Y is directly connected to it.

[0030] One example of a functional connection between X and Y is enabling a functional connection between X and Y. Circuits that perform this function (for example, logic circuits (inverters, NAND gates, NOR gates, etc.), signal transformers) Conversion circuits (D / A conversion circuits, A / D conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (Power supply circuits (boost circuits, buck circuits, etc.), level shifter circuits that change the potential level of signals, etc.) (etc.), voltage source, current source, switching circuit, amplification circuit (to increase signal amplitude or current amount, etc.) (Incoming circuits, operational amplifiers, differential amplifiers, source follower circuits, buffer circuits, etc.), signal One or more generation circuits, memory circuits, control circuits, etc., can be connected between X and Y. As an example, even if another circuit is placed between X and Y, the output from X If a signal is transmitted to Y, then X and Y are assumed to be functionally connected. When X and Y are functionally connected, the situation is different from when X and Y are directly connected. This includes the case where and Y are electrically connected.

[0031] Furthermore, if it is explicitly stated that X and Y are electrically connected, then X and Y and When they are electrically connected (i.e., when there is another element or circuit between X and Y) (when connected by) and when X and Y are functionally connected (i.e., X and Y and (When they are functionally connected with another circuit in between) and when X and Y are directly connected In the case where (that is, when X and Y are connected without another element or circuit in between) ) and are disclosed in this specification, etc. That is, electrically connected and If explicitly stated, simply explicitly stated as connected. The same information as in this case is disclosed in this specification, etc.

[0032] For example, the source (or first terminal, etc.) of the transistor is connected via Z1 (and (Without intervening), electrically connected to X, and the drain of the transistor (or second terminal, etc.) However, if Y is electrically connected via (or without) Z2, or if a transistor The source (or first terminal, etc.) is directly connected to a part of Z1, and another part of Z1 It is directly connected to X, and the drain (or second terminal, etc.) of the transistor is connected to Z2. If one part is directly connected to Z2, and another part of Z2 is directly connected to Y, then: It can be expressed as follows.

[0033] For example, "X and Y and the source (or first terminal, etc.) and drain (or The second terminal, etc., is electrically connected to each other, and X is the source of the transistor ( (or the first terminal, etc.), the transistor's drain (or the second terminal, etc.), and Y in that order. It can be expressed as, "It is electrically connected." Or, "The source of the transistor." (or the first terminal, etc.) is electrically connected to X and the drain of the transistor (or The second terminal (or other terminal) is electrically connected to Y, and X is the source of the transistor (or the first terminal). Y is electrically connected to the drain (or second terminal, etc.) of the transistor in this order. It can be expressed as "X is connected to the source of the transistor ( or via the first terminal (or the second terminal, etc.) and the drain (or the second terminal, etc.), Y is electrically connected. Connected, X, the source of the transistor (or the first terminal, etc.), the slave of the transistor It can be expressed as "N (or the second terminal, etc.), Y are provided in this connection order." Yes, it is possible. Using similar notation to these examples, the order of connections in a circuit configuration can be specified. By defining the source (or first terminal, etc.) and drain (and The technical scope can be determined by distinguishing between (for example, a second terminal) and other components.

[0034] Alternatively, another way to express it is, for example, "the source (or first terminal, etc.) of the transistor." ) is electrically connected to X via at least a first connection path, and the first connection path It does not have a second connection path, and the second connection path is via a transistor. The source of the transistor (or the first terminal, etc.) and the drain of the transistor (or the second terminal) The first connection path is a path via Z1, and the terminal is a path between terminals, etc. The drain of the inverter (or a second terminal, etc.) is connected via at least a third connection path. Electrically connected to Y, the third connection path does not have the second connection path, The third connection route is the route via Z2. This can be expressed as: The source (or first terminal, etc.) of the transistor is connected by at least the first connection path. , electrically connected to X via Z1, the first connection path has a second connection path The second connection path has a connection path via a transistor, The drain (or second terminal, etc.) is connected via at least a third connection path through Z2. The third connection path is electrically connected to Y, and the third connection path does not have the second connection path. It can be expressed as, "The source (or first terminal) of the transistor." (d) is electrically connected to X via Z1 by at least a first electrical path, The first electrical path does not have a second electrical path, and the second electrical path does not have a second electrical path. From the source (or first terminal, etc.) of the transistor to the drain (or second terminal, etc.) of the transistor This is an electrical path to the transistor's drain (or second terminal, etc.), and the drain of the transistor (or second terminal, etc.). ) is electrically connected to Y via Z2 by at least a third electrical path, and The third electrical path does not have a fourth electrical path, and the fourth electrical path is From the drain of the transistor (or the second terminal, etc.) to the source of the transistor (or the first terminal) It is an electrical path to terminals, etc. This can be expressed as "a table similar to these examples." By using the current method to define the connection paths in the circuit configuration, Distinguish between the source (or first terminal, etc.) and the drain (or second terminal, etc.). This allows us to determine the technical scope.

[0035] Note that these methods of expression are just examples and are not limited to these methods. Here, X Y, Z1, and Z2 are the objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, etc.) Let's assume it is a layer, etc.

[0036] Note that, in circuit diagrams, independent components are shown as being electrically connected to each other. Even in such cases, one component may possess the functions of multiple components. For example, if part of the wiring also functions as an electrode, one conductive film will function as the wiring, and It possesses the functions of both components of the electrode. Therefore, in this specification Electrically connected means that a single conductive film combines the functions of multiple components. This also falls under that category.

[0037] Note that the words "membrane" and "layer" may differ in some cases or depending on the situation. Therefore, they can be interchanged. For example, the term "conductive layer" can be replaced with "conductive film." In some cases, it may be possible to change the term to "insulating film". Alternatively, for example, the term "insulating film" may be used. In some cases, it may be possible to change the term to "insulating layer."

[0038] Generally speaking, electric potential (voltage) is relative, and its relative magnitude from a reference potential is... The size is determined by the degree. Therefore, terms such as "grounding," "GND," and "earth" are used. Even if it is stated, the potential is not necessarily 0 volts. For example, when defining "ground" or "GND" based on the lowest potential in a circuit, Yes, it exists. Alternatively, in a circuit, an intermediate potential can be used as a reference to define "ground" or "GND". In some cases, positive and negative potentials are defined based on that potential. And so it becomes.

[0039] (Embodiment 1) This embodiment describes the configuration of an imaging device that is one aspect of the present invention.

[0040] One aspect of the present invention is an imaging device having a photoelectric conversion element and a transistor. The device and transistor are integrated in a three-dimensional structure, using materials suitable for each component. By carrying out the manufacturing process in this way, it is possible to create image sensors with higher functionality.

[0041] Figure 1(A) is a cross-sectional view of a pixel 20 in an imaging device according to one embodiment of the present invention, and consists of 3 pixels ( This shows the configuration of pixels 20a, 20b, and 20c.

[0042] Figure 1(B) is a circuit diagram of pixel 20. In this embodiment, the transistor is nc An example of the h-type case is shown, but one aspect of the present invention is not limited thereto, and some transistors This can be replaced with a p-channel transistor.

[0043] As shown in Figure 1(B), one electrode of the photoelectric conversion element PD is the source of transistor 41. Alternatively, it is electrically connected to one of the drains. Source or drain of transistor 41 The other end is electrically connected to either the source or the drain of transistor 42. The source or drain of transistor 41 is electrically connected to the gate of transistor 43. The connection continues. Either the source or drain of transistor 43 is connected to the source of transistor 44. It is electrically connected to either the spool or the drain.

[0044] Here, the source or drain of transistor 41, and the source of transistor 42 Alternatively, the drain is connected to node FD, to which the gate of transistor 43 is connected, and the charge storage section is connected to node FD. In addition, as shown in Figure 2(A), the configuration is such that a capacitive element is connected to node FD. That's good too.

[0045] The other electrode of the photoelectric conversion element PD is electrically connected to wiring 71 (VPD). The source or drain of station 42 is electrically connected to wiring 72 (VRS). The source or drain of transistor 43 is electrically connected to wiring 73 (VPI). The source or drain of transistor 44 is connected to the wiring 91 (OUT1). They are connected by air.

[0046] Note that the connection configuration between elements such as transistors and photoelectric conversion elements and wiring is just one example. When each element is electrically connected to different wiring, or when multiple elements are electrically connected to the same wiring... They can also be connected electrically.

[0047] Wiring 71 (VPD), wiring 72 (VRS), and wiring 73 (VPI) are power lines. It has a function. For example, wiring 71 (VPD) has the function of a low-potential power line. Line 72 (VRS) and wiring 73 (VPI) function as high-potential power lines.

[0048] The gate of transistor 41 is electrically connected to wiring 61 (TX). Transistor 4 The gate of transistor 2 is electrically connected to wiring 62 (RS). The gate of transistor 44 is It is electrically connected to wiring 63(SE).

[0049] Wires 61 (TX), 62 (RS), and 63 (SE) are connected to each other. It functions as a signal line that controls the conduction of a transistor.

[0050] Transistor 41 is for transferring the cathode potential of the photoelectric conversion element PD to node FD. It functions as a transistor. Transistor 42 resets the potential of node FD. It functions as a transistor for the purpose of [doing something]. Transistor 43 is at the potential of node FD. It functions as a transistor to produce an output corresponding to the following. Transistor 44 is It functions as a transistor for selecting pixel 20.

[0051] Furthermore, as shown in Figure 2(B), the orientation of the photoelectric conversion element PD in pixel 20 is reversed compared to Figure 1(B). This is also acceptable. In this case, region 510 is the anode (p-type region) and region 520 is the cathode. It can be defined as a (n-type region). For example, using an n-type single-crystal silicon substrate, region 5 The p-type can be achieved by adding a dopant such as boron to compound 10.

[0052] Note that the above-described configuration of pixel 20 is just one example, and some circuits, some transistors, and some Capacitive elements or some wiring may not be included. Or, they may not be included in the above-mentioned configuration. It may also include circuits, transistors, capacitive elements, wiring, etc. The connection configuration may differ from the one described above.

[0053] As shown in Figure 1(A), pixel 20 has layers 1100, 1200 and 1300. This configuration can be achieved. For example, layer 1100 contains transistors 4 that constitute the pixel circuit. It has 1 to 44, etc. Layer 1200 has a photoelectric conversion element PD, etc. Layer 1300 is It includes a color filter and a microlens array, among other things.

[0054] In the cross-sectional view described in this embodiment, each layer is a protective film, an interlayer insulating film, or a flat film. Insulating layers 81a to 81e, etc., which have the function of a film are provided. For example, insulating layer 81 a to 81e are CVD (Chemical Vapor Deposition) methods. Inorganic insulating films such as silicon oxide films and silicon oxide nitride films can be used to form films. Alternatively, an organic insulating film such as acrylic resin or polyimide resin may be used. The upper surfaces of layers 81a to 81e, etc., are treated with CMP (Chemical Mechanism) as needed. Planarization treatment may be performed using methods such as the ical polishing method.

[0055] In the transistors 41 to 44 provided in layer 1100, an oxide semiconductor is used in the channel formation region. It is preferable to use the transistor used (hereinafter referred to as OS transistor). A transistor is a transistor that uses silicon in the channel formation region (hereinafter referred to as a Si transistor). Furthermore, the off-current is small. Therefore, all pixels can be controlled without complicating the circuit configuration or operating method. A global shutter system that simultaneously performs charge accumulation operations can be applied. An imaging device according to one aspect of the present invention can also be operated using a rolling shutter method.

[0056] In this specification, etc., when oxide semiconductors are referred to as metal oxides. There is.

[0057] OS transistors have less temperature dependence on electrical characteristics than Si transistors, It can be used over an extremely wide temperature range. Therefore, an image with an OS transistor The imaging devices and semiconductor equipment are also suitable for installation in automobiles, aircraft, spacecraft, and other applications.

[0058] Furthermore, OS transistors have superior 1 / f noise characteristics compared to Si transistors. (Figure 3) This refers to the 1 / f noise of OS transistors and Si transistors (n-channel type, p-channel type). This is data comparing the characteristics of the series.

[0059] The vertical axis is S id / Id 2 ·L·W[m 2 [ / Hz], the spectral density of the drain current is measured. This is a value normalized by the input current and the transistor channel size, and the frequency is 1Hz or longer. Measurements were taken in the 10kHz range. L represents the transistor channel length, and W represents the transistor channel length. This is the channel width of the transistor, and for OS transistors, L / W = 30nm / 30nm or L For a silicon transistor, the wattage (W) is 30 nm / 60 nm, while for a silicon transistor, the wattage (L / W) is 0.8 μm / 10 μm. Furthermore, the measurement conditions for the OS transistor were Vd=1.0V, Id=1μA, Si transistor The measurement conditions for the voltage were Vd = 0.1V and Id = 1μA.

[0060] Figure 3 shows the use of an IGZO target with an In:Ga:Zn = 4:2:4.1 (atomic ratio). OS transistor (L) using an oxide semiconductor layer deposited by sputtering as the channel formation region The data is for (W=30nm / 30nm). The 1 / f noise of the OS transistor is n- It is smaller than a ch-type Si transistor. Furthermore, it is smaller than a p-ch type Si transistor. Then, in the range of 1Hz to 500Hz, it is small, and at frequencies above that, The results are almost identical. That is, the frequency logarithmic axis in Figure 3 from 1 Hz to 10 kHz. In the range of 60% or more below, the 1 / f noise is greater than that of a p-channel Si transistor. It can be said that OS transistors are smaller.

[0061] In other words, using an IGZO target with an In:Ga:Zn ratio of 4:2:4.1 (atomic ratio) The OS transistor fabricated using this method exhibits better 1 / f noise characteristics than the Si transistor. Therefore, for example, the OS transistor can be used as a pixel in a CMOS image sensor. By using it in such applications, it produces a clearer image with less noise than when using Si transistors. It becomes possible to obtain an image. Also, In:Ga:Zn=3:1:4 or 5:1:6( It may also be an OS transistor fabricated using an IGZO target (atomic ratio). Oh, the vicinity of the above atomic ratio is also included in that category.

[0062] Figure 1(A) shows an example of transistor 41. As shown in Figure 1(A), the transistor STA41 can be, for example, a top-gate type OS transistor. The zista is provided on the insulating layer 81c formed on the layer 1200, and the oxide semiconductor layer 130 And a conductive layer 140 that functions as either a source electrode or a drain electrode, and the source electrode A conductive layer 150 that functions as the other side of the drain electrode, and an insulating layer that functions as the gate insulating layer. It has an edge layer 160 and a conductive layer 170 that functions as a gate electrode. The insulating layer 81c is It can also function as a gate insulating layer on the back gate side, as described later.

[0063] In Figure 1(A), a conductive layer 173 is provided on transistor 41 to function as a back gate electrode. This illustrates a configuration in which an OS transistor is provided in the pixel circuit as a top-gate type transistor. In the case of a stabilization, light transmitted through layer 1200 may enter layer 1100, It is preferable to have a configuration that provides a back gate electrode to shield from light. However, the thickness of layer 1200 If there is sufficient clearance and the amount of light transmitted is within an acceptable range, a configuration without a back gate electrode can be used. It is also possible to provide a back gate electrode if a light-shielding layer or the like is provided separately. It is also possible to create a configuration that does not allow this.

[0064] The photoelectric conversion element PD provided in layer 1200 is a photodiode provided on a single-crystal silicon substrate. A photodiode can be used. This photodiode has excellent photoelectric conversion characteristics. Also, In this photodiode, the single-crystal silicon substrate of the base material functions as the photoelectric conversion layer, It can be manufactured relatively easily. The single-crystal silicon substrate is polished as needed, for example. A thickness of 3 to 30 μm is sufficient.

[0065] Note that Figure 1(A) shows a pn junction photodiode as an example, and the rotation shown in Figure 1(B) According to the path diagram, region 510 is the cathode (n-type region) and region 520 is the anode (p-type region). This can be done. For example, using a p-type single-crystal silicon substrate, phosphorus, etc. can be placed in region 510. The n-type can be achieved by adding the dopant.

[0066] Furthermore, the photodiode provided in layer 1200 is isolated from region 510 as shown in Figure 4(A). A region 530 having a conductivity type opposite to that of region 510 may be provided in a portion of the space between the border layer 81d and the region 530. Furthermore, as shown in Figure 4(B), region 530 extends to the entire area between region 510 and the insulating layer 81d. It may be provided. With this configuration, the photodiode is embedded and Therefore, noise generated at the interface between silicon and the insulating layer can be suppressed.

[0067] Furthermore, the photodiodes provided in layer 1200 have partitions between pixels, as shown in Figure 4(C). The configuration may also be such that a groove is formed between the pixels and the groove is filled with an insulating layer 81e. It should be formed to fill the gap. With this configuration, light incident from an oblique direction It can prevent the intrusion of stray light.

[0068] Furthermore, it is preferable to use a material with a lower refractive index than silicon as the partition wall. For example, The insulating layer 81e can be made from the materials mentioned above. Alternatively, a material that easily absorbs light can be used. A partition wall may be formed. For example, carbon-based black pigments such as carbon black, titanium Titanium-based black pigments such as black, iron oxides, copper and chromium composite oxides, copper, chromium Resins containing materials such as composite oxides of zinc and other metals can also be used.

[0069] Furthermore, the photodiode provided in layer 1200 is isolated from region 520 as shown in Figure 4(D). Between the border layer 81e is a region with the same conductivity type as region 520 but with a higher dopant concentration than region 520. A region 540 may be provided. This configuration allows for efficient collection of carrier data. It is possible.

[0070] Furthermore, the photodiode provided in layer 1200 is adjacent to region 530, as shown in Figure 4(E). A region 540 may be provided adjacent to it.

[0071] Note that in the configurations shown in Figures 1(A), 4(A), (B), and (C), each of the multiple pixels has a region of 520. The wiring 71 should be electrically connected to the other components. Also, in the configuration shown in Figure 4(D), multiple For each pixel, the region 540 and the wiring 71 should be electrically connected via region 545. Furthermore, region 545, like region 540, has the same conductivity type as region 520, but is more conductive than region 520. This is a region with a high dopant concentration. Also, in the configuration shown in Figure 4(E), each region 540 is connected to wiring 7 The configuration should be one that is electrically connected to 1.

[0072] In an imaging apparatus according to one aspect of the present invention, as shown in Figure 1(A), the source of transistor 41 Alternatively, the electrical connection between one of the drains and one of the electrodes of the photoelectric conversion element PD is made by the conductor 82. This is done via. The conductor 82 consists of an insulating layer 81b, a conductive layer 140, an oxide semiconductor layer 130, and an insulating layer. It is provided so as to penetrate layer 81c and insulating layer 81d.

[0073] This configuration allows for the use of multiple conductors 82 and connecting wires to form a bridge. The above electrical connection can be obtained without making any connections, thus simplifying the process. Furthermore, it is necessary to create openings in the insulating layers 81c, 81d, etc., before forming the transistor 41. This eliminates the need for steps and other shape irregularities, thereby suppressing the occurrence of process defects.

[0074] The electrical connection between the conductor 82 and one electrode of the photoelectric conversion element PD is shown in Figure 5(A). This may be done via a conductive layer 550. The conductive layer 550 may be made of, for example, W, Ta, Al Metal layers such as Ti, Ni, SUS, and Pd can be used. The conductive layer 550 is photoelectric In addition to acting as an electrode for the conversion element PD, it also serves as an electrode when forming a through-hole for the conductor 82. It also acts as a chnostopper. Furthermore, it acts as a light-shielding layer for transistors and photoelectric transformers. It also acts as a reflective electrode for the photodiode (PD) converter.

[0075] Furthermore, the conductor 82 consists of a conductive layer 140 and an oxide semiconductor layer 130, as shown in Figure 5(B). It does not penetrate, and does not come into contact with the upper and side surfaces of the conductive layer 140, as well as the side surfaces of the oxide semiconductor layer 130. An electrical connection may be obtained by doing so. The conductive layer 140 mainly consists of a difficult-to-etch material. Because a metal layer is used, this configuration makes etching difficult when forming through-holes. This can reduce the workload on the process.

[0076] Furthermore, as shown in Figure 5(C), one electrode of the photoelectric conversion element PD has an electrical connection. The conductive layer 560 and the conductor 82 may be configured to have an electrical connection. The conductive layer 560 is After providing an opening in the insulating layer 81d, it can be formed using the same process as the conductive layer 173. 560 acts as an etching stopper when forming a through-hole for the conductive material 82. ru.

[0077] Furthermore, for example, the back gate electrodes of each transistor 41 in the pixel 20 are made common. This is possible. In this case, pixel 20 can be configured as shown in Figure 6(A). Also, for example In addition to transistor 41, the backgear of each transistor provided in layer 1100 The electrode can be made common. In the pixel 20 with the above configuration, the conductive layer 173 This can enhance the light-shielding effect on transistors.

[0078] Furthermore, as shown in Figure 6(B), the conductive layer 173 and the wiring 71 are electrically connected. This is also good. In Figure 6(B), the conductive layer 17 of pixels 20a, 20b and 20c Figure 3 shows the configuration when the wiring 71 is electrically connected. By adopting this configuration, This controls the potential of the wiring 71 and the back gate potential of the transistor in the pixel 20 simultaneously. Because it can be controlled, the operation of pixel 20 can be easily controlled.

[0079] In addition, in the pixel 20 with the configuration shown in Figures 6(A) and (B), the conductor 82 and the conductive layer 173 The structure is designed so that it does not intersect with other elements.

[0080] Furthermore, the pixel 20 can have the configuration shown in Figure 7(A). In the pixel 20 with this configuration, Regions 143 and 153 are provided on the single-crystal silicon substrate 500. Region 143 And region 153, like region 510, may be modified by adding a dopant such as phosphorus. This can result in an n-type region formed by the aforementioned method.

[0081] Furthermore, the oxide semiconductor layer 130 is provided so as to be in contact with regions 143 and 153. The conductive layer 140 is provided so as to overlap with region 143, and the conductive layer 150 is provided so as to region 15 It is provided so as to overlap with 3. In this configuration, region 143 and the conductive layer 140 and region 1 The region sandwiched between 43 functions as either a source or a drain, and region 153 and the guide The region sandwiched between the electrode layer 150 and region 153 functions as either a source or a drain. In other words, the transistor 41 is located on the single-crystal silicon substrate 500 in addition to the oxide semiconductor layer 130. A channel region is also formed. Therefore, the channel region of transistor 41 is made of oxide This results in a layered structure of semiconductor and silicon. This increases the on-current of transistor 41. It can be done.

[0082] Furthermore, region 143 extends to form region 510, thereby the transistor 41 One of the source or drain is electrically connected to one of the electrodes of the photoelectric conversion element PD. Yes. In other words, one of the sources or drains of transistor 41 and the photoelectric conversion element PD There is no need to provide a conductive layer or the like for electrically connecting one electrode to the other. The manufacturing process of one embodiment of the imaging device can be simplified.

[0083] Furthermore, the OS transistor used in one aspect of the present invention may have the configuration shown in Figure 7(B). The transistor shown in Figure 7(B) is in contact with region 510 of the photoelectric conversion element PD, and the source power A conductive layer 140 that functions as either a pole or a drain electrode, and region 510 that is exposed an oxide semiconductor layer 130 covering the opening provided in the insulating layer 81j, and an oxide semiconductor layer 13 A conductive layer 150 provided on the 0, which functions as the other of a source electrode or a drain electrode, The gate overlaps with the oxide semiconductor layer 130 and the insulating layer 160 which functions as a gate insulating layer. It has a conductive layer 170 that functions as an electrode.

[0084] This type of configuration can also be called a vertical transistor. In a vertical transistor, insulation Since the region including the side wall of the opening provided in layer 81j becomes the channel region, the transistor The occupied area can be reduced.

[0085] Note that in the pixel 20 with the configuration shown in Figures 7(A) and (B), the insulating layer 81c and insulating layer 81d It is not provided.

[0086] Layer 1300 contains a light-shielding layer 1530, optical conversion layers 1550a, 1550b, 1550c, and A microlens array 1540 and the like can be installed.

[0087] An insulating layer 81e is formed in the region in contact with layer 1200. The insulating layer 81e is visible light A highly light-transmitting silicon oxide film can be used. In addition, a passivation film and Alternatively, a silicon nitride film may be laminated in this configuration. Furthermore, as an anti-reflective film, hafny oxide may be used. A configuration in which dielectric films such as um are stacked may also be used.

[0088] A light-shielding layer 1530 can be provided on the insulating layer 81e. The light-shielding layer 1530 is provided on adjacent frames. It is disposed at the bare boundary and has a function of shielding stray light that enters from an oblique direction. The light-shielding layer 1530 can be configured to stack a metal layer such as aluminum or tungsten, and a dielectric film having the function as an antireflection film on the metal layer.

[0089] An optical conversion layer 1550a, 1550b, 155 0c can be provided on the insulating layer 81e and the light-shielding layer 1530. For example, by assigning color filters such as R (red), G (green), B (blue), Y (yellow), C (cyan), and M (magenta) to the optical conversion layers 1550a, 1550b, and 1550c, a color image can be obtained.

[0090] Note that if a filter that blocks light with a wavelength equal to or less than that of visible light is used for the optical conversion layer, an infrared imaging device can be formed. Also, if a filter that blocks light with a wavelength equal to or less than that of near-infrared light is used for the optical conversion layer, a far-infrared imaging device can be formed. Further, if a filter that blocks light with a wavelength equal to or greater than that of visible light is used for the optical conversion layer, an ultraviolet imaging device can be formed.

[0091] In addition, if a scintillator is used for the optical conversion layer, an imaging device that obtains an image visualizing the intensity of radiation used for an X-ray imaging device or the like can be formed. When radiation such as X-rays transmitted through a subject enters the scintillator, it is converted into visible light, ultraviolet light, or any other light (fluorescence) by the photoluminescence phenomenon. Then, the image data is obtained by detecting the light with the photoelectric conversion element PD. Also, an imaging device having such a configuration may be used for a radiation detector or the like.

[0092] When the scintillator is irradiated with radiation such as X-rays or gamma rays, it absorbs the energy ​​​​​​It contains substances that emit visible light or ultraviolet light. For example, Gd2O2S:Tb, Gd2O2S:P r, Gd2O2S:Eu, BaFCl:Eu, NaI, CsI, CaF2, BaF2, C eF3, LiF, LiI, ZnO dispersed in resins or ceramics can be used. It is possible.

[0093] On the optical conversion layers 1550a, 1550b, and 1550c, a microlens array 1540 can be provided. The light passing through the individual lenses of the microlens array 1540 passes through the directly underlying optical conversion layers 1550a, 1550b, and 1550c and irradiates the photoelectric conversion element PD.

[0094] Also, as shown in FIG. 8, the pixel 20 can have a configuration including a layer 1400 in addition to the layers 1100, 1200, and 1300. The layer 1400 has external circuits other than pixel circuits, such as drive circuits like column drivers and load drivers, data conversion circuits like A / D converters, noise reduction circuits like CDS (Cor related Double Sampling) circuits, and control circuits for the entire imaging device.

[0095] The layer 1400 has transistors 46 and 47 provided on the single crystal silicon substrate 600, and insulating layers 81f, 81g, 81h, etc. provided on the transistors 46 and 47.

[0096] Hydrogen in the insulating layer provided near the active regions of the transistors 46 and 47, etc. terminates the dangling bonds of silicon. Therefore, the hydrogen has the effect of improving the reliability of the transistors 46 and 47, etc. On the other hand, the transitors 4 Hydrogen in an insulating layer provided near an oxide semiconductor layer which is a channel-forming region such as 1, It is one of the factors that generate carriers in the oxide semiconductor layer. Therefore, the hydrogen is transacted. This can sometimes lead to a decrease in the reliability of components such as the ZISTA 41. Therefore, Si transients When stacking one layer having a transistor and the other layer having an OS transistor, these It is preferable to provide an insulating layer 81h in between, which has the function of preventing hydrogen diffusion. By 1h, hydrogen is confined to one layer, resulting in transistors 46 and 4 This can improve the reliability of things like 7. Also, it can improve the diffusion of hydrogen from one layer to the other. By suppressing this, the reliability of transistors such as transistor 41 can also be improved.

[0097] The conductive layer 64 and the conductive layer 94 are formed such that they have regions embedded in the insulating layer 81g. The conductive layer 64 is provided so as to fill the openings formed in the insulating layer 81f. It is electrically connected to the gate of transistor 47 via the conductive layer 94 and the insulating layer 8 Through a conductive layer provided to fill the opening formed in 1f, the transistor 47 It is electrically connected to either the source or the drain.

[0098] Transistors 46 and 47 and transistor 41 are on the gates of each other. The surfaces are arranged facing each other. Also, they are in contact with the insulating layer 81e, and microlens array The conductive layer 84 is provided so as not to have an overlapping region with I1540. 84 is located on the light-receiving side of the photoelectric conversion element PD on the single-crystal silicon substrate 500.

[0099] The conductive layer 94 and the conductive layer 84 are electrically connected via the conductor 83. The conductor 83 does not have an area overlapping with the microlens array 1540. The conductor 83 is provided to fill the openings formed in the insulating layers 81a to 81e, the insulating layer 81g, the insulating layer 81h, and the single crystal silicon substrate 50. That is, the conductor 83 is provided outside the area having the pixel 20 and penetrating through the layers 1100 and 1200. By adopting such a configuration, the manufacturing process of the imaging device according to one aspect of the present invention can be simplified. The insulating layer 81e is embedded in the opening provided in the single crystal silicon substrate 500, and the conductor 83 is provided so as to be in contact with the insulating layer 81e. That is, the conductor 83 does not have an area in contact with the single crystal silicon substrate 500. By adopting such a configuration, it is possible to suppress the conduction between the conductor 83 and the photoelectric conversion element PD. The imaging device according to one aspect of the present invention can have the configuration shown in FIG. 9. In the imaging device having such a configuration, the conductor 83 is provided to fill the openings formed in the insulating layer 81f and the single crystal silicon substrate 600. That is, the conductor 83 is provided outside the area having the pixel 20 and penetrating through the layer 1400. In FIGS. 8 and 9, the transistors 46 and 47 are illustrated with a fin-type configuration, but as shown in FIG. 10(A), they may be of a planar type. Alternatively, as shown in FIG. 10(B), it may be a transistor having a channel formation region 660 of a silicon thin film. The channel formation region 660 can be made of polycrystalline silicon or single crystal silicon of SOI (Silicon on Insulator). <*

[0100] Note that an insulating layer 81e is embedded in the opening provided in the single crystal silicon substrate 500, and the conductor 83 is provided so as to be in contact with the insulating layer 81e. That is, the conductor 83 does not have an area in contact with the single crystal silicon substrate 500. By adopting such a configuration, it is possible to suppress the conduction between the conductor 83 and the photoelectric conversion element PD. The imaging device according to one aspect of the present invention can have the configuration shown in FIG. 9. In the imaging device having such a configuration, the conductor 83 is provided to fill the openings formed in the insulating layer 81f and the single crystal silicon substrate 600. That is, the conductor 83 is provided outside the area having the pixel 20 and penetrating through the layer 1400. Note that in FIGS. 8 and 9, the transistors 46 and 47 are illustrated with a fin-type configuration, but as shown in FIG. 10(A), they may be of a planar type. Alternatively, as shown in FIG. 10(B), it may be a transistor having a channel formation region 660 of a silicon thin film. The channel formation region 660 can be made of polycrystalline silicon or single crystal silicon of SOI (Silicon on Insulator).

[0101] The imaging device according to one aspect of the present invention can have the configuration shown in FIG. 9. The imaging device having such a configuration has the conductor 83 provided to fill the openings formed in the insulating layer 81f and the single crystal silicon substrate 600. That is, the conductor 83 is provided outside the area having the pixel 20 and penetrating through the layer 1400. Note that in FIGS. 8 and 9, the transistors 46 and 47 are illustrated with a fin-type configuration, but as shown in FIG. 10(A), they may be of a planar type. Alternatively, as shown in FIG. 10(B), it may be a transistor having a channel formation region 660 of a silicon thin film. The channel formation region 660 can be made of polycrystalline silicon or single crystal silicon of SOI (Silicon on Insulator). [[ID= / / ]] <00*00967>

[0102] Note that in FIGS. 8 and 9, the transistors 46 and 47 are illustrated with a fin-type configuration, but as shown in FIG. 10(A), they may be of a planar type. Alternatively, as shown in FIG. 10(B), it may be a transistor having a channel formation region 660 of a silicon thin film. The channel formation region 660 can be made of polycrystalline silicon or single crystal silicon of SOI (Silicon on Insulator). Note that in FIGS. 8 and 9, the transistors 46 and 47 are illustrated with a fin-type configuration, but as shown in FIG. 10(A), they may be of a planar type. Alternatively, as shown in FIG. 10(B), it may be a transistor having a channel formation region 660 of a silicon thin film. The channel formation region 660 can be made of polycrystalline silicon or single crystal silicon of SOI (Silicon on Insulator). ​​​​​​

[0103] Figure 11(A) is a block diagram of an image sensor 11 according to one embodiment of the present invention. The image sensor 11 is A pixel array 21, a column driver 23, a row driver 24, an analog switch 25, and an electric It has a flow source circuit 26 and terminals 30.

[0104] The pixel array 21 has pixels 20 arranged in a matrix and various wirings. Figure 1 In 1(A), wiring 63(SE) and wiring 91(OUT1) are shown, but other Wiring details have been omitted.

[0105] The column driver 23 and row driver 24 can be configured with a shift register circuit, and are unipolar. It can be constructed using only OS transistors. Also, the analog switch 25 and the electric OS transistors can be used in the current source circuit 26. That is, in layer 1100, A circuit for outputting image data to an external source can also be provided.

[0106] In the configuration shown in Figure 11(A), the output is sent to terminal 30 via wiring 92 (OUT2). The data to be processed is analog data. This analog data needs to be converted to digital data. To do this, the analog data is output to an A / D converter located outside the image sensor 11. do.

[0107] Figure 11(B) is a block diagram showing an example of an A / D converter 12. The terminal 12 has a comparator 28, a counter circuit 29, etc., and multiple bits are connected to the wiring 93. It can output digital data.

[0108] In the comparator 28, the signal potential input from terminal 30 to terminal 31 is compared with the rising or falling of the signal potential. The reference potential (VREF) is swept in the same way as the comparator 28. In response to the output, the counter circuit 29 operates, and a digital signal is output to wiring 93 (OUT3). To be empowered.

[0109] Here, the A / D converter 12 is configured as a CMOS circuit for high-speed operation and power saving. It is preferable to form it using a Si transistor.

[0110] The connection between the image sensor 11 and the A / D converter 12 is, for example, as shown in Figure 11(C): Terminals 30 and 31 can be connected with a wire using a method such as wire bonding.

[0111] Here, we discuss the configuration of a unipolar shift register that can be formed with OS transistors. This will be explained using Figure 12.

[0112] The shift register 700 shown in Figure 12(A) outputs n pulses (where n is a natural number greater than or equal to 2). It has a power circuit 710. In this specification, the first stage pulse output circuit 710 is referred to as "pulse output Circuit 710 _ It may be written as "1", and the nth stage pulse output circuit 710 is referred to as "pulse output circuit It is sometimes written as "710_n". Also, the i-th pulse (where i is a natural number between 1 and n). Output circuit 710 is called "Pulse output circuit 710" _ It is sometimes written as "i". Note that pulse output cycle The terminals and output signal OUT of line 710 may also be described in the same manner as above. For example, if the output signal OUT of the pulse output circuit 710_i is written as "output signal OUT_i" There is.

[0113] Furthermore, the shift register 700 is connected to wiring 705 to which the reset signal RES is supplied, and cross It has wirings 701 to 704 to which a signal is supplied. Wiring 701 has a first cross A clock signal CLK1 is supplied, and a second clock signal CLK2 is supplied to wiring 702. Wiring 703 is supplied with the third clock signal CLK3, and wiring 704 is supplied with the fourth clock signal Signal CLK4 is supplied.

[0114] A clock signal is a signal that changes between high potential and low potential at regular intervals, and the first clock signal The clock signals CLK1 through CLK4 are sequentially delayed by 1 / 4 of a period. In this configuration, the first clock signal CLK1 to the fourth clock signal CLK4 are used, It controls pulse output circuits, etc.

[0115] The pulse output circuit 710 has terminals 711 to 716 (see Figure 12(B)). Terminals 711 and 712 are electrically connected to any of the wires 701 to 704. For example, in Figure 12(A), the pulse output circuit 710_1 has terminal 711. It is electrically connected to wiring 701, and terminal 712 is electrically connected to wiring 702. Furthermore, the pulse output circuit 710_2 has terminal 711 electrically connected to wiring 702, and terminal 7 Terminal 12 is electrically connected to wiring 703. Also, terminal 714 is electrically connected to wiring 705. It is connected.

[0116] A start signal SP is supplied to terminal 713 of the pulse output circuit 710_1, and terminal 716 The output signal OUT_1 is output from there. Also, terminal 71 of the pulse output circuit 710_i 3 is terminal 71 of pulse output circuit 710_i-1 (the i-1 stage pulse output circuit 710). It is electrically connected to 5. Also, terminal 715 of the pulse output circuit 710_i is pulse It is electrically connected to terminal 713 of output circuit 710_i+1. Pulse output circuit 710 The output signal OUT_i is output from terminal 716 of _i. Also, the nth stage pulse output The output signal OUT_n is output from terminal 716 of circuit 710_n.

[0117] Note that the pulse output circuit 710_n does not need to have terminal 715. If 10_n has terminal 715, then terminal 715 (terminal 715_n) is placed in the first stage It may also be electrically connected to terminal 713 (terminal 713_1) of the output circuit 710_1. .

[0118] Next, the configuration of the pulse output circuit 710 will be described (see Figure 12(C)). The power circuit 710 consists of transistors 721, 722, 724 and so on. Transistor 729, transistor 731, transistor 732, capacitive element 733, and It has a capacitive element 734.

[0119] Either the source or drain of transistor 721 is electrically connected to wiring 741, The other end of the drain or gate is electrically connected to node 762, and the gate is electrically connected to terminal 712. They are electrically connected. Either the source or drain of transistor 722 is connected to wire 741. It is electrically connected to and the other end of the source or drain is electrically connected to node 762, The gate is electrically connected to terminal 714. The source or drain of transistor 724. One end of the input is electrically connected to wiring 741, and the other end of the source or drain is connected to node 76. It is electrically connected to terminal 3, and the gate is electrically connected to terminal 713. Transistor 7 Either the source or drain of the 25 is electrically connected to node 763, and the source or drain The other end of the rain is electrically connected to wiring 746, and the gate is electrically connected to node 762. One of the sources or drains of transistor 726 is electrically connected to terminal 711. The source or drain is electrically connected to terminal 715, and the gate is at node It is electrically connected to 761. Either the source or the drain of transistor 727 is Terminal 715 is electrically connected, and the other end of either the source or drain is electrically connected to wiring 746. The gate is then electrically connected to node 762. Source of transistor 728 Alternatively, one of the drains is electrically connected to terminal 711, and the other of the source or drain is The terminal 716 is electrically connected, and the gate is electrically connected to node 761. Either the source or drain of the converter 729 is electrically connected to terminal 716, and the source Alternatively, the other end of the drain is electrically connected to wiring 746, and the gate is electrically connected to node 762. It is connected to node 762. Either the source or drain of transistor 731 is connected to node 762. Electrically connected, the source or drain is electrically connected to wiring 746, and the gate The source or drain of transistor 732 is electrically connected to terminal 713. One end is electrically connected to node 763, and the other end, either source or drain, is connected to node 761. The gate is electrically connected to wiring 741. Capacitive element 733 One electrode is electrically connected to node 762, and the other electrode is electrically connected to wiring 746. It is being done.

[0120] Furthermore, the transistor used for pixel 20 is transistor 41, as shown in Figure 13(A). A circuit configuration with a back gate at or 44 is also possible. Figure 13(A) shows a back gate. This configuration applies a constant potential, allowing the threshold voltage to be controlled.

[0121] The wiring 75 to 78 connected to each back gate is supplied with a different potential individually. It is possible to do so. Alternatively, as shown in Figure 13(B), transistor 41 and transistor The wiring connected to the tailgate of the STA42 may be electrically connected. The wiring connected to the back gates of transistors 43 and 44 is electrically It may be connected electrically.

[0122] In an n-channel transistor, when a potential lower than the source potential is applied to the back gate... The threshold voltage shifts in the positive direction. Conversely, if the back gate is higher than the source potential, When an electric potential is applied, the threshold voltage shifts in the negative direction. Therefore, a predetermined... When controlling the on / off state of each transistor with a set gate voltage, the source voltage is applied to the back gate. Applying a potential lower than the specified value can reduce the off-current. Also, backgain Applying a potential higher than the source potential to the tortoise can reduce the on-current.

[0123] In the circuits shown in Figures 1(B), 4(A), (B), and 13(A), (B), node FD Since high potential holding ability is desired, as mentioned above, transistors 41 and 42 are O It is preferable to use OS transistors with low current. By applying a potential lower than the source potential to the gate, the off-current can be reduced. This is possible. Therefore, the potential holding ability of node FD can be increased.

[0124] Furthermore, as mentioned above, transistors 43 and 44 are transistors with high on-current. It is preferable to have a potential higher than the source potential at the back gates of transistors 43 and 44. By applying this, the on-current can be increased. Therefore, wiring 91(O The readout potential output to UT1) can be quickly determined, i.e., high frequency It can be operated by wavenumber.

[0125] Furthermore, as shown in Figure 13(C), transistor 44 has the same potential as the front gate. It may also be a configuration applied to the gate.

[0126] Furthermore, within the imaging device, in addition to the power supply potentials, the signal potential and the potential applied to the back gate are also considered. Multiple potentials are used, such as a specific potential. When multiple potentials are supplied from outside the imaging device, the number of terminals... Because factors such as these increase, the imaging device has a power supply circuit that generates multiple potentials inside. It is preferable.

[0127] The operation of the pixel circuit shown in Figure 13(A) will be explained using the timing chart shown in Figure 14. In a timing chart, "V1" is a potential higher than the reference potential, for example, high This can be the power supply potential (VDD). "V0" is the reference potential, i.e., the source potential. For example, it can be 0V, GND potential, or low power supply potential (VSS).

[0128] First, at time T1, the potential of wiring 62 (RS) and wiring 61 (TX) is set to "V1". Then, transistors 41 and 42 conduct, and node FD reaches the reset potential (e.g., VDD). It is reset (reset operation). At this time, wires 75 and 76 are connected to “V0”. By setting a high potential (>"V0"), the on-current of transistors 41 and 42 is increased. A reset operation can be performed quickly.

[0129] If the potential of wiring 62(RS) is set to "V0" at time T2, then transistor 42 becomes non-conductive. Then, the reset operation is completed and the storage operation begins. At this time, wire 76 is connected to “V0”. By setting a low potential, the off-current of transistor 42 can be reduced, and the leakage current... This prevents the supply of charge to node FD. Note that at time T2, The potential of line 75 may be defined as "V0".

[0130] If the potential of wiring 61 (TX) is set to "V0" at time T3, then transistor 41 will be non-conductive. Then, the potential of node FD is determined and held (holding operation). At this time, wiring 75 is set to “V0 By setting a lower potential (<"V0"), the off-current of transistor 41 is reduced. This allows for the prevention of charge outflow from the node FD due to leakage current.

[0131] If the potential of wiring 63(SE) at time T4 is set to "V1", then transistor 44 will conduct, The potential of wiring 91 (OUT1) changes according to the current flowing through transistor 43 (readout). Operation). At this time, wires 77 and 78 are set to a potential higher than "V0" (> "V0"). This increases the on-current of transistors 43 and 44, allowing for quick connection of the wiring 91 (OUT1 The potential of ) can be determined.

[0132] If the potential of wiring 63(SE) is set to "V0" at time T5, then transistor 44 will be non-conductive. The read operation is then completed. Note that the potential of node FD remains constant until the read operation is finished. To prevent changes, keep the potential of wires 75 and 76 at a potential lower than "V0" (<"V0"). It is preferable to do so. In the above description, wiring 76 is done at the same timing as wiring 75. The potential may be changed.

[0133] As a result, a signal corresponding to the potential of node FD can be read out. (See Figure 1(B)) The pixel 20 shown is controlled by omitting the control of wiring 75 to 78 in the timing chart shown in Figure 14. Simply run it. Pixel 20 shown in Figure 13(B) corresponds to the timing chart shown in Figure 14. You can operate it by omitting the control of wiring 76 and 78.

[0134] Furthermore, a pixel circuit according to one aspect of the present invention has multiple pixels as shown in Figures 15(A) and (B). A configuration that shares the transistors is also acceptable.

[0135] In the transistor-shared pixel shown in Figure 15(A), pixels 20h to 20k are each photoelectric It has a conversion element PD and a transistor 41 separately, and transistors 42, 43, 44 and The configuration shares a capacitance element C1. The transistors in pixels 20h to 20k... Each of the 41 is controlled by wiring 61h to 61k. In this configuration, each pixel It can sequentially perform reset, storage, hold, and read operations, mainly for low-power storage. It is suitable for imaging using a long-shutter method.

[0136] In the transistor-shared pixel shown in Figure 15(B), pixels 20h to 20k are each photoelectric It has a conversion element PD and transistors 41, 45 individually, and transistors 42, 43, 4 This configuration shares 4 and the capacitive element C1. It operates based on the potential of wiring 65 (GPD). A transistor 45, which controls the function, is provided between the photoelectric conversion element PD and the wiring 71 (VPD). This allows the potential to be maintained at the cathode of the photoelectric conversion element PD. Therefore, all Simultaneously, reset, storage, and hold operations are performed sequentially for each pixel, followed by a read operation for each pixel. It is suitable for imaging using a global shutter method.

[0137] The pixel circuits shown in Figures 15(A) and (B) are in the direction in which the wiring 91 (OUT1) extends (hereinafter, Multiple pixels (pixels 20h, 20i, 20j, 20k) arranged vertically form a transistor The configuration shows a shared wiring, but in the direction in which wiring 63(SE) extends (hereinafter referred to as the horizontal direction) A configuration in which multiple pixels arranged in a row share a transistor is also possible. Alternatively, in the horizontal and vertical directions. It may also be a configuration in which multiple pixels arranged in a row share a transistor.

[0138] Furthermore, the number of pixels sharing a transistor is not limited to 4 pixels; it can be 2, 3, or 5 pixels. That's fine too.

[0139] In Figures 15(A) and (B), wiring 72(VRS) and wiring 73(V) are shown in Figure 1(B). The configuration shows the integration of PI) and the omission of wiring 72 (VRS), but wiring 72 (VRS) ) may also be configured to have a configuration having a wiring 73 (VPI The example shown involves connecting to ), but it may also be connected to wiring 71 (VPD).

[0140] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is the case.

[0141] (Embodiment 2) In this embodiment, the OS transistor that can be used in one aspect of the present invention is shown in the drawings. This will be explained using [the following]. Note that in the drawings of this embodiment, some elements are [the following] for clarity. The illustrations are enlarged, reduced, or abbreviated.

[0142] Figures 16(A) and (B) show a top view and a cross-sectional view of a transistor 101 according to one embodiment of the present invention. Yes. Figure 16(A) is a top view, and the cross section is in the direction of the dashed line B1-B2 shown in Figure 16(A). This corresponds to Figure 16(B). Also, the cross section in the direction of the dashed line B3-B4 shown in Figure 16(A) is This corresponds to Figure 18(A). Also, the direction of the dashed line B1-B2 is the channel length direction, and the dashed line B The 3-B4 direction is referred to as the channel width direction.

[0143] The transistor 101 has an insulating layer 120 that is in contact with the substrate 119, and an oxide layer that is in contact with the insulating layer 120. A monocrystalline semiconductor layer 130, a conductive layer 140 that is electrically connected to the oxide semiconductor layer 130, and a conductive Layer 150, oxide semiconductor layer 130, conductive layer 140, and insulating layer 1 in contact with conductive layer 150 60, conductive layer 170 in contact with insulating layer 160, conductive layer 140, conductive layer 150, insulating layer 1 60 and an insulating layer 175 in contact with the conductive layer 170, and an insulating layer 180 in contact with the insulating layer 175 , and also, if necessary, the insulating layer 180 may be given the function of a planarizing film. .

[0144] The conductive layer 140 is the source electrode layer, the conductive layer 150 is the drain electrode layer, and the insulating layer 160 is the gate insulating layer. The edge film and the conductive layer 170 can each function as gate electrode layers.

[0145] In Figure 16(B), region 231 is the source region, region 232 is the drain region, and region 233 is It can function as a channel-forming region. Regions 231 and 232 are conductive layer 1 40 and conductive layer 150 are in contact with each other, and conductive layer 140 and conductive layer 150 are Using a conductive material that readily bonds with oxygen will reduce the resistance of regions 231 and 232. It is possible.

[0146] Specifically, the oxide semiconductor layer 130 and the conductive layer 140 and conductive layer 150 come into contact with each other. Oxygen vacancies occur within the oxide semiconductor layer 130, and these oxygen vacancies remain within the oxide semiconductor layer 130. Due to interactions with hydrogen that is either distilled or diffused from the outside, regions 231 and 232 have low resistance. It becomes an n-type resistance.

[0147] Furthermore, the "source" and "drain" functions of a transistor are related to transistors with different polarities. When adopting a circuit, or when the direction of current changes during circuit operation, the configuration may be reversed. Therefore, in this specification, the terms "source" and "drain" are interchangeable. It may be used in this manner. Also, "electrode layer" can be replaced with "wiring." can.

[0148] The diagram shows an example where the conductive layer 170 is formed by two layers: conductive layer 171 and conductive layer 172. However, it may be a single layer or a stack of three or more layers. This configuration is similar to the other configurations described in this embodiment. It can also be applied to transistors.

[0149] The diagram shows examples where conductive layers 140 and 150 are formed as single layers, but two or more layers are also shown. It may also be a layer. This configuration can be applied to other transistors described in this embodiment. .

[0150] The insulating layer 175 primarily suppresses the diffusion of external impurities to the oxide semiconductor layer 130. It acts as a blocking layer, but by selecting the appropriate material, oxidation of the conductive layer 170 can be prevented. Furthermore, it also functions as a hydrogen source that reduces the resistance of a portion of the oxide semiconductor layer 130.

[0151] A transistor according to one aspect of the present invention may have the configuration shown in Figures 16(C) and (D). Figure 16(C) is a top view of transistor 102, and the dashed line C1-C shown in Figure 16(C) The cross-sections in two directions correspond to Figure 16(D). Also, the dashed line C3-C4 shown in Figure 16(C) The cross-section in the direction corresponds to Figure 18(B). Also, the direction of the dashed line C1-C2 is the length of the channel. The direction of the dashed line C3-C4 is referred to as the channel width direction.

[0152] The transistor 102 has an insulating layer 160 that acts as a gate insulating film and a gate electrode layer. Except for the fact that it does not coincide with the edge of the conductive layer 170 which acts as a transistor, it is the same as transistor 101. It has the following configuration. The structure of transistor 102 is such that conductive layer 140 and conductive layer 150 are insulated Because it is broadly covered by the edge layer 160, the conductive layer 140 and conductive layer 150 and conductive layer 170 It has the characteristic of high resistance between the terminals and low gate leakage current.

[0153] Transistors 101 and 102 have conductive layers 170 and 140 and This is a top gate structure having a region where the electrochemical layer 150 overlaps. The width is preferably 3 nm or more and less than 300 nm in order to reduce parasitic capacity. In this configuration, since no offset region is formed in the oxide semiconductor layer 130, the on-current is high It is easy to form transistors.

[0154] A transistor according to one aspect of the present invention may have the configuration shown in Figures 16(E) and (F). Figure 16(E) is a top view of transistor 103, and the dashed line D1-D shown in Figure 16(E) The cross-sections in two directions correspond to Figure 16(F). Also, the dashed line D3-D4 shown in Figure 16(E) The cross-section in the direction corresponds to Figure 18(A). Also, the direction of the dashed line D1-D2 is the length of the channel. The direction indicated by the dashed line D3-D4 is referred to as the channel width direction.

[0155] Transistor 103 has an insulating layer 120 in contact with the substrate 119 and an oxide layer in contact with the insulating layer 120. A material semiconductor layer 130, an insulating layer 160 in contact with the oxide semiconductor layer 130, and an insulating layer 160 in contact with The conductive layer 170, the oxide semiconductor layer 130, the insulating layer 160, and the insulating layer covering the conductive layer 170 are all connected. Edge layer 175, insulating layer 180 in contact with insulating layer 175, insulating layer 175 and insulating layer 180 A conductive layer 140 is electrically connected to the oxide semiconductor layer 130 through an opening provided therein. It also has a conductive layer 150. Furthermore, an insulating layer 180, a conductive layer 140, and a conductive layer may be added as needed. It may have an insulating layer (planarized film) in contact with 150.

[0156] The conductive layer 140 is the source electrode layer, the conductive layer 150 is the drain electrode layer, and the insulating layer 160 is the gate insulating layer. The edge film and the conductive layer 170 can each function as gate electrode layers.

[0157] In Figure 16(F), region 231 is the source region, region 232 is the drain region, and region 233 is It can function as a channel-forming region. Regions 231 and 232 are insulating layer 1 It is in contact with 75, and if, for example, an insulating material containing hydrogen is used as the insulating layer 175, then region 231 Furthermore, the resistance of region 232 can be reduced.

[0158] Specifically, the process up to forming the insulating layer 175 generates in regions 231 and 232 The interaction between the oxygen deficiency and the hydrogen diffusing from the insulating layer 175 to regions 231 and 232 As a result of this action, regions 231 and 232 become low-resistance n-type. Note that this is an insulating material containing hydrogen. Materials such as silicon nitride and aluminum nitride can be used.

[0159] A transistor according to one aspect of the present invention may have the configuration shown in Figures 17(A) and (B). Figure 17(A) is a top view of transistor 104, and the dashed line E1-E shown in Figure 17(A) The cross-sections in two directions correspond to Figure 17(B). Also, the dashed line E3-E4 shown in Figure 17(A) The cross-section in the direction corresponds to Figure 18(A). Also, the direction of the dashed line E1-E2 is the length of the channel. The direction indicated by the dashed line E3-E4 is referred to as the channel width direction.

[0160] Transistor 104 has conductive layers 140 and 150 at the edges of oxide semiconductor layer 130. Except for the fact that it is in contact with the other element in a way that covers it, it has the same configuration as transistor 103.

[0161] Regions 331 and 334 shown in Figure 17(B) are the source region, region 332 and region 3 Region 35 can function as a drain region, and region 333 can function as a channel-forming region.

[0162] Regions 331 and 332 correspond to regions 231 and 23 in transistor 101. Similar to method 2, the resistance can be reduced.

[0163] Regions 334 and 335 correspond to regions 231 and 23 in transistor 103. Similar to 2, the resistance can be reduced. Note that region 334 and in the channel length direction When the length of region 335 is 100 nm or less, preferably 50 nm or less, the gate electric field The ON current does not decrease significantly due to the contribution. Therefore, the low of regions 334 and 335 Resistance training may not always be performed.

[0164] Transistors 103 and 104 have conductive layers 170 and 140 and It is a self-aligned structure in which the electrolytic layer 150 does not have any overlapping regions. The lampistor has extremely low parasitic capacitance between the gate electrode layer and the source and drain electrode layers. Therefore, it is suitable for high-speed operation applications.

[0165] A transistor according to one aspect of the present invention may have the configuration shown in Figures 17(C) and (D). Figure 17(C) is a top view of transistor 105, and the dashed line F1-F shown in Figure 17(C) The cross-sections in two directions correspond to Figure 17(D). Also, the dashed line F3-F4 shown in Figure 17(C) The cross-section in the direction corresponds to Figure 18(A). Also, the dashed line F1-F2 direction is the length of the channel. The direction indicated by the dashed line F3-F4 is referred to as the channel width direction.

[0166] Transistor 105 has an insulating layer 120 in contact with the substrate 119 and an oxide layer in contact with the insulating layer 120. A monocrystalline semiconductor layer 130, a conductive layer 141 that is electrically connected to the oxide semiconductor layer 130, and a conductive Layer 151, oxide semiconductor layer 130, conductive layer 141, insulating layer 160 in contact with conductive layer 151 And, a conductive layer 170 in contact with the insulating layer 160, an oxide semiconductor layer 130, a conductive layer 141, and a conductive layer. An insulating layer 175 that is in contact with layer 151, insulating layer 160 and conductive layer 170, and an insulating layer 175 that is in contact with The insulating layer 180 and the insulating layer 175 and the insulating layer 180 are conductive through openings provided in them. Conductive layers 142 and 15 are electrically connected to layer 141 and conductive layer 151, respectively. It has 2. It also comes into contact with the insulating layer 180, the conductive layer 142 and the conductive layer 152 as needed. It may have an insulating layer or the like.

[0167] The conductive layer 141 and the conductive layer 151 are in contact with the upper surface of the oxide semiconductor layer 130 and the side surface. It has no such configuration.

[0168] The transistor 105 has conductive layers 141 and 151, and insulating layers 175 and The insulating layer 180 has an opening, and the conductive layer 14 is accessible through the opening. It has conductive layers 142 and 152 that are electrically connected to conductive layer 151 and conductive layer 151, respectively. It has the same configuration as transistor 101, except for the following point. Conductive layer 140 (conductive layer 141 The conductive layer 142) can be used as a source electrode layer, and the conductive layer 150 (conductive Layer 151 and conductive layer 152 can be used as drain electrode layers.

[0169] A transistor according to one aspect of the present invention may have the configuration shown in Figures 17(E) and (F). Figure 17(E) is a top view of transistor 106, and the dashed line G1-G shown in Figure 17(E) The cross-sections in two directions correspond to Figure 17(F). Also, the dashed line G3-G4 shown in Figure 17(E) The cross-section in the direction corresponds to Figure 18(A). Also, the dashed line G1-G2 direction is the length of the channel. The direction of the dashed line G3-G4 is referred to as the channel width direction.

[0170] Transistor 106 has an insulating layer 120 in contact with the substrate 119 and an oxide layer in contact with the insulating layer 120. A monocrystalline semiconductor layer 130, a conductive layer 141 that is electrically connected to the oxide semiconductor layer 130, and a conductive Layer 151, an insulating layer 160 in contact with the oxide semiconductor layer 130, and a conductive layer in contact with the insulating layer 160. Layer 170, insulating layer 120, oxide semiconductor layer 130, conductive layer 141, conductive layer 151, insulating An insulating layer 175 in contact with layer 160, conductive layer 170, and an insulating layer 180 in contact with insulating layer 175. Through openings provided in the insulating layer 175 and the insulating layer 180, the conductive layer 141 and the conductive It has conductive layers 142 and 152 that are electrically connected to layer 151, respectively. If necessary, an insulating layer (planarized film) in contact with the insulating layer 180, conductive layer 142, and conductive layer 152. They may also have, etc.

[0171] The conductive layer 141 and the conductive layer 151 are in contact with the upper surface of the oxide semiconductor layer 130 and the side surface. It has no such configuration.

[0172] Transistor 106 has conductive layers 141 and 151, except that the transistor It has the same configuration as Ta 103. The conductive layer 140 (conductive layer 141 and conductive layer 142) is - It can be used as an electrode layer, conductive layer 150 (conductive layer 151 and conductive layer 15 2) can be used as a drain electrode layer.

[0173] In the configuration of transistors 105 and 106, conductive layer 140 and conductive layer 1 Since 50 is not in contact with the insulating layer 120, oxygen in the insulating layer 120 enters the conductive layer 140. Furthermore, it becomes less likely for the conductive layer 150 to absorb acid, and acid from the insulating layer 120 into the oxide semiconductor layer 130 This makes it easier to supply raw materials.

[0174] Regions 231 and 232 in transistor 103, transistor 104 and Regions 334 and 335 in the lampistor 106 form oxygen vacancies and improve conductivity. Impurities may be added to enhance the properties. These impurities may form oxygen vacancies in the oxide semiconductor layer. For example, phosphorus, arsenic, antimony, boron, aluminum, silicon, nitrogen, helical Um, neon, argon, krypton, xenon, indium, fluorine, chlorine, titanium, One or more elements selected from zinc and carbon may be used. Methods of adding include plasma treatment, ion implantation, ion doping, and plasma treatment. Methods such as Merjohn ion implantation can be used.

[0175] When the above elements are added to the oxide semiconductor layer as impurity elements, the metal in the oxide semiconductor layer The bonds between elements and oxygen are broken, and an oxygen vacancy is formed. Due to the interaction between elementary defects and hydrogen remaining in or later added in the oxide semiconductor layer, The conductivity of the semiconductor layer can be increased.

[0176] When hydrogen is added to an oxide semiconductor in which oxygen vacancies have been formed by the addition of impurity elements, oxygen vacancies are formed. Hydrogen enters the loss site and a donor level is formed near the conduction band. As a result, the oxide conductor It can be formed. Here, an oxide semiconductor that has been made conductive is called an oxide conductor. Furthermore, oxide conductors, like oxide semiconductors, are translucent.

[0177] Oxide conductors are degenerate semiconductors in which the conduction band edge and the Fermi level coincide or nearly coincide. It is presumed that there is an oxide conductor layer, a source electrode layer and a drain electrode layer. The contact with the conductive layer that functions is ohmic contact, and the oxide conductive layer and the source electrode layer This reduces the contact resistance with the conductive layer that functions as the drain electrode layer.

[0178] A transistor according to one aspect of the present invention is shown in Figure 19(A), (B), (C), (D), (E), ( F) shows a cross-sectional view in the length direction of the channel, and 18(C) and (D) shows a cross-sectional view in the width direction of the channel. As shown in the cross-sectional view, a conductive layer 173 is provided between the oxide semiconductor layer 130 and the substrate 119. It is also possible to use the conductive layer as a second gate electrode layer (back gate). It is possible to increase the current and control the threshold voltage. (See Figures 19(A) and (B)) In the cross-sectional views shown in (C), (D), (E), and (F), the width of the conductive layer 173 is the oxide semiconductor. The width of the conductive layer 173 may be shorter than the width of the conductive layer 170. It can also be shortened.

[0179] To increase the ON current, for example, the conductive layer 170 and conductive layer 173 are set to the same potential, double It can be driven as a gate transistor. Also, to control the threshold voltage, A constant potential different from that of the conductive layer 170 should be supplied to the conductive layer 173. To make 73 at the same potential, for example, as shown in Figure 18(D), conductive layer 170 and conductive layer 1 73 can be electrically connected via the contact hole.

[0180] In transistors 101 to 106 in Figures 16 and 17, the oxide semiconductor Although an example where the conductive layer 130 is a single layer is shown, the oxide semiconductor layer 130 may be a stacked layer. The oxide semiconductor layer 130 of transistors 101 to 106 is shown in Figure 20(B). It can be replaced with the oxide semiconductor layer 130 shown in (C) or Figure 20(D), (E). Cut.

[0181] Figure 20(A) is a top view of the oxide semiconductor layer 130, and Figures 20(B) and (C) show the two-layer structure. This is a cross-sectional view of the oxide semiconductor layer 130, which is constructed in three layers. Figures 20(D) and (E) show the three-layer structure. This is a cross-sectional view of the oxide semiconductor layer 130.

[0182] In oxide semiconductor layer 130a, oxide semiconductor layer 130b, and oxide semiconductor layer 130c, Oxide semiconductor layers with different compositions can be used.

[0183] A transistor according to one aspect of the present invention may have the configuration shown in Figures 21(A) and (B). Figure 21(A) is a top view of transistor 107, and the dashed line H1-H shown in Figure 21(A) The cross-section in two directions corresponds to Figure 21(B). Also, the dashed line H3-H4 shown in Figure 21(A) The cross-section in that direction corresponds to Figure 23(A). Also, the dashed line H1-H2 direction is the channel length direction. The direction of the dashed line H3-H4 is referred to as the channel width direction.

[0184] Transistor 107 has an insulating layer 120 that is in contact with the substrate 119, and an oxide layer that is in contact with the insulating layer 120. A stack consisting of a monocrystalline semiconductor layer 130a and an oxide semiconductor layer 130b, and electrically connected to the stack Connecting conductive layer 140 and conductive layer 150, and the laminate, conductive layer 140 and conductive layer 15 The oxide semiconductor layer 130c in contact with 0, and the insulating layer 160 in contact with the oxide semiconductor layer 130c , conductive layer 170 in contact with insulating layer 160, conductive layer 140, conductive layer 150, oxide semiconductor layer 130c, an insulating layer 175 in contact with the insulating layer 160 and the conductive layer 170, and an insulating layer 175 in contact with It has an insulating layer 180 and, if necessary, a planarizing film as a functional You may add the ability.

[0185] In transistor 107, the oxide semiconductor layer 130 is divided into two regions 231 and 232. In region 233, where the layers are oxide semiconductor layer 130a and oxide semiconductor layer 130b The oxide semiconductor layer 130 consists of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide The point is that it is a semiconductor layer 130c), and conductive layer 140 and conductive layer 150 and insulating layer 160 Except for the fact that a portion of the oxide semiconductor layer (oxide semiconductor layer 130c) is interposed between them, It has the same configuration as the Ranjista 101.

[0186] A transistor according to one aspect of the present invention may have the configuration shown in Figures 21(C) and (D). Figure 21(C) is a top view of transistor 108, and the dashed line I1-I shown in Figure 21(C) The cross-sections in two directions correspond to Figure 21(D). Also, the dashed line I3-I4 shown in Figure 21(C) The cross-section in that direction corresponds to Figure 23(B). Also, the dashed line I1-I2 direction is the channel length direction. The direction from the dashed line I3 to I4 is referred to as the channel width direction.

[0187] The transistor 108 has an insulating layer 160 and an oxide semiconductor layer 130c, with the edges connected to the conductive layer 17. It differs from transistor 107 in that its terminals do not coincide with the zero point.

[0188] A transistor according to one aspect of the present invention may have the configuration shown in Figures 21(E) and (F). Figure 21(E) is a top view of transistor 109, and the dashed line J1-J shown in Figure 21(E) The cross-section in two directions corresponds to Figure 21(F). Also, the dashed line J3-J4 shown in Figure 21(E) The cross-section in that direction corresponds to Figure 23(A). Also, the dashed line J1-J2 direction is the channel length direction. The direction from the dashed line J3 to J4 is referred to as the channel width direction.

[0189] The transistor 109 has an insulating layer 120 that is in contact with the substrate 119, and an oxide layer that is in contact with the insulating layer 120. A stack consisting of a monocrystalline semiconductor layer 130a and an oxide semiconductor layer 130b, and an acid in contact with the stack. A oxide semiconductor layer 130c, an insulating layer 160 in contact with the oxide semiconductor layer 130c, and an insulating layer 16 A conductive layer 170 in contact with 0, the laminate, oxide semiconductor layer 130c, insulating layer 160 and conductive An insulating layer 175 covering the electrical layer 170, an insulating layer 180 in contact with the insulating layer 175, and the insulating layer 175 and conductive layer 14 which is electrically connected to the laminate through an opening provided in the insulating layer 180. It has a conductive layer 150 and an insulating layer 180, conductive layer 140 and as needed. The conductive layer 150 may have an insulating layer (planarized film) or the like in contact with it.

[0190] In transistor 109, the oxide semiconductor layer 130 is divided into two regions 231 and 232. In region 233, where the layers are oxide semiconductor layer 130a and oxide semiconductor layer 130b The oxide semiconductor layer 130 consists of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide It has the same configuration as transistor 103, except that it is a physical semiconductor layer 130c.

[0191] A transistor according to one aspect of the present invention may have the configuration shown in Figures 22(A) and (B). Figure 22(A) is a top view of transistor 110, and the dashed line K1-K shown in Figure 22(A) The cross-sections in two directions correspond to Figure 22(B). Also, the dashed line K3-K4 shown in Figure 22(A) The cross-section in that direction corresponds to Figure 23(A). Also, the dashed line K1-K2 direction is the channel length direction. The direction of the dashed line K3-K4 is referred to as the channel width direction.

[0192] In transistor 110, the oxide semiconductor layer 130 is divided into two regions 331 and 332. In region 333, where the layers are oxide semiconductor layer 130a and oxide semiconductor layer 130b The oxide semiconductor layer 130 consists of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide It has the same configuration as transistor 104, except that it is a solid semiconductor layer (130c).

[0193] A transistor according to one aspect of the present invention may have the configuration shown in Figures 22(C) and (D). Figure 22(C) is a top view of transistor 111, and the dashed line L1-L shown in Figure 22(C) The cross-section in two directions corresponds to Figure 22(D). Also, the dashed line L3-L4 shown in Figure 22(C) The cross-section in that direction corresponds to Figure 23(A). Also, the direction of the dashed line L1-L2 is the channel length direction. The direction of the dashed line L3-L4 is referred to as the channel width direction.

[0194] The transistor 111 has an insulating layer 120 in contact with the substrate 119 and an oxide layer in contact with the insulating layer 120. A stack consisting of a monocrystalline semiconductor layer 130a and an oxide semiconductor layer 130b, and electrically connected to the stack Connecting conductive layers 141 and 151, and the laminate, conductive layer 141 and conductive layer 15 A 1 oxide semiconductor layer 130c in contact with 1, and an insulating layer 160 in contact with the oxide semiconductor layer 130c. , conductive layer 170 in contact with insulating layer 160, said lamination, conductive layer 141, conductive layer 151, oxidation A semiconductor layer 130c, an insulating layer 160, and an insulating layer 175 in contact with the conductive layer 170, and an insulating layer The insulating layer 180 is in contact with 175, and the openings provided in the insulating layer 175 and the insulating layer 180 Conductive layers 142 and 151 are electrically connected through conductive layer 141 and conductive layer 151, respectively. It has a conductive layer 152. Additionally, an insulating layer 180, a conductive layer 142, and a conductive layer 1 may be provided as needed. It may have an insulating layer (planarized film) or the like in contact with 52.

[0195] In transistor 111, the oxide semiconductor layer 130 is divided into two regions 231 and 232. In region 233, where the layers are oxide semiconductor layer 130a and oxide semiconductor layer 130b The oxide semiconductor layer 130 consists of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide The fact that it is a semiconductor layer 130c), and that it is a conductive layer 141 and a conductive layer 151 and an insulating layer 16 Except for the fact that a portion of the oxide semiconductor layer (oxide semiconductor layer 130c) is interposed between it and 0, It has the same configuration as transistor 105.

[0196] A transistor according to one aspect of the present invention may have the configuration shown in Figures 22(E) and (F). Figure 22(E) is a top view of transistor 112, and the dashed line M1-M shown in Figure 22(E) The cross-sections in two directions correspond to Figure 22(F). Also, the dashed line M3-M4 shown in Figure 22(E) The cross-section in that direction corresponds to Figure 23(A). Also, the dashed line M1-M2 direction is the channel length direction. The direction of the dashed line M3-M4 is referred to as the channel width direction.

[0197] Transistor 112 is located in regions 331, 332, 334, and 335. The oxide semiconductor layer 130 consists of two layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b). At point 333, the oxide semiconductor layer 130 is made up of three layers (oxide semiconductor layer 130a, oxide Except for the fact that it is a monocrystalline semiconductor layer 130b and an oxide semiconductor layer 130c, transistor 106 and They have a similar configuration.

[0198] A transistor according to one aspect of the present invention is shown in Figures 24(A), (B), (C), (D), (E), ( F) shows a cross-sectional view in the channel length direction, and Figures 23(C) and (D) show the channel width direction. As shown in the cross-sectional view, a conductive layer 173 is provided between the oxide semiconductor layer 130 and the substrate 119. It may be used as a second gate electrode layer (back gate). This allows for an increase in on-current and control of the threshold voltage. Note that, as shown in Figure 24(A), In the cross-sectional views shown in (B), (C), (D), (E), and (F), the width of the conductive layer 173 is acid The width of the conductive layer 173 may be shorter than that of the conductive layer 170. It can be made shorter than the width.

[0199] A transistor according to one aspect of the present invention has the configuration shown in Figures 25(A), (B), and (C). It is also possible. Figure 25(A) is a top view, and Figure 25(B) is a dashed line shown in Figure 25(A). This is a cross-sectional view corresponding to N1-N2, and Figure 25(C) shows the dashed line N3 shown in Figure 25(A). This is a cross-sectional view corresponding to -N4. Note that in the top view of Figure 25(A), for clarity of the diagram... Some elements have been omitted from the illustration.

[0200] The transistor 113 has an oxide semiconductor layer 130c and an insulating layer 160 connected to the conductive layer 141. It has the same configuration as the transistor 111, except that it covers the conductive layer 151. With this configuration, the oxide semiconductor layer 130c acts as a blocking layer, providing insulation. From layer 175, impurities such as hydrogen, water, and halogens diffuse into the oxide semiconductor layer 130b. This can be suppressed. Note that the configuration of transistor 113 is as described in one aspect of the present invention. This can also be applied to transistors with that configuration.

[0201] Furthermore, as shown in the cross-sectional views in Figures 25(D) and (E), the oxide semiconductor layer 130 and the substrate 119 It is equipped with a conductive layer 173 that functions as a second gate electrode layer (back gate) between them. That's good too.

[0202] A transistor according to one aspect of the present invention has the configuration shown in Figures 26(A), (B), and (C). It is also possible. Figure 26(A) is a top view, and Figure 26(B) is a dashed line shown in Figure 26(A). This is a cross-sectional view corresponding to O1-O2, and Figure 26(C) shows the dashed line O3 shown in Figure 26(A). -This is a cross-sectional view corresponding to O4. Note that in the top view of Figure 26(A), for clarity of the diagram... Some elements have been omitted from the illustration.

[0203] Transistor 114 consists of an oxide semiconductor layer 130a, an oxide semiconductor layer 130b, and a conductive layer 14 Except for the fact that the side surface of the conductive layer 151 is not in contact with the insulating layer 175, transistor 1 It has the same configuration as 11. That is, oxide semiconductor layer 130a, oxide semiconductor layer 130b The sides of the conductive layer 141 and the conductive layer 151 are in contact with the insulating layer 180.

[0204] By adopting this configuration, the antioxidant effect of the insulating layer 175 on the conductive layer 170 is maintained while This allows for efficient supply of oxygen from the insulating layer 180 to the oxide semiconductor layer 130b. .

[0205] Furthermore, as shown in the cross-sectional views in Figures 26(D) and (E), the oxide semiconductor layer 130 and the substrate 119 It is equipped with a conductive layer 173 that functions as a second gate electrode layer (back gate) between them. That's good too.

[0206] A transistor according to one aspect of the present invention has the configuration shown in Figures 27(A), (B), and (C). It is also possible. Figure 27(A) is a top view, and Figure 27(B) is a dashed line shown in Figure 27(A). This is a cross-sectional view corresponding to P1-P2, and Figure 27(C) shows the dashed line P3 shown in Figure 27(A). -This is a cross-sectional view corresponding to P4. Note that in the top view of Figure 27(A), for clarity of the diagram... Some elements have been omitted from the illustration.

[0207] The transistor 115 shown in Figures 27(A), (B), and (C) is connected to substrate 119, and substrate 119 The upper insulating layer 120 and the oxide semiconductor layer 130 (oxide semiconductor layer 130a) on the insulating layer 120 (Oxide semiconductor layer 130b, oxide semiconductor layer 130c), and in contact with oxide semiconductor layer 130 , conductive layers 140 and 150 arranged at intervals, and oxide semiconductor layer 130c It has an insulating layer 160 in contact with the insulating layer 160 and a conductive layer 170 in contact with the insulating layer 160. The conductive layer 130c, insulating layer 160, and conductive layer 170 are located on the insulating layer 1 of the transistor 115. Openings that reach oxide semiconductor layer 130a and oxide semiconductor layer 130b provided in 90 It is provided in [location]. Furthermore, the insulating layer 190 can be made of the same material as the insulating layer 180, for example. It is possible.

[0208] The configuration of transistor 115 is, compared to the configurations of the other transistors mentioned above, source Alternatively, because the overlapping region between the drain conductor and the gate electrode conductor is small, parasitic The capacitance can be reduced. Therefore, transistor 115 does not require high-speed operation. It is suitable as an element of the circuit. The top surface of transistor 115 is as shown in Figure 27(B). Using methods such as CMP (Chemical Mechanical Polishing) for sea urchins It is preferable to flatten the surface, but a configuration that does not flatten the surface is also possible.

[0209] Furthermore, as shown in the cross-sectional views in Figures 27(D) and (E), the oxide semiconductor layer 130 and the substrate 119 It is equipped with a conductive layer 173 that functions as a second gate electrode layer (back gate) between them. That's good too.

[0210] A transistor according to one aspect of the present invention has the configuration shown in Figures 28(A), (B), and (C). It is also possible. Figure 28(A) is a top view, and Figure 28(B) is a dashed line shown in Figure 28(A). This is a cross-sectional view corresponding to Q1-Q2, and Figure 28(C) shows the dashed line Q3 shown in Figure 28(A). -This is a cross-sectional view corresponding to Q4. Note that in the top view of Figure 28(A), for clarity of the diagram... Some elements have been omitted from the illustration.

[0211] Transistor 116 consists of an insulating layer 120, an oxide semiconductor layer 130a, and an oxide semiconductor layer 130 b. Oxide semiconductor layer 130c, conductive layer 140 and conductive layer 150 are in contact with the oxide semiconductor layer 130c and conductive layer 140. A conductive layer 130d is formed and in contact with the oxide semiconductor layer 130c and the oxide semiconductor layer 130d. Except for the fact that an insulating layer 190 is formed in such a way, the configuration is the same as that of the transistor 115. It has. For example, the oxide semiconductor layer 130d is made of the same material as the oxide semiconductor layer 130c. This can be used. With this configuration, the oxide semiconductor layer 130d blocks Acting as a layer, impurities such as hydrogen, water, and halogens are released from the insulating layer 190 into the oxide semiconductor layer. This can suppress the diffusion to 130b.

[0212] Furthermore, as shown in the cross-sectional views in Figures 28(D) and (E), the oxide semiconductor layer 130 and the substrate 119 It is equipped with a conductive layer 173 that functions as a second gate electrode layer (back gate) between them. That's good too.

[0213] A transistor according to one aspect of the present invention has the configuration shown in Figures 29(A), (B), and (C). It is also possible. Figure 29(A) is a top view, and Figure 29(B) is a dashed line shown in Figure 29(A). This is a cross-sectional view corresponding to R1-R2, and Figure 29(C) shows the dashed line R3 shown in Figure 29(A). -This is a cross-sectional view corresponding to R4. Note that in the top view of Figure 29(A), for clarity of the diagram... Some elements have been omitted from the illustration.

[0214] Transistor 117 consists of an oxide semiconductor layer 130c, an insulating layer 160, a conductive layer 170, and an insulating layer. Except for the fact that an insulating layer 191 is provided so as to cover the edge layer 190, the transistor 115 and It has a similar configuration. For example, the same material as the insulating layer 175 can be used as the insulating layer 191. This can be achieved. By adopting this configuration, oxidation of the conductive layer 170 can be prevented. Furthermore, the oxygen contained in the insulating layer 190 can be efficiently supplied to the oxide semiconductor layer 130b. ru.

[0215] Furthermore, as shown in the cross-sectional views in Figures 29(D) and (E), the oxide semiconductor layer 130 and the substrate 119 It is equipped with a conductive layer 173 that functions as a second gate electrode layer (back gate) between them. That's good too.

[0216] Conductive layer 140 (source electrode layer) and conductive layer 15 in a transistor according to one aspect of the present invention 0 (drain electrode layer) is shown in the top view of Figures 30(A) and (B) (oxide semiconductor layer 130, The width (W) of the oxide semiconductor layer 130 is shown as shown in the figure (only conductive layers 140 and 150 are shown). O S The width of conductive layer 140 and conductive layer 150 is greater than (W SD Even if a long gap is formed Moreover, it may be formed short. W OS ≧W SD (W SD is W OS or less), the gate electric field is likely to be applied to the entire oxide semiconductor layer 130, and the electrical characteristics of the transistor can be improved. Further, as shown in FIG. 30(C), the conductive layer 140 and the conductive layer 150 may be formed only in a region overlapping the oxide semiconductor layer 130.

[0217] In the transistor (transistors 101 to 114) according to one embodiment of the present invention, in any configuration, the conductive layer 170, which is the gate electrode layer, electrically surrounds the channel width direction of the oxide semiconductor layer 130 via the insulating layer 160, which is the gate insulating film, and the on-current is increased. Such a transistor structure is called a surrounded channel (s-channel) structure.

[0218] In a transistor having the oxide semiconductor layer 130a and the oxide semiconductor layer 130b, and in a transistor having the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c, by appropriately selecting two or three layers of materials constituting the oxide semiconductor layer 130, current can flow through the oxide semiconductor layer 130b. By flowing current through the oxide semiconductor layer 130b, it is less affected by interface scattering, and a high on-current can be obtained Therefore, there are cases where the on-current is improved by increasing the thickness of the oxide semiconductor layer 130b.

[0219] By using the transistor having the above configuration, good electrical characteristics can be imparted to the semiconductor device

[0220] ​​ The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments. can.

[0221] (Embodiment 3) In this embodiment, the components of the transistor shown in Embodiment 2 will be described in detail. ru.

[0222] The substrate 119 includes a glass substrate, a quartz substrate, a semiconductor substrate, a ceramic substrate, and a surface that is insulated. Processed metal substrates can be used. Alternatively, transistors and photodiodes can be used. A silicon substrate on which a silicon layer is formed, and an insulating layer, wiring, and contact plastics are placed on the silicon substrate. Materials that have a conductive or similar material forming a component that functions as a conductor can be used. When forming a p-channel transistor on a substrate, n - Silicon group having a conductive type It is preferable to use a plate. Alternatively, n - SOI substrate having a type or i-type silicon layer This is also acceptable. Furthermore, if the transistor provided on the silicon substrate is of the p-channel type, The plane orientation of the surface forming the transistor is (110) plane when using a silicon substrate. Preferred. By forming a p-channel transistor on the (110) plane, mobility can be increased. It is possible.

[0223] The insulating layer 120 has the role of preventing the diffusion of impurities from elements contained in the substrate 119. In addition, it can play a role in supplying oxygen to the oxide semiconductor layer 130. Therefore, The margin layer 120 is preferably an insulating film containing oxygen, and contains more oxygen than the stoichiometric composition. It is more preferable that the film is an insulating film. For example, the surface temperature of the film is between 100°C and 700°C. Preferably, in a TDS method performed with a heat treatment of 100°C to 500°C, oxygen atoms The converted oxygen release amount is 1.0 × 10 19 atoms / cm 3 The membrane is defined as described above. If the substrate 119 is a substrate on which other devices are formed, the insulating layer 120 is an interlayer insulating film. It also functions as such. In that case, the surface is planarized using methods such as CMP to make it flat. It is preferable to do so.

[0224] For example, the insulating layer 120 contains aluminum oxide, magnesium oxide, silicon oxide, and oxide Silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide oxide insulating films such as lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. , nitrous oxide such as silicon nitride, silicon nitride, aluminum nitride, aluminum nitride A dielectric insulating film or a mixture thereof can be used. Furthermore, a lamination of the above materials is also possible. That's fine.

[0225] The oxide semiconductor layer 130 consists of oxide semiconductor layer 130a, oxide semiconductor layer 130b and oxide A three-layer structure can be formed by stacking the semiconductor layer 130c sequentially from the insulating layer 120 side.

[0226] In the case of a single layer oxide semiconductor layer 130, the oxide semiconductor layer 13 shown in this embodiment You can use the layer corresponding to 0b.

[0227] If the oxide semiconductor layer 130 consists of two layers, then the layer corresponding to oxide semiconductor layer 130a and the oxide layer are considered to be two layers. A laminated structure can be used in which layers corresponding to the material semiconductor layer 130b are stacked sequentially from the insulating layer 120 side. In this configuration, the oxide semiconductor layer 130a and the oxide semiconductor layer 130b are swapped. It's also possible.

[0228] For example, the oxide semiconductor layer 130b contains the oxide semiconductor layer 130a and the oxide semiconductor layer Acids with a higher electron affinity (energy from the vacuum level to the bottom of the conduction band) than body layer 130c. Ion semiconductors are used.

[0229] In such a structure, when an electric field is applied to the conductive layer 170, the oxide semiconductor layer 130 A channel is formed in the oxide semiconductor layer 130b, which has the lowest energy at the lower end of the conduction band. Therefore, it can be said that the oxide semiconductor layer 130b has a region that functions as a semiconductor. However, the oxide semiconductor layer 130a and the oxide semiconductor layer 130c are insulators or semi-insulators. It could also be said that it has an area in which it functions.

[0230] The oxide semiconductor layer 130a, oxide semiconductor layer 130b, and oxide semiconductor layer 130c are used. The oxide semiconductor that can be used preferably contains at least In or Zn. i. Alternatively, it is preferable to include both In and Zn. Also, a to To reduce variations in the electrical properties of transistors, along with them, Al, Ga, Y, or It is preferable to include a stabilizer such as Sn.

[0231] The oxide semiconductor layer 130a, oxide semiconductor layer 130b, and oxide semiconductor layer 130c contain: It is preferable that the crystalline portion is included. In particular, using a crystal oriented along the c-axis allows for the creation of transistors. It can impart stable electrical properties. Furthermore, crystals oriented along the c-axis are resistant to distortion. This can improve the reliability of semiconductor devices using flexible substrates.

[0232] Conductive layer 140 acting as source electrode layer and conductive layer 1 acting as drain electrode layer 50 includes, for example, Al, Cr, Cu, Ta, Ti, Mo, W, Ni, Mn, Nd, Sc , and a single layer or laminate of a material selected from alloys or conductive nitrides of the said metallic material. This can be used. In addition, lamination of low-resistance alloys such as Cu or Cu-Mn with the above materials is possible. You may also use: Transistor 105, Transistor 106, Transistor 111, Transistor In the converter 112, for example, W is used in conductive layer 141 and conductive layer 151, and conductive layer 14 A multilayer film of Ti and Al can be used for layer 2 and the conductive layer 152.

[0233] The above material has the property of extracting oxygen from the oxide semiconductor layer. Therefore, when in contact with the above material... In some regions of the oxide semiconductor layer, oxygen is desorbed from the oxide semiconductor layer, forming an oxygen vacancy. The region becomes noticeably affected when the small amount of hydrogen contained in the membrane combines with the oxygen deficiency. It is converted to n-type. Therefore, the n-type region is the source or drain of the transistor. It can be made to work in this way.

[0234] When W is used in conductive layers 140 and 150, nitrogen doping may be performed. By doping with nitrogen, the property of extracting oxygen can be moderately weakened, resulting in an n-type compound. This prevents the region from expanding into the channel region. Also, the conductive layer 140 and the conductive The electrode layer 150 is stacked with an n-type semiconductor layer, and the n-type semiconductor layer and the oxide semiconductor layer are in contact. This also prevents the n-type region from expanding into the channel region. Examples of n-type semiconductor layers include nitrogen-doped In-Ga-Zn oxide, zinc oxide, and zinc oxide. Indium, tin oxide, indium tin oxide, etc., can be used.

[0235] The insulating layer 160, which acts as a gate insulating film, contains aluminum oxide, magnesium oxide, Silicon oxide, silicon oxide nitride, silicon nitride, silicon nitride, gallium oxide, acid Germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, An insulating film containing one or more hafnium oxide and tantalum oxide can be used. The insulating layer 160 may be a laminate of the above materials. These may be included as impurities.

[0236] Furthermore, an example of the laminated structure of the insulating layer 160 will be described. The insulating layer 160 is, for example, oxygen It contains nitrogen, silicon, hafnium, etc. Specifically, hafnium oxide, and oxide It is preferable that the material contains silicon or silicon oxide nitride.

[0237] Hafnium oxide and aluminum oxide are compared to silicon oxide and silicon oxide-nitride. It has a high dielectric constant. Therefore, compared to the case where silicon oxide is used, the thickness of the insulating layer 160 is Because it can be made larger, the leakage current due to tunnel current can be reduced. That is, This makes it possible to realize transistors with low current. Furthermore, a crystalline oxide can be used. Hafnium has a higher dielectric constant compared to hafnium oxide, which has an amorphous structure. Therefore, in order to create a transistor with a small off-current, hafnium oxide, which has a crystalline structure, is used. It is preferable to use [this]. Examples of crystal structures include monoclinic and cubic systems. However, one aspect of the present invention is not limited to these.

[0238] Furthermore, the insulating layer 120 and insulating layer 160 that are in contact with the oxide semiconductor layer 130 are made of nitrogen oxide It is preferable to use a film with low emission levels. An insulating layer and an oxide semiconductor with high nitrogen oxide emission levels are preferable. When conductors come into contact, the energy level density may increase due to nitrogen oxides. Insulating layer 120 And the insulating layer 160 is, for example, a silicon oxide nitride film that emits a small amount of nitrogen oxides. An oxide insulating layer such as an aluminum oxide nitride film can be used.

[0239] Silicon oxiditride films with low nitrogen oxide emissions are used in the TDS method. This is a membrane where the amount of ammonia released is greater than the amount of ammonia discharged, typically when the amount of ammonia released is 1 × 10⁻⁶. 18 cm -3 The above 5 x 10 19 cm -3 The following applies. Note that the amount of ammonia released is from the membrane. By heat treatment to a surface temperature of 50°C to 650°C, preferably 50°C to 550°C This shall be the amount of release.

[0240] By using the above oxide insulating layer as the insulating layer 120 and insulating layer 160, the transient This makes it possible to reduce the threshold voltage shift of the transistor and the variation in the transistor's electrical characteristics. This can be reduced.

[0241] The conductive layer 170 acting as the gate electrode layer may be, for example, Al, Ti, Cr, Co, or Ni Conductive films such as Cu, Y, Zr, Mo, Ru, Ag, Mn, Nd, Sc, Ta, and W It can be used. Furthermore, alloys of the above materials or conductive nitrides of the above materials may also be used. Furthermore, a plurality of materials selected from the above materials, alloys of the above materials, and conductive nitrides of the above materials Layers of materials are also possible. Typical examples include tungsten and tungsten and titanium nitride layers. Laminated layers of tungsten and tantalum nitride can be used. Also, low-resistance Cu can be used. Alternatively, using alloys such as Cu-Mn or laminates of the above materials with alloys such as Cu or Cu-Mn. This may also be the case. In this embodiment, the conductive layer 171 is made of tantalum nitride, and the conductive layer 172 is made of tungsten A conductive layer 170 is formed using [a specific method / tool].

[0242] Furthermore, the conductive layer 170 contains In-Ga-Zn oxide, zinc oxide, indium oxide, and tin oxide. Alternatively, an oxide conductive layer such as indium tin oxide may be used.

[0243] The insulating layer 175 may be made of a silicon nitride film or an aluminum nitride film containing hydrogen. This is possible. Transistors 103, 104, and 2 shown in Embodiment 2 In transistors 106, 109, 110, and 112: By using a hydrogen-containing insulating film as the insulating layer 175, a portion of the oxide semiconductor layer is converted to n-type. It is possible. In addition, the nitride insulating film also acts as a blocking film for moisture, etc. This can improve the reliability of the transistor.

[0244] Furthermore, an aluminum oxide film can also be used as the insulating layer 175. In particular, the embodiment Transistors 101, 102, 105, and 2 shown in state 2 In transistors 107, 108, and 111, the insulating layer 175 contains oxide It is preferable to use a luminium film. The aluminum oxide film contains impurities such as hydrogen and water. It has a high barrier effect that prevents both aluminum oxide and oxygen from permeating the membrane. The nium film contains impurities such as hydrogen and water during and after the transistor fabrication process. Prevention of contamination into the oxide semiconductor layer 130, prevention of oxygen release from the oxide semiconductor layer, insulating layer 1 It is suitable for use as a protective film that prevents the unnecessary release of oxygen from 20°C. .

[0245] Preferably, an insulating layer 180 is formed on the insulating layer 175. Magnesium oxide, silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, Gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide Using an insulating film containing one or more neodymium oxide, hafnium oxide, and tantalum oxide. This is possible. Furthermore, the insulating layer may be a laminate of the above-mentioned materials.

[0246] Here, the insulating layer 180, like the insulating layer 120, has more oxygen than its stoichiometric composition. This is preferable. Oxygen released from the insulating layer 180 passes through the insulating layer 160 to the oxide semiconductor Since it can diffuse into the channel-forming region of layer 130, it can form a shape in the channel-forming region. The oxygen deficiency that has occurred can be compensated for by oxygen. Therefore, a stable transistor Electrical properties can be obtained.

[0247] Miniaturization of transistors is essential for highly integrating semiconductor devices. Miniaturization tends to worsen the electrical characteristics of transistors, for example, by reducing the channel width. Doing so will reduce the on-current.

[0248] In transistors 107 to 112 of one aspect of the present invention, a channel is formed An oxide semiconductor layer 130c is formed so as to cover the oxide semiconductor layer 130b, The channel-forming layer and the gate insulating film are not in contact. This suppresses carrier scattering at the interface with the insulating film, thus reducing the on-voltage of the transistor. The flow can be made larger.

[0249] In one embodiment of the present invention, the channel width of the oxide semiconductor layer 130 is as described above. Because the gate electrode layer (conductive layer 170) is formed so as to electrically surround the direction, acid For the ionized semiconductor layer 130, in addition to the gate electric field from a direction perpendicular to the top surface, there is also a gate electric field perpendicular to the side surface. A gate electric field is applied from an angle. That is, a gate electric field is applied to the entire channel formation layer. As an electric field is applied, the effective channel width is expanded, further increasing the on-current. It can be done.

[0250] The various films described in this embodiment, such as metal films, semiconductor films, and inorganic insulating films, are typically spalled. It can be formed by the condensate method or plasma CVD, but other methods, such as thermal CVD, can also be used. It may also be formed by law. An example of the thermal CVD method is MOCVD (Metal Organic Compounds). nic Chemical Vapor Deposition (NIC) method and ALD (Atom Examples include the IC Layer Deposition method.

[0251] Thermal CVD is a film deposition method that does not use plasma, so defects are generated by plasma damage. It has the advantage of not being affected.

[0252] Furthermore, in the thermal CVD method, the raw material gas and oxidizer are simultaneously introduced into the chamber, and the contents of the chamber are processed By using atmospheric pressure or reduced pressure, the reaction is carried out near or on the substrate, causing the deposit to be deposited on the substrate. Film deposition may be performed.

[0253] The ALD method involves maintaining atmospheric pressure or reduced pressure inside the chamber and supplying the raw material gas for the reaction to the chamber. - The material is introduced and reacted with, and this process is repeated to form a film. Along with the raw material gas, an inert gas is also used. Argon or nitrogen may be introduced as a carrier gas. For example, two or more types The raw material gases may be supplied to the chamber in sequence. In this case, multiple types of raw material gases must not be mixed. As described above, after the reaction of the first raw material gas, an inert gas is introduced, and then the second raw material gas is introduced. Instead of introducing an inert gas, the first raw material gas is discharged by vacuum evacuation, and then the A second raw material gas may be introduced. The first raw material gas is adsorbed and reacts with the surface of the substrate to form the first layer. A film is formed, and a second raw material gas introduced later is adsorbed and reacts, causing the second layer to form on top of the first layer. The layers are stacked to form a thin film. This process is repeated while controlling the gas introduction sequence until the desired thickness is achieved. By repeating the process several times, a thin film with excellent step coverage can be formed. The thickness of the thin film is Because it can be adjusted by the number of times the injection is repeated, precise film thickness adjustment is possible. It is suitable for fabricating miniature FETs.

[0254] Thermal CVD methods such as MOCVD and ALD are disclosed in the embodiments described above. It can form various films such as metal films, semiconductor films, and inorganic insulating films, for example, In-Ga -When forming a Zn-O film, trimethylindium (In(CH3)3), trimethyl Tilgarium (Ga(CH3)3) and dimethylzinc (Zn(CH3)2) are used. This is possible. It is not limited to these combinations, and trimethylgallium can be substituted with triethyl Lugarium (Ga(C2H5)3) can also be used, and diethyl can be used instead of dimethylzinc. Zinc (Zn(C2H5)2) can also be used.

[0255] For example, when forming a hafnium oxide film using a film deposition apparatus that utilizes ALD, the solvent and Liquids containing hafnium precursors (such as hafnium alkoxide or tetrakisdimethylamide) Fnium (TDMAH, Hf[N(CH3)2]4) and tetrakis (ethylmethylamide) (The raw material gas is a vaporized hafnium amide such as hafnium, and ozone is used as an oxidizer.) Two types of gases (O3) are used.

[0256] For example, when forming an aluminum oxide film using a film deposition apparatus that utilizes ALD, the solvent and a liquid containing an aluminum precursor (trimethylaluminum (TMA, Al(CH3)3) Two types of gases are used: a raw material gas obtained by vaporizing (such as) and H2O as an oxidizing agent. The materials include tris(dimethylamide)aluminum, triisobutylaluminum, and Luminium tris(2,2,6,6-tetramethyl-3,5-heptanedione), etc. There is.

[0257] For example, when forming a silicon oxide film using a film deposition apparatus that utilizes ALD, hexa Roloticilane is adsorbed onto the film-forming surface, and radicals of oxidizing gases (O2, nitrous oxide) are supplied. It is supplied and reacted with the adsorbed material.

[0258] For example, when depositing a tungsten film using a film deposition apparatus that utilizes ALD, WF6 gas The initial tungsten film is formed by sequentially introducing S and B2H6 gas, and then WF6 gas and H Two gases are introduced sequentially to form a tungsten film. Note that SiH4 gas is used instead of B2H6 gas. Gas may be used.

[0259] For example, an oxide semiconductor layer, such as In-Ga-Zn-O, can be deposited using an ALD (Alternating Dead Lens) deposition system. When forming a layer, In(CH3)3 gas and O3 gas are introduced sequentially to form an In-O layer. Then, Ga(CH3)3 gas and O3 gas are sequentially introduced to form a GaO layer, and further Subsequently, Zn(CH3)2 gas and O3 gas are introduced sequentially to form a ZnO layer. The order of these layers is not limited to this example. These gases can be used to create In-Ga-O layers and In-Zn layers. A mixed compound layer such as an O layer or a Ga-Zn-O layer may be formed. Note that instead of O3 gas, H2O gas obtained by bubbling with an inert gas such as Ar may be used, but it does not contain H. It is preferable to use O3 gas, which does not contain oxygen.

[0260] A counter-target sputtering system can also be used to deposit oxide semiconductor layers. The film deposition method using a counter-target sputtering system is called VDSP (vapor deposition). It can also be called tion SP.

[0261] By depositing an oxide semiconductor layer using a counter-target sputtering apparatus, Plasma damage during semiconductor layer deposition can be reduced. Therefore, oxygen in the film Defects can be reduced. Also, by using a counter-target sputtering device, low pressure Since film formation becomes possible, the impurity concentration in the formed oxide semiconductor layer (e.g., hydrogen, dilute) It can reduce gases (such as argon and water).

[0262] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments. can.

[0263] (Embodiment 4) This embodiment describes an oxide semiconductor material that can be used in one aspect of the present invention. I will reveal it.

[0264] The oxide semiconductor preferably contains at least indium or zinc. In particular, indium It is preferable to include aluminum and zinc. In addition to these, aluminum, gallium, It is preferable that it contains yttrium or tin, etc. Also, boron, silicon, Titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium Selected from neodymium, hafnium, tantalum, tungsten, or magnesium, etc. It may contain one or more types.

[0265] Here, we consider the case where the oxide semiconductor contains indium, element M, and zinc. Element M may be aluminum, gallium, yttrium, or tin, etc. Other elements The elements applicable to M are boron, silicon, titanium, iron, nickel, and germanium. Zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, Examples include tungsten and magnesium. However, as element M, multiple elements mentioned above can be combined. There are times when it's acceptable to combine them.

[0266] First, using Figures 31(A), 31(B), and 31(C), the oxide according to the present invention This section describes the preferred range of atomic ratios of indium, element M, and zinc in semiconductors. Note that the atomic ratio of oxygen is not shown in Figure 31. Also, oxide semiconductors have The terms representing the atomic ratios of indium, element M, and zinc are [In], [M], and Let's call it [Zn].

[0267] In Figures 31(A), 31(B), and 31(C), the dashed line represents [In]:[M] The line where the atomic ratio of Zn is (-1≦α≦1) is [ ] In]:[M]:[Zn]=(1+α):(1-α):2 is the line where the atomic ratio is [I The line [In]:[M]:[Zn]=(1+α):(1-α):3 represents the atomic ratio. The line where the atomic ratio of ]:[M]:[Zn]=(1+α):(1-α):4, and [ This represents a line where the atomic ratio of In]:[M]:[Zn]=(1+α):(1-α):5. .

[0268] Furthermore, the dashed line represents the atomic ratio [In]:[M]:[Zn]=1:1:β (β≧0). The line where the atomic ratio is [In]:[M]:[Zn]=1:2:β, [In] The line where the atomic ratio of :[M]:[Zn]=1:3:β is [In]:[M]:[Zn] The line with an atomic ratio of 1:4:β, where [In]:[M]:[Zn]=2:1:β atoms. Lines that represent numerical ratios, and lines that represent the atomic ratio of [In]:[M]:[Zn]=5:1:β. It represents "n".

[0269] Furthermore, as shown in Figure 31, the atomic ratio of [In]:[M]:[Zn]=0:2:1 or a near-percentage of this ratio is used. Oxide semiconductors with lateral values ​​tend to adopt a spinel-type crystal structure.

[0270] Figures 31(A) and 31(B) show the indicators of an oxide semiconductor according to one embodiment of the present invention. An example of a preferred range for the atomic ratio of um, element M, and zinc is shown.

[0271] As an example, Figure 32 shows InMZnO, where [In]:[M]:[Zn]=1:1:1. Figure 4 shows the crystal structure. Figure 32 also shows InMZn when observed from a direction parallel to the b-axis. This is the crystal structure of O4. Note that the layer containing M, Zn, and oxygen shown in Figure 32 (hereinafter referred to as (M,Z) In layer n), the metallic element represents either element M or zinc. In this case, element M and zinc. Assume that the proportions are equal. Element M and zinc are substituted for each other, and their arrangement is irregular. .

[0272] InMZnO4 has a layered crystalline structure (also called a layered structure), as shown in Figure 32. One layer contains indium and oxygen (hereinafter referred to as the In layer), while the other layer contains elements M, zinc, and The (M,Zn) layer containing oxygen is 2.

[0273] Furthermore, indium and element M are mutually substitutable. Therefore, the elements in the (M,Zn) layer... It can also be represented as an (In,M,Zn) layer, where M is substituted with indium. In that case, the In layer... It has a layered structure where there is 1 layer and 2 (In,M,Zn) layers.

[0274] In an oxide semiconductor with an atomic ratio of [In]:[M]:[Zn]=1:1:2, the In layer is 1 In contrast, it has a layered structure with 3 (M,Zn) layers. That is, in contrast to [In] and [M] When [Zn] becomes large, if the oxide semiconductor crystallizes, (M,Zn) relative to the In layer The proportion of the ) layer increases.

[0275] However, in oxide semiconductors, the number of (M,Zn) layers relative to the number of In layers is a non-integer. In this case, there are multiple layered structures in which the number of (M,Zn) layers is an integer for every one In layer. It may have. For example, if [In]:[M]:[Zn]=1:1:1.5, A layered structure with 1 In layer and 2 (M,Zn) layers, and a layered structure with 3 (M,Zn) layers. In some cases, a layered structure may be formed, which is a mixture of crystalline and crystalline structures.

[0276] For example, when depositing an oxide semiconductor film using a sputtering apparatus, the atomic ratio of the target is A film with a misaligned atomic ratio is formed. In particular, depending on the substrate temperature during film formation, the target In some cases, the [Zn] in the film may be smaller than the [Zn] in the film itself.

[0277] Furthermore, multiple phases may coexist within an oxide semiconductor (e.g., two-phase coexistence, three-phase coexistence). Example For example, in the atomic ratios that are close to the atomic ratio [In]:[M]:[Zn]=0:2:1 Furthermore, two phases, a spinel-type crystal structure and a layered crystal structure, tend to coexist. In atomic ratios that are close to the atomic ratio that shows M]:[Zn]=1:0:0, the Bixby Two phases, such as a T-shaped crystal structure and a layered crystal structure, can easily coexist. Multiple phases exist in oxide semiconductors. When they coexist, grain boundaries (also called grain boundaries) exist between different crystal structures. It may form.

[0278] Furthermore, by increasing the indium content, the carrier mobility (electron mobility) of oxide semiconductors can be improved. The degree can be increased. This is an oxide semiconductor having indium, element M and zinc. In the body, the s orbitals of heavy metals primarily contribute to carrier conduction, and the indium content... By increasing the density, the region where the s orbitals overlap becomes larger, thus increasing the indium content. Oxide semiconductors with a high indium content have higher carrier mobility compared to oxide semiconductors with a low indium content. This is because it will become more expensive.

[0279] On the other hand, when the content of indium and zinc in oxide semiconductors decreases, the carrier mobility decreases. It becomes lower. Therefore, the atomic ratio that shows [In]:[M]:[Zn]=0:1:0, and In the vicinity of this value, the atomic ratio (for example, region C shown in Figure 31(C)) exhibits high insulating properties.

[0280] Therefore, an oxide semiconductor according to one aspect of the present invention has high carrier mobility and few grain boundaries. It is preferable to have the atomic ratio shown in region A of Figure 31(A), which tends to form a layered structure. stomach.

[0281] Furthermore, region B shown in Figure 31(B) is 4 from [In]:[M]:[Zn]=4:2:3. 1 and its neighboring values ​​are shown. Neighboring values ​​include, for example, atomic ratios [In]:[M]. [Zn]=5:3:4 is included. Oxide semiconductors having the atomic ratio shown in region B are In particular, it is an excellent oxide semiconductor with high crystallinity and high carrier mobility.

[0282] Furthermore, the conditions under which oxide semiconductors form a layered structure are not uniquely determined by the atomic ratio. The difficulty of forming a layered structure varies depending on the atomic ratio. On the other hand, with the same atomic ratio... Even if present, depending on the formation conditions, it may or may not form a layered structure. Therefore The region shown in the illustration is the region where the oxide semiconductor has a layered structure and the atomic ratio is such that the region The boundaries between region A and region C are not strictly defined.

[0283] Next, we will explain the case where the above oxide semiconductor is used in a transistor.

[0284] Furthermore, by using the above oxide semiconductor in a transistor, carrier scattering at grain boundaries can be improved. Because it can be reduced, it is possible to realize transistors with high field-effect mobility. Furthermore, it enables the creation of highly reliable transistors.

[0285] Furthermore, it is preferable to use an oxide semiconductor with a low carrier density for the transistor. Example For example, oxide semiconductors have a carrier density of 8 × 10⁻¹⁰ 11 / cm 3 Less than 1 × 10 11 / cm 3 Less than 1 × 10 10 / cm 3 It is less than 1 × 10 -9 / cm 3 That should suffice.

[0286] Furthermore, oxide semiconductors that are high-purity intrinsic or substantially high-purity intrinsic have fewer carrier sources. Therefore, carrier density can be lowered. Also, high-purity intrinsic or substantially high-purity In highly intrinsic oxide semiconductors, the defect level density is low, and therefore the trap level density is also low. There is a match.

[0287] Furthermore, the time required for charges trapped in the trap levels of oxide semiconductors to disappear is long. Furthermore, it can behave as if it were a fixed charge. Therefore, it can behave as if it were a fixed charge. In transistors where a channel region is formed in an oxide semiconductor, the electrical properties can become unstable. There is.

[0288] Therefore, in order to stabilize the electrical characteristics of the transistor, the impurity concentration in the oxide semiconductor must be Reducing it is effective. Also, in order to reduce the impurity concentration in oxide semiconductors, It is also preferable to reduce the concentration of impurities in the contacting film. Examples of impurities include hydrogen, nitrogen, and aluminum. Examples include potash metals, alkaline earth metals, iron, nickel, and silicon.

[0289] Here, we will explain the effects of various impurities in oxide semiconductors.

[0290] In oxide semiconductors, if silicon or carbon, which are among the Group 14 elements, are present, the oxide Defect levels are formed in semiconductors. Therefore, silicon and carbon in oxide semiconductors. The concentration of silicon and carbon near the interface with the oxide semiconductor (by secondary ion mass spectrometry) SIMS (Secondary Ion Mass Spectrometry) The resulting concentration is 2 × 10 18 atoms / cm 3 The following is preferably 2 × 10 17 at oms / cm 3 The following applies:

[0291] Furthermore, if alkali metals or alkaline earth metals are present in the oxide semiconductor, defect levels are formed. This can result in the generation of carriers. Therefore, alkali metals or alkaline earth metals Transistors using oxide semiconductors containing this material tend to exhibit normally-on characteristics. Therefore, reducing the concentration of alkali metals or alkaline earth metals in oxide semiconductors is possible. Preferably. Specifically, alkali metals or a in oxide semiconductor obtained by SIMS The concentration of rutile earth metals is 1 × 10⁻⁶ 18 atoms / cm 3 The following is preferably 2 × 10 1 6 atoms / cm 3 Do the following:

[0292] Furthermore, in oxide semiconductors, when nitrogen is present, electrons, which are carriers, are generated. The density increases, making it easier to convert to n-type. As a result, oxide semiconductors containing nitrogen can be converted into semiconductors. The transistor used tends to exhibit normally-on characteristics. Therefore, in the oxide semiconductor... Therefore, it is preferable that nitrogen is reduced as much as possible. For example, nitrogen concentration in oxide semiconductors In SIMS, the degree is 5 × 10 19 atoms / cm 3 Less than 5 × 10 1 8 atoms / cm 3 More preferably 1 × 10 18 atoms / cm 3 The following, Preferably 5 × 10 17 atoms / cm 3 The following applies:

[0293] Furthermore, the hydrogen contained in oxide semiconductors reacts with the oxygen bonded to the metal atoms to form water. This can sometimes form an oxygen vacancy. When hydrogen enters this oxygen vacancy, the electrons, which are carriers, In some cases, this can be generated. Also, some of the hydrogen combines with oxygen that is bonded to a metal atom, resulting in a It can generate electrons, which are rear electrons. Therefore, using an oxide semiconductor containing hydrogen... Transistors tend to exhibit normally-on characteristics. Therefore, hydrogen in oxide semiconductors It is preferable that it be reduced as much as possible. Specifically, in oxide semiconductors, SIM The hydrogen concentration obtained by S is 1 × 10 20 atoms / cm 3 Less than 1 × 1 0 19 atoms / cm 3 Less than 5x10 18 atoms / cm 3 less than, More preferably 1 × 10 18 atoms / cm 3 Less than.

[0294] Using oxide semiconductors with sufficiently reduced impurities in the channel formation region of transistors. This allows for the provision of stable electrical characteristics.

[0295] Next, we will discuss the case where the oxide semiconductor has a two-layer or three-layer structure. A stacked structure of semiconductor S1, oxide semiconductor S2, and oxide semiconductor S3, and a stacked structure The band diagram of the contacting insulator, the layered structure of oxide semiconductor S2 and oxide semiconductor S3, and The band diagram of the insulator in contact with the laminated structure will be explained using Figure 33. The oxide semiconductor S1 is oxide semiconductor layer 130a, and the oxide semiconductor S2 is oxide semiconductor layer 130b The oxide semiconductor S3 corresponds to the oxide semiconductor layer 130c.

[0296] Figure 33(A) shows insulator I1, oxide semiconductor S1, oxide semiconductor S2, oxide semiconductor S3 Figure 33 is an example of a band diagram in the film thickness direction of a laminated structure having an insulator I2. B) is a compound having an insulator I1, an oxide semiconductor S2, an oxide semiconductor S3, and an insulator I2. This is an example of a band diagram in the film thickness direction of a layered structure. Note that the band diagram is abbreviated for easier understanding. Edge material I1, oxide semiconductor S1, oxide semiconductor S2, oxide semiconductor S3, and insulator I2 This shows the energy level (Ec) at the lower end of the conduction band.

[0297] Oxide semiconductors S1 and S3 have a lower energy at the bottom of the conduction band than oxide semiconductor S2. - The energy level is close to the vacuum level, and typically corresponds to the energy level at the lower end of the conduction band in oxide semiconductors S2. The difference between the energy levels of the lower end of the conduction band of oxide semiconductor S1 and oxide semiconductor S3 is 0. The voltage must be 15 eV or higher, or 0.5 eV or higher and 2 eV or lower, or 1 eV or lower. Preferably. That is, the electron affinity of oxide semiconductor S1 and oxide semiconductor S3 is greater than that of oxide semiconductor S1. The electron affinity of semiconductor S2 is high, and the electron affinity of oxide semiconductors S1 and S3 is... The difference from the electron affinity of the oxide semiconductor S2 is 0.15 eV or more, or 0.5 eV or more. Furthermore, it is preferable that the voltage is 2 eV or less, or 1 eV or less.

[0298] As shown in Figures 33(A) and 33(B), oxide semiconductor S1, oxide semiconductor S2 In oxide semiconductors S3, the energy levels at the lower end of the conduction band change gradually. In other words... Therefore, it can be said that it changes continuously or is continuously joined. Such a band diagram In order to have it, the interface between oxide semiconductor S1 and oxide semiconductor S2, or oxide semiconductor S By lowering the defect level density of the mixed layer formed at the interface between 2 and the oxide semiconductor S3, stomach.

[0299] Specifically, oxide semiconductor S1 and oxide semiconductor S2, oxide semiconductor S2 and oxide semiconductor S Mixture 3 has a low defect level density because it contains a common element other than oxygen (it is the main component). A layer can be formed. For example, if the oxide semiconductor S2 is an In-Ga-Zn oxide semiconductor In this case, the oxide semiconductor S1 and oxide semiconductor S3 are In-Ga-Zn oxide semiconductors. Ga-Zn oxide semiconductors, gallium oxide, etc., are suitable materials to use.

[0300] In this case, the main carrier pathway is through the oxide semiconductor S2. Oxide semiconductor S1 and oxide Defects at the interface with semiconductor S2, and at the interface between oxide semiconductor S2 and oxide semiconductor S3. Because the level density can be lowered, the influence of interfacial scattering on carrier conduction is small. High on-current can be obtained.

[0301] When an electron is trapped in a trap level, the trapped electron behaves like a fixed charge. Therefore, the transistor's threshold voltage shifts in the positive direction. Oxide semiconductor S1, By providing the oxide semiconductor S3, the trap level is moved further away from the oxide semiconductor S2. This configuration allows the transistor's threshold voltage to shift in the positive direction. This can prevent that from happening.

[0302] Oxide semiconductors S1 and S3 have significantly better conductivity compared to oxide semiconductor S2. Low-cost materials are used. In this case, oxide semiconductor S2, oxide semiconductor S2 and oxide semiconductor S1 The interface with and the interface between oxide semiconductor S2 and oxide semiconductor S3 are mainly the channel region and It functions in this way. For example, in oxide semiconductor S1 and oxide semiconductor S3, as shown in Figure 31(C) Therefore, an oxide semiconductor with the atomic ratio shown in region C, where insulation is high, should be used. (See Figure 3) The region C shown in 1(C) is [In]:[M]:[Zn]=0:1:0, or its neighbors. This shows the atomic ratio.

[0303] In particular, when using an oxide semiconductor with the atomic ratio shown in region A for the oxide semiconductor S2, The monocrystalline semiconductor S1 and the oxide semiconductor S3 have a [M] / [In] ratio of 1 or more, preferably 2 or more. It is preferable to use an oxide semiconductor as shown above. Also, as the oxide semiconductor S3, it is preferable to use a sufficiently High insulating properties can be obtained from oxide semiconductors with a ratio of [M] / ([Zn]+[In]) of 1 or more. It is preferable to use a conductor.

[0304] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments. can.

[0305] (Embodiment 5) The following describes the structure of an oxide semiconductor that can be used in one aspect of the present invention.

[0306] In this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. This refers to the state in which something is positioned. Therefore, it also includes cases where the angle is between -5° and 5°. Also, "Perpendicular" refers to a state where two lines are positioned at an angle between 80° and 100°. Therefore, this also includes cases where the angle is between 85° and 95°.

[0307] Furthermore, in this specification, if a crystal is trigonal or rhombohedral, it will be represented as a hexagonal crystal system. .

[0308] Oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, CAAC-OS (c-axis-aligned (crystalline oxide semiconductor), polycrystalline oxide Semiconductors, nc-OS (nanocrystalline oxide semiconductor) uctor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous-l Examples include oxide semiconductors and amorphous oxide semiconductors. ru.

[0309] From another perspective, oxide semiconductors include amorphous oxide semiconductors and other crystalline oxide semiconductors. It can be divided into conductors and crystalline oxide semiconductors. As for crystalline oxide semiconductors, there are single-crystal oxide semiconductors, CAAC- Examples include OS, polycrystalline oxide semiconductors, and nc-OS.

[0310] Amorphous structures are generally isotropic and lack heterogeneous structures, representing a metastable state of atomic arrangement. It is not fixed, the bonding angle is flexible, and it has short-range order but not long-range order. It is said that...

[0311] In other words, a stable oxide semiconductor is completely amorphous. ) It cannot be called an oxide semiconductor. Also, it is not isotropic (for example, periodic structure in a minute region). Oxide semiconductors (which have a structure) cannot be called perfectly amorphous oxide semiconductors. On the other hand, a-li ke OS is an unstable structure that is not isotropic but contains voids (also called porous structures). In terms of instability, a-like OSs are physically similar to amorphous oxide semiconductors. .

[0312] First, let me explain CAAC-OS.

[0313] CAAC-OS is an oxide semiconductor having multiple c-axis oriented crystalline portions (also called pellets). It is a type of conductor.

[0314] CAAC-OS can be analyzed by X-ray diffraction (XRD). Let's explain the case of analysis. For example, InGaZnO4, which is classified as space group R-3m Structural analysis of crystalline CAAC-OS is performed using the out-of-plane method. As shown in Figure 34(A), a peak appears near a diffraction angle (2θ) of 31°. Since the 'k' is attributed to the (009) plane of the InGaZnO4 crystal, CAAC-OS The crystal has c-axis orientation, and the c-axis is the surface that forms the CAAC-OS film (also called the surface to be formed). It can be confirmed that it is facing in a direction approximately perpendicular to the top surface. Note that 2θ is 31° In addition to the nearby peak, a peak may also appear when 2θ is near 36°. The adjacent peak is due to a crystal structure classified as space group Fd-3m. Therefore, CAAC -OS preferably does not show the peak.

[0315] On the other hand, in CAAC-OS, X-rays are incident from a direction parallel to the surface being formed. Structural analysis using the ne method reveals a peak near 2θ = 56°. This peak corresponds to I It is attributed to the (110) plane of the nGaZnO4 crystal. Then, 2θ is fixed near 56°. The analysis (φ-scan) is performed while rotating the sample around the normal vector of the sample surface as the axis (φ-axis). Even when this is done, no clear peak appears, as shown in Figure 34(B). On the other hand, single crystal InGaZ When φ scanning is performed on nO4 with 2θ fixed near 56°, the result is as shown in Figure 34(C). Six peaks are observed that belong to a crystal plane equivalent to the (110) plane. Therefore, X Structural analysis using RD revealed that CAAC-OS has irregular orientations in its a-axis and b-axis. This can be confirmed.

[0316] Next, we will explain CAAC-OS analyzed by electron diffraction. For example, InGaZ For CAAC-OS having nO4 crystals, a probe is applied parallel to the surface of the CAAC-OS being formed. When an electron beam with a diameter of 300 nm is incident, a diffraction pattern like the one shown in Figure 34(D) (control) is observed. This is also called a limited-field electron diffraction pattern. A diffraction pattern may appear. This diffraction pattern includes In The spot contains a location originating from the (009) plane of the GaZnO4 crystal. Therefore, the electron rotation Depending on the circumstances, the pellets contained in CAAC-OS may have c-axis orientation, and the c-axis may be the surface to be formed. Alternatively, it can be seen that it is oriented in a direction approximately perpendicular to the upper surface. On the other hand, for the same sample, on the sample surface Figure 34(E) shows the diffraction pattern when an electron beam with a probe diameter of 300 nm is incident perpendicularly. As shown in Figure 34(E), a ring-shaped diffraction pattern can be observed. Therefore, Electron diffraction using an electron beam with a diameter of 300 nm also revealed the presence of peridotites in CAAC-OS. It can be seen that the a-axis and b-axis of the net do not have orientation. Note that in Figure 34(E) The ring is caused by the (010) and (100) planes of the InGaZnO4 crystal, among other things. It is thought that the second ring in Figure 34(E) is caused by the (110) plane, etc. It's possible.

[0317] Furthermore, a transmission electron microscope (TEM) A composite image of the bright-field image and diffraction pattern of CAAC-OS obtained by (croscope) analysis. When observing a high-resolution TEM image (also known as a TEM image), multiple pellets can be identified. On the other hand, even in high-resolution TEM images, the boundaries between pellets, i.e., grain boundaries, are not visible. Also called "Nandaly." ) There are cases where it is not possible to clearly confirm this. Therefore, CAAC -OS can be said to be less prone to the decrease in electron mobility caused by grain boundaries.

[0318] Figure 35(A) shows a high-resolution T of the cross-section of CAAC-OS observed from a direction approximately parallel to the sample surface. The EM image is shown. For observing high-resolution TEM images, spherical aberration correction is required. The aberration correction function was used. High-resolution analysis was performed using the spherical aberration correction function. High-resolution TEM images are specifically called Cs-corrected high-resolution TEM images. For example, using an atomic resolution analytical electron microscope such as the JEM-ARM200F manufactured by JEOL Ltd. This can be observed.

[0319] From Figure 35(A), we can see that the pellet is a region in which metal atoms are arranged in layers. Yes, it is possible. It has been found that the size of a single pellet can be 1 nm or larger, or even 3 nm or larger. Therefore, pellets are called nanocrystals (nc). It is also possible to use CAAC-OS with CANC(C-Axis Aligned nan It can also be called an oxide semiconductor having (ocrystals). The pellet is CAAC -Reflects the unevenness of the surface or top surface of the OS, and the surface or top surface of the CAAC-OS It becomes parallel to the plane.

[0320] Furthermore, Figures 35(B) and 35(C) show CAAC observed from a direction approximately perpendicular to the sample surface. -Shows a Cs-corrected high-resolution TEM image of the OS plane. Figures 35(D) and 35(E) are shown. These are images obtained by image processing Figure 35(B) and Figure 35(C), respectively. The following describes the image processing. Let's explain the method. First, Figure 35(B) is converted to the Fast Fourier Transform (FFT). The FFT image is obtained by performing a Fourier Transform (FFT) process. Next, the acquisition In the resulting FFT image, with the origin as the reference point, 2.8 nm -1 from 5.0nm -1 Leave the range between Next, the masked FFT image is subjected to the inverse Fast Fourier Transform (IFFT). By processing the image (Inverse Fast Fourier Transform), The processed image is obtained. The image obtained in this way is called an FFT filtered image. The filtered image is an image obtained by extracting the periodic component from the Cs-corrected high-resolution TEM image, and is a grid image. This shows the array.

[0321] In Figure 35(D), areas where the grid arrangement is disordered are indicated by dashed lines. The area enclosed by the dashed lines is It is a single pellet. The dotted line indicates the connection point between the pellets. The dashed line indicates a hexagonal shape, showing that the pellet is hexagonal. The shape of the net is not always a regular hexagon; it is often a non-regular hexagon.

[0322] In Figure 35(E), a dotted line is drawn between a region with a aligned grid arrangement and another region with a aligned grid arrangement. As shown, even near the dotted line, a clear grain boundary cannot be confirmed. Connecting the surrounding grid points to a central grid point creates a distorted hexagon, or a pentagon and / or heptagon. Shapes and other features can be formed. That is, by distorting the lattice arrangement, the formation of grain boundaries can be suppressed. It can be seen that the arrangement of oxygen atoms in CAAC-OS in the ab plane is Due to factors such as the lack of density and the change in interatomic bond distances caused by the substitution of metallic elements, This is thought to be because it allows for some distortion.

[0323] As described above, CAAC-OS has c-axis orientation and multiple properties in the ab-plane direction. A number of pellets (nanocrystals) are linked together, forming a distorted crystalline structure. Therefore, CA AC-OS, CAA crystal(c-axis-aligned ab-pl It can also be called an oxide semiconductor having an anchored crystal. ru.

[0324] CAAC-OS is a highly crystalline oxide semiconductor. The crystallinity of oxide semiconductors depends on the presence of impurities. CAAC-OS may decrease due to impurities and defects ( It can be described as an oxide semiconductor with few oxygen vacancies, etc.

[0325] Impurities are elements other than the main components of oxide semiconductors, such as hydrogen, carbon, silicon, and transition metals. There are elements, for example. For instance, oxygen is more abundant than the metallic elements that make up oxide semiconductors such as silicon. Elements with strong bonding forces can alter the atomic arrangement of oxide semiconductors by removing oxygen from them. It disrupts the crystallinity and causes a decrease in its properties. Also, heavy metals such as iron and nickel, argon, and nickel... Because carbon oxides and other elements have a large atomic radius (or molecular radius), they affect the atomic arrangement of oxide semiconductors. This disrupts the crystallinity and reduces its properties.

[0326] Next, I will explain nc-OS.

[0327] This section describes the case of analyzing nc-OS using XRD. For example, for nc-OS When structural analysis is performed using the out-of-plane method, no peaks indicating orientation appear. In other words, nc-OS crystals do not have orientation.

[0328] Furthermore, for example, nc-OS having an InGaZnO4 crystal is thinned to a thickness of 34 nm. When an electron beam with a probe diameter of 50 nm is incident on the region parallel to the surface to be formed, Figure 36 A ring-shaped diffraction pattern (nanobeam electron diffraction pattern) as shown in (A) was observed. Furthermore, the diffraction pattern when an electron beam with a probe diameter of 1 nm is incident on the same sample (na The beam electron diffraction pattern is shown in Figure 36(B). From Figure 36(B), a ring-shaped region is visible. Multiple spots are observed within. Therefore, nc-OS has a probe diameter of 50 nm. Order is not confirmed by irradiating with an electron beam, but when an electron beam with a probe diameter of 1 nm is irradiated... Order can be confirmed by having them shoot.

[0329] Furthermore, when an electron beam with a probe diameter of 1 nm is incident on a region with a thickness of less than 10 nm, As shown in Figure 36(C), an electron diffraction pattern was observed in which the spots were arranged in a roughly regular hexagonal shape. This may occur. Therefore, in the range of thickness less than 10 nm, nc-OS is ordered. It can be seen that there is a region with high fissure, i.e., a crystal. Furthermore, the crystals are oriented in various directions. Therefore, there are also regions where a regular electron diffraction pattern is not observed.

[0330] Figure 36(D) shows the Cs-corrected elevation of the cross-section of nc-OS observed from a direction approximately parallel to the surface being formed. High-resolution TEM images are shown. nc-OS refers to areas indicated by auxiliary lines in the high-resolution TEM image. As shown, there are regions where the crystalline structure can be observed and regions where the crystalline structure cannot be clearly observed. It has a region and a crystal portion contained in nc-OS, with a size of 1 nm to 10 nm. Yes, and they are often between 1 nm and 3 nm in size. Oxide semiconductors with a wavelength greater than 0 nm and less than or equal to 100 nm are called microcrystalline oxide semiconductors (micro It is sometimes called a crystalline oxide semiconductor. nc-OS is useful, for example, when grain boundaries cannot be clearly identified in high-resolution TEM images. There is a possibility that the nanocrystals share the same origin as the pellets in CAAC-OS. Therefore, the crystalline portion of nc-OS may be referred to as a pellet in the following text.

[0331] Thus, nc-OS is suitable for minute regions (for example, regions between 1 nm and 10 nm, particularly The atomic arrangement has periodicity in the region between 1 nm and 3 nm. Furthermore, nc-OS is Furthermore, no regularity is observed in the crystal orientation between different pellets. Therefore, orientation is not observed throughout the entire film. Therefore, nc-OS can be analyzed using methods that produce a-like OS or amorphous OS. It can sometimes be indistinguishable from oxide semiconductors.

[0332] Furthermore, since there is no regularity in the crystal orientation between pellets (nanocrystals), nc-OS is used. Oxides containing RANC (Random Aligned nanocrystals) semiconductors, or containing NANC (Non-Aligned nanocrystals) It can also be called an oxide semiconductor.

[0333] nc-OS is an oxide semiconductor with higher orderliness than amorphous oxide semiconductors. Therefore, nc-OS has a lower defect level density than a-like OS and amorphous oxide semiconductors. However, nc-OS does not show any regularity in crystal orientation between different pellets. nc-OS has a higher defect level density compared to CAAC-OS.

[0334] a-like OS is an oxide semiconductor having a structure between nc-OS and amorphous oxide semiconductors. It is a conductor.

[0335] Figure 37 shows a high-resolution cross-sectional TEM image of an a-like OS. Here, Figure 37(A) is This is a high-resolution cross-sectional TEM image of a-like OS at the start of electron irradiation. Figure 37(B) ) is 4.3 × 10 8 e - / nm 2 electrons (e - ) High a-like OS after irradiation These are high-resolution cross-sectional TEM images. From Figures 37(A) and 37(B), a-like OS It can be seen that, from the start of electron irradiation, striped bright regions extending in the vertical direction are observed. The bright regions show a change in shape after electron irradiation. Furthermore, the bright regions are either porous or low-density. It is presumed to be in the degree range.

[0336] Because it has porosity, a-like OS has an unstable structure. Below, a-like To demonstrate that the OS has a less stable structure compared to CAAC-OS and nc-OS. This shows the structural changes caused by electron irradiation.

[0337] As samples, prepare a-like OS, nc-OS, and CAAC-OS. The sample is also an In-Ga-Zn oxide.

[0338] First, high-resolution cross-sectional TEM images are obtained for each sample. All of them have a crystalline portion.

[0339] Furthermore, the unit cell of the InGaZnO4 crystal has three In-O layers, and Ga-Zn- It is known to have a structure in which a total of nine layers, including six O layers, are stacked in layers along the c-axis. The spacing between these adjacent layers is the same as the spacing between the grid planes of the (009) plane (also called the d value). It is approximately [value], and from crystal structure analysis, its value has been determined to be 0.29 nm. Therefore, Below, areas where the spacing of the grid stripes is between 0.28 nm and 0.30 nm are represented as InGaZn. This was considered to be the crystalline portion of O4. Note that the lattice fringes correspond to the ab-plane of the InGaZnO4 crystal. ru.

[0340] Figure 38 shows an example of investigating the average size of the crystalline regions (22 to 30 locations) in each sample. The length of the lattice fringes mentioned above is used to define the size of the crystal portion. From Figure 38, a-like The crystalline portion of the OS grows larger in proportion to the cumulative amount of electrons irradiated during TEM image acquisition, etc. It can be seen that, as shown in Figure 38, the size is about 1.2 nm in the initial stages of TEM observation. The crystal region (also called the initial nucleus) is then transformed into an electron (e - The cumulative radiation dose was 4.2 × 10⁻⁶ 8 e - / nm 2 In this case, it can be seen that it has grown to a size of about 1.9 nm. On the other hand, nc -OS and CAAC-OS are defined as the cumulative electron dose from the start of electron irradiation being 4.2 × 10⁻⁶. 8 e - / nm 2 Within this range, it can be seen that there is no change in the size of the crystal portion. (Figure 38) Furthermore, regardless of the cumulative electron irradiation dose, the size of the crystal region in nc-OS and CAAC-OS is, It can be seen that they are approximately 1.3 nm and 1.8 nm, respectively. TEM observations were performed using a Hitachi transmission electron microscope H-9000NAR. Electron beam irradiation conditions The acceleration voltage is 300kV and the current density is 6.7 × 10⁻⁶. 5 e - / (nm 2 ·s), irradiation area The diameter was set to 230 nm.

[0341] Thus, in a-like OS, crystalline growth can sometimes be observed upon electron irradiation. On the other hand, nc-OS and CAAC-OS show almost no crystal growth due to electron irradiation. It cannot be seen. In other words, a-like OS is different from nc-OS and CAAC-OS. It is clear that the structure is unstable.

[0342] Furthermore, because it has porosity, a-like OS is superior to nc-OS and CAAC-OS. It has a low-density structure. Specifically, the density of a-like OS is the same as that of a single crystal of the same composition. The density is between 78.6% and 92.3%. Also, the density of nc-OS and CAAC - The density of OS is between 92.3% and 100% of the density of a single crystal of the same composition. Oxide semiconductors with a density of less than 78% are inherently difficult to deposit.

[0343] For example, in an oxide semiconductor satisfying In:Ga:Zn=1:1:1 [atomic ratio], The density of single-crystal InGaZnO4 with a faceted crystal structure is 6.357 g / cm³. 3 That's right. For example, in an oxide semiconductor satisfying In:Ga:Zn=1:1:1 [atomic ratio] The density of a-like OS is 5.0 g / cm³. 3 More than 5.9g / cm 3 It is less than. For example, in an oxide semiconductor satisfying In:Ga:Zn=1:1:1 [atomic ratio], The density of nc-OS and CAAC-OS is 5.9 g / cm³. 3 More than 6.3g / cm 3 It is less than.

[0344] If single crystals with the same composition do not exist, single crystals with different compositions can be combined in any proportion. By doing so, the density equivalent to a single crystal at the desired composition can be estimated. The density corresponding to a single crystal of the desired composition is, with respect to the ratio of single crystals with different compositions combined, The density can be estimated using a weighted average. However, the density should be calculated using as few types of single crystals as possible. It is preferable to estimate by combining the costs.

[0345] As described above, oxide semiconductors can take on various structures, each possessing a variety of properties. Oxide semiconductors include, for example, amorphous oxide semiconductors, a-like OS, nc-OS, The multilayer film may have two or more types of CAAC-OS.

[0346] Next, the carrier density of oxide semiconductors will be explained below.

[0347] Factors that affect the carrier density of oxide semiconductors include oxygen vacancies in oxide semiconductors. Examples include vo, or impurities in oxide semiconductors.

[0348] When the number of oxygen vacancies in an oxide semiconductor increases, hydrogen atoms bond to these oxygen vacancies (this state is called VoH). When this occurs, the defect level density increases. Alternatively, when there are many impurities in the oxide semiconductor... Consequently, the defect level density increases due to the impurity. By controlling the carrier density, the carrier density of oxide semiconductors can be controlled.

[0349] Now, let's consider a transistor that uses an oxide semiconductor in the channel region.

[0350] Suppression of negative shift in the transistor threshold voltage, or the transistor off-current When the goal is reduction, it is preferable to lower the carrier density of the oxide semiconductor. When lowering the carrier density of an oxide semiconductor, the impurity concentration in the oxide semiconductor is The defect level density should be reduced by lowering the impurity concentration. In this specification, the impurity concentration is low and the defect level density is low. A low void density is referred to as high-purity intrinsic or substantially high-purity intrinsic. Oxidation of high-purity intrinsic The carrier density of a semiconductor is 8 × 10⁻¹⁰ 15 cm -3 Less than 1 × 10 11 cm -3 Less than 1 × 10 10 cm -3 It is less than 1 × 10 -9 cm- 3 That's all that needs to be done.

[0351] On the other hand, when aiming to improve the on-current of a transistor or the field-effect mobility of a transistor, it is preferable to increase the carrier density of the oxide semiconductor. When increasing the carrier density of the oxide semiconductor, the impurity concentration of the oxide semiconductor may be slightly increased, or the density of defect levels of the oxide semiconductor may be slightly increased. Alternatively, the bandgap of the oxide semiconductor may be made smaller. For example, within the range where the on / off ratio of the Id-Vg characteristics of a transistor can be obtained, an oxide semiconductor with a slightly higher impurity concentration or a slightly higher density of defect levels can be regarded as substantially intrinsic. Also, an oxide semiconductor with a large electron affinity, and accordingly a small bandgap, and as a result, an increased density of thermally excited electrons (carriers) can be regarded as substantially intrinsic. Note that when an oxide semiconductor with a larger electron affinity is used, the threshold voltage of the transistor becomes lower. When aiming to improve the on-current of a transistor or the field-effect mobility of a transistor, it is preferable to increase the carrier density of the oxide semiconductor. When increasing the carrier density of the oxide semiconductor, the impurity concentration of the oxide semiconductor may be slightly increased, or the density of defect levels of the oxide semiconductor may be slightly increased. Alternatively, the bandgap of the oxide semiconductor may be made smaller. For example, within the range where the on / off ratio of the Id-Vg characteristics of a transistor can be obtained, an oxide semiconductor with a slightly higher impurity concentration or a slightly higher density of defect levels can be regarded as substantially intrinsic. Also, an oxide semiconductor with a large electron affinity, and accordingly a small bandgap, and as a result, an increased density of thermally excited electrons (carriers) can be regarded as substantially intrinsic. Note that when an oxide semiconductor with a larger electron affinity is used, the threshold voltage of the transistor becomes lower. When increasing the carrier density of the oxide semiconductor, the impurity concentration of the oxide semiconductor may be slightly increased, or the density of defect levels of the oxide semiconductor may be slightly increased. Alternatively, the bandgap of the oxide semiconductor may be made smaller. For example, within the range where the on / off ratio of the Id-Vg characteristics of a transistor can be obtained, an oxide semiconductor with a slightly higher impurity concentration or a slightly higher density of defect levels can be regarded as substantially intrinsic. Also, an oxide semiconductor with a large electron affinity, and accordingly a small bandgap, and as a result, an increased density of thermally excited electrons (carriers) can be regarded as substantially intrinsic. Note that when an oxide semiconductor with a larger electron affinity is used, the threshold voltage of the transistor becomes lower. Alternatively, the bandgap of the oxide semiconductor may be made smaller. For example, within the range where the on / off ratio of the Id-Vg characteristics of a transistor can be obtained, an oxide semiconductor with a slightly higher impurity concentration or a slightly higher density of defect levels can be regarded as substantially intrinsic. Also, an oxide semiconductor with a large electron affinity, and accordingly a small bandgap, and as a result, an increased density of thermally excited electrons (carriers) can be regarded as substantially intrinsic. Note that when an oxide semiconductor with a larger electron affinity is used, the threshold voltage of the transistor becomes lower. For example, within the range where the on / off ratio of the Id-Vg characteristics of a transistor can be obtained, an oxide semiconductor with a slightly higher impurity concentration or a slightly higher density of defect levels can be regarded as substantially intrinsic. Also, an oxide semiconductor with a large electron affinity, and accordingly a small bandgap, and as a result, an increased density of thermally excited electrons (carriers) can be regarded as substantially intrinsic. Note that when an oxide semiconductor with a larger electron affinity is used, the threshold voltage of the transistor becomes lower. Also, an oxide semiconductor with a large electron affinity, and accordingly a small bandgap, and as a result, an increased density of thermally excited electrons (carriers) can be regarded as substantially intrinsic. Note that when an oxide semiconductor with a larger electron affinity is used, the threshold voltage of the transistor becomes lower. Also, an oxide semiconductor with a large electron affinity, and accordingly a small bandgap, and as a result, an increased density of thermally excited electrons (carriers) can be regarded as substantially intrinsic. Note that when an oxide semiconductor with a larger electron affinity is used, the threshold voltage of the transistor becomes lower. Note that when an oxide semiconductor with a larger electron affinity is used, the threshold voltage of the transistor becomes lower. .

[0352] The above-described oxide semiconductor with an increased carrier density is slightly n-type. Therefore, the oxide semiconductor with an increased carrier density may be referred to as "Slightly-n". The above-described oxide semiconductor with an increased carrier density is slightly n-type. Therefore, the oxide semiconductor with an increased carrier density may be referred to as "Slightly-n". The above-described oxide semiconductor with an increased carrier density is slightly n-type. Therefore, the oxide semiconductor with an increased carrier density may be referred to as "Slightly-n".

[0353] The carrier density of a substantially intrinsic oxide semiconductor is preferably 1×10 5 cm -3 or more and less than 1×10 18 c m -3 or more and less than 1×10 7 cm -3 or more and less than 1×10 17 cm -3 is more preferable. <, 1×10 9 cm -3 or more, 5×10 16 cm -3 or less is more preferable, 1×10 10 cm -3 or more, 1×10 16 cm -3 or less is more preferable, 1×10 11 cm -3 or more, 1 ×10 15 cm -3 or less is even more preferable.

[0354] The configuration shown in this embodiment can be used in appropriate combination with the configuration shown in other embodiments. It can be done.

[0355] (Embodiment 6) Hereinafter, the configuration of the CAC (Cl oud-Aligned Composite) -OS that can be used for the transistor disclosed in one aspect of the present invention will be described.

[0356] The CAC-OS is, for example, a material in which the elements constituting the oxide semiconductor are unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less, or in the vicinity thereof. In addition, hereinafter, in the oxide semiconductor, one or more metal elements are unevenly distributed, and the region having the metal element is in a state of being mixed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less, or in the vicinity thereof, and is also referred to as a mosaic state or a patch state. In addition, the oxide semiconductor preferably contains at least indium. Particularly preferably, it contains indium and zinc. In addition to these, aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium

[0357] Note that the oxide semiconductor preferably contains at least indium. Particularly preferably, it contains indium and zinc. In addition to these, aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium ium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium Lumanium, Zirconium, Molybdenum, Lanthanum, Cerium, Neodymium, Hafnium, Contains one or more elements selected from tantalum, tungsten, or magnesium. It's okay if they're born.

[0358] For example, CAC-OS in In-Ga-Zn oxide (among CAC-OS, In-Ga α-Zn oxide may also be specifically referred to as CAC-IGZO. ) is indium oxide (Hereinafter, InO X1 (Let X1 be a real number greater than 0.) ) or indium zinc acid compound (hereinafter referred to as In X2 Zn Y2 O Z2 (X2, Y2, and Z2 are real numbers greater than 0) Let's assume that...) and gallium oxide (hereinafter referred to as GaO X3 (Let X3 be a real number greater than 0) . ), or gallium zinc oxide (hereinafter referred to as Ga X4 Zn Y4 O Z4 (X4, Y4, and Let Z4 be a real number greater than 0. The material separates into parts such as ), resulting in a mosaic pattern. and a mosaic-like InO X1 , or In X2 Zn Y2 O Z2 However, it was uniformly distributed within the membrane. This configuration (hereinafter also referred to as cloud-based) is as follows.

[0359] In other words, CAC-OS is GaO X3 The region in which is the main component, and In X2 Zn Y2 O Z2 , or InO X1 A composite oxide semiconductor having a structure in which a region is the main component and a region is mixed. In this specification, for example, the atomic ratio of In to element M in the first region. However, the first region is greater than the atomic ratio of In to element M in the second region. Assume that the concentration of In is higher in this region compared to region 2.

[0360] Note that IGZO is a common name and refers to a single compound composed of In, Ga, Zn, and O. There are combinations. A typical example is InGaO3(ZnO). m1 (m1 is a natural number), or In ( 1+x0) Ga (1-x0) O3(ZnO) m0 (-1≦x0≦1, m0 is any number) Examples of crystalline compounds include those that are produced.

[0361] The above crystalline compounds have a single-crystal structure, a polycrystalline structure, or a CAAC structure. A CAAC structure is one in which multiple IGZO nanocrystals have c-axis orientation and in the ab-plane. This is a crystal structure in which the elements are linked without orientation.

[0362] On the other hand, CAC-OS relates to the material composition of oxide semiconductors. CAC-OS is In, G In a material composition containing a, Zn, and O, a portion of it is observed to be in the form of nanoparticles mainly composed of Ga. The region where the substance is suspected and the region where it is observed as nanoparticles mainly composed of In are, respectively This refers to a configuration in which elements are randomly dispersed in a mosaic-like manner. Therefore, in CAC-OS, crystals Structure is a secondary element.

[0363] Furthermore, CAC-OS does not include a layered structure of two or more films with different compositions. For example, a structure consisting of two layers, one with In as the main component and the other with Ga as the main component, is included. do not have.

[0364] Note that GaO X3 The region in which is the main component, and In X2 ZnY2 O Z2 , or InO X1 but In some cases, a clear boundary may not be observable between the principal component region and the surrounding area.

[0365] Note that aluminum, yttrium, copper, vanadium, and beryllium can be used instead of gallium. Boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum Lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium If one or more species selected from Cium, etc., are included, CAC-OS will be partially The region is observed to be in the form of nanoparticles mainly composed of the metal element, and a part of it is mainly composed of In. The regions observed in the nanoparticle form are randomly dispersed in a mosaic-like manner. say.

[0366] CAC-OS is formed, for example, by sputtering under conditions where the substrate is not intentionally heated. It is possible. Also, when forming CAC-OS by sputtering, the deposition gas and Then, select from inert gases (typically argon), oxygen gas, and nitrogen gas. You can use one or more of these. Also, the oxygen gas in relation to the total flow rate of the deposition gas during film formation. A lower flow rate ratio is preferable, for example, a flow rate ratio of oxygen gas of 0% or more and less than 30% is preferable. It is preferable that the value be between 0% and 10%.

[0367] CAC-OS is a type of X-ray diffraction (XRD) measurement method. When measured using the θ / 2θ scan method, which is the only Out-of-plane method, It has the characteristic of not showing a clear peak. In other words, from X-ray diffraction, the measurement area It can be seen that no orientation is observed in the ab-plane direction or the c-axis direction.

[0368] Furthermore, CAC-OS uses an electron beam with a probe diameter of 1 nm (also called a nanobeam electron beam) to illuminate the surface. In the electron diffraction pattern obtained by irradiation, there is a ring-shaped region of high brightness, and Multiple bright spots are observed in the ting region. Therefore, from the electron diffraction pattern, CAC-OS The crystal structure is non-oriented in both the planar and cross-sectional directions (nc(nano-c)). It can be seen that it has a rystal structure.

[0369] For example, in CAC-OS in In-Ga-Zn oxide, energy-dispersive X-rays Spectroscopy (EDX: Energy Dispersive X-ray spectroscopy) GaO X3 The region in which is the main component and In X2 Zn Y2 O Z2 , or InO X1 Regions where it is the main component are unevenly distributed and mixed. It can be confirmed that it has the following structure.

[0370] CAC-OS has a different structure from IGZO compounds in which metal elements are uniformly distributed, It has different properties from ZO compounds. In other words, CAC-OS is GaO X3 These are the main components. In a certain area, X2 Zn Y2 O Z2 , or InO X1 The region in which is the main component, and It exhibits phase separation, and has a mosaic-like structure in which regions composed of each element are the main components.

[0371] Here, In X2 Zn Y2 O Z2, or InO X1 The region in which is the main component is GaO X3 Compared to regions where these are the main components, this region has high conductivity. In other words, In X2 Zn Y 20 Z2 , or InO X1 In the region where this is the main component, the carrier flows, causing oxidation. Conductivity as a material semiconductor is exhibited. Therefore, In X2 Zn Y2 O Z2 , or InO X Regions where 1 is the main component are distributed in a cloud-like manner within the oxide semiconductor, resulting in a high field effect. Mobility (μ) can be achieved.

[0372] On the other hand, GaO X3 Regions in which these are the main components are, X2 Zn Y2 O Z2 , or InO X This region has higher insulating properties compared to the region where 1 is the main component. In other words, GaO X3 etc. The distribution of the main component region within the oxide semiconductor suppresses leakage current and improves performance. It can perform itching operations.

[0373] Therefore, when CAC-OS is used in semiconductor devices, GaO X3 Insulation caused by factors such as, In X2 Zn Y2 O Z2 , or InO X1 The conductivity resulting from this works in a complementary manner. As a result, high on-current (I on ), and achieving high field-effect mobility (μ) can.

[0374] Furthermore, semiconductor devices using CAC-OS have high reliability. Therefore, CAC-OS is... It is optimal for various semiconductor devices including displays.

[0375] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments. It can be.

[0376] (Embodiment 7) In this embodiment, an example of a package containing an image sensor chip and a camera module will be described. The imaging device configuration of one aspect of the present invention can be used for the image sensor chip. For the image sensor chip, the configuration of the imaging device of one aspect of the present invention can be used. It can be used.

[0377] FIG. 39(A) is an external perspective view of the upper surface side of a package containing an image sensor chip. The package has a package substrate 810 for fixing the image sensor chip 850, a cover glass 820, an adhesive 830 for bonding the two, and the like. The package has a package substrate 810 for fixing the image sensor chip 850, a cover glass 820, an adhesive 830 for bonding the two, and the like. The package has a package substrate 810 for fixing the image sensor chip 850, a cover glass 820, an adhesive 830 for bonding the two, and the like.

[0378] FIG. 39(B) is an external perspective view of the lower surface side of the package. The lower surface of the package has a BGA (Ball grid array) configuration with solder balls as bumps 840. Note that it is not limited to BGA, and it may be LGA (Land grid array), PGA (Pin Grid Array), or the like. The lower surface of the package has a BGA (Ball grid array) configuration with solder balls as bumps 840. Note that it is not limited to BGA, and it may be LGA (Land grid array), PGA (Pin Grid Array), or the like. The lower surface of the package has a BGA (Ball grid array) configuration with solder balls as bumps 840. Note that it is not limited to BGA, and it may be LGA (Land grid array), PGA (Pin Grid Array), or the like. The lower surface of the package has a BGA (Ball grid array) configuration with solder balls as bumps 840. Note that it is not limited to BGA, and it may be LGA (Land grid array), PGA (Pin Grid Array), or the like.

[0379] FIG. 39(C) is a perspective view of the package shown with a part of the cover glass 820 and the adhesive 830 omitted, and FIG. 39(D) is a cross-sectional view of the package. On the package substrate 810, electrode pads 860 are formed, and the electrode pads 860 and the bumps 840 are electrically connected via through-holes 880 and lands 885. The electrode pads 860 FIG. 39(C) is a perspective view of the package shown with a part of the cover glass 820 and the adhesive 830 omitted, and FIG. 39(D) is a cross-sectional view of the package. On the package substrate 810, electrode pads 860 are formed, and the electrode pads 860 and the bumps 840 are electrically connected via through-holes 880 and lands 885. The electrode pads 860 On the package substrate 810, electrode pads 860 are formed, and the electrode pads �60 and the bumps 840 are electrically connected via through-holes 880 and lands 885. The electrode pads 860 On the package substrate 810, electrode pads 860 are formed, and the electrode pads 860 and the bumps 840 are electrically connected via through-holes 880 and lands 885. The electrode pads 860 The electrodes of the image sensor chip 850 are electrically connected by the wire 870. It is.

[0380] Furthermore, Figure 40(A) shows a camera with an image sensor chip housed in a lens-integrated package. This is a perspective view of the top side of the camera module. The camera module is an image sensor. Package substrate 811, lens cover 821, and lens 835 for fixing the top 851 It has the following features. Also, between the package substrate 811 and the image sensor chip 851 An IC chip 890 is also provided, which has functions such as a drive circuit and a signal conversion circuit for the image device. It has a configuration as a SiP (System in Package).

[0381] Figure 40(B) is a perspective view of the lower side of the camera module. Package substrate 8 The bottom and four sides of 11 are provided with mounting lands 841 for the QFN (Quad f It has a lat no-lead package configuration. Note that this configuration is just one example. Yes, it can be a QFP (Quad flat package) or the aforementioned BGA, etc. stomach.

[0382] Figure 40(C) shows the module with the lens cover 821 and part of the lens 835 omitted. This is a perspective view of the frame, and Figure 40(D) ​​is a cross-sectional view of the camera module. A portion of 41 is used as an electrode pad 861, and the electrode pad 861 is an image sensor chip The electrodes of the pin 851 and IC chip 890 are electrically connected by wire 871. It is.

[0383] By housing the image sensor chip in the type of package described above, implementation becomes easier. It can be incorporated into various semiconductor devices and electronic equipment.

[0384] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments. can.

[0385] (Embodiment 8) An imaging device, a display device, and a semiconductor device including both according to one aspect of the present invention can be used. As an electronic device, it includes a display device, a personal computer, and an image storage device equipped with a recording medium. Devices or image playback devices, mobile phones, game consoles including portable models, mobile data terminals, e-book terminals In addition, cameras such as video cameras and digital still cameras, goggle-type displays (head Mounted display), navigation system, sound playback device (car audio, de Digital audio players, etc.), photocopiers, fax machines, printers, multifunction printers, Examples include automated teller machines (ATMs) and vending machines. These electronic devices An example is shown in Figure 41.

[0386] Figure 41(A) shows a surveillance camera, which has a housing 951, a lens 952, a support part 953, etc. One component for acquiring images in the said surveillance camera is an imaging device according to one aspect of the present invention. The device can be equipped with such equipment. Note that "surveillance camera" is a common term and does not specify its intended use. It's not a camera. For example, a device that functions as a surveillance camera is a camera, or a video camera. It is also called Ra.

[0387] Figure 41(B) shows a video camera, comprising a first housing 971, a second housing 972, a display unit 973, It has an operation key 974, a lens 975, a connecting part 976, etc. Operation key 974 and lens 975 is provided in the first housing 971, and the display unit 973 is provided in the second housing 972. It exists. One aspect of the present invention is a component for acquiring images in the video camera. It can be equipped with an imaging device.

[0388] Figure 41(C) shows a digital camera, consisting of a housing 961, a shutter button 962, and a microphone 9 It has components 63, a light-emitting unit 967, a lens 965, etc. Images are acquired with this digital camera. One component for this purpose may be an imaging device according to one embodiment of the present invention.

[0389] Figure 41(D) shows a wristwatch-type information terminal, comprising a housing 931, a display unit 932, and a wristband 9 33, it has operating buttons 935, a crown 936, a camera 939, etc. The display unit 932 is It may be a touch panel. It is one of the components for acquiring images on the information terminal. The present invention may be provided with an imaging device according to one embodiment of the present invention.

[0390] Figure 41(E) shows a portable game console, consisting of a casing 901, a display unit 903, a microphone 905, and a speaker. It includes a marker 906, operation keys 907, a stylus 908, a camera 909, etc. The portable game console shown in 41(E) has only one display unit, but portable game console The number of display units it has is not limited to this. One component for this purpose may be an imaging device according to one embodiment of the present invention.

[0391] Figure 41(F) shows a portable data terminal, which includes a housing 911, a display unit 912, a camera 919, etc. The display unit 912 has a touch panel function that allows for the input and output of information. One aspect of the present invention is a component for acquiring images in the mobile data terminal. It can be equipped with an imaging device.

[0392] This embodiment can be appropriately combined with other embodiments shown herein. . [Explanation of symbols]

[0393] 11 Image sensor 12 A / D converters 20 pixels 20a pixels 20b pixels 20c pixels 20h pixels 20i pixels 20j pixels 20k pixels 21-pixel array 23-row driver 24-line driver 25 Analog Switches 26 Current source circuit 28 Comparator 29 Counter Circuit 30 terminals 31 terminals 41 Transistors 42 transistors 43 transistors 44 transistors 45 transistors 46 transistors 47 transistors 61 Wiring 61h wiring 61i Wiring 61j wiring 61k wiring 62 Wiring 63 Wiring 64 Conductive layer 65 Wiring 71 Wiring 72 Wiring 73 Wiring 75 Wiring 76 Wiring 77 Wiring 78 Wiring 81a Insulating layer 81b Insulating layer 81c insulating layer 81d insulating layer 81e Insulating layer 81f insulating layer 81g insulating layer 81h insulating layer 81j insulating layer 82 Conductors 83 Conductors 84 Conductive layer 91 Wiring 92 Wiring 93 Wiring 94 Conductive layer 101 Transistors 102 transistors 103 Transistors 104 transistors 105 transistors 106 transistors 107 transistors 108 transistors 109 transistors 110 transistors 111 transistors 112 transistors 113 Transistors 114 transistors 115 transistors 116 transistors 117 transistors 119 circuit boards 120 Insulating layer 130 Oxide semiconductor layer 130a Oxide semiconductor layer 130b Oxide Semiconductor Layer 130c oxide semiconductor layer 130d oxide semiconductor layer 140 Conductive layer 141 Conductive layer 142 Conductive layer 143 areas 150 conductive layer 151 Conductive layer 152 Conductive layer 153 areas 160 Insulating layer 170 Conductive layer 171 Conductive layer 172 Conductive layer 173 Conductive layer 175 Insulating layer 180 Insulating layer 190 Insulating layer 191 Insulating layer 231 areas 232 areas 233 areas 331 areas 332 areas 333 areas 334 areas 335 areas 500 Single-crystal silicon substrate 510 areas 520 areas 530 areas 540 areas 545 areas 550 conductive layer 560 Conductive layer 600 Single-crystal silicon substrate 660 Channel formation region 700 Shift Registers 701 Wiring 702 Wiring 703 Wiring 704 Wiring 705 Wiring 710 Pulse Output Circuit 710_i Pulse Output Circuit 710_i-1 Pulse Output Circuit 710_n Pulse Output Circuit 710_1 Pulse output circuit 710_2 Pulse Output Circuit 711 terminal 712 terminals 713 terminal 713_1 terminal 714 terminals 715 terminal 715_n terminal 716 terminals 721 transistors 722 transistors 724 transistors 725 Transistors 726 transistors 727 transistors 728 transistors 729 transistors 731 transistors 732 transistors 733 Capacitive element 734 Capacitive element 741 Wiring 746 Wiring 761 nodes 762 nodes 763 nodes 810 Package Substrate 811 Package substrate 820 Cover Glass 821 Lens Cover 830 Adhesive 835 lens 840 Bump 841 Land 850 Image Sensor Chips 851 Image Sensor Chip 860 Electrode Pads 861 Electrode Pads 870 wire 871 Wire 880 Through Hole 885 Rand 890 IC chip 901 cabinet 903 Display section 905 Microphone 906 Speakers 907 Operation Keys 908 Stylus 909 Camera 911 cabinet 912 Display section 919 Camera 931 cabinet 932 Display section 933 Wristband 935 buttons 936 Crown 939 Camera 951 cabinet 952 Lens 953 Support part 961 cabinet 962 Shutter button 963 Mike 965 lens 967 Light-emitting part 971 cabinet 972 cabinets 973 Display section 974 Operation Keys 975 lens 976 Connection part 1100 layers 1200 layers 1300 layers 1400 layers 1530 Light blocking layer 1540 Microlens Array 1550a Optical conversion layer 1550b Optical conversion layer 1550c Optical Conversion Layer

Claims

1. A first layer having a first transistor, A second layer having a region located above the first layer and having a second transistor, A conductor that penetrates the second layer and the interface between the first layer and the second layer, A first photodiode and a second photodiode having a region positioned above the second layer, An insulating layer having a region positioned above the first photodiode and a region positioned above the second photodiode, A color filter having a region positioned above the insulating layer, The system includes a microlens array having a region positioned above the color filter, The second transistor, the first photodiode, and the second photodiode are included in the pixel array. The first transistor is included in the circuit that controls the pixel array, The conductor is electrically connected to the circuit, The conductor is arranged in a region that does not overlap with the microlens array. The insulating layer has a region disposed between the single-crystal silicon substrate on which the first photodiode and the second photodiode are formed and the conductor. The insulating layer has a region located in the groove between the first photodiode and the second photodiode. The insulating layer is a hafnium oxide film. Imaging device.

2. A first layer having a first transistor, A second layer having a region located above the first layer and having a second transistor, A conductor that penetrates the second layer and the interface between the first layer and the second layer, A first photodiode and a second photodiode having a region positioned above the second layer, An insulating layer having a region positioned above the first photodiode and a region positioned above the second photodiode, A color filter and a light-shielding layer having a region positioned above the insulating layer, The device comprises a microlens array having a region positioned above the color filter and a region positioned above the light-shielding layer, The second transistor, the first photodiode, and the second photodiode are included in the pixel array. The first transistor is included in the circuit that controls the pixel array, The conductor is electrically connected to the circuit, The conductor is arranged in a region that does not overlap with the microlens array. The insulating layer has a region disposed between the single-crystal silicon substrate on which the first photodiode and the second photodiode are formed and the conductor. The insulating layer has a region located in the groove between the first photodiode and the second photodiode. The insulating layer is a hafnium oxide film. Imaging device.

3. A first layer having a first transistor, A second layer having a region located above the first layer and having a second transistor, A conductor that penetrates the second layer and the interface between the first layer and the second layer, A first photodiode and a second photodiode having a region positioned above the second layer, An insulating layer having a region positioned above the first photodiode and a region positioned above the second photodiode, A color filter having a region positioned above the insulating layer, The system includes a microlens array having a region positioned above the color filter, The second transistor, the first photodiode, and the second photodiode are included in the pixel array. The first transistor is included in the circuit that controls the pixel array, The conductor is electrically connected to the circuit, The conductor is arranged in a region that does not overlap with the microlens array. The insulating layer has a region disposed between the single-crystal silicon substrate on which the first photodiode and the second photodiode are formed and the conductor. The insulating layer has a region located in the groove between the first photodiode and the second photodiode. The insulating layer has a laminated first insulating film and a second insulating film, The first insulating film is a silicon oxide film, The second insulating film is a hafnium oxide film. Imaging device.

4. A first layer having a first transistor, A second layer having a region located above the first layer and having a second transistor, A conductor that penetrates the second layer and the interface between the first layer and the second layer, A first photodiode and a second photodiode having a region positioned above the second layer, An insulating layer having a region positioned above the first photodiode and a region positioned above the second photodiode, A color filter and a light-shielding layer having a region positioned above the insulating layer, The device comprises a microlens array having a region positioned above the color filter and a region positioned above the light-shielding layer, The second transistor, the first photodiode, and the second photodiode are included in the pixel array. The first transistor is included in the circuit that controls the pixel array, The conductor is electrically connected to the circuit, The conductor is arranged in a region that does not overlap with the microlens array. The insulating layer has a region disposed between the single-crystal silicon substrate on which the first photodiode and the second photodiode are formed and the conductor. The insulating layer has a region located in the groove between the first photodiode and the second photodiode. The insulating layer has a laminated first insulating film and a second insulating film, The first insulating film is a silicon oxide film, The second insulating film is a hafnium oxide film. Imaging device.

Images