Imaging device

Abstract

To provide an imaging device with low power consumption.SOLUTION: An imaging device comprises: pixels that have a function of holding first imaging data, and a function of acquiring difference data between the first imaging data and second imaging data; and an A / D conversion circuit that has a comparator circuit and a counter circuit. When outputs of the pixels correspond to the difference data, a clock signal to be supplied to the counter circuit is stopped.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] One aspect of the present invention relates to an imaging device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. The technical field of one aspect of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Or, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter). Therefore, as an example, the technical field of one aspect of the present invention disclosed in this specification can include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, lighting devices, power storage devices, storage devices, imaging devices, their driving methods, or their manufacturing methods. Note that in this specification and the like, the semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics. Transistors and semiconductor circuits are one aspect of semiconductor devices. Also, storage devices, display devices, imaging devices, and electronic devices may have semiconductor devices. [[ID=...]]

[0003] [[ID=...]]

[0004]

Background Art

[0005] [[ID=4...]]

[0006] [[ID=4...]] <000...]] <000...]] <000...]] <000...]] An imaging device having a configuration in which a transistor having an oxide semiconductor is used as part of a pixel circuit is disclosed in Patent Document 3.

[0007] [[ID=...]] [[ID=...]] [[ID=...]] [[ID=...]] Furthermore, it has a 133-megapixel CMOS sensor that supports 8K4K imaging (Complem Regarding image sensors (metal oxide semiconductor) The technology is disclosed in Non-Patent Document 1. [Prior art documents] [Patent Documents]

[0007] [Patent Document 1] Japanese Patent Publication No. 2007-123861 [Patent Document 2] Japanese Patent Publication No. 2007-96055 [Patent Document 3] Japanese Patent Publication No. 2011-119711 [Non-patent literature]

[0008] [Non-Patent Document 1] R. Funatsu et al., “133Mpixel 60fps CMOS Image Sensor with 32-Column Shared High-Speed ​​Column-Parallel SAR ADCs”, IEEE ISSCC Dig.Tech.Papers, 2015. [Overview of the project] [Problems that the invention aims to solve]

[0009] When transmitting data acquired by an imaging device, the data is compressed during transmission. The amount of data can be reduced. For example, in video compression methods, a reference frame is used every few frames. Set the frame, and between reference frames, the imaging data of the reference frame and the imaging data of the current frame are used. Methods for obtaining the difference between two values ​​are examples of such methods.

[0010] Furthermore, in an imaging device having pixels arranged in a matrix, between several consecutive frames Therefore, there are often many pixels in the output data that do not change. In other words, over the course of those few frames In this case, the difference data for the same pixel is often "0". Therefore, "0 By using encoding processes that can efficiently represent ", the net amount of data can be reduced. ru.

[0011] On the other hand, compressing the data acquired by the imaging device reduces the load on data transmission, Compressing data requires a huge amount of power for digital image processing. For example, imaging A / D conversion of data output from each pixel of the device, output of A / D converted data, frame This includes storing data in memory and differential processing. In particular, the data output from each pixel of the imaging device The power consumption is primarily due to the A / D conversion and differential processing required for the data entry.

[0012] Therefore, one aspect of the present invention aims to provide an imaging device with low power consumption. To do so. Or, to provide an imaging device that reduces power consumption in A / D conversion processing. To use as one of the targets. Or, an imaging device that acquires difference data in consecutive frames. One of the objectives is to provide, or to provide an imaging device suitable for high-speed operation. One of the objectives is to provide a high-resolution imaging device. Alternatively, one of the objectives is to provide an imaging device with a high degree of integration. Alternatively, under low light conditions One of the objectives is to provide an imaging device capable of capturing images. Alternatively, dynamic One of the objectives is to provide an imaging device with a wide clean range. Alternatively, to provide an imaging device with a wide temperature range. One of the objectives is to provide an imaging device that can be used in a variety of ways. Alternatively, an imaging device with a high aperture ratio. One of the objectives is to provide a reliable imaging device. One of the objectives is to provide a novel imaging device, etc. Alternatively, one of the objectives is to provide a method for driving the above-mentioned imaging device. One of the objectives is to provide body devices and other related equipment.

[0013] Furthermore, the description of these problems does not preclude the existence of other problems. The approach does not need to solve all of these problems. This will become clear from the description in the specification, drawings, claims, etc., and the specification, drawings It is possible to extract other issues from the descriptions in the surfaces, claims, etc. [Means for solving the problem]

[0014] One aspect of the present invention relates to the difference data between the imaging data of the reference frame and the imaging data of the current frame. This relates to an imaging device that outputs an image.

[0015] One aspect of the present invention relates to an imaging system having a matrix of pixels and an A / D conversion circuit. The device comprises an A / D conversion circuit consisting of a first circuit, a second circuit, a third circuit, and a fourth The device has a circuit and a pixel which is electrically connected to the first circuit, and the first to fourth circuits are Hi-Re The first circuit can input and output signals of bell potential or low level potential, and the first signal The first circuit has a function that stops operation according to the number, and the second signal output from the pixel It has the function of comparing a third signal, which is a reference potential signal, with the second signal and outputting a fourth signal. The circuit consists of a fourth signal, a fifth signal that controls the fourth circuit, and a sixth signal that controls the second circuit. The third circuit has the function of outputting a seventh signal determined from the combination with the signal, The fourth circuit has the function of stopping the output of the clock signal according to the seventh signal, and the clock It is characterized by having a function that performs counting according to a signal and outputs the counted data. It is an imaging device.

[0016] The first circuit can be configured as a comparator circuit, and the fourth circuit as a counter circuit.

[0017] The pixel has the function of holding the first imaging data, and the first imaging data and the second imaging data It can have the functionality to acquire differential data from the previous state.

[0018] Furthermore, the first circuit operates when the first signal is at a high potential, and when the first signal is at a low potential... It can be stopped when the potential is at the bell.

[0019] The fourth signal output by the first circuit is such that the first signal is at a high potential and the second signal is at the third potential. When the signal is greater than the first signal, it is at a high level potential, and the first signal is at a high level potential and the second The signal is at a low level potential when it is smaller than the third signal, and the first signal is at a low level potential. This allows for a low-level potential.

[0020] Furthermore, the seventh signal output by the second circuit is when the sixth signal is at a high potential and the fifth signal is at a high potential. And when both the fourth signal and the fourth signal are at a high level potential or both are at a low level potential, the high level The potential is high, and the sixth signal is at a high potential and one of the fifth signal and the fourth signal is at a high potential. When the other is at a low level potential, the sixth signal is at a low level potential. When a potential is low, it can be considered a low-level potential.

[0021] Furthermore, when the first signal is at a low potential, the sixth signal can be set to a low potential. can.

[0022] Furthermore, the third circuit outputs a clock signal when the seventh signal is at a high potential, and the seventh The clock signal can be stopped when the signal is at a low potential.

[0023] Furthermore, the fourth circuit performs an additive operation when the fifth signal is at a high potential, and when the fifth signal is low. Subtraction operation can be performed when the level potential is low.

[0024] The pixel consists of first to fifth transistors, a first capacitive element, a second capacitive element, and a photoelectric converter. The element has a photoelectric conversion element, and one electrode of the photoelectric conversion element is the source electrode or drain of the first transistor. It is electrically connected to one of the in electrodes and to the source electrode or drain electrode of the first transistor. The other pole is electrically connected to either the source or drain electrode of the second transistor. The source electrode or the other of the drain electrode of the first transistor is the first capacitive element One electrode is electrically connected to the other electrode of the first capacitive element, and the other electrode of the third transistor is connected to the third transistor. It is electrically connected to either the source electrode or the drain electrode, and to the other electrode of the first capacitive element. It is electrically connected to the gate electrode of the fourth transistor and to the other electrode of the first capacitive element. It is electrically connected to one electrode of the second capacitive element and to the source electrode of the fourth transistor. Alternatively, one of the drain electrodes may be the source electrode or drain electrode of the fifth transistor. One side is electrically connected to the other, and the other side is either the source electrode or the drain electrode of the fifth transistor. The first circuit can be electrically connected to it.

[0025] Furthermore, the first to sixth transistors have an oxide semiconductor in their active layer. A transistor can be used. The oxide semiconductor is composed of In, Zn, and M (where M is A It is preferable to have l, Ti, Ga, Sn, Y, Zr, La, Ce, Nd or Hf. It seems so.

[0026] Furthermore, the photoelectric conversion element can use selenium or a compound containing selenium in its photoelectric conversion layer. For example, amorphous selenium or crystalline selenium can be used as the selenium. ru. [Effects of the Invention]

[0027] By using one aspect of the present invention, a low-power imaging device can be provided. This allows for the provision of an imaging device that reduces power consumption during A / D conversion processing. This allows us to provide an imaging device that acquires difference data in consecutive frames. Alternatively, an imaging device suitable for high-speed operation can be provided. Alternatively, high-resolution imaging can be provided. We can provide the device. Alternatively, we can provide a highly integrated imaging device. Alternatively, an imaging device capable of imaging under low light conditions can be provided. It is possible to provide an imaging device with a wide dynamic range. Alternatively, it can provide an imaging device with a wide temperature range. We can provide an imaging device that can be used in that manner. Or, we can provide an imaging device with a high aperture ratio. It is possible to do so. Or, it is possible to provide a highly reliable imaging device. Or, a novel We can provide an imaging device, or a method for driving the above-mentioned imaging device. This is possible. Alternatively, it is possible to provide novel semiconductor devices, etc.

[0028] Furthermore, one aspect of the present invention is not limited to these effects. For example, one aspect of the present invention In some cases, or depending on the circumstances, it may have effects other than those listed above. Yes. Or, for example, one aspect of the present invention may, depending on the circumstances, These effects may not always be present. [Brief explanation of the drawing]

[0029] [Figure 1] Block diagram and circuit diagram explaining the imaging device. [Figure 2] Block diagram and circuit diagram explaining the imaging device. [Figure 3] A circuit diagram illustrating the pixels and readout circuit. [Figure 4] A timing chart illustrating the operation of imaging and A / D conversion processing. [Figure 5] A timing chart illustrating the operation of imaging and A / D conversion processing. [Figure 6] A circuit diagram illustrating the pixels and readout circuit. [Figure 7] A circuit diagram illustrating the pixels and readout circuit. [Figure 8] A circuit diagram explaining pixels. [Figure 9] A cross-sectional diagram illustrating the configuration of the imaging device. [Figure 10] A diagram illustrating the operation of rolling shutter and global shutter systems. [Figure 11] A cross-sectional diagram illustrating the connection configuration of a photoelectric conversion element. [Figure 12] A cross-sectional diagram illustrating the connection configuration of a photoelectric conversion element. [Figure 13] A cross-sectional view illustrating the imaging device. [Figure 14] A cross-sectional diagram illustrating the connection configuration of a photoelectric conversion element. [Figure 15] A cross-sectional view illustrating the imaging device. [Figure 16] A cross-sectional view illustrating the imaging device. [Figure 17]Cross-sectional and circuit diagrams illustrating the imaging device. [Figure 18] A cross-sectional view illustrating the imaging device. [Figure 19] A cross-sectional view illustrating the imaging device. [Figure 20] A cross-sectional view illustrating the imaging device. [Figure 21] A cross-sectional view illustrating the imaging device. [Figure 22] A cross-sectional diagram illustrating the configuration of the imaging device. [Figure 23] A cross-sectional diagram illustrating the configuration of the imaging device. [Figure 24] A cross-sectional diagram illustrating the configuration of the imaging device. [Figure 25] A diagram illustrating a curved imaging device. [Figure 26] Top view and cross-sectional view illustrating a transistor. [Figure 27] Top view and cross-sectional view illustrating a transistor. [Figure 28] A diagram illustrating the cross-section of a transistor in the channel width direction. [Figure 29] A diagram illustrating the cross-section of a transistor along its channel length. [Figure 30] Top view and cross-sectional view illustrating the semiconductor layer. [Figure 31] Top view and cross-sectional view illustrating a transistor. [Figure 32] Top view and cross-sectional view illustrating a transistor. [Figure 33] A diagram illustrating the cross-section of a transistor in the channel width direction. [Figure 34] A diagram illustrating the cross-section of a transistor along its channel length. [Figure 35] Top view and cross-sectional view illustrating a transistor. [Figure 36] A top view illustrating a transistor. [Figure 37] Figures illustrating the XRD structural analysis of CAAC-OS and single-crystal oxide semiconductors, as well as a figure showing the limited-field electron diffraction pattern of CAAC-OS. [Figure 38]Cross-sectional TEM images of CAAC-OS, as well as planar TEM images and their image analysis results. [Figure 39] Figure showing the electron diffraction pattern of nc-OS, and a cross-sectional TEM image of nc-OS. [Figure 40] Cross-sectional TEM image of an a-like OS. [Figure 41] A diagram showing the changes in the crystalline structure of In-Ga-Zn oxide due to electron irradiation. [Figure 42] Perspective and cross-sectional views of the package containing the imaging device. [Figure 43] Perspective and cross-sectional views of the package containing the imaging device. [Figure 44] A diagram illustrating electronic devices. [Modes for carrying out the invention]

[0030] Embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. Without departing from the spirit and scope of the present invention, its form and details may be changed in various ways. Those skilled in the art will readily understand that further improvements are possible. Therefore, the present invention can be implemented as follows: The description of the form is not to be interpreted as being limited to the content of the description. Furthermore, the structure of the invention described below In this context, the same reference numeral is used for identical parts or parts having similar functions across different drawings. It is used in this way, and the explanation of its repetition may be omitted. Note that the same elements that make up the figure Matching may be omitted or modified as appropriate between different drawings.

[0031] For example, in this specification, etc., if it is explicitly stated that X and Y are connected The cases are when X and Y are electrically connected and when X and Y are functionally connected. The cases disclosed in this specification, etc., include the case where X and Y are directly connected. Therefore, the connection relationships are not limited to those shown in the diagram or text. In addition to the connection relationships shown in the diagram or text, other connections may also be included as described in the diagram or text. do.

[0032] Here, X and Y are the object (e.g., device, element, circuit, wiring, electrode, terminal, conductive film, layer). (etc.)

[0033] One example of a case where X and Y are directly connected is when an electrical connection between X and Y is possible. Elements such as switches, transistors, capacitive elements, inductors, resistive elements, and dies. If the diode, display element, light-emitting element, load, etc. are not connected between X and Y and elements that enable electrical connection between X and Y (e.g., switches, transistors, capacitors). Without the need for elements such as components, inductors, resistors, diodes, display elements, light-emitting elements, loads, etc. This is the case when X and Y are connected.

[0034] One example of a case where X and Y are electrically connected is the ability to make an electrical connection between X and Y possible. Elements such as switches, transistors, capacitive elements, inductors, resistive elements, and dies. One or more devices (such as diodes, display elements, light-emitting elements, and loads) are connected between X and Y. Yes, it is possible. Furthermore, a switch has the function of being controlled to be on or off. In other words, a switch The switch can be in a conductive (on) or non-conductive (off) state, allowing current to flow. It has a function to control whether or not current flows. Alternatively, the switch selects the path through which current flows. It has a function to switch between them. Furthermore, if X and Y are electrically connected, X and This includes cases where Y is directly connected to it.

[0035] One example of a functional connection between X and Y is enabling a functional connection between X and Y. Circuits that perform this function (for example, logic circuits (inverters, NAND gates, NOR gates, etc.), signal transformers) Conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (electric (Source circuits (boost circuits, buck circuits, etc.), level shifter circuits that change the potential level of a signal, etc.) Voltage source, current source, switching circuit, amplification circuit (which can increase signal amplitude or current amount, etc.) Circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc., signal generation One or more circuits (such as memory circuits and control circuits) can be connected between X and Y. For example, even if another circuit is placed between X and Y, the signal output from X If the signal is transmitted to Y, then X and Y are assumed to be functionally connected. When X and Y are functionally connected, the situation is different from when X and Y are directly connected. This includes cases where and are electrically connected.

[0036] Furthermore, if it is explicitly stated that X and Y are electrically connected, then X and Y and When they are electrically connected (i.e., when there is another element or circuit between X and Y) (when connected) and when X and Y are functionally connected (i.e., X and Y are connected) (When functionally connected with another circuit in between) and when X and Y are directly connected In the case of (that is, when X and Y are connected without another element or circuit in between) and However, this shall be as disclosed in this specification, etc. That is, explicitly stated that they are electrically connected. If it is explicitly stated that it is connected, then Similar information is disclosed in this specification, etc.

[0037] For example, if the source (or first terminal, etc.) of the transistor is connected via Z1 (or via (In short), electrically connected to X, the drain (or second terminal, etc.) of the transistor is connected to Z. If Y is electrically connected via (or without) 2, or if the transistor source (or the first terminal, etc.) is directly connected to a part of Z1, and another part of Z1 is directly connected to X. They are directly connected, with the transistor's drain (or second terminal, etc.) directly connected to a portion of Z2. If it is connected to and another part of Z2 is directly connected to Y, it can be expressed as follows: It is possible to do so.

[0038] For example, "X and Y and the source (or first terminal, etc.) and drain (or second terminal) of the transistor." The terminals (such as the X terminal) are electrically connected to each other, and X is the source (or the X terminal) of the transistor. The electrical connections are in the following order: terminal 1, the drain of the transistor (or terminal 2, etc.), and Y. It can be expressed as "It is connected." Or, "The source (or the source) of the transistor." Terminal 1 (or terminal 2) is electrically connected to X, and the drain (or terminal 2) of the transistor is connected to X. (d) is electrically connected to Y, X is the source of the transistor (or the first terminal, etc.), and the transistor The drain (or second terminal, etc.) of the converter, Y, is electrically connected in this order. It can be expressed as "X is the source (or first terminal) of the transistor." Alternatively, "X is the source (or first terminal) of the transistor." Y is electrically connected to X via the drain (or second terminal, etc.) and X, the transistor The source of the transistor (or the first terminal, etc.), the drain of the transistor (or the second terminal, etc.) ), Y is provided in this connection order. By using a specific method of expression to define the order of connections in the circuit configuration, Distinguish between the source (or first terminal, etc.) and drain (or second terminal, etc.) of the zista. This allows us to determine the technical scope.

[0039] Alternatively, another way to express it is, for example, "the source (or first terminal, etc.) of the transistor." It is electrically connected to X via at least a first connection path, and the first connection path is It does not have a second connection path, and the aforementioned second connection path is via a transistor, The source (or first terminal, etc.) of the transistor and the drain (or second terminal, etc.) of the transistor. The path between ( and ), and the first connection path is a path via Z1, and the transit The drain (or second terminal, etc.) of the terminal is electrically connected to Y via at least a third connection path. They are connected in a manner, and the third connection path does not have the second connection path, and the third The connection path is the path via Z2. This can be expressed as "The transition The source of the starter (or the first terminal, etc.) is connected via Z1 through at least the first connection path. And, electrically connected to X, the first connection path does not have a second connection path, The second connection path has a connection path via a transistor, and the drain of the transistor (or a second terminal, etc.) is connected to Y via Z2 by at least a third connection path. It is expressed as: "They are electrically connected, and the third connection path does not have the second connection path." It is possible. Or, "the source (or first terminal, etc.) of the transistor is less Both are electrically connected to X via Z1 through a first electrical path, and the first electrical The target path does not have a second electrical path, and the second electrical path is the transistor From the source (or first terminal, etc.) to the drain (or second terminal, etc.) of the transistor It is an electrical path, and the drain (or second terminal, etc.) of the transistor is at least third The electrical path is electrically connected to Y via Z2, and the third electrical path is , it does not have a fourth electrical path, and the fourth electrical path is the drain of the transistor The electrical pulse from (or the second terminal, etc.) to the source (or the first terminal, etc.) of the transistor It can be expressed as "It is S." Using similar methods of expression as these examples, the circuit configuration By defining the connection path in the transistor, the source (or first terminal) To distinguish between the drain (or second terminal, etc.) and the second terminal, and to determine the technical scope. It is possible.

[0040] Note that these methods of expression are just examples and are not limited to these methods. Here, X Y, Z1, and Z2 are the objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, etc.) Let's assume it is a layer, etc.

[0041] Note that, in circuit diagrams, independent components are shown as being electrically connected to each other. Even in such cases, one component may possess the functions of multiple components. For example, if part of the wiring also functions as an electrode, one conductive film will perform the function of the wiring, and It possesses the functions of both components of the electrode's function. Therefore, the electrode in this specification A conductive connection is a situation where a single conductive film combines the functions of multiple components. Combined forms are also included in that category.

[0042] Note that the words "membrane" and "layer" may differ in some cases or depending on the situation. Therefore, they can be interchanged. For example, the term "conductive layer" can be replaced with "conductive film." In some cases, it may be possible to change the term to "insulating film". Alternatively, for example, the term "insulating film" may be used. In some cases, it may be possible to change the term to "insulating layer."

[0043] Generally speaking, electric potential (voltage) is relative, and its relative magnitude from a reference potential is... The size is determined by the degree. Therefore, terms such as "grounding," "GND," and "earth" are used. Even if it is stated, the potential is not necessarily 0 volts. For example, when defining "ground" or "GND" based on the lowest potential in a circuit, Yes, it exists. Alternatively, in a circuit, an intermediate potential can be used as a reference to define "ground" or "GND". In some cases, positive and negative potentials are defined based on that potential. And so it becomes.

[0044] (Embodiment 1) In this embodiment, an imaging device, which is one aspect of the present invention, will be described with reference to the drawings.

[0045] An imaging device according to one aspect of the present invention has a plurality of pixels and an A / D conversion circuit. The pixels are Function to retain the first imaging data, and the difference between the first imaging data and the second imaging data. It has the functionality to retrieve data.

[0046] The A / D conversion circuit has a comparator circuit and a counter circuit, and the comparator circuit is It has the function of comparing the raw output potential with the reference potential, and the counter circuit is the output of the comparator circuit. It has a function that counts according to the force applied.

[0047] When the pixel output corresponds to the above difference data, the reference potential is increased from the first reference potential. A first period is provided, and a second period is provided during which the potential is reduced from the second reference potential. During the second period, when the output of the comparator circuit inverts, the counter circuit is supplied. It is characterized by stopping the clock signal.

[0048] Figure 1 is a diagram illustrating an imaging device according to one aspect of the present invention. The imaging device is matrix-shaped It has pixels 20 arranged in a row and circuits 23 and 24 for driving those pixels. Furthermore, it has a circuit 25 (A / D conversion circuit) to which the signal output from the pixel 20 is input. .

[0049] Circuit 25 has the function of converting the analog signal output from pixel 20 into a digital signal. Figure 1 shows the specific circuit diagram. Note that in Figure 1, the first row of pixels 20 is connected. This shows the connection configuration between wiring 90 (OUT[1]) and circuit 25[1]. Similarly, the second column The wiring 90 (OUT[2]) of pixel 20 is connected to circuit 25[2], and the nth pixel 20 The wiring 90 (OUT[n]) can be configured to be connected to circuit 25[n]. Oh, one circuit 25 is electrically connected to each of the multiple wires 90 (OUT), and the wires 90 ( Alternatively, the process may be carried out by switching the OUT port.

[0050] Circuit 25 includes a comparison circuit, a determination circuit, and a counter circuit. As an example, the configuration and operation of circuit 25 having a 3-bit counter circuit will be described, A counter circuit with more bits may also be used.

[0051] A comparator circuit 31 can be used as the comparison circuit. The first input terminal (+) receives the signal output by pixel 20 via wiring 90 (OUT). It can be powered. Also, the second input terminal (-) is referenced from wiring 91 (RAMP). It can accept an electric potential signal as input.

[0052] Here, the output signal COMP output from the output terminal of the comparator circuit 31 is, pixel 20 When the reference potential signal is lower than the signal output by pixel 20, it becomes "H", and the signal output by pixel 20 is lower than the reference potential signal. The reference potential signal is low ("L"). The comparator circuit 31 is connected to the third input When "H" is input from wire 92 (CEN) connected to the terminal, it enters operation mode, and "L" When this signal is input, the system enters a non-operating state (output signal COMP is "L"). Note that the signal description is as follows: In this context, "H" signifies a high-potential signal and is expressed as "1" or a high-level potential signal. It is also possible to do this. Furthermore, "L" indicates a low-potential signal and is expressed as "0" or a low-level potential signal. It can also be expressed.

[0053] The determination circuit can be composed of circuits 32 and 33. Circuit 32 has two inputs When both are "H" in response to a signal, or when both are "L", an "H" signal is output. The configuration will allow for this. For example, the circuit configuration shown in Figure 1 can be used, Its configuration is not limited.

[0054] One of the signals input to circuit 32 is the output signal COMP of comparator circuit 31, and the other The signal in question is a signal input from wiring 93 (UPDN). The input signal varies depending on the operating mode of the counter circuit. When performing addition as a step, "H" is input from wiring 93 (UPDN), and the downcomer To perform a subtraction operation as a counter, "L" is entered.

[0055] Furthermore, the control signal EN is input to circuit 32 from wiring 94(EN). The control signal EN is If it is H, circuit 32 is input from output signal COMP and wiring 93 (UPDN). Depending on the combination of signals, it can output either an "H" or an "L" signal. On the other hand, When the control signal EN is "L", circuit 32 will have a "L" signal regardless of the value of the output signal COMP. It can output numbers.

[0056] Circuit 33 outputs an "H" signal when both input signals are "H". The configuration will allow for this. One of the signals input to circuit 33 is the output signal of circuit 32, and the other The signal in question is the clock signal (CLK1) input from wiring 95 (CLK). However, When the output signal of circuit 32 is "H", the clock signal (CLK2) is received from circuit 33. The output is as follows. Here, the clock signal (CLK2) is used to operate the counter circuit.

[0057] The counter circuit consists of flip-flop circuits 34, 35, 36, and inverter circuits 51, 52. The configuration includes 53, 54, 55 and selector circuits 56, 57, 58, 59. Yes, it is possible. Note that these components are just examples, and they perform similar operations to those described below. Other elements can be used as components of the counter circuit. Alternatively, the functions of the above elements can be used. Other elements that integrate the function can be used as components of the counter circuit.

[0058] Flip-flop circuits 34, 35, and 36 have a clock signal input terminal, an input terminal (D), and an output terminal. The configuration can include a power terminal (Q) and a reset terminal (R). The reset terminal (R) of the rop circuits 34, 35, and 36 is used to supply a reset signal. It is electrically connected to wiring 96 (RST).

[0059] The clock signal input terminal of the flip-flop circuit 34 is electrically connected to the output terminal of circuit 33. It is connected. Also, the input terminal (D) of the flip-flop circuit 34 is connected to the inverter circuit 5 The output terminal of 1 is electrically connected. Also, the output terminal (Q) of the flip-flop circuit 34 This is electrically connected to wiring 67 (DATA[0]). Also, flip-flop circuit 3 The output terminal (Q) of 4 is electrically connected to the input terminal of the inverter circuit 51.

[0060] The output terminal of the selector circuit 56 is connected to the clock signal input terminal of the flip-flop circuit 35. They are electrically connected. Also, the first input terminal of the selector circuit 56 is connected to the inverter circuit 5 The output terminals of 2 are electrically connected. Also, the second input terminal of the selector circuit 56 and The output terminal (Q) of the flip-flop circuit 34 is electrically connected to the input terminal of the converter circuit 52. It is connected to the following. Also, the selection control signal terminal of the selector circuit 56 is connected to wiring 93 (UPDN) and It is electrically connected.

[0061] In the selector circuit 56, when the signal input from wiring 93 (UPDN) is "H", The signal input from the first input terminal becomes the output signal. Also, from wiring 93 (UPDN) When the input signal is "L", the signal input from the second input terminal becomes the output signal.

[0062] The input terminal (D) of the flip-flop circuit 35 is electrically connected to the output terminal of the selector circuit 57. It is connected to the output of the inverter circuit 53. The power terminals are electrically connected. Also, the second input terminal and inverter of the selector circuit 57 are connected. The input terminal of circuit 53 is electrically connected to the output terminal (Q) of flip-flop circuit 35. It is done. Also, the selection control signal terminal of the selector circuit 57 is connected to the wiring 97 (COUNT) and the electrical It connects to the target.

[0063] In the selector circuit 57, when the signal input from wiring 97 (COUNT) is "H" The signal input from the first input terminal becomes the output signal. Also, wiring 97 (COUNT) When the input signal from is "L", the signal input from the second input terminal becomes the output signal. Furthermore, when the signal input from wiring 97 (COUNT) is "L", the counter circuit It will not be counted.

[0064] Furthermore, the output terminal (Q) of the flip-flop circuit 35 is connected to wiring 68 (DATA[1]) and power They are connected by air.

[0065] The output terminal of the selector circuit 58 is connected to the clock signal input terminal of the flip-flop circuit 36. They are electrically connected. Also, the first input terminal of the selector circuit 58 is connected to the inverter circuit 5 The output terminal of 4 is electrically connected. Also, the second input terminal of the selector circuit 58 and The output terminal (Q) of the flip-flop circuit 35 is electrically connected to the input terminal of the converter circuit 54. It is connected to the following. Also, the selection control signal terminal of the selector circuit 58 is connected to wiring 93 (UPDN) and They are electrically connected. Note that selector circuit 58 operates in the same manner as selector circuit 56. It is possible.

[0066] The input terminal (D) of the flip-flop circuit 36 ​​is electrically connected to the output terminal of the selector circuit 59. It is connected to the output of the inverter circuit 55. The power terminals are electrically connected. Also, the second input terminal and inverter of the selector circuit 59 are connected. The input terminal of circuit 55 is electrically connected to the output terminal (Q) of flip-flop circuit 36. It is done. Also, the selection control signal terminal of the selector circuit 59 is connected to wiring 97 (COUNT) and electrical They are connected precisely. Furthermore, the selector circuit 59 operates in the same way as the selector circuit 57. can.

[0067] Furthermore, the output terminal (Q) of the flip-flop circuit 36 ​​is connected to wiring 69 (DATA[2]) and power They are connected by air.

[0068] Wiring 67 (DATA[0]), Wiring 68 (DATA[1]), Wiring 69 (DATA[2] The signal output to ) is the output value of the counter circuit (DATA[2:0]). By setting line 96 (RST) to "H", the counter circuit is reset, and the counter circuit The output value DATA[2:0] = "000" is assumed.

[0069] Furthermore, the flip-flop circuits 34, 35, and 36 have an inverting output terminal (Q-bar). When using a circuit, the inverter circuits 52 and 54 can be omitted, as shown in Figure 2.

[0070] The pixels 20 used in an imaging device according to one aspect of the present invention are imaging data of a previously acquired reference frame. It has a function to hold (first imaging data) and the imaging data of the current frame (second imaging data) It is desirable to have a configuration that can output the difference from (T).

[0071] Pixel 20 can have the configuration shown in the circuit diagram in Figure 3, for example. Pixel 20 is a photoelectric converter. Element PD, transistor 41, transistor 42, transistor 43, transistor 44 It has a transistor 45, a capacitive element C1 and a capacitive element C2. The capacitance value of capacitive element C1 It is preferable that this is greater than the capacitance value of the capacitive element C2. Also, in Figure 3, the readout circuit 2 As shown in 6, a configuration having a current source composed of transistor 46 is shown. A sample-and-hold circuit may be provided in the output circuit 26.

[0072] One electrode of the photoelectric conversion element PD (photodiode) is the source electrode of transistor 41. Alternatively, it is electrically connected to one of the drain electrodes. Also, the source electrode of transistor 41. Alternatively, the other end of the drain electrode may be one of the source or drain electrodes of transistor 42. And it is electrically connected to one electrode of the capacitive element C1. Also, the other electrode of the capacitive element C1 The electrodes are either the source electrode or the drain electrode of transistor 43, and the gate electrode of transistor 44. The electrode and one electrode of the capacitive element C2 are electrically connected. Also, transistor 4 One of the source or drain electrodes of transistor 45 is connected to the source or drain electrode of transistor 45. It is electrically connected to one of the input electrodes. Also, the source electrode or drain of transistor 45. The other end of the in electrode is electrically connected to either the source electrode or the drain electrode of transistor 46. Connected.

[0073] Furthermore, the other electrode of the photoelectric conversion element PD is electrically connected to the wiring 71 (VPD). The source electrode or the other of the drain electrode of the transistor 42 is electrically connected to wiring 72 (VPR). The source electrode or the other of the drain electrode of transistor 43 is connected to wiring 73. It is electrically connected to VFR. The other electrode of the capacitive element C2 is electrically connected to wiring 74 (VC). They are connected precisely. The source electrode or the other of the drain electrode of transistor 44 is connected to wiring 75. It is electrically connected to (VO). In addition to the source electrode or drain electrode of transistor 46. This is electrically connected to wiring 76 (VR).

[0074] Here, wiring 71 (VPD), wiring 72 (VPR), wiring 73 (VFR), wiring 74 (V C) Wiring 75(VO) and wiring 76(VR) may function as power lines. For example, wiring 71 (VPD), wiring 74 (VC), and wiring 76 (VR) are low-voltage It can function as a source potential line. Wiring 72 (VPR), Wiring 73 (VFR) Wiring 75(VO) can be used as a high-power potential line.

[0075] Furthermore, the gate electrode of transistor 41 is electrically connected to wiring 61 (TX). The gate electrode of transistor 42 is electrically connected to wiring 62(PR). The gate electrode of transistor 3 is electrically connected to wiring 63(FR). The electrodes are electrically connected to wiring 64 (SEL). The gate electrode of transistor 46 is It is electrically connected to wiring 65 (RBIAS).

[0076] Here, wiring 61 (TX), wiring 62 (PR), wiring 63 (FR), wiring 64 (SEL) And wiring 65 (RBIAS) functions as a signal line that controls the on / off state of the transistor. It can be made to happen.

[0077] Transistor 41 controls the potential of the charge holding section (FD1) according to the output of the photoelectric conversion element PD. It can function as a transfer transistor for control. Also, transistor 42 This is to function as a reset transistor that initializes the potential of the charge holding section (FD1). This can be done. In addition, transistor 43 resets the potential of the charge detection unit (FD2). It can function as a flat transistor. Also, transistor 44 is used for charge detection. It can function as an amplifying transistor that outputs according to the potential of part (FD2). Furthermore, transistor 45 functions as a selection transistor to select pixel 20. This is possible. Also, transistor 46 has electrical connections with either the source electrode or the drain electrode. A current source transistor to supply the appropriate signal potential to the wiring 90(OUT) connected to it, and It can be made to function.

[0078] Note that the configuration of circuit 25, pixel 20, and readout circuit 26 described above is just one example, and some circuits Some transistors, some capacitive elements, or some wiring may be omitted. Alternatively, if the configuration includes circuits, transistors, capacitive elements, wiring, etc. that are not included in the above-mentioned configuration, There are also cases where the wiring configuration differs from the one described above.

[0079] Next, using the timing charts shown in Figures 4 and 5, the pixel 20 and circuit described above are used. The operation of 25 will be explained. Note that wiring 71 (VPD), wiring 74 (VC), and wiring 76 ( VR) is set to a low potential, and wiring 72 (VPR), wiring 73 (VFR), and wiring 75 (VO) This is considered to be at a high potential.

[0080] At times T01 to T04 and T11 to T14, the imaging data of the reference frame Get the data.

[0081] Between time T01 and time T02, wiring 62(PR) is set to "H", wiring 63(FR) is set to " Let H'' and wiring 61(TX) be set to "H". At this time, the potential of the charge detection unit FD2 is wiring 73 The potential of the charge holding unit FD1 is set to the potential of the wiring 72 (VPR), with the potential of the (VFR) set to VFR. The position is set to VPR.

[0082] Between time T02 and time T03, wiring 62 (PR) is set to "L", and wiring 63 (FR) is set to " Let H'' and wiring 61(TX) be "H". At this time, the light irradiated onto the photoelectric conversion element PD corresponds Then, the potential of the charge holding part FD1 decreases to VP' and becomes VPR-VP'. The stronger the light irradiated onto the element PD, the lower the potential of the charge holding part FD1. The potential of section FD2 maintains the potential VFR.

[0083] Between time T03 and time T04, wiring 62(PR) is set to "L", and wiring 63(FR) is set to " Let L and wiring 61(TX) be "H". In this case, the light irradiated onto the photoelectric conversion element PD corresponds Then, the potential of the charge-holding part FD1 decreases further to VP', becoming VPR-2VP'. Due to the capacitive coupling between capacitive element C1 and capacitive element C2, the potential VP of the charge detection unit FD2 decreases. This results in VFR-VP. Furthermore, the stronger the light irradiated onto the photoelectric conversion element PD, the stronger the charge retention part FD. The potential of point 1 and the potential of the charge detection unit FD2 will decrease.

[0084] In addition, in the above operation, the interval between time T02 and time T03 and time T03 to time T Let T be the interval between 04, and assume that the intervals between them are equal. Also, time T02 to time T03 And between time T03 and time T04, the amount of light irradiated onto the photoelectric conversion element PD can be considered to be the same. It shall be assumed that...

[0085] Between time T11 and time T12, wiring 62(PR) is set to "H", and wiring 63(FR) is set to " Let L'' and wiring 61(TX) be set to "H". In this case, the potential of charge holding unit FD1 is VPR- The potential of wiring 72 (VPR) is set to VPR from 2VP'. That is, the charge holding section FD In case 1, the potential rises by 2VP', which is the voltage drop between time T02 and time T04. Meanwhile, the potential of the charge detection unit FD2 is obtained from VFR-VP, between capacitive element C1 and capacitive element C2. The potential rises by 2VP due to capacitive coupling. That is, the potential of the charge detection unit FD2 is... 3 (VFR) is the potential VFR, and the potential is the voltage drop at time T03 to time T04. -VP plus the potential 2VP results in the potential VFR+VP.

[0086] Between time T13 and time T14, wiring 64(SEL) is set to "H". At this time, By applying an appropriate potential to line 65 (RBIAS), the potential VFR+ of the charge detection unit FD2 is adjusted. Depending on the VP, a voltage corresponding to the imaging data is output to wiring 90 (OUT).

[0087] Here, at time T131, wire 96 (RST) is set to "H". At this time, circuit 2 The counter circuit of 5 is reset, wiring 69 (DATA[2]), wiring 68 (DATA[ 1) The DATA[2:0] output to wiring 67 (DATA[0]) will be "000". ru.

[0088] Subsequently, by time T132, wire 97 (COUNT) was set to "H", and wire 93 (UPDN) was set to "UPDN". Set to "H" and operate the counter circuit as an up counter, wiring 92( Set CEN to "H" to activate the comparator circuit 31. Initially, wiring 91 The potential of (RAMP) is set to a low potential, and is lower than the potential of wiring 90(OUT), The output signal COMP of the comparator circuit 31 will be "H".

[0089] Note that the potential of wiring 94 (EN) is such that when wiring 97 (COUNT) is "H", wiring 93 The conditions are met when (UPDN) is "H" and the output signal COMP of the comparator circuit 31 is "H". When this happens, or when wiring 93 (UPDN) is "L" and the output signal of comparator circuit 31 is The configuration is such that when COMP satisfies the condition of "L", it becomes "H". Therefore, the above conditions will be met between time T131 and time T132, so wiring 94(E The potential of N), i.e., the control signal EN, becomes "H", and circuit 32 outputs a "H" signal. It becomes possible to do so.

[0090] Furthermore, the control signal EN is transmitted when wiring 97 (COUNT) is "H", wiring 93 (UPDN When the condition is met that ) is "H" and the output signal COMP of the comparator circuit 31 is "L" Alternatively, if wiring 93 (UPDN) is "L" and the output signal COMP of comparator circuit 31 is The configuration is such that when the condition for "H" is met, it becomes "L". However, wiring 92(C If EN is "L", the control signal EN should be configured to be "L". When line 92 (CEN) is "L", the output signal COMP of the comparator circuit 31 is "L". This is the result. Furthermore, wiring 94(EN) has the control signals shown in the table below for the potential of each wire. You just need to connect the circuit that generates EN.

[0091] [Table 1]

[0092] At time T132, the potential of wiring 91 (RAMP) begins to rise. Also, wiring 95 (CLK) supplies the clock signal CLK1 to circuit 33. Initially, the output signal of circuit 32 Since it is "H", the circuit 33 outputs a clock signal with the same waveform as the clock signal CLK1. CLK2 is output, and the counter circuit begins counting.

[0093] At time T13X, the potential of wire 91 (RAMP) is higher than the potential of wire 90 (OUT). As a result, the output signal COMP of the comparator circuit 31 becomes "L". At this time, the clock The signal CLK2 becomes "L," and the counter circuit stops counting. After stopping, the configuration includes setting the signal line CEN to "L" to stop the operation of the comparator circuit 31. It is effective. Also, if the potential of wiring 91 (RAMP) reaches its maximum value, quickly close the cable. It is desirable to stop supplying the CLK1 signal. Doing so will reduce power consumption. It can be reduced. Note that DATA[2:0] at time T13X is "110" Yes.

[0094] Time T21 to time T25 is the acquisition of imaging data in the first frame and the first frame This corresponds to the period during which the difference data between the frame's imaging data and the reference frame's imaging data is acquired. Here, the imaging data of the reference frame and the first frame are identical, i.e., the difference. Let's take an example where the data is 0.

[0095] At time T21 to time T22, set wiring 62 (PR) to "H", wiring 63 (FR) to " L", and wiring 61 (TX) to "H". At this time, the potential of charge holding unit FD1 is set to the potential VPR of wiring 72 (VPR). On the other hand, the potential of charge detection unit FD2 becomes VFR + VP .

[0096] At time T22 to time T23, set wiring 62 (PR) to "L", wiring 63 (FR) to " L", and wiring 61 (TX) to "H". At this time, in response to the light irradiating the photoelectric conversion element PD , the potential of charge holding unit FD1 decreases. Also, due to the capacitance coupling between capacitor C1 and capacitor C2 , the potential of charge detection unit FD2 also decreases.

[0097] In addition, in the above operation, the interval from time T22 to time T23 is assumed to be equal to the interval T from the aforementioned time T02 to time T03 or from time T03 to time T04. Also, the amount of light irradiating the photoelectric conversion element PD at time T22 to time T23 is considered to be the same as the amount of light irradiating the photoelectric conversion element PD at time T02 to time T03 or from time T03 to time T04 . At this time, the potential VP2' corresponding to the voltage drop of charge holding unit FD1 is the same as the potential VP' corresponding to the voltage drop at time T02 to time T 03 or from time T03 to time T04. Also, the potential VP2 corresponding to the voltage drop of charge detection unit FD2 is the same as the potential VP of the voltage drop at time T03 to time T04. Therefore, the potential VFR + VP - VP2 of charge detection unit FD 2 becomes the same potential as the potential of wiring 73 (VFR). This means

[0098] that the difference between the imaging data of the reference frame and the imaging data in the first frame is 0 . ​​​​corresponds to

[0099] At time T24 to time T25, set wiring 64(SEL) to "H". At this time, by applying an appropriate potential to wiring 65(RBIAS), a voltage corresponding to the imaging data is output to wiring 90(OUT) according to the potential VFR+VP-VP2(=VFR) of charge detection unit FD2. At time T241, set wiring 96(RST) to "H". At this time, the counter circuit of circuit 25 is reset, and DATA[2:0] output to wiring 69(DATA[2]), wiring 68(DATA[1]), and wiring 67(DATA[0]) becomes "000". Thereafter, until time T242, set wiring 97(COUNT) to "H" and wiring 93(UPDN) to "H" to operate the counter circuit as an up-counter, and set wiring 92(CEN) to "H" to operate comparator circuit 31. At time T242, after setting the potential of wiring 91(RAMP) to the first reference potential, gradually increase the potential of wiring 91(RAMP). Also, supply clock signal CLK1 to wiring 95(CLK).

[0100] Here, the first reference potential is a potential slightly exceeding the potential of wiring 90(OUT) when the potential of charge detection unit FD2 is potential VFR. More specifically, it can be said to be the lowest potential at which comparator circuit 31 can determine that it is higher than the potential of wiring 90(OUT) when the potential of charge detection unit FD2 is potential VFR.

[0101]

[0102]

[0103] [[ID= forty]]Note that the first reference potential is a potential slightly exceeding the potential of wiring 90(OUT) when the potential of charge detection unit FD2 is potential VFR. More specifically, it can be said to be the lowest potential at which comparator circuit 31 can determine that it is higher than the potential of wiring 90(OUT) when the potential of charge detection unit FD2 is potential VFR.

[0104] ​​​​​​​​​​​​Initially, the potential of wiring 91 (RAMP) was higher than the potential of wiring 90 (OUT), so the comparator The output signal COMP of circuit 31 is "L". At this time, wiring 94 (EN) is "L". The clock signal CLK2 becomes "L", and the counter circuit does not count. Here, the counter Since the circuit counting has stopped, set wire 92 (CEN) to "L" and the comparator circuit A configuration that stops the operation of 31 is effective. By doing so, power consumption can be reduced. It is possible.

[0105] Between times T243 and T244, set wiring 97 (COUNT) to "L". Then, by time T244, set wiring 93 (UPDN) to "L" and then wiring 97 (COUNT Set ) to "H" to operate the counter circuit as a down counter. Set wiring 92 (CEN) to "H" to activate the comparator circuit 31.

[0106] At time T244, the potential of wiring 91 (RAMP) was set as the second reference potential, and then wiring 9 The potential of 1 (RAMP) is gradually reduced, and the clock signal CLK1 is connected to wiring 95 (CLK). To supply.

[0107] The second reference potential refers to the wiring 90 when the potential of the charge detection unit FD2 is potential VFR. This is a potential slightly below the potential of (OUT). More specifically, it is the potential of the charge detection unit FD2. When the potential is VFR, the comparator circuit 31 is lower than the potential of wiring 90 (OUT). This can be considered the highest potential that can be determined.

[0108] During this time, the potential of wiring 91 (RAMP) became lower than the potential of wiring 90 (OUT). When this happens, the output signal COMP of the comparator circuit 31 becomes "H".

[0109] At this time, the wiring 94 (EN) is "L", the clock signal CLK2 is "L", and the counter circuit does not count. Here, since the counting of the counter circuit has stopped, it is effective to stop the operation of the comparator circuit 31 by setting the wiring 92 (CEN ) to "L". Also, when the potential of the wiring 91 (RAMP) reaches the minimum value, it is desirable to promptly stop the supply of the clock signal CLK1. By doing so, the power consumption can be reduced .. Here, DATA[2:0] which is the output of the circuit 25 becomes "000".

[0110] Times T31 to T35 correspond to the period of acquiring the imaging data in the second frame and acquiring the difference data between the imaging data of the second frame and the imaging data of the reference frame .. Here, the case where the difference between the reference frame and the second frame is finite (the value is positive) is shown as an example .. Note that the imaging data of the second frame can be obtained by subtracting the difference data from the imaging data of the reference frame

[0111] At times T31 to T32, set the wiring 62 (PR) to "H", the wiring 63 (FR) to " L", and the wiring 61 (TX) to "H". At this time, the potential of the charge holding part FD1 is set to the potential VPR of the wiring 72 (VPR). On the other hand, the potential of the charge detection part FD2 becomes VFR + VP

[0112] At times T32 to T33, set the wiring 62 (PR) to "L", the wiring 63 (FR) to " L", and the wiring 61 (TX) to "H". At this time, according to the light irradiating the photoelectric conversion element PD the potential of the charge holding part FD1 decreases. Also, the capacitance of the capacitance element C1 and the capacitance element C2​​​​​ The coupling also lowers the potential of the charge detection unit FD2.

[0113] In the above operation, the interval between time T32 and time T33 is the same as the interval between time T02 and time T02 mentioned above. Let it be equal to the interval T between time interval T03 and time interval T04. Also, time interval T3 The amount of light irradiated onto the photoelectric conversion element PD from time 2 to time T33 is, from time T02 to time T0 3 or less than the amount of light irradiated onto the photoelectric conversion element PD at time T03 to time T04 Let's do it this way.

[0114] At this time, the potential VP3' corresponding to the voltage drop across the charge holding unit FD1 is from time T02 to time From the potential VP' corresponding to the voltage drop at time T03 or between time T03 and time T04 It is small. Also, the potential VP3, which corresponds to the voltage drop of the charge detection unit FD2, is small from time T03 to The voltage drop VP at time T04 is smaller. Therefore, the potential VF of the charge detection unit FD2 is smaller. R+VP-VP3 will be at a higher potential than wiring 73 (VFR). This is the reference frame. The difference between the imaging data of the first frame and the imaging data of the second frame is finite (the value is positive). To deal with the situation.

[0115] Between times T34 and T35, wiring 64(SEL) is set to "H". At this time, By applying an appropriate potential to line 65 (RBIAS), the potential VFR+ of the charge detection unit FD2 is adjusted. Depending on VP-VP3 (>VFR), the voltage corresponding to the imaging data is connected to wiring 90 (OUT). Output.

[0116] Here, at time T341, wire 96 (RST) is set to "H". At this time, circuit 2 The counter circuit of 5 is reset, wiring 69 (DATA[2]), wiring 68 (DATA[ 1) The DATA[2:0] output to wiring 67 (DATA[0]) will be "000". ru.

[0117] Subsequently, by time T342, wire 97 (COUNT) was set to "H", and wire 93 (UPDN) was set to "UPDN". Set to "H" and wiring 94(EN) to "H", and operate the counter circuit as an up counter. Set the circuit to a state where it can be operated, and set wiring 92 (CEN) to "H" to activate the comparator circuit 31. This is the state.

[0118] At time T342, the potential of wiring 91 (RAMP) was set as the first reference potential, and then wiring 9 The potential of 1 (RAMP) is gradually increased. Also, the clock signal C is connected to wiring 95 (CLK). We will supply LK1.

[0119] Initially, the potential of wiring 91 (RAMP) was lower than the potential of wiring 90 (OUT), so the comparator The output signal COMP of the data circuit 31 becomes "H". At this time, the clock signal CLK2 is The waveform becomes the same as the lock signal CLK1, and the counter circuit continues counting.

[0120] At time T34X, the potential of wire 91 (RAMP) is higher than the potential of wire 90 (OUT). As a result, the output signal COMP of the comparator circuit 31 becomes "L". At this time, wiring 94 (EN) becomes "L", the clock signal CLK2 becomes "L", and the counter circuit stops counting. Here, after the counter circuit stops counting, set wiring 92 (CEN) to "L" and A configuration that stops the operation of the comparator circuit 31 is effective. In this way, power consumption The force can be reduced.

[0121] Between times T343 and T344, set wiring 97 (COUNT) to "L". Then, by time T344, set wiring 93 (UPDN) to "L" and then wiring 97 (COUNT Set ) to "H" to operate the counter circuit as a down counter. Set wiring 92 (CEN) to "H" to activate the comparator circuit 31.

[0122] By time T344, the potential of wiring 91 (RAMP) should be set to be below the second reference potential. It is gradually reduced. Also, the clock signal CLK1 is supplied to wiring 95 (CLK). During this period, the potential of wiring 91 (RAMP) became lower than the potential of wiring 90 (OUT). In this case, the output signal COMP of the comparator circuit 31 becomes "H".

[0123] At this time, wiring 94(EN) is "L" and the clock signal CLK2 is "L", and the counter The circuit does not count. At this point, the counter circuit has stopped counting, so wiring 92 (CEN A configuration in which the operation of the comparator circuit 31 is stopped by setting ) to "L" is effective. When the potential of line 91 (RAMP) reaches its minimum value, the clock signal CLK1 is immediately supplied. It is desirable to stop the power supply. Doing so will reduce power consumption. Here, DATA[2:0] at time T34X is "010".

[0124] Time T41 to time T45 is when the acquisition of imaging data in the third frame and the third frame This corresponds to the period during which the difference data between the frame's imaging data and the reference frame's imaging data is acquired. Here, we take the example where the difference between the reference frame and the third frame is finite (negative value). This is shown. Note that the imaging data of the third frame is obtained from the imaging data of the reference frame using the difference data. It can be obtained by subtracting "Ta".

[0125] Between time T41 and time T42, wiring 62(PR) is set to "H", and wiring 63(FR) is set to " Let L and wiring 61(TX) be set to H. In this case, the potential of charge holding unit FD1 is wiring 72 The potential of (VPR) is set to VPR. On the other hand, the potential of the charge detection unit FD2 is VFR+VP. Yes.

[0126] Between time T42 and time T43, wiring 62 (PR) is set to "L", and wiring 63 (FR) is set to " Let L and wiring 61(TX) be "H". In this case, the light irradiated onto the photoelectric conversion element PD corresponds As a result, the potential of the charge holding part FD1 decreases. Also, the capacitance between capacitive element C1 and capacitive element C2 The coupling also lowers the potential of the charge detection unit FD2.

[0127] In the above operation, the interval between time T42 and time T43 is the same as the interval between time T02 and time T02 mentioned above. Let it be equal to the interval T between time interval T03 and time interval T04. The amount of light irradiated onto the photoelectric conversion element PD from time T02 to time T0 3 or more than the amount of light irradiated onto the photoelectric conversion element PD at time T03 to time T04 Let's assume that.

[0128] At this time, the potential VP4' corresponding to the voltage drop across the charge holding unit FD1 is from time T02 to time From the potential VP' corresponding to the voltage drop at time T03 or between time T03 and time T04 It is large. Also, the potential VP4, which corresponds to the voltage drop of the charge detection unit FD2, is large from time T03 to The voltage drop VP at time T04 is greater than the potential VF of the charge detection unit FD2. R+VP-VP4 will be at a lower potential than wiring 73 (VFR). This is the reference frame. The difference between the imaging data of the first frame and the imaging data in the third frame is finite (the value is negative). This corresponds to...

[0129] At time T44 to time T45, set wiring 64 (SEL) to "H". At this time, by applying an appropriate potential to wiring 65 (RBIAS), according to the potential VFR+VP-VP4 (<VFR) of the charge detection unit FD2, a voltage corresponding to the imaging data is output to wiring 90 (OUT). At time T44 to time T45, set wiring 64 (SEL) to "H". At this time, by applying an appropriate potential to wiring 65 (RBIAS), according to the potential VFR+VP-VP4 (<VFR) of the charge detection unit FD2, a voltage corresponding to the imaging data is output to wiring 90 (OUT). At time T44 to time T45, set wiring 64 (SEL) to "H". At this time, by applying an appropriate potential to wiring 65 (RBIAS), according to the potential VFR+VP-VP4 (<VFR) of the charge detection unit FD2, a voltage corresponding to the imaging data is output to wiring 90 (OUT). Output is generated.

[0130] Here, at time T441, set wiring 96 (RST) to "H". At this time, the counter circuit of circuit 25 is reset, and DATA[2:0] output to wiring 69 (DATA[2]), wiring 68 (DATA[1]), and wiring 67 (DATA[0]) becomes "000". Here, at time T441, set wiring 96 (RST) to "H". At this time, the counter circuit of circuit 25 is reset, and DATA[2:0] output to wiring 69 (DATA[2]), wiring 68 (DATA[1]), and wiring 67 (DATA[0]) becomes "000". Here, at time T441, set wiring 96 (RST) to "H". At this time, the counter circuit of circuit 25 is reset, and DATA[2:0] output to wiring 69 (DATA[2]), wiring 68 (DATA[1]), and wiring 67 (DATA[0]) becomes "000". It becomes...

[0131] [[ID=X]]After that, by time T442, set wiring 97 (COUNT) to "H" and wiring 93 (UPDN) to "H" to operate the counter circuit as an up-counter, and set wiring 92 (CEN) to "H" to operate the comparator circuit 31. After that, by time T442, set wiring 97 (COUNT) to "H" and wiring 93 (UPDN) to "H" to operate the counter circuit as an up-counter, and set wiring 92 (CEN) to "H" to operate the comparator circuit 31. After that, by time T442, set wiring 97 (COUNT) to "H" and wiring 93 (UPDN) to "H" to operate the counter circuit as an up-counter, and set wiring 92 (CEN) to "H" to operate the comparator circuit 31.

[0132] At time T442, after setting the potential of wiring 91 (RAMP) to the first reference potential, gradually increase the potential of wiring 91 (RAMP). Also, supply the clock signal CLK1 to wiring 95 (CLK). At time T442, after setting the potential of wiring 91 (RAMP) to the first reference potential, gradually increase the potential of wiring 91 (RAMP). Also, supply the clock signal CLK1 to wiring 95 (CLK). At time T442, after setting the potential of wiring 91 (RAMP) to the first reference potential, gradually increase the potential of wiring 91 (RAMP). Also, supply the clock signal CLK1 to wiring 95 (CLK).

[0133] Initially, since the potential of wiring 91 (RAMP) is higher than the potential of wiring 90 (OUT), the output signal COMP of the comparator circuit 31 becomes "L". At this time, wiring 94 (EN) is "L", the clock signal CLK2 is "L", and the counter circuit does not count. Here, the counter... Initially, since the potential of wiring 91 (RAMP) is higher than the potential of wiring 90 (OUT), the output signal COMP of the comparator circuit 31 becomes "L". At this time, wiring 94 (EN) is "L", the clock signal CLK2 is "L", and the counter circuit does not count. Here, the counter... Initially, since the potential of wiring 91 (RAMP) is higher than the potential of wiring 90 (OUT), the output signal COMP of the comparator circuit 31 becomes "L". At this time, wiring 94 (EN) is "L", the clock signal CLK2 is "L", and the counter circuit does not count. Here, the counter... It should be noted that there may be some inaccuracies in the translation due to the complexity and potential ambiguity of the original text, especially in the context of technical patent terms. It is recommended to review and verify the translation in combination with the relevant technical background.Since the circuit counting has stopped, set wire 92 (CEN) to "L" and the comparator circuit A configuration that stops the operation of 31 is effective. By doing so, power consumption can be reduced. It is possible.

[0134] Between times T443 and T444, set wiring 97 (COUNT) to "L". Then, by time T444, set wiring 93 (UPDN) to "L" and then wiring 97 (COUNT Set ) to "H", wiring 94(EN) to "H", and the counter circuit as a down counter Set to the operating state. Also, set wiring 92 (CEN) to "H" and comparator circuit 3 Set the device to the state where it is operational (1).

[0135] Between now and time T444, the potential of wiring 91 (RAMP) is set as the second reference potential, and then wiring The potential of 91 (RAMP) is gradually reduced, and the clock signal CLK1 is sent to wiring 95 (CLK). To supply.

[0136] At time T444, the potential of wiring 91 (RAMP) is higher than the potential of wiring 90 (OUT). Therefore, the output signal COMP of the comparator circuit 31 becomes "L". Thus, The CLK2 signal has the same waveform as the CLK1 clock signal, and the counter circuit counts accordingly. .

[0137] Furthermore, if the potential of wiring 91 (RAMP) is lowered after time T444, at time T44X In this configuration, the potential of wiring 91 (RAMP) becomes lower than the potential of wiring 90 (OUT), and the comparison The output signal COMP of the inverter circuit 31 will be "H".

[0138] At this time, the signal line EN is "L" and the clock signal CLK2 is "L", and the counter circuit is No counting. At this point, the counter circuit has stopped counting, so wire 92 (CEN) is “ A configuration that stops the operation of the comparator circuit 31 by setting it to "L" is effective. Also, wiring 91 If the potential of (RAMP) reaches its lowest value, the supply of the clock signal CLK1 is immediately stopped. It is desirable to stop this. By doing so, power consumption can be reduced. Here Therefore, DATA[2:0] at time T44X is "101".

[0139] With the circuit configuration and operation described above, the imaging data and difference data are converted into digital data. This makes it possible to reduce power consumption during the A / D conversion process. This allows us to provide an imaging device that can perform data compression processing with low power consumption.

[0140] Note that the circuit of pixel 20 is not limited to the configuration shown in Figure 3, but can also be configured as shown in Figures 6(A) to 6(C). It may also be possible. Figure 6(A) shows a configuration in which the orientation of the photoelectric conversion element PD connection is reversed compared to Figure 3. In this configuration, wiring 71 (VPD) is at a high potential, and wiring 72 (VPR) and wiring 7 The potential at 3(VFR) can be set to a low potential for operation. Figure 6(B) shows a transistor. This configuration does not include 42. In this configuration, the potential of wiring 71 (VPD) is set to a high potential. This allows the charge retention unit FD1 to be reset. Figure 6(C) shows transistor 44 The other of either the source electrode or the drain electrode is connected to wiring 90 (OUT).

[0141] Furthermore, the transistors used in the pixel circuit are as shown in Figures 7(A) to 7(C), A configuration in which back gates are provided on transistors 41 to 46 is also possible. (Figure 7) A) is a configuration in which a constant potential is applied to the back gate, and the threshold voltage can be controlled. For example, wiring 66 (VSS) and wiring 74 ( The back gate supplies low potential. The diagram shows a connection to the source side of either a VC or a transistor, but only one of the configurations is shown. It may also be possible. Also, Figure 7(B) shows that the same potential as the front gate is applied to the back gate. This configuration allows for an increase in on-current. Also, Figure 7(C) shows the desired transformer. The configurations shown in Figures 7(A) and 7(B) are combined so that the inverter has appropriate electrical characteristics. The configuration is as shown. Note that the configuration in Figure 7(C) is just one example. Also, Figures 3 and 6(A) The configurations up to Figure 6(C) and the configurations from Figures 7(A) to 7(C) can be combined as needed. It is possible.

[0142] Furthermore, the circuit of pixel 20 is configured to include multiple transistors 42 to 45, as shown in Figure 8. It may also be a configuration shared by multiple pixels. Figure 8 shows transistor 42 in multiple pixels in the vertical direction. The example shows a configuration in which transistor 45 is shared, but in the horizontal or horizontal-vertical direction Multiple pixels may share transistors 42 to 45. This allows us to reduce the number of transistors per pixel. In Figure 8, the source electrode or the other of the drain electrode of transistor 43 is wired 72 (VPR). The example shows how to connect, but the configuration involves providing wiring 73 (VFR) and connecting to that wiring. It is also possible to do so. In addition, in Figure 8, the other electrode of the capacitive element C1 is connected to the wiring 74 (VC). Although an example is shown, it is also possible to configure the electrode to be connected to wiring 71 (VPD). .

[0143] Figure 8 illustrates a configuration in which transistors 42 to 45 are shared by four pixels. However, it may also be a form shared by 2 pixels, 3 pixels, or 5 or more pixels. The configuration shown in Figures 6(A) to 6(C) and Figures 7(A) to 7(C) The configuration can be combined in any way you like.

[0144] Next, a specific example of the configuration of an imaging device according to one aspect of the present invention will be described with reference to the drawings. Figure 9(A) shows the photoelectric conversion element PD, transistor 41, and transistor in the pixel 20 shown in Figure 3. This shows an example of a specific connection configuration for the inverter 42 and the capacitive element C1. Note that Figure 9( Transistors 43 to 45 are not shown in A). Pixel 20 is a transistor A layer 1100 on which transistors 41 to 45 and capacitive elements C1 are provided, It has a layer 1200 on which a photoelectric conversion element PD is provided.

[0145] In the cross-sectional view described in this embodiment, each wiring, each electrode, and each conductor 81 are individually Although they are shown as separate elements, if they are electrically connected, they are identical. It may also be provided as an element. Furthermore, it can be used as the gate electrode or source electrode of a transistor. One example is a configuration in which the drain electrode is connected to each wiring via a conductor 81, and the transistor Each of the gate electrode, source electrode, or drain electrode of the terminal functions as a wire. In some cases, this may be the case.

[0146] Furthermore, each element has an insulating layer 82 that functions as a protective film, an interlayer insulating film, or a planarizing film. And an insulating layer 83, etc. is provided. For example, the insulating layer 82 and insulating layer 83, etc. are made of silica Inorganic insulating films such as acrylic film and silicon oxidnitride film can be used. Resins, polyimide resins, and other organic insulating films may be used. Insulating layer 82 and insulating layer 8 The top surface of the third grade is treated with CMP (Chemical Mechanical Pol) as needed. It is preferable to perform a planarization treatment using the ishing method or similar methods.

[0147] In addition, if some of the wiring shown in the drawings is not provided, or if there is wiring or other elements not shown in the drawings, Rangings and other components may be included in each layer. Additionally, layers not shown in the drawings may be included. Yes, it is. Also, some of the layers shown in the drawing may not be included.

[0148] Transistors 41 through 45 are transistors using oxide semiconductors (hereinafter It is particularly preferable to use an OS transistor.

[0149] OS transistors have extremely low off-current characteristics, thus improving the dynamic range of imaging. It can be enlarged. In the circuit configuration of pixel 20 shown in Figure 3, the photoelectric conversion element PD is incident on When the intensity of the light is high, the potential of the charge holding part FD1 decreases. The OS transistor is Because the off-current is extremely low, even when the gate potential is extremely small, the gate potential is... It can accurately output the corresponding current. Therefore, the range of illuminance that can be detected... It can widen the dynamic range.

[0150] Furthermore, transistors 41, 42, and 43 have low off-current characteristics. This allows the charge holding unit FD1 and the charge detection unit FD2 to hold charge for an extremely long period of time. Therefore, it is possible to simultaneously perform operations on all pixels without complicating the circuit configuration or operating method. A global shutter system that performs charge accumulation can be applied to this.

[0151] Generally, in imaging devices where pixels are arranged in a matrix, as shown in Figure 10(A), each row Rolling is a drive method that performs imaging operation 12, data holding operation 13, and readout operation 14. A shutter method is used. When using a rolling shutter method, the simultaneity of imaging is Because this is lost, if the subject moves, the image will become distorted.

[0152] Therefore, one aspect of the present invention involves simultaneous imaging operation 12 in all rows as shown in Figure 10(B), and data A global shutter that can perform a holding operation 13 and a reading operation 14 for each row. It is preferable to use the formula. By using the global shutter method, each pixel of the imaging device Simultaneous imaging can be ensured, and distortion is minimized even when the subject is moving. Images can be easily obtained.

[0153] Furthermore, an OS transistor is a transistor that uses silicon in its active region or active layer (and Because the temperature dependence of electrical characteristics is smaller than that of a Si transistor (see below), it can operate over an extremely wide temperature range. It can be used within the range. Therefore, imaging devices and semiconductors having OS transistors The conductive device is also suitable for installation in automobiles, aircraft, spacecraft, and other applications.

[0154] Furthermore, OS transistors have a higher drain breakdown voltage than Si transistors. In photoelectric devices using selenium-based materials as the photoelectric conversion layer, the avalanche phenomenon is likely to occur. Therefore, it is preferable to apply a relatively high voltage (for example, 10V or more). Combining an S-transistor with a photoelectric conversion element using a selenium-based material as the photoelectric conversion layer. This allows for a highly reliable imaging device.

[0155] Note that in Figure 9(A), each transistor is shown as having a back gate. However, as shown in Figure 9(B), it may also be a configuration without a back gate. Also, Figure 9 As shown in (C), only some transistors, for example transistor 41, have a back gate. It may be in a form that has such a configuration. The back gate is provided opposite to the transit It may be electrically connected to the front gate of the tailgate. Alternatively, the tailgate may be electrically connected to the rear gate. A fixed potential different from that of the back gate may be supplied. This configuration can also be applied to other pixel configurations described in this embodiment.

[0156] The photoelectric conversion element PD provided in layer 1200 can be of various forms. Figure 9(A) illustrates a configuration in which a selenium-based material is used in the photoelectric conversion layer 561. Photoelectric converters (PDs) using this material exhibit high external quantum efficiency for visible light. Furthermore, selenium-based materials have a high light absorption coefficient, which has the advantage of making it easier to thin the photoelectric conversion layer 561. In photoelectric conversion elements (PDs) using selenium-based materials, incident light is absorbed by the avalanche phenomenon. This allows for a highly sensitive sensor with large electron amplification in response to light intensity. In other words, a selenium-based sensor. By using this material in the photoelectric conversion layer 561, sufficient photocurrent can be obtained even when the pixel area is reduced. This is possible. In addition, photoelectric converters (PDs) using selenium-based materials can be used for imaging in low-light environments. It can also be said that it is suitable.

[0157] As selenium-based materials, amorphous selenium or crystalline selenium can be used. For example, it can be obtained by heat-treating amorphous selenium after film formation. By making the crystal grain size of crystalline selenium smaller than the pixel pitch, the variation in characteristics from pixel to pixel is reduced. It can be reduced. Also, crystalline selenium has a greater spectral sensitivity to visible light than amorphous selenium. It possesses characteristics such as high intensity and high light absorption coefficient.

[0158] Although the photoelectric conversion layer 561 is shown as a single layer, holes are injected into the light-receiving surface side of the selenium-based material. A blocking layer such as gallium oxide or cerium oxide is provided, and electron injection blocking is applied to the electrode 566 side. The configuration can also include nickel oxide or antimony sulfide as a sealing layer.

[0159] Furthermore, the photoelectric conversion layer 561 was a layer containing a copper, indium, and selenium compound (CIS). Alternatively, a layer containing a copper, indium, gallium, and selenium compound (CIGS) may be used. It may be present. In CIS and CIGS, the avalanche phenomenon is advantageous, similar to that of elemental selenium. A usable photoelectric conversion element can be formed.

[0160] A photoelectric conversion element PD using a selenium-based material has electrodes 56 formed from, for example, a metal material. A configuration can be provided in which a photoelectric conversion layer 561 is located between 6 and the light-transmitting conductive layer 562. Furthermore, CIS and CIGS are p-type semiconductors, and the sulfidation of n-type semiconductors is necessary to form a junction. Cadmium or zinc sulfide may be provided in contact with the material.

[0161] In order to generate the avalanche phenomenon, a relatively high voltage (for example, 10) is applied to the photoelectric conversion element. It is preferable to apply a voltage of V or higher. OS transistors are more durable than Si transistors. Because it has high breakdown voltage characteristics, it is easy to apply relatively high voltages to the photoelectric conversion element. Therefore, an OS transistor with a high drain breakdown voltage and a selenium-based material for photoelectric conversion. By combining it with a layered photoelectric conversion element, a highly sensitive and reliable imaging device can be created. It is possible.

[0162] In Figure 9(A), the photoelectric conversion layer 561 and the light-transmitting conductive layer 562 are separated between the pixel circuits. Although this configuration does not involve separation between circuits, it is also possible to use a configuration that separates the circuits as shown in Figure 11(A). Furthermore, in the region between pixels where there is no electrode 566, an insulating partition 567 is provided. It is preferable to prevent cracks from forming in the photoelectric conversion layer 561 and the light-transmitting conductive layer 562. However, as shown in Figure 11(B), a configuration without a partition wall 567 is also possible. Also, as shown in Figure 9(A In this configuration, wiring 88 and conductor 81 are interposed between the light-transmitting conductive layer 562 and the wiring 87. Although this is illustrated, as shown in Figures 11(C) and (D), the translucent conductive layer 562 and the wiring 87 It may also be in a form of direct contact.

[0163] Furthermore, electrodes 566 and wiring 87, etc., may be multilayered. For example, as shown in Figure 12(A) In addition, the electrode 566 is made of two layers, conductive layer 566a and conductive layer 566b, and the wiring 87 is made of conductive layer It can consist of two layers: 87a and a conductive layer 87b. In the configuration shown in Figure 12(A), For example, conductive layers 566a and 87a may be formed using a low-resistance metal or the like, and conductive layer 566b and the conductive layer 87b are selected from metals or other materials that have good contact characteristics with the photoelectric conversion layer 561. It is preferable to form it in this way. By adopting such a configuration, the electrical characteristics of the photoelectric conversion element PD can be improved. It can be done. Also, some metals can be galvanically treated by contact with the translucent conductive layer 562. This can occur. Even if such a metal is used for the conductive layer 87a, the conductive layer 87b will still be involved. This can prevent galvanic corrosion.

[0164] For example, the conductive layers 566b and 87b may be made of molybdenum or tungsten. It is possible to do so. In addition, conductive layers 566a and 87a may contain, for example, aluminum. Lamination can be used, such as sandwiching titanium or aluminum between layers of titanium.

[0165] Furthermore, the insulating layer 82, etc., may be in a multilayer configuration. For example, as shown in Figure 12(B) Furthermore, the insulating layer 82 has insulating layer 82a and insulating layer 82b, and insulating layer 82a and insulating layer 8 If the etching rate, etc., differs from that of 2b, the conductor 81 will have a step. Similarly, when other insulating layers used in interinsulating films or planarizing films are multilayered, the conductor 81 is A step will be created. Note that here we have shown an example where the insulating layer 82 is two layers, but the insulating layer Layers 82 and other insulating layers may consist of three or more layers.

[0166] Furthermore, the partition wall 567 can be formed using an inorganic insulator or an insulating organic resin. Furthermore, the partition wall 567 is for shielding transistors, etc., and / or per pixel The area of ​​the light-receiving part may be colored black or another color to determine its size.

[0167] Furthermore, photoelectric conversion elements (PDs) use a pin-like structure with an amorphous silicon film or a microcrystalline silicon film. Diode elements such as type diodes may also be used.

[0168] For example, Figure 13 shows an example in which a pin-type thin-film photodiode is used as the photoelectric conversion element PD. The photodiode consists of an n-type semiconductor layer 565, an i-type semiconductor layer 564, and a p-type semiconductor layer. The semiconductor layer 563 of type i is stacked in order. It is preferable to use silicon. Also, p-type semiconductor layer 563 and n-type semiconductor layer 5 65 contains amorphous silicon or microcrystalline silicon containing dopants that impart each conductivity type. Recon and other materials can be used. A photodiode using amorphous silicon as the photoelectric conversion layer. It has high sensitivity in the visible light wavelength range and can easily detect weak visible light.

[0169] In the photoelectric conversion element PD shown in Figure 13, the n-type semiconductor layer 565 that acts as the cathode is It has an electrical connection with electrode 566 which has an electrical connection with transistor 41. The p-type semiconductor layer 563, acting as a wire, is electrically connected to the wiring 87 via the conductor 81. It has.

[0170] Note that, as shown in Figure 6(A), the connection configuration of the photoelectric conversion element PD is reversed from the orientation shown in Figure 3. This configuration is also acceptable. Therefore, in Figure 13, the anode of the photoelectric conversion element PD and In some cases, the connection configuration between the cathode, electrode layer, and wiring may be reversed.

[0171] In all cases, the p-type semiconductor layer 563 is configured to act as the light-receiving surface, and the photoelectric conversion element is configured accordingly. It is preferable to form a sub-PD. By using the p-type semiconductor layer 563 as the light-receiving surface, the photoelectric transform This allows for an increase in the output current of the photovoltaic converter (PD).

[0172] Furthermore, the configuration of the photoelectric conversion element PD having the form of a pin-type thin-film photodiode, and The connection configuration of the photoelectric conversion element PD and wiring is shown in Figures 14(A), (B), (C), and (D). Examples shown in (E) and (F) may also be used. Note that the configuration of the photoelectric conversion element PD and the photoelectric conversion element The connection configuration between the PD and the wiring is not limited to these and may be in other configurations.

[0173] Figure 14(A) shows the translucent conductive layer 562 in contact with the p-type semiconductor layer 563 of the photoelectric conversion element PD. The configuration includes the translucent conductive layer 562 acting as an electrode, and the output of the photoelectric conversion element PD. The current can be increased.

[0174] The translucent conductive layer 562 contains, for example, indium tin oxide, silicon-containing indium tin oxide. Indium oxide containing zinc, zinc oxide, zinc oxide containing gallium, aluminum Contains zinc oxide, tin oxide, fluorine-containing tin oxide, antimony-containing tin oxide, or graphite Materials such as n can be used. In addition, the translucent conductive layer 562 is not limited to a single layer, but can be made by laminating different films. That's fine too.

[0175] Figure 14(B) shows the electrical connection between the p-type semiconductor layer 563 and the wiring 88 of the photoelectric conversion element PD. It is a configuration that is directly possessed.

[0176] Figure 14(C) shows the translucent conductive layer 562 in contact with the p-type semiconductor layer 563 of the photoelectric conversion element PD. A wiring harness 87 and a light-transmitting conductive layer 562 are provided, and the wiring harness 87 and the light-transmitting conductive layer 562 have an electrical connection.

[0177] Figure 14(D) shows an opening where a p-type semiconductor layer 563 is exposed in the insulating layer covering the photoelectric conversion element PD. A section is provided, and the light-transmitting conductive layer 562 covering the opening and the wiring 88 have an electrical connection. It is structured.

[0178] Figure 14(E) shows a configuration in which a conductor 81 is provided that penetrates the photoelectric conversion element PD. In this configuration, the wiring 87 is electrically connected to the p-type semiconductor layer 563 via the conductor 81. In the drawing, the wiring 87 and electrode 566 appear to be connected via the n-type semiconductor layer 565. It shows a form that allows for electrical conductivity. However, the lateral resistance of the n-type semiconductor layer 565 Because the resistance is high, if an appropriate gap is provided between the wiring 87 and the electrode 566, the resistance between them will be extremely high. Therefore, the photoelectric conversion element PD does not short-circuit the anode and cathode. It can have diode characteristics. Furthermore, it is electrically connected to the p-type semiconductor layer 563. There may be multiple conductive elements 81.

[0179] Figure 14(F) shows the p-type semiconductor layer 563 in contact with the photoelectric conversion element PD in Figure 14(E). The structure includes a translucent conductive layer 562.

[0180] Furthermore, in the photoelectric conversion element PD shown in Figures 14(D), 14(E), and 14(F), Since the light-receiving area and wiring do not overlap, it has the advantage of being able to secure a large light-receiving area.

[0181] Furthermore, as shown in Figure 15, the photoelectric conversion element PD has a silicon substrate 600 as the photoelectric conversion layer. A photodiode can also be used.

[0182] The photoelectric conversion element PD formed using the aforementioned selenium-based material or amorphous silicon is a thin film. It is manufactured using common semiconductor fabrication processes such as lithography and etching. Furthermore, selenium-based materials have high resistance, and as shown in Figure 9(A), photoelectric transformation is possible. The switching layer 561 can also be configured not to be separated between circuits. Therefore, one aspect of the present invention The imaging device has a high yield and can be manufactured at low cost. On the other hand, the silicon substrate When forming a photodiode with 600 as the photoelectric conversion layer, polishing and bonding processes are required. This requires highly complex processes such as [specific steps / methods].

[0183] Furthermore, an imaging device according to one aspect of the present invention is provided in which a silicon substrate 600 on which a circuit is formed is stacked This configuration may also be used. For example, as shown in Figure 16(A), the active region is on the silicon substrate 600. Layer 1400 having transistors 610 and 620 overlaps with the pixel circuit. This configuration can be achieved. Note that Figure 16(B) shows a cross-section of the transistor in the channel width direction. This corresponds to a surface drawing.

[0184] Here, in Figures 16(A) and (B), the Si transistor is shown as an example of a fin-type configuration. However, a planar type may also be used, as shown in Figure 17(A). Or, Figure 17(B) As shown, the transistor may have an active layer 650 made of a silicon thin film. The active layer 650 is made of polycrystalline silicon or SOI (Silicon on Insulation). It can be a single crystal silicon of type r).

[0185] The circuit formed on the silicon substrate 600 has the function of reading out the signal output by the pixel circuit and the It can have functions to perform signal conversion processing, for example, as shown in Figure 17(C) The configuration can include a CMOS inverter as shown in the diagram. Transistor 610( The gates of the n-channel transistor and the p-channel transistor 620 are electrically connected. Also, one of the sources or drains of one transistor is connected to the source of the other transistor. It is electrically connected to either the source or the drain of both transistors. The other end of the drain is electrically connected to a separate wire.

[0186] The circuits formed on the silicon substrate 600 are, for example, circuits 23 and 24 shown in Figure 1. This corresponds to circuit 25, etc.

[0187] Furthermore, the silicon substrate 600 is not limited to bulk silicon substrates, but also germanium, silicon, and Lumanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphate It is also possible to use substrates made of gallium nitride or organic semiconductors.

[0188] Here, as shown in Figures 15 and 16(A), a transistor having an oxide semiconductor The region that is formed and the Si device (Si transistor or Si photodiode) An insulating layer 80 is provided between the region being formed and the surrounding area.

[0189] Water in the insulating layer provided near the active regions of transistors 610 and 620 The element terminates the dangling bond of silicon. Therefore, the hydrogen is in transistor 6. This has the effect of improving the reliability of transistors 10 and 620. On the other hand, transistor 4 Hydrogen in the insulating layer located near the oxide semiconductor layer, which is the first active layer, is in the oxide semiconductor It is one of the factors that generate carriers in the layer. Therefore, the hydrogen is used in transistor 41, etc. This can sometimes lead to a decrease in reliability. Therefore, when using silicon-based semiconductor materials... One layer has transistors, and the other layer has transistors made of oxide semiconductors. When stacking layers, an insulating layer 80 is provided between them to prevent hydrogen diffusion. Preferably, the insulating layer 80 traps hydrogen in one layer, thereby enabling the transistor 6 The reliability of transistors 10 and 620 can be improved. Also, from one layer to the other By suppressing the diffusion of hydrogen into the other layer, the reliability of transistors such as transistor 41 is also improved. It is possible.

[0190] Examples of insulating layer 80 include aluminum oxide, aluminum oxide nitride, and gallium oxide. Gallium oxide nitride, yttrium oxide, yttrium oxide nitride, hafnium oxide, oxide Hafnium nitride, yttria-stabilized zirconia (YSZ), etc., can be used.

[0191] In the configuration shown in Figure 16(A), the circuit formed on the silicon substrate 600 (for example) The drive circuit, transistor 41, etc., and photoelectric conversion element PD are formed to overlap. This allows for an increase in the density of pixels. In other words, the resolution of the imaging device can be increased. It can be increased. For example, imaging with a pixel count of 4k2k, 8k4k, or 16k8k. It is suitable for use in devices. Furthermore, the transistors 44, etc., of the pixel 20 are Si transistors. Formed by a st, the overlapping region of transistor 41, transistor 42, photoelectric conversion element PD, etc. It can also be configured to include a region.

[0192] Furthermore, an imaging device according to one embodiment of the present invention can have the configuration shown in Figure 18.

[0193] The imaging device shown in Figure 18 is a modified version of the imaging device shown in Figure 16(A), and OS Transis An example of a CMOS inverter constructed using t-transistors and Si transistors is illustrated.

[0194] Here, the Si transistor 620 provided in layer 1400 is of the p-channel type. Furthermore, the OS transistor 610 provided in layer 1100 is of the n-channel type. By providing only p-channel transistors on the silicon substrate 600, well formation and n-channel transistors can be achieved. This eliminates the need for processes such as impurity layer formation.

[0195] Note that the imaging device shown in Figure 18 is an example in which selenium or the like is used as the photoelectric conversion element PD. A configuration using a pin-type thin-film photodiode may also be used, similar to configuration 13.

[0196] In the imaging device shown in Figure 18, the transistor 610 is a transistor formed in layer 1100 It can be manufactured using the same process as the st 41 and transistor 42. The manufacturing process for the imaging device can be simplified.

[0197] Furthermore, as shown in Figure 19, an imaging device according to one aspect of the present invention is formed on a silicon substrate 660 A pixel composed of a photoelectric conversion element PD and an OS transistor formed on it. This configuration may be used in which a silicon substrate 600 on which a circuit is formed is bonded together. By adopting this configuration, the effective performance of the photoelectric conversion element PD formed on the silicon substrate 660 It becomes easier to improve the surface area. Also, it becomes easier to miniaturize the circuits formed on the silicon substrate 600. By highly integrating these Si transistors, high-performance semiconductor devices can be provided. .

[0198] Furthermore, as a modified example of Figure 19, as shown in Figures 20 and 21, an OS transistor and The circuit may also be constructed using Si transistors. This makes it easy to improve the effective area of ​​the photoelectric conversion element PD formed on the silicon substrate 660. Furthermore, the circuits formed on the silicon substrate 600 are miniaturized Si transistors for high concentration. By using integration technology, high-performance semiconductor devices can be provided.

[0199] In the configuration shown in Figure 20, the OS transistor and Si transistor are located on the silicon substrate 600. CMOS circuits can be constructed using these transistors. OS transistors have extremely low off-currents. Therefore, it is possible to construct a CMOS circuit with extremely low static leakage current.

[0200] In the configuration shown in Figure 21, the OS transistor and silicon substrate 660 are on the silicon substrate 6 A CMOS circuit can be constructed using Si transistors on top of the 00.

[0201] The configuration of the transistors and photoelectric conversion elements in the imaging device in this embodiment is as follows: This is just one example. Therefore, for example, any of transistors 41 to 45, Alternatively, one or more transistors may be constructed with silicon or the like in their active region or active layer. It is also possible to activate both or either transistor 610 and transistor 620. It can also be constructed using a transistor with an oxide semiconductor layer.

[0202] Figure 22(A) is a cross-sectional view of an example of an imaging device with a color filter and the like added. The cross-sectional view shows a portion of the region having a pixel circuit for 3 pixels. The photoelectric conversion element PD is An insulating layer 2500 is formed on the layer 1200 that is formed. The insulating layer 2500 is visible to light. In contrast, highly light-transmitting silicon oxide films can be used. Also, passivation A configuration in which silicon nitride films are laminated as the film may also be used. Alternatively, as the anti-reflective film, A configuration in which dielectric films such as humic acid are stacked may also be used.

[0203] A light-shielding layer 2510 may be formed on the insulating layer 2500. The light-shielding layer 2510 is on top It has the function of preventing the mixing of colors of light passing through the color filter. The light-shielding layer 2510 is made of aluminum Metal layers such as um and tungsten, or dielectrics that function as an anti-reflective coating with the said metal layers. A configuration in which multiple films are stacked can be used.

[0204] An organic resin layer 2520 is provided on the insulating layer 2500 and the light-shielding layer 2510 as a planarizing film. It can be configured as follows. Also, a color filter 2530 (color filter 25 30a, color filter 2530b, color filter 2530c) are formed. , color filter 2530a, color filter 2530b and color filter 2530 c can represent R (red), G (green), B (blue), Y (yellow), C (cyan), M (magenta), etc. By assigning colors, a color image can be obtained.

[0205] A light-transmitting insulating layer 2560 or the like can be provided on the color filter 2530. ru.

[0206] Also, as shown in Figure 22(B), instead of the color filter 2530, the optical conversion layer 255 You may also use 0. With this configuration, images can be obtained in various wavelength ranges. It can be used as an imaging device.

[0207] For example, if a filter that blocks light with wavelengths below visible light is used in the optical conversion layer 2550, infrared It can be used as an imaging device. Furthermore, the optical conversion layer 2550 blocks light with wavelengths below near-infrared. By using a filter, it can be made into a far-infrared imaging device. Also, the optical conversion layer 2550 By using a filter that blocks light with wavelengths greater than visible light, it can be converted into an ultraviolet imaging device. .

[0208] Furthermore, if a scintillator is used in the optical conversion layer 2550, radiation can be used in X-ray imaging devices, etc. An imaging device capable of obtaining an image visualizing the intensity of lines can be used. X-rays or the like that have passed through a subject When radiation such as this enters a scintillator, it is converted into light (fluorescence) such as visible light or ultraviolet light by a phenomenon called photoluminescence. Then, image data is acquired by detecting the light with a photoelectric conversion element PD. Further, an imaging device having such a configuration may be used for a radiation detector or the like. The scintillator is made of a substance that emits visible light or ultraviolet light by absorbing the energy when irradiated with radiation such as X-rays or gamma rays, or a material containing the substance. For example, materials such as Gd2O 2S:Tb, Gd2O2S:Pr, Gd2O2S:Eu, BaFCl:Eu, NaI, C sI, CaF2, BaF2, CeF3, LiF, LiI, ZnO, etc., or those dispersed in resins or ceramics can be used.

[0209] In a photoelectric conversion element PD using a selenium-based material, since radiation such as X-rays can be directly converted into charges, a configuration that does not require a scintillator can also be adopted. Furthermore, as shown in Fig. 22(C), a microlens array 2540 may be provided on color filters 2530a, color filters 2530 b, and color filters 2530c. Light passing through the individual lenses of the microlens array 2540 passes through the color filter directly below and is irradiated onto the photoelectric conversion element PD. Note that regions other than the layer 1200 shown in Figs. 22(A), (B), and (C) are defined as layer 1600. Fig. 23 shows pixel 20 of one aspect of the present invention and microlens array 2 shown in Fig. 22(C). <000已翻译内容1632>

[0211]

[0212] 5>

[0212] This figure illustrates specific layering configurations such as 540. Note that Figure 23 is shown in Figure 16(A). This is an example using the pixel configuration. When using the pixels shown in Figure 20, the configuration is as shown in Figure 24. It will come to fruition.

[0213] Thus, the photoelectric conversion element PD, the transistor or capacitor that constitutes the circuit of the pixel 20 Since each of the quantitative elements can be configured to have overlapping regions, the imaging device The device can be made smaller.

[0214] Furthermore, as shown in Figures 23 and 24, a diffraction grating is located above the microlens array 2540. A configuration with 1500 is also possible. Image of the subject through the diffraction grating 1500 (diffraction image) The image is captured into a pixel, and the input image (image of the subject) is calculated from the captured image at the pixel. It can be configured. Also, by using a diffraction grating 1500 instead of a lens, the imaging device Installation costs can be reduced.

[0215] The diffraction grating 1500 can be formed from a translucent material. For example, silicone oxide Inorganic insulating films such as silicon oxide nitride films can be used. Alternatively, acrylic resin can be used. Organic insulating films such as lipids and polyimide resins may be used. Alternatively, the above inorganic insulating film and It may also be laminated with an insulating film.

[0216] Furthermore, the diffraction grating 1500 can be formed by a lithography process using a photosensitive resin or the like. Yes, it is possible. It can also be formed using lithography and etching processes. Furthermore, it can also be formed using nanoimprint lithography or laser scribing. ru.

[0217] A gap X may be provided between the diffraction grating 1500 and the microlens array 2540. The interval X can be 1 mm or less, preferably 100 μm or less. The separation may be a space, or a light-transmitting material may be provided as a sealing layer or adhesive layer. For example, inert gases such as nitrogen or noble gases can be contained within that interval. Alternatively, Acrylic resin, epoxy resin, or polyimide resin may be provided at the intervals. A liquid such as silicone oil may be provided. Furthermore, a microlens array 2540 is provided. Even if this is not the case, a gap X is provided between the color filter 2530 and the diffraction grating 1500. You may leave it.

[0218] Furthermore, the imaging device may be curved as shown in Figures 25(A1) and 25(B1). Figure 25(A1) shows the imaging device curved in the direction of the dashed line X1-X2 in the figure. This is shown. Figure 25(A2) shows the area indicated by the dashed line X1-X2 in Figure 25(A1). This is a cross-sectional view. Figure 25(A3) shows the area indicated by the dashed line Y1-Y2 in Figure 25(A1). This is a cross-section.

[0219] Figure 25(B1) shows the imaging device curved in the direction of the dashed line X3-X4 in the figure, and The diagram shows the curved state in the direction of the dashed line Y3-Y4. Figure 25(B2) is a diagram. This is a cross-sectional view of the area indicated by the dashed line X3-X4 in 25(B1). Figure 25(B3) is This is a cross-sectional view of the area indicated by the dashed line Y3-Y4 in Figure 25(B1).

[0220] By curving the imaging device, image field curvature and astigmatism can be reduced. This facilitates the optical design of lenses and other components used in combination with imaging devices. For example, This allows for a reduction in the number of lenses required for aberration correction, thus enabling miniaturization of electronic devices using imaging equipment. It can also be made lighter. Furthermore, it can improve the quality of the captured images. ru.

[0221] In this embodiment, one aspect of the present invention has been described. Or, other embodiments may be described. In this section, one aspect of the present invention will be described. However, this aspect of the present invention is not limited to these. It is not possible. In other words, various aspects of the invention are described in this embodiment and other embodiments. Therefore, one aspect of the present invention is not limited to a specific aspect. For example, one aspect of the present invention and An example of its application to an imaging device has been shown, but one aspect of the present invention is not limited thereto. In some cases, or depending on the circumstances, one aspect of the present invention may not be applied to an imaging device. This is also possible. For example, one aspect of the present invention may be applied to a semiconductor device having a different function. Example For example, in one aspect of the present invention, the channel formation region and source-drain region of a transistor Although examples of cases having oxide semiconductors have been shown, one aspect of the present invention is not limited thereto. In some cases, or depending on the circumstances, various transitions in one aspect of the present invention The channel formation region of a transistor, or the source-drain region of a transistor, etc. The present invention may have various semiconductors. Depending on the circumstances, the present invention may be used in some cases or situations. Various transistors, channel formation regions of transistors, or transistors in one embodiment The source and drain regions of a converter are, for example, made of silicon, germanium, or silicon gel. Manium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphate, It may have at least one of the following: gallium nitride, or an organic semiconductor. Or, for example... For example, depending on the circumstances, or depending on the situation, various transitions in one aspect of the present invention The channel formation region of a transistor, or the source-drain region of a transistor. These do not necessarily have to contain an oxide semiconductor.

[0222] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is the case.

[0223] (Embodiment 2) In this embodiment, a transient having an oxide semiconductor that can be used in one aspect of the present invention The sta will be explained using drawings. Note that in the drawings of this embodiment, for clarity, Some elements are enlarged, reduced, or omitted in the illustration for illustrative purposes.

[0224] Figures 26(A) and (B) show a top view and a cross-sectional view of a transistor 101 according to one embodiment of the present invention. Yes. Figure 26(A) is a top view, and the cross section is in the direction of the dashed line B1-B2 shown in Figure 26(A). This corresponds to Figure 26(B). Also, the cross section in the direction of the dashed line B3-B4 shown in Figure 26(A) is This corresponds to Figure 28(A). Also, the direction of the dashed line B1-B2 is the channel length direction, and the dashed line B The 3-B4 direction is referred to as the channel width direction.

[0225] The transistor 101 has an insulating layer 120 that is in contact with the substrate 115, and an oxide layer that is in contact with the insulating layer 120. A monocrystalline semiconductor layer 130, a conductive layer 140 that is electrically connected to the oxide semiconductor layer 130, and a conductive Layer 150, oxide semiconductor layer 130, conductive layer 140, and insulating layer 1 in contact with conductive layer 150 60, conductive layer 170 in contact with insulating layer 160, conductive layer 140, conductive layer 150, insulating layer 1 60 and an insulating layer 175 in contact with the conductive layer 170, and an insulating layer 180 in contact with the insulating layer 175 , and also, if necessary, the insulating layer 180 may be given the function of a planarizing film. .

[0226] Here, the conductive layer 140 is the source electrode layer, the conductive layer 150 is the drain electrode layer, and the insulating layer 160 is The gate insulating film and the conductive layer 170 can each function as a gate electrode layer.

[0227] Furthermore, region 231 shown in Figure 26(B) is the source region, region 232 is the drain region, and region 2 Region 33 can function as a channel-forming region. Regions 231 and 232 are guided The conductive layer 140 and the conductive layer 150 are in contact with each other, and the conductive layer 140 and the conductive layer 150 By using a conductive material that readily bonds with oxygen, the resistance of regions 231 and 232 can be reduced. It is possible.

[0228] Specifically, the oxide semiconductor layer 130 and the conductive layer 140 and conductive layer 150 come into contact with each other. Oxygen vacancies occur within the oxide semiconductor layer 130, and these oxygen vacancies remain within the oxide semiconductor layer 130. Due to interactions with hydrogen that is either distilled or diffused from the outside, regions 231 and 232 have low resistance. It becomes an n-type resistance.

[0229] Furthermore, the "source" and "drain" functions of a transistor are related to transistors with different polarities. When adopting a circuit, or when the direction of current changes during circuit operation, the configuration may be reversed. Therefore, in this specification, the terms "source" and "drain" are interchangeable. It may be used in this manner. Also, "electrode layer" can be replaced with "wiring." can.

[0230] Furthermore, the diagram illustrates an example in which the conductive layer 170 is formed of two layers, conductive layer 171 and conductive layer 172. However, it may be a single layer or a stack of three or more layers. This configuration will be explained in this embodiment. This can also be applied to other transistors.

[0231] Furthermore, although the diagram shows examples where the conductive layer 140 and conductive layer 150 are formed as a single layer, two or more layers are also shown. The above stacking may also be used. This configuration is also applicable to other transistors described in this embodiment. can.

[0232] Furthermore, a transistor according to one aspect of the present invention may have the configuration shown in Figures 26(C) and (D). Figure 26(C) is a top view of transistor 102, and the dashed line C shown in Figure 26(C) The cross-section in the direction of 1-C2 corresponds to Figure 26(D). Also, the dashed line C3 shown in Figure 26(C) -The cross-section in the C4 direction corresponds to Figure 28(B). Also, the dashed line C1-C2 direction is channeled The direction of the channel length and the direction of the dashed line C3-C4 are referred to as the channel width direction.

[0233] The transistor 102 has an insulating layer 160 that acts as a gate insulating film and a gate electrode layer. Except for the fact that it does not coincide with the edge of the conductive layer 170 which acts as a transistor, it is the same as transistor 101. It has the following configuration. The structure of transistor 102 is such that conductive layer 140 and conductive layer 150 are insulated Because it is broadly covered by the edge layer 160, the conductive layer 140 and conductive layer 150 and conductive layer 170 It has the characteristic of high resistance between the terminals and low gate leakage current.

[0234] Transistors 101 and 102 have conductive layers 170 and 140 and This is a top gate structure having a region where the electrochemical layer 150 overlaps. The width is preferably 3 nm or more and less than 300 nm in order to reduce parasitic capacity. In this configuration, since no offset region is formed in the oxide semiconductor layer 130, the on-current is high It is easy to form transistors.

[0235] Furthermore, a transistor according to one aspect of the present invention may have the configuration shown in Figures 26(E) and (F). Figure 26(E) is a top view of transistor 103, and the dashed line D shown in Figure 26(E) The cross-section in the 1-D2 direction corresponds to Figure 26(F). Also, the dashed line D3 shown in Figure 26(E) -The cross-section in the D4 direction corresponds to Figure 28(A). Also, the dashed line D1-D2 direction is channeled The direction of the channel length and the direction of the dashed line D3-D4 are referred to as the channel width direction.

[0236] Transistor 103 has an insulating layer 120 in contact with the substrate 115 and an oxide layer in contact with the insulating layer 120. A material semiconductor layer 130, an insulating layer 160 in contact with the oxide semiconductor layer 130, and an insulating layer 160 in contact with The conductive layer 170, the oxide semiconductor layer 130, the insulating layer 160, and the insulating layer covering the conductive layer 170 are all connected. Edge layer 175, insulating layer 180 in contact with insulating layer 175, insulating layer 175 and insulating layer 180 A conductive layer 140 is electrically connected to the oxide semiconductor layer 130 through an opening provided therein. It also has a conductive layer 150. Furthermore, an insulating layer 180, a conductive layer 140, and a conductive layer may be added as needed. It may have an insulating layer (planarized film) in contact with 150.

[0237] Here, the conductive layer 140 is the source electrode layer, the conductive layer 150 is the drain electrode layer, and the insulating layer 160 is The gate insulating film and the conductive layer 170 can each function as a gate electrode layer.

[0238] Furthermore, region 231 shown in Figure 26(F) is the source region, region 232 is the drain region, and region 2 Region 33 can function as a channel-forming region. Regions 231 and 232 are absolute It is in contact with the edge layer 175, and if, for example, an insulating material containing hydrogen is used as the insulating layer 175, the region Regions 231 and 232 can be made to have lower resistance.

[0239] Specifically, the process up to forming the insulating layer 175 generates in regions 231 and 232 The interaction between the oxygen deficiency and the hydrogen diffusing from the insulating layer 175 to regions 231 and 232 As a result of this action, regions 231 and 232 become low-resistance n-type. Note that this is an insulating material containing hydrogen. Materials such as silicon nitride and aluminum nitride can be used.

[0240] Furthermore, a transistor according to one aspect of the present invention may have the configuration shown in Figures 27(A) and (B). Figure 27(A) is a top view of transistor 104, and the dashed line E shown in Figure 27(A) The cross-section in the direction of 1-E2 corresponds to Figure 27(B). Also, the dashed line E3 shown in Figure 27(A) -The cross-section in the E4 direction corresponds to Figure 28(A). Also, the dashed line E1-E2 direction is channeled The direction of the channel length and the direction of the dashed line E3-E4 are referred to as the channel width direction.

[0241] Transistor 104 has conductive layers 140 and 150 at the edges of oxide semiconductor layer 130. Except for the fact that it is in contact with the other element in a way that covers it, it has the same configuration as transistor 103.

[0242] Furthermore, regions 331 and 334 shown in Figure 27(B) are the source region, region 332 and Region 335 can function as a drain region, and region 333 can function as a channel-forming region. .

[0243] Regions 331 and 332 correspond to regions 231 and 23 in transistor 101. Similar to method 2, the resistance can be reduced.

[0244] Furthermore, regions 334 and 335 are regions 231 and region 335 in transistor 103. Similar to region 232, resistance can be reduced. Note that region 334 in the channel length direction And when the width of region 335 is 100 nm or less, preferably 50 nm or less, the gate electric Due to the field's contribution, the on-current does not decrease significantly. Therefore, regions 334 and 335 In some cases, the resistance reduction is not performed.

[0245] Transistors 103 and 104 have conductive layers 170 and 140 and It is a self-aligned structure in which the electrolytic layer 150 does not have any overlapping regions. The lampistor has extremely low parasitic capacitance between the gate electrode layer and the source and drain electrode layers. Therefore, it is suitable for high-speed operation applications.

[0246] Furthermore, a transistor according to one aspect of the present invention may have the configuration shown in Figures 27(C) and (D). Figure 27(C) is a top view of transistor 105, and the dashed line F shown in Figure 27(C) The cross-section in the 1-F2 direction corresponds to Figure 27(D). Also, the dashed line F3 shown in Figure 27(C) -The cross-section in the F4 direction corresponds to Figure 28(A). Also, the dashed line F1-F2 direction is channeled. The direction of the channel length and the direction of the dashed line F3-F4 are referred to as the channel width direction.

[0247] Transistor 105 has an insulating layer 120 in contact with the substrate 115 and an oxide layer in contact with the insulating layer 120. A monocrystalline semiconductor layer 130, a conductive layer 141 that is electrically connected to the oxide semiconductor layer 130, and a conductive Layer 151, oxide semiconductor layer 130, conductive layer 141, insulating layer 160 in contact with conductive layer 151 And, a conductive layer 170 in contact with the insulating layer 160, an oxide semiconductor layer 130, a conductive layer 141, and a conductive layer. An insulating layer 175 that is in contact with layer 151, insulating layer 160 and conductive layer 170, and an insulating layer 175 that is in contact with The insulating layer 180 and the insulating layer 175 and the insulating layer 180 are conductive through openings provided in them. Conductive layers 142 and 15 are electrically connected to layer 141 and conductive layer 151, respectively. It has 2. It also comes into contact with the insulating layer 180, the conductive layer 142 and the conductive layer 152 as needed. It may have an insulating layer or the like.

[0248] Here, conductive layers 141 and 151 are in contact with the upper surface of the oxide semiconductor layer 130, and the sides The configuration is designed so that it does not come into contact with anything.

[0249] The transistor 105 has conductive layers 141 and 151, and insulating layers 175 and The insulating layer 180 has an opening, and the conductive layer 14 is accessible through the opening. It has conductive layers 142 and 152 that are electrically connected to conductive layer 151 and conductive layer 151, respectively. It has the same configuration as transistor 101, except for the following point. Conductive layer 140 (conductive layer 141 The conductive layer 142) can be used as a source electrode layer, and the conductive layer 150 (conductive Layer 151 and conductive layer 152 can be used as drain electrode layers.

[0250] Furthermore, a transistor according to one aspect of the present invention may have the configuration shown in Figures 27(E) and (F). Figure 27(E) is a top view of transistor 106, and the dashed line G shown in Figure 27(E) The cross-section in the 1-G2 direction corresponds to Figure 27(F). Also, the dashed line G3 shown in Figure 27(A) -The cross-section in the G4 direction corresponds to Figure 28(A). Also, the dashed line G1-G2 direction is channeled. The direction of the channel length and the direction of the dashed line G3-G4 are referred to as the channel width direction.

[0251] Transistor 106 has an insulating layer 120 that is in contact with the substrate 115 and an oxide layer that is in contact with the insulating layer 120. A monocrystalline semiconductor layer 130, a conductive layer 141 that is electrically connected to the oxide semiconductor layer 130, and a conductive Layer 151, an insulating layer 160 in contact with the oxide semiconductor layer 130, and a conductive layer in contact with the insulating layer 160. Layer 170, insulating layer 120, oxide semiconductor layer 130, conductive layer 141, conductive layer 151, insulating An insulating layer 175 in contact with layer 160, conductive layer 170, and an insulating layer 180 in contact with insulating layer 175. Through openings provided in the insulating layer 175 and the insulating layer 180, the conductive layer 141 and the conductive It has conductive layers 142 and 152 that are electrically connected to layer 151, respectively. If necessary, an insulating layer (planarized film) in contact with the insulating layer 180, conductive layer 142, and conductive layer 152. They may also have, etc.

[0252] Here, conductive layers 141 and 151 are in contact with the upper surface of the oxide semiconductor layer 130, and the sides The configuration is designed so that it does not come into contact with anything.

[0253] Transistor 106 has conductive layers 141 and 151, except that the transistor It has the same configuration as Ta 103. The conductive layer 140 (conductive layer 141 and conductive layer 142) is - It can be used as an electrode layer, conductive layer 150 (conductive layer 151 and conductive layer 15 2) can be used as a drain electrode layer.

[0254] In the configuration of transistors 105 and 106, conductive layer 140 and conductive layer 1 Since 50 is not in contact with the insulating layer 120, oxygen in the insulating layer 120 enters the conductive layer 140. Furthermore, it becomes less likely for the conductive layer 150 to absorb acid, and acid from the insulating layer 120 into the oxide semiconductor layer 130 This makes it easier to supply raw materials.

[0255] Regions 231 and 232 in transistor 103, transistor 104 and Regions 334 and 335 in the lampistor 106 form oxygen vacancies and improve conductivity. Impurities may be added to enhance the properties. These impurities may form oxygen vacancies in the oxide semiconductor layer. For example, phosphorus, arsenic, antimony, boron, aluminum, silicon, nitrogen, helical Um, neon, argon, krypton, xenon, indium, fluorine, chlorine, titanium, One or more elements selected from zinc and carbon may be used. Methods of adding include plasma treatment, ion implantation, ion doping, and plasma treatment. Methods such as Merjohn ion implantation can be used.

[0256] When the above elements are added to the oxide semiconductor layer as impurity elements, the metal in the oxide semiconductor layer The bonds between elements and oxygen are broken, and an oxygen vacancy is formed. Due to the interaction between elementary defects and hydrogen remaining in or later added in the oxide semiconductor layer, The conductivity of the semiconductor layer can be increased.

[0257] When hydrogen is added to an oxide semiconductor in which oxygen vacancies have been formed by the addition of impurity elements, oxygen vacancies are formed. Hydrogen enters the loss site and a donor level is formed near the conduction band. As a result, the oxide conductor It can be formed. Here, an oxide semiconductor that has been made conductive is called an oxide conductor. Furthermore, oxide conductors, like oxide semiconductors, are translucent.

[0258] Oxide conductors are degenerate semiconductors in which the conduction band edge and the Fermi level coincide or nearly coincide. It is presumed that there is an oxide conductor layer, a source electrode layer and a drain electrode layer. The contact with the conductive layer that functions is ohmic contact, and the oxide conductive layer and the source electrode layer This reduces the contact resistance with the conductive layer that functions as the drain electrode layer.

[0259] Furthermore, a transistor according to one aspect of the present invention is shown in Figures 29(A), (B), (C), (D), (E) ), (F) shown are cross-sectional views in the channel length direction, and the channels shown in Figures 28(C) and (D) As shown in the cross-sectional view in the width direction, a conductive layer 173 is placed between the oxide semiconductor layer 130 and the substrate 115. It may be provided. The conductive layer may be used as a second gate electrode layer (back gate). This allows for increasing the on-current and controlling the threshold voltage. (See Figure 29(A)) In the cross-sectional views shown in (B), (C), (D), (E), and (F), the width of the conductive layer 173 is acid The width of the conductive layer 173 may be shorter than that of the conductive layer 170. It can be made shorter than the width.

[0260] To increase the ON current, for example, the conductive layer 170 and conductive layer 173 are set to the same potential, double It can be driven as a gate transistor. Also, to control the threshold voltage, A constant potential different from that of the conductive layer 170 should be supplied to the conductive layer 173. To make 73 at the same potential, for example, as shown in Figure 28(D), conductive layer 170 and conductive layer 1 73 can be electrically connected via the contact hole.

[0261] Furthermore, in transistors 101 to 106 in Figures 26 and 27, acid Although an example where the oxide semiconductor layer 130 is a single layer is shown, the oxide semiconductor layer 130 is stacked. This is also acceptable. The oxide semiconductor layer 130 of transistors 101 to 106 is shown in Figure 30. (B), (C) or Figure 30(D), (E) can be replaced with the oxide semiconductor layer 130 shown. It is possible.

[0262] Figure 30(A) is a top view of the oxide semiconductor layer 130, and Figures 30(B) and (C) show the two-layer structure. This is a cross-sectional view of the oxide semiconductor layer 130, which is constructed in a three-layer structure. Figures 30(D) and (E) show the three-layer structure. This is a cross-sectional view of the oxide semiconductor layer 130.

[0263] In oxide semiconductor layer 130a, oxide semiconductor layer 130b, and oxide semiconductor layer 130c, Oxide semiconductor layers with different compositions can be used.

[0264] Furthermore, a transistor according to one aspect of the present invention may have the configuration shown in Figures 31(A) and (B). Figure 31(A) is a top view of transistor 107, and the dashed line H shown in Figure 31(A) The cross-section in the 1-H2 direction corresponds to Figure 31(B). Also, the dashed line H3 shown in Figure 31(A) -The cross-section in the H4 direction corresponds to Figure 33(A). Also, the dashed line H1-H2 direction is channeled. The direction in the longitudinal direction, and the direction of the dashed line H3-H4, are referred to as the channel width direction.

[0265] Transistor 107 has an insulating layer 120 that is in contact with the substrate 115, and an oxide layer that is in contact with the insulating layer 120. A stack consisting of a monocrystalline semiconductor layer 130a and an oxide semiconductor layer 130b, and electrically connected to the stack Connecting conductive layer 140 and conductive layer 150, and the laminate, conductive layer 140 and conductive layer 15 The oxide semiconductor layer 130c in contact with 0, and the insulating layer 160 in contact with the oxide semiconductor layer 130c , conductive layer 170 in contact with insulating layer 160, conductive layer 140, conductive layer 150, oxide semiconductor layer 130c, an insulating layer 175 in contact with the insulating layer 160 and the conductive layer 170, and an insulating layer 175 in contact with It has an insulating layer 180 and, if necessary, a planarizing film as a functional You may add the ability.

[0266] In transistor 107, the oxide semiconductor layer 130 is divided into two regions 231 and 232. In region 233, where the layers are oxide semiconductor layer 130a and oxide semiconductor layer 130b The oxide semiconductor layer 130 consists of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide The point is that it is a semiconductor layer 130c), and conductive layer 140 and conductive layer 150 and insulating layer 160 Except for the fact that a portion of the oxide semiconductor layer (oxide semiconductor layer 130c) is interposed between them, It has the same configuration as the Ranjista 101.

[0267] Furthermore, a transistor according to one aspect of the present invention may have the configuration shown in Figures 31(C) and (D). Figure 31(C) is a top view of transistor 108, and the dashed line I shown in Figure 31(C) The cross-section in the 1-I2 direction corresponds to Figure 31(D). Also, the dashed line I3 shown in Figure 31(C) -The cross-section in the I4 direction corresponds to Figure 33(B). Also, the dashed line I1-I2 direction is the channel. The direction in the longitudinal direction, and the direction of the dashed line I3-I4, are referred to as the channel width direction.

[0268] The transistor 108 has an insulating layer 160 and an oxide semiconductor layer 130c, with the edges connected to the conductive layer 17. It differs from transistor 107 in that its terminals do not coincide with the zero point.

[0269] Furthermore, a transistor according to one aspect of the present invention may have the configuration shown in Figures 31(E) and (F). Figure 31(E) is a top view of transistor 109, and the dashed line J shown in Figure 31(E) The cross-section in the direction of 1-J2 corresponds to Figure 31(F). Also, the dashed line J3 shown in Figure 31(E) -The cross-section in the J4 direction corresponds to Figure 33(A). Also, the dashed line J1-J2 direction is the channel. The direction in the longitudinal direction, and the direction of the dashed line J3-J4, are referred to as the channel width direction.

[0270] The transistor 109 has an insulating layer 120 that is in contact with the substrate 115, and an oxide layer that is in contact with the insulating layer 120. A stack consisting of a monocrystalline semiconductor layer 130a and an oxide semiconductor layer 130b, and an acid in contact with the stack. A oxide semiconductor layer 130c, an insulating layer 160 in contact with the oxide semiconductor layer 130c, and an insulating layer 16 A conductive layer 170 in contact with 0, the laminate, oxide semiconductor layer 130c, insulating layer 160 and conductive An insulating layer 175 covering the electrical layer 170, an insulating layer 180 in contact with the insulating layer 175, and the insulating layer 175 and conductive layer 14 which is electrically connected to the laminate through an opening provided in the insulating layer 180. It has a conductive layer 150 and an insulating layer 180, conductive layer 140 and as needed. The conductive layer 150 may have an insulating layer (planarized film) or the like in contact with it.

[0271] In transistor 109, the oxide semiconductor layer 130 is divided into two regions 231 and 232. In region 233, where the layers are oxide semiconductor layer 130a and oxide semiconductor layer 130b The oxide semiconductor layer 130 consists of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide It has the same configuration as transistor 103, except that it is a physical semiconductor layer 130c.

[0272] Furthermore, a transistor according to one aspect of the present invention may have the configuration shown in Figures 32(A) and (B). Figure 32(A) is a top view of transistor 110, and the dashed line K shown in Figure 32(A) The cross-section in the 1-K2 direction corresponds to Figure 32(B). Also, the dashed line K3 shown in Figure 32(A) -The cross-section in the K4 direction corresponds to Figure 33(A). Also, the dashed line K1-K2 direction is the channel. The direction in the longitudinal direction, along the dashed line K3-K4, is referred to as the channel width direction.

[0273] In transistor 110, the oxide semiconductor layer 130 is divided into two regions 331 and 332. In region 333, where the layers are oxide semiconductor layer 130a and oxide semiconductor layer 130b The oxide semiconductor layer 130 consists of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide It has the same configuration as transistor 104, except that it is a solid semiconductor layer (130c).

[0274] Furthermore, a transistor according to one aspect of the present invention may have the configuration shown in Figures 32(C) and (D). Figure 32(C) is a top view of transistor 111, and the dashed line K shown in Figure 32(C) The cross-section in the 1-K2 direction corresponds to Figure 32(D). Also, the dashed line K3 shown in Figure 32(C) -The cross-section in the K4 direction corresponds to Figure 33(A). Also, the dashed line K1-K2 direction is the channel. The direction in the longitudinal direction, along the dashed line K3-K4, is referred to as the channel width direction.

[0275] The transistor 111 has an insulating layer 120 that is in contact with the substrate 115, and an oxide layer that is in contact with the insulating layer 120. A stack consisting of a monocrystalline semiconductor layer 130a and an oxide semiconductor layer 130b, and electrically connected to the stack Connecting conductive layers 141 and 151, and the laminate, conductive layer 141 and conductive layer 15 A 1 oxide semiconductor layer 130c in contact with 1, and an insulating layer 160 in contact with the oxide semiconductor layer 130c. , conductive layer 170 in contact with insulating layer 160, said lamination, conductive layer 141, conductive layer 151, oxidation A semiconductor layer 130c, an insulating layer 160, and an insulating layer 175 in contact with the conductive layer 170, and an insulating layer The insulating layer 180 is in contact with 175, and the openings provided in the insulating layer 175 and the insulating layer 180 Conductive layers 142 and 151 are electrically connected through conductive layer 141 and conductive layer 151, respectively. It has a conductive layer 152. Additionally, an insulating layer 180, a conductive layer 142, and a conductive layer 1 may be provided as needed. It may have an insulating layer (planarized film) or the like in contact with 52.

[0276] In transistor 111, the oxide semiconductor layer 130 is divided into two regions 231 and 232. In region 233, where the layers are oxide semiconductor layer 130a and oxide semiconductor layer 130b The oxide semiconductor layer 130 consists of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide The fact that it is a semiconductor layer 130c), and that it is a conductive layer 141 and a conductive layer 151 and an insulating layer 16 Except for the fact that a portion of the oxide semiconductor layer (oxide semiconductor layer 130c) is interposed between it and 0, It has the same configuration as transistor 105.

[0277] Furthermore, a transistor according to one aspect of the present invention may have the configuration shown in Figures 32(E) and (F). Figure 32(E) is a top view of transistor 112, and the dashed line M shown in Figure 32(E) The cross-section in the 1-M2 direction corresponds to Figure 32(F). Also, the dashed line M3 shown in Figure 32(E) -The cross-section in the M4 direction corresponds to Figure 33(A). Also, the dashed line M1-M2 direction is the channel. The direction in the longitudinal direction, and the direction of the dashed line M3-M4, are referred to as the channel width direction.

[0278] Transistor 112 is located in regions 331, 332, 334, and 335. The oxide semiconductor layer 130 consists of two layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b). At point 333, the oxide semiconductor layer 130 is made up of three layers (oxide semiconductor layer 130a, oxide Except for the fact that it is a monocrystalline semiconductor layer 130b and an oxide semiconductor layer 130c, transistor 106 and They have a similar configuration.

[0279] Furthermore, a transistor according to one aspect of the present invention is shown in Figures 34(A), (B), (C), (D), (E) ), (F) shown are cross-sectional views in the channel length direction, and the channels shown in Figures 33(C) and (D) As shown in the cross-sectional view in the width direction, a conductive layer 173 is placed between the oxide semiconductor layer 130 and the substrate 115. It may be provided. The conductive layer may be used as a second gate electrode layer (back gate). This allows for increasing the on-current and controlling the threshold voltage. (See Figure 34(A)) In the cross-sectional views shown in (B), (C), (D), (E), and (F), the width of the conductive layer 173 is acid The width of the conductive layer 173 may be shorter than that of the conductive layer 170. It can be made shorter than the width.

[0280] Furthermore, a transistor according to one aspect of the present invention has the configuration shown in Figures 35(A) and 35(B) It is also possible. Figure 35(A) is a top view, and Figure 35(B) is shown in Figure 35(A). These are cross-sectional views corresponding to the dashed lines N1-N2 and N3-N4. (See Figure 35) In the top view (A), some elements have been omitted for clarity.

[0281] The transistor 113 shown in Figures 35(A) and 35(B) is connected to substrate 115 and substrate 11 5. An insulating layer 120 on top of the insulating layer 120, and an oxide semiconductor layer 130 on top of the insulating layer 120 (oxide semiconductor layer 130 a) oxide semiconductor layer 130b, oxide semiconductor layer 130c) and oxide semiconductor layer 130 in contact And conductive layers 140 and 150 are arranged with gaps between them, and an oxide semiconductor layer 130 It has an insulating layer 160 in contact with c and a conductive layer 170 in contact with the insulating layer 160. The semiconductor layer 130c, the insulating layer 160, and the conductive layer 170 are on the transistor 113. The oxide semiconductor layer 130a, oxide semiconductor layer 130b, and insulating layer 12 are provided on 190. It is located in an opening that reaches 0.

[0282] The configuration of transistor 113 is, compared to the configurations of the other transistors mentioned above, source Because the overlapping region between the conductor that serves as the electrode or drain electrode and the conductor that serves as the gate electrode is small. Therefore, parasitic capacitance can be reduced. Consequently, transistor 113 can operate at high speed. It is suitable as an element for circuits that require it. Note that the top surface of transistor 113 is shown in Figure 35. (B) As shown, CMP (Chemical Mechanical Polishing) It is preferable to flatten the surface using methods such as the ng) method, but it is also possible to have a configuration that does not flatten the surface. .

[0283] Furthermore, the conductive layer 140 (source electrode layer) and conductive in a transistor according to one aspect of the present invention Layer 150 (drain electrode layer) is shown in the top view (oxide semiconductor layer 1) in Figures 36(A) and (B). 30. Only conductive layers 140 and 150 are shown in the figure. The width of the oxide semiconductor layer (W O S The width of conductive layer 140 and conductive layer 150 is greater than (W SD Even if a long gap is formed And it may be formed in a short form. OS ≥W SD (W SD is W OS By doing the following, The gate electric field is more easily applied to the entire oxide semiconductor layer 130, affecting the electrical characteristics of the transistor. It can be improved. Also, as shown in Figure 36(C), the conductive layer 140 and the conductive layer 150 may be formed only in the region that overlaps with the oxide semiconductor layer 130.

[0284] In one embodiment of the present invention, a transistor (transistors 101 to 113) is Even in the misaligned configuration, the conductive layer 170, which is the gate electrode layer, is an insulating layer, which is the gate insulating film. The oxide semiconductor layer 130 is electrically surrounded in the channel width direction via 160, and the on current is This can be improved. Such a transistor structure is called a surrounded channel This is called an (s-channel) structure.

[0285] Furthermore, a transistor having an oxide semiconductor layer 130a and an oxide semiconductor layer 130b, Furthermore, oxide semiconductor layer 130a, oxide semiconductor layer 130b, and oxide semiconductor layer 130c In a transistor having the oxide semiconductor layer 130, the two or three layers of material By appropriately selecting the material, an electric current can be passed through the oxide semiconductor layer 130b. The current flowing through the conductive layer 130b reduces the effects of interfacial scattering, resulting in a high on-current. Therefore, increasing the thickness of the oxide semiconductor layer 130b improves the on-current. It may happen.

[0286] By using the above configuration, the electrical characteristics of the transistor can be improved.

[0287] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments. can.

[0288] (Embodiment 3) In this embodiment, the components of the transistor shown in Embodiment 2 will be described in detail. It is.

[0289] For the substrate 115, a glass substrate, a quartz substrate, a semiconductor substrate, a ceramic substrate, a metal substrate whose surface is insulated, etc. can be used. Or, a silicon substrate on which transistors and photodiodes are formed, and a substrate on which an insulating layer, wiring, a conductor having a function as a contact plug, etc. are formed on the silicon substrate can be used. When forming a p-ch type transistor on the silicon substrate, it is preferable to use a silicon substrate having an n type conductivity type. Or, an SOI substrate having an n type or i-type silicon layer may be used. Also, when the transistor provided on the silicon substrate is p-ch type, it is preferable to use a silicon substrate whose plane orientation of the surface on which the transistor is formed is the (110) plane. By forming a p-ch type transistor on the (110) plane, the mobility can be increased. When forming a p-ch type transistor on the silicon substrate, - it is preferable to use a silicon substrate having an n type conductivity type. Or, an SOI substrate having an n - type or i-type silicon layer may be used. Also, when the transistor provided on the silicon substrate is p-ch type, it is preferable to use a silicon substrate whose plane orientation of the surface on which the transistor is formed is the (110) plane. By forming a p-ch type transistor on the (110) plane, the mobility can be increased. it is preferable to use a silicon substrate whose plane orientation of the surface on which the transistor is formed is the (110) plane. By forming a p-ch type transistor on the (110) plane, the mobility can be increased. it is preferable to use a silicon substrate whose plane orientation of the surface on which the transistor is formed is the (110) plane. By forming a p-ch type transistor on the (110) plane, the mobility can be increased. This can be done.

[0290] The insulating layer 120 has a role of preventing the diffusion of impurities from the elements contained in the substrate 115. In addition, it can play a role of supplying oxygen to the oxide semiconductor layer 130. Therefore, the insulating layer 120 is preferably an insulating film containing oxygen, and more preferably an insulating film containing more oxygen than the stoichiometric composition. The insulating layer 120 preferably has an oxygen release amount converted to oxygen atoms measured by the TDS method of 1.0×10 atoms / cm or more. In addition, the surface temperature of the film during the above TDS analysis is in the range of 100°C or more and 700°C or less, or 10 19 0°C or more and 500°C or less. Also, when the substrate 115 is a substrate on which other devices are formed 3 This is preferable. In addition, the surface temperature of the film during the above TDS analysis is in the range of 100°C or more and 700°C or less, or 10 0°C or more and 500°C or less. Also, when the substrate 115 is a substrate on which other devices are formed In this case, the insulating layer 120 also functions as an interlayer insulating film. In that case, the surface is flat. It is preferable to perform a planarization treatment using methods such as CMP to make the surface flat.

[0291] For example, the insulating layer 120 contains aluminum oxide, magnesium oxide, silicon oxide, and oxide Silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide oxide insulating films such as lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. , nitrous oxide such as silicon nitride, silicon nitride, aluminum nitride, aluminum nitride A dielectric insulating film or a mixture thereof can be used. Furthermore, a lamination of the above materials is also possible. That's fine.

[0292] In this embodiment, the oxide semiconductor layer 130 of the transistor is an oxide semiconductor layer 130 a. The oxide semiconductor layer 130b and the oxide semiconductor layer 130c are stacked sequentially from the insulating layer 120 side. This section will primarily explain the details of the case where it has a three-layer structure.

[0293] In the case of a single layer oxide semiconductor layer 130, the oxide semiconductor layer 13 shown in this embodiment You can use the layer corresponding to 0b.

[0294] Furthermore, if the oxide semiconductor layer 130 consists of two layers, the oxide semiconductor layer 13 shown in this embodiment... The layer corresponding to 0a and the layer corresponding to the oxide semiconductor layer 130b are arranged in order from the insulating layer 120 side. A stacked layer can be used. In this configuration, the oxide semiconductor layer 130a and the oxide semiconductor layer It can also be swapped with 130b.

[0295] Furthermore, if there are four or more oxide semiconductor layers 130, for example, as described in this embodiment... The configuration involves adding another oxide semiconductor layer to the three-layer oxide semiconductor layer 130. It is possible.

[0296] For example, the oxide semiconductor layer 130b contains the oxide semiconductor layer 130a and the oxide semiconductor layer Acids with a higher electron affinity (energy from the vacuum level to the bottom of the conduction band) than body layer 130c. Ion semiconductors are used. Electron affinity is the energy difference between the vacuum level and the top of the valence band (ions). From the potential, the energy difference between the lower end of the conduction band and the upper end of the valence band (energy gap) It can be calculated by subtracting (P).

[0297] The oxide semiconductor layer 130a and the oxide semiconductor layer 130c constitute the oxide semiconductor layer 130b. It contains one or more metallic elements, for example, the energy at the lower end of the conduction band is the oxide semiconductor layer 13 Greater than 0b, at least 0.05eV, 0.07eV, 0.1eV, or 0.15eV. If present, it approaches the vacuum level within the range of 2eV, 1eV, 0.5eV, or 0.4eV. It is preferable to form it with an oxide semiconductor.

[0298] In such a structure, when an electric field is applied to the conductive layer 170, the oxide semiconductor layer 130 A channel is formed in the oxide semiconductor layer 130b, which has the lowest energy at the lower end of the conduction band. Therefore, it can be said that the oxide semiconductor layer 130b has a region that functions as a semiconductor. However, the oxide semiconductor layer 130a and the oxide semiconductor layer 130c are insulators or semi-insulators. It could also be said that it has an area in which it functions.

[0299] Furthermore, the oxide semiconductor layer 130a contains one or more of the metal elements that make up the oxide semiconductor layer 130b. Because it is composed of the above, the interface when the oxide semiconductor layer 130b and the insulating layer 120 are in contact In comparison, interface states are formed at the interface between the oxide semiconductor layer 130b and the oxide semiconductor layer 130a. This becomes less likely to occur. The interface level may form a channel, so the transistor The key voltage may fluctuate. Therefore, an oxide semiconductor layer 130a is provided. This can reduce variations in electrical characteristics such as the threshold voltage of transistors. Furthermore, the reliability of the transistor can be improved.

[0300] Furthermore, the oxide semiconductor layer 130c contains one or more of the metal elements that make up the oxide semiconductor layer 130b. Because it is composed of the above, the oxide semiconductor layer 130b and the gate insulating film (insulating layer 160) are in contact. Compared to the interface in the case of [the other case], the interface between oxide semiconductor layer 130b and oxide semiconductor layer 130c This reduces the likelihood of carrier scattering. Therefore, an oxide semiconductor layer 130c is provided. This allows for an increase in the field-effect mobility of the transistor.

[0301] For example, the oxide semiconductor layer 130a and the oxide semiconductor layer 130c contain Al, Ti, Ga Ge, Y, Zr, Sn, La, Ce, or Hf are used in a material higher than the oxide semiconductor layer 130b. Materials containing the atoms in a specific ratio can be used. Specifically, materials with an atomic ratio of 1.5 times or more are preferred. The ratio should be at least twice, and more preferably at least three times. The aforementioned elements bond strongly with oxygen. Therefore, it has the function of suppressing the occurrence of oxygen vacancies in the oxide semiconductor layer. The monocrystalline semiconductor layer 130a and the oxide semiconductor layer 130c are more acidic than the oxide semiconductor layer 130b. It can be said that primary defects are less likely to occur.

[0302] Furthermore, oxide semiconductor layer 130a, oxide semiconductor layer 130b, and oxide semiconductor layer 130 The oxide semiconductor that can be used as c contains at least In or Zn. Preferably, it contains both In and Zn. To reduce variations in the electrical characteristics of the transistors, stabilizers were added along with them. It is preferable to include it.

[0303] Stabilizers include Ga, Sn, Hf, Al, or Zr. The stabilizers are lanthanides such as La, Ce, Pr, Nd, Sm, Eu, and G. Examples include d, Tb, Dy, Ho, Er, Tm, Yb, Lu, etc.

[0304] For example, as oxide semiconductors, indium oxide, tin oxide, gallium oxide, zinc oxide, I n-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Sn-Mg Oxides, In-Mg oxide, In-Ga oxide, In-Ga-Zn oxide, In-Al- Zn oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide Materials, Sn-Al-Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, In -Ce-Zn oxide, In-Pr-Zn oxide, In-Nd-Zn oxide, In-Sm- Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide In-Dy-Zn oxide, In-Ho-Zn oxide, In-Er-Zn oxide, In -Tm-Zn oxide, In-Yb-Zn oxide, In-Lu-Zn ​​oxide, In-Sn- Ga-Zn oxide, In-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, I n-Sn-Al-Zn oxide, In-Sn-Hf-Zn oxide, In-Hf-Al-Zn Oxides can be used.

[0305] For example, in-Ga-Zn oxide is a material whose main components are In, Ga, and Zn. It means an oxide containing In, Ga, and Zn. Good. Also, in this specification, a film composed of In-Ga-Zn oxide is referred to as an IGZO film. They also call them that.

[0306] Also, InMO3(ZnO) m Materials represented as (m>0, and m is not an integer) It may be included. Note that M is one selected from Ga, Y, Zr, La, Ce, or Nd. This indicates a metallic element or multiple metallic elements. Also, In2SnO5(ZnO) n (n>0, and You may also use materials represented by n (where n is an integer).

[0307] Furthermore, oxide semiconductor layer 130a, oxide semiconductor layer 130b, and oxide semiconductor layer 130c are At least indium, zinc, and M(Al, Ti, Ga, Ge, Y, Zr, Sn, La) When it is an In-M-Zn oxide containing a metal such as Ce or Hf, the oxide semiconductor layer 1 30a is In:M:Zn=x1:y1:z1 [atomic ratio], oxide semiconductor layer 130b is I n:M:Zn=x2:y2:z2 [atomic ratio], oxide semiconductor layer 130c is In:M:Z If n = x3:y3:z3 [atomic ratio], then y1 / x1 and y3 / x3 become y2 / x2 It is preferable that y1 / x1 and y3 / x3 are 1 greater than y2 / x2. The ratio should be 5 times or more, preferably 2 times or more, and more preferably 3 times or more. At this time, the oxide semi In the conductor layer 130b, if y2 is greater than or equal to x2, the electrical characteristics of the transistor are stabilized. This is possible. However, when y2 becomes more than 3 times x2, the field-effect mobility of the transistor Because this would cause a decrease in the value, it is preferable that y2 be less than three times x2.

[0308] In the oxide semiconductor layer 130a and oxide semiconductor layer 130c, the fields excluding Zn and O In the mixture, the atomic ratio of In and M is preferably such that In is less than 50 atomic%, M is 50 atomic% or more, more preferably In is less than 25 atomic%, and M is 7 The atomic content should be 5% or more. Also, the oxide semiconductor layer 130b should be excluding Zn and O. The atomic ratio of In and M is preferably 25 atomic% or more for In and 75 atomic% for M. Less than 0 omic%, more preferably In is 34 atomic% or more, and M is 66 atomic%. It should be less than c%.

[0309] Furthermore, the oxide semiconductor layer 130b is composed of oxide semiconductor layer 130a and oxide semiconductor layer 130 It is desirable to have a higher indium content than carbon. In oxide semiconductors, heavy metals are primarily used for the s-railway. The pathway contributes to carrier conduction, and by increasing the In content, more s-trajectories are formed. Because the pathways overlap, oxides with a composition where In is greater than M are those with In equal to or less than M. Compared to the oxide that forms the final product, it has higher mobility. Therefore, it is incorporated into the oxide semiconductor layer 130b. By using oxides with a high zinc content, transistors with high field-effect mobility can be realized. It is possible.

[0310] The thickness of the oxide semiconductor layer 130a is 3 nm or more and 100 nm or less, preferably 5 nm or more. The oxide semiconductor layer 1 is 0 nm or less, more preferably 5 nm to 25 nm. The thickness of 30b is 3 nm to 200 nm, preferably 5 nm to 150 nm. Furthermore, the thickness of the oxide semiconductor layer 130c is preferably 10 nm or more and 100 nm or less. The wavelength is 1 nm to 50 nm, preferably 2 nm to 30 nm, and more preferably The thickness shall be between 3 nm and 15 nm. In addition, the oxide semiconductor layer 130b shall be oxide semiconductor layer 13 A thickness greater than 0c is preferable.

[0311] In order to impart stable electrical characteristics to a transistor with an oxide semiconductor layer as its channel, The impurity concentration in the oxide semiconductor layer is reduced, making the oxide semiconductor layer intrinsic (type i) or substantially Making it intrinsic is effective. Here, substantially intrinsic means that the carrier density of the oxide semiconductor layer is The degree is 1 x 10 19 / cm 3 It must be less than 1 × 10 15 / cm 3 Less than 1 ×10 13 / cm 3 Being less than, or 1 × 10 8 / cm 3 It is less than 1 × 10 -9 / cm 3 This refers to something that is greater than or equal to the above.

[0312] Furthermore, in the oxide semiconductor layer, hydrogen, nitrogen, carbon, silicon, and metals other than the main component are present. Elements act as impurities. For example, hydrogen and nitrogen contribute to the formation of donor levels, making them carrier-dense. This increases the degree of the problem. Furthermore, silicon contributes to the formation of impurity levels in the oxide semiconductor layer. These impurity levels can act as traps, potentially degrading the electrical characteristics of the transistor. Therefore, oxide semiconductor layer 130a, oxide semiconductor layer 130b and oxide semiconductor layer It is preferable to reduce the impurity concentration in the 130c layer and at each interface.

[0313] To make an oxide semiconductor layer intrinsically or substantially intrinsically, SIMS (Secondary The hydrogen concentration estimated by ion mass spectrometry analysis is 2 ×10 20 atoms / cm 3 The following is preferably 5 × 10 19 atoms / cm 3 below, Better 1 × 10 19 atoms / cm 3 More preferably 5 × 10 18 a toms / cm 3 The following, 1 × 10 17 atoms / cm 3 It has an area that is greater than or equal to Control it so that it does not exceed 5 × 10. Also, the nitrogen concentration is 5 × 10 19 atoms / cm 3 Less than, preferably is 5 x 10 18 atoms / cm 3 More preferably 1 × 10 18 atoms / cm 3 More preferably 5 × 10 17 atoms / cm 3 The following, 5 × 10 16 atoms / cm 3 Control the region to have a range greater than or equal to the above.

[0314] Furthermore, high concentrations of silicon and carbon can reduce the crystallinity of the oxide semiconductor layer. In order to avoid reducing the crystallinity of the oxide semiconductor layer, the silicon concentration should be 1 × 10⁻⁶. 19 atoms / cm 3 Less than 5 × 10 18 atoms / cm 3 It is less than 1 × 10 18 atoms / cm 3 The region is controlled to have a range of the above. Also, the carbon concentration 1 x 10 19 atoms / cm 3 Less than 5 × 10 18 atoms / cm 3 less than More preferably 1 × 10 18 atoms / cm 3 Less than 6 × 10 17 ato ms / cm 3 Control the region to have a range greater than or equal to the above.

[0315] Furthermore, as mentioned above, a transient using a highly purified oxide semiconductor film in the channel formation region The off-current of the sta is extremely small. For example, if the voltage between the source and drain is 0.1V, 5 When set to V or approximately 10V, the off-current per channel width of the transistor is several It becomes possible to reduce the level to yA / μm or even a few zA / μm.

[0316] Since silicon-containing insulating films are often used as gate insulating films for transistors, For the reasons stated above, the region that becomes the channel of the oxide semiconductor layer is the transistor of one aspect of the present invention. It can be said that a structure that does not come into contact with the gate insulating film is preferable. When a channel is formed at the interface between the oxide semiconductor layer and the oxide semiconductor layer, carrier scattering occurs at the interface. This can lead to a decrease in the field-effect mobility of the transistor. From this perspective as well, oxidation It is preferable to keep the channel region of the semiconductor layer away from the gate insulating film.

[0317] Therefore, the oxide semiconductor layer 130 is divided into oxide semiconductor layer 130a and oxide semiconductor layer 130b By using a stacked structure of oxide semiconductor layer 130c, channels are formed in oxide semiconductor layer 130b. A transistor can be formed that has high field-effect mobility and stable electrical characteristics. It can form a ta.

[0318] Band structure of oxide semiconductor layer 130a, oxide semiconductor layer 130b, and oxide semiconductor layer 130c In this structure, the energy at the lower end of the conduction band changes continuously. This is because the oxide semiconductor layer 1 By making the compositions of 30a, oxide semiconductor layer 130b, and oxide semiconductor layer 130c similar, This can also be understood from the fact that oxygen readily diffuses between them. Therefore, oxide semiconductor layer 130a The oxide semiconductor layer 130b and oxide semiconductor layer 130c are laminates of layers with different compositions. However, it can also be said that it is continuous in terms of physical properties, and in the drawing, each interface of the laminate It is represented by a dotted line.

[0319] The oxide semiconductor layers 130, which are stacked with a common main component, are not simply stacked one layer at a time. Continuous junctions (in this case, U-shaped junctions where the energy at the lower end of the conduction band changes continuously between each layer) The structure is prepared so that a well structure (U-shaped well) is formed. That is, each layer If impurities that form defect levels such as trap centers or recombination centers are present at the interface A layered structure is formed in such a way. If impurities are mixed between the layers of the stacked oxide semiconductor layers, When this occurs, the continuity of the energy band is lost, and carriers are trapped or re-established at the interface. It disappears due to the combination.

[0320] For example, oxide semiconductor layer 130a and oxide semiconductor layer 130c have In:Ga:Zn= 1:3:2, 1:3:3, 1:3:4, 1:3:6, 1:4:5, 1:6:4 or 1: In-Ga-Zn oxides such as 9:6 (atomic ratio) can be used. Also, acid The ion semiconductor layer 130b has In:Ga:Zn=1:1:1, 2:1:3, 5:5:6, Alternatively, In-Ga-Zn oxides such as those in an atomic ratio of 3:1:2 can be used. Note that oxide semiconductor layer 130a, oxide semiconductor layer 130b, and oxide semiconductor layer 130 The atomic ratios of c each include a variation of plus or minus 40% of the above atomic ratios as an error. nothing.

[0321] In the oxide semiconductor layer 130, the oxide semiconductor layer 130b becomes a well, and channel The energy is formed in the oxide semiconductor layer 130b. The oxide semiconductor layer 130 has energy at the lower end of the conduction band. Because the ghee changes continuously, it can also be called a U-shaped well. Channels formed through configuration can also be called embedded channels.

[0322] Furthermore, the oxide semiconductor layer 130a and the oxide semiconductor layer 130c, and the silicon oxide film, etc. Near the interface with the insulating layer, trap levels can form due to impurities and defects. Due to the presence of the semiconductor layer 130a and the oxide semiconductor layer 130c, the oxide semiconductor layer 13 This allows us to move 0b away from the trap level.

[0323] However, the energy at the lower end of the conduction band of the oxide semiconductor layer 130a and the oxide semiconductor layer 130c - When the difference between this and the energy at the lower end of the conduction band of the oxide semiconductor layer 130b is small, the oxide semiconductor Electrons in the conductive layer 130b may exceed the energy difference and reach the trap level. When it is trapped in a trap level, a negative charge is generated at the insulating layer interface, and the transistor The threshold voltage shifts in the positive direction.

[0324] The oxide semiconductor layer 130a, oxide semiconductor layer 130b, and oxide semiconductor layer 130c contain: It is preferable that the crystalline portion is included. In particular, using a crystal oriented along the c-axis allows for the creation of transistors. It can impart stable electrical properties. Furthermore, crystals oriented along the c-axis are resistant to distortion. This can improve the reliability of semiconductor devices using flexible substrates.

[0325] Conductive layer 140 acting as source electrode layer and conductive layer 1 acting as drain electrode layer 50 includes, for example, Al, Cr, Cu, Ta, Ti, Mo, W, Ni, Mn, Nd, Sc , and a single layer or laminate of a material selected from the alloy of the metal material can be used. Typical examples include Ti, which readily combines with oxygen, and materials that allow for relatively high subsequent processing temperatures. For these reasons, it is preferable to use W, which has a high melting point. Also, low-resistance Cu or Cu-M Lamination of alloys such as n and the above materials may also be used. Transistor 105, Transistor 1 06. In transistors 111 and 112, for example, the conductive layer 141 and The conductive layer 151 is made of W, and the conductive layers 142 and 152 are made of a laminated film of Ti and Al, etc. It is possible to be there.

[0326] The above material has the property of extracting oxygen from oxide semiconductor films. Therefore, when in contact with the above material... In some regions of the oxide semiconductor layer, oxygen is desorbed from the oxide semiconductor layer, forming an oxygen vacancy. The region becomes noticeably affected when the small amount of hydrogen contained in the membrane combines with the oxygen deficiency. It is converted to n-type. Therefore, the n-type region is the source or drain of the transistor. It can be made to work in this way.

[0327] Furthermore, when W is used in conductive layers 140 and 150, even if nitrogen is doped... Good. By doping with nitrogen, the property of extracting oxygen can be moderately weakened, resulting in an n-type. This prevents the transformed region from expanding into the channel region. Also, the conductive layer 140 The conductive layer 150 is stacked with an n-type semiconductor layer, and the n-type semiconductor layer and the oxide semiconductor layer are connected. By causing contact, it is possible to prevent the n-type region from expanding into the channel region. It is possible. As for the n-type semiconductor layer, nitrogen-doped In-Ga-Zn oxide, zinc oxide, Indium oxide, tin oxide, indium tin oxide, etc., can be used.

[0328] The insulating layer 160, which acts as a gate insulating film, contains aluminum oxide, magnesium oxide, Silicon oxide, silicon oxide nitride, silicon nitride, silicon nitride, gallium oxide, acid Germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, An insulating film containing one or more hafnium oxide and tantalum oxide can be used. The insulating layer 160 may be a laminate of the above materials. These may be included as impurities.

[0329] Furthermore, an example of the laminated structure of the insulating layer 160 will be described. The insulating layer 160 is, for example, oxygen It contains nitrogen, silicon, hafnium, etc. Specifically, hafnium oxide, and oxide It is preferable that the material contains silicon or silicon oxide nitride.

[0330] Hafnium oxide and aluminum oxide are compared to silicon oxide and silicon oxide-nitride. It has a high dielectric constant. Therefore, compared to the case where silicon oxide is used, the thickness of the insulating layer 160 is Because it can be made larger, the leakage current due to tunnel current can be reduced. That is, This makes it possible to realize transistors with low current. Furthermore, a crystalline oxide can be used. Hafnium has a higher dielectric constant compared to hafnium oxide, which has an amorphous structure. Therefore, in order to create a transistor with a small off-current, hafnium oxide, which has a crystalline structure, is used. It is preferable to use [this]. Examples of crystal structures include monoclinic and cubic systems. However, one aspect of the present invention is not limited to these.

[0331] Furthermore, the insulating layer 120 and insulating layer 160 that are in contact with the oxide semiconductor layer 130 are made of nitrogen oxide It is preferable to use a film with low emission levels. An insulating layer and an oxide semiconductor with high nitrogen oxide emission levels are preferable. When conductors come into contact, the energy level density may increase due to nitrogen oxides. Insulating layer 120 And the insulating layer 160 is, for example, a silicon oxide nitride film that emits a small amount of nitrogen oxides. An oxide insulating layer such as an aluminum oxide nitride film can be used.

[0332] Silicon oxiditride films with low nitrogen oxide emissions are used in the TDS method. This is a membrane where the amount of ammonia released is greater than the amount of ammonia discharged, typically when the amount of ammonia released is 1 × 10⁻⁶. 18 pieces / cm 3 The above 5 x 10 19 pieces / cm 3 The following applies. Note that the amount of ammonia released is: Heat treatment to a film surface temperature of 50°C to 650°C, preferably 50°C to 550°C. This will be the amount released.

[0333] By using the above oxide insulating layer as the insulating layer 120 and insulating layer 160, the transient This makes it possible to reduce the threshold voltage shift of the transistor and the variation in the transistor's electrical characteristics. This can be reduced.

[0334] The conductive layer 170 acting as the gate electrode layer may be, for example, Al, Ti, Cr, Co, or Ni Conductive films such as Cu, Y, Zr, Mo, Ru, Ag, Mn, Nd, Sc, Ta, and W It can be used. Furthermore, alloys of the above materials or conductive nitrides of the above materials may also be used. Furthermore, a plurality of materials selected from the above materials, alloys of the above materials, and conductive nitrides of the above materials Layers of materials are also possible. Typical examples include tungsten and tungsten and titanium nitride layers. Laminated layers of tungsten and tantalum nitride can be used. Also, low-resistance Cu can be used. Alternatively, using alloys such as Cu-Mn or laminates of the above materials with alloys such as Cu or Cu-Mn. This may also be the case. In this embodiment, the conductive layer 171 is made of tantalum nitride, and the conductive layer 172 is made of tungsten A conductive layer 170 is formed using [a specific method / tool].

[0335] The insulating layer 175 may be made of a silicon nitride film or an aluminum nitride film containing hydrogen. This is possible. Transistors 103, 104, and 2 shown in Embodiment 2 In transistors 106, 109, 110, and 112: By using a hydrogen-containing insulating film as the insulating layer 175, a portion of the oxide semiconductor layer is converted to n-type. It is possible. In addition, the nitride insulating film also acts as a blocking film for moisture, etc. This can improve the reliability of the transistor.

[0336] Furthermore, an aluminum oxide film can also be used as the insulating layer 175. In particular, the embodiment Transistors 101, 102, 105, and 2 shown in state 2 In transistors 107, 108, and 111, the insulating layer 175 contains oxide It is preferable to use a luminium film. The aluminum oxide film contains impurities such as hydrogen and water. It has a high barrier effect that prevents both aluminum oxide and oxygen from permeating the membrane. The nium film contains impurities such as hydrogen and water during and after the transistor fabrication process. Prevention of contamination into the oxide semiconductor layer 130, prevention of oxygen release from the oxide semiconductor layer, insulating layer 1 It is suitable for use as a protective film that prevents the unnecessary release of oxygen from 20°C. Furthermore, it is also possible to diffuse the oxygen contained in the aluminum oxide film into the oxide semiconductor layer. ru.

[0337] Furthermore, it is preferable that an insulating layer 180 is formed on the insulating layer 175. This includes magnesium oxide, silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride Cone, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, rayon oxide Using an insulating film containing one or more of tantalum, neodymium oxide, hafnium oxide, and tantalum oxide This is possible. Furthermore, the insulating layer may be a laminate of the above-mentioned materials.

[0338] Here, the insulating layer 180, like the insulating layer 120, has more oxygen than its stoichiometric composition. This is preferable. Oxygen released from the insulating layer 180 passes through the insulating layer 160 to the oxide semiconductor Since it can diffuse into the channel-forming region of layer 130, it can form a shape in the channel-forming region. The oxygen deficiency that has occurred can be compensated for by oxygen. Therefore, a stable transistor Electrical properties can be obtained.

[0339] Miniaturization of transistors is essential for highly integrating semiconductor devices. It is known that miniaturization degrades the electrical characteristics of transistors, particularly the channel width. When it shrinks, the on-current decreases.

[0340] In transistors 107 to 112 of one aspect of the present invention, a channel is formed An oxide semiconductor layer 130c is formed so as to cover the oxide semiconductor layer 130b, The channel-forming layer and the gate insulating film are not in contact. This suppresses carrier scattering at the interface with the insulating film, thus reducing the on-voltage of the transistor. The flow can be increased.

[0341] Furthermore, in a transistor according to one aspect of the present invention, as described above, the oxide semiconductor layer 130 is A gate electrode layer (conductive layer 170) is formed so as to electrically surround the width direction of the fiber. Therefore, for the oxide semiconductor layer 130, in addition to the gate electric field from the direction perpendicular to the top surface, the side A gate electric field is applied from a direction perpendicular to it. That is, the entire channel formation layer A gate electric field is applied, which expands the effective channel width, and therefore the on current is further increased. It can be improved.

[0342] Furthermore, in one aspect of the present invention, the oxide semiconductor layer 130 is a two- or three-layer transistor. This involves forming an oxide semiconductor layer 130b on an oxide semiconductor layer 130a in which a channel is formed. This has the effect of making it difficult for interfacial states to form. Furthermore, oxidation in one aspect of the present invention In a transistor with three semiconductor layers 130, the oxide semiconductor layer 130b is an intermediate layer in the three-layer structure. By positioning it as a layer, it has the added benefit of eliminating the influence of impurities from above and below. Therefore, in addition to improving the on-current of the transistor as described above, the threshold voltage stabilization is also important. This allows for the reduction of the S value (subthreshold value). Therefore, the gate The current can be reduced when the voltage VG is 0V, thereby reducing power consumption. This stabilizes the threshold voltage of the transistor, thereby improving the long-term reliability of semiconductor devices. It can be made possible. Furthermore, the transistor according to one aspect of the present invention has electrical characteristics that improve with miniaturization. Because degradation is suppressed, it can be said that it is suitable for forming highly integrated semiconductor devices.

[0343] The various films described in this embodiment, such as metal films, semiconductor films, and inorganic insulating films, are typically spalled. It can be formed by the condensate method or plasma CVD, but other methods, such as thermal CVD, can also be used. It may also be formed by law. An example of the thermal CVD method is MOCVD (Metal Organic Compounds). nic Chemical Vapor Deposition (NIC) method and ALD (Atom Examples include the IC Layer Deposition method.

[0344] Thermal CVD is a film deposition method that does not use plasma, so defects are generated by plasma damage. It has the advantage of not being affected.

[0345] Furthermore, in the thermal CVD method, the raw material gas and oxidizer are simultaneously introduced into the chamber, and the contents of the chamber are processed By using atmospheric pressure or reduced pressure, the reaction is carried out near or on the substrate, causing the deposit to be deposited on the substrate. Film deposition may be performed.

[0346] The ALD method involves maintaining atmospheric pressure or reduced pressure inside the chamber and supplying the raw material gas for the reaction to the chamber. - The material is introduced and reacted with, and this process is repeated to form a film. Along with the raw material gas, an inert gas is also used. Argon or nitrogen may be introduced as a carrier gas. For example, two or more types The raw material gases may be supplied to the chamber in sequence. In this case, multiple types of raw material gases must not be mixed. As described above, after the reaction of the first raw material gas, an inert gas is introduced, and then the second raw material gas is introduced. Instead of introducing an inert gas, the first raw material gas is discharged by vacuum evacuation, and then the A second raw material gas may be introduced. The first raw material gas is adsorbed and reacts with the surface of the substrate to form the first layer. A film is formed, and a second raw material gas introduced later is adsorbed and reacts, causing the second layer to form on top of the first layer. The layers are stacked to form a thin film. This process is repeated while controlling the gas introduction sequence until the desired thickness is achieved. By repeating the process several times, a thin film with excellent step coverage can be formed. The thickness of the thin film is Because it can be adjusted by the number of times the injection is repeated, precise film thickness adjustment is possible. It is suitable for fabricating miniature FETs.

[0347] Thermal CVD methods such as MOCVD and ALD are disclosed in the embodiments described above. It can form various films such as metal films, semiconductor films, and inorganic insulating films, for example, In-Ga -When forming a Zn-O film, trimethylindium (In(CH3)3), trimethyl Tilgarium (Ga(CH3)3) and dimethylzinc (Zn(CH3)2) are used. This is possible. It is not limited to these combinations, and trimethylgallium can be substituted with triethyl Lugarium (Ga(C2H5)3) can also be used, and diethyl can be used instead of dimethylzinc. Zinc (Zn(C2H5)2) can also be used.

[0348] For example, when forming a hafnium oxide film using a film deposition apparatus that utilizes ALD, the solvent and Liquids containing hafnium precursors (such as hafnium alkoxide or tetrakisdimethylamide) Fnium (TDMAH, Hf[N(CH3)2]4) and tetrakis (ethylmethylamide) (The raw material gas is a vaporized hafnium amide such as hafnium, and ozone is used as an oxidizer.) Two types of gases (O3) are used.

[0349] For example, when forming an aluminum oxide film using a film deposition apparatus that utilizes ALD, the solvent and a liquid containing an aluminum precursor (trimethylaluminum (TMA, Al(CH3)3) Two types of gases are used: a raw material gas obtained by vaporizing (such as) and H2O as an oxidizing agent. The materials include tris(dimethylamide)aluminum, triisobutylaluminum, and Luminium tris(2,2,6,6-tetramethyl-3,5-heptanedione), etc. There is.

[0350] For example, when forming a silicon oxide film using a film deposition apparatus that utilizes ALD, hexa Roloticilane is adsorbed onto the film-forming surface, and radicals of oxidizing gases (O2, nitrous oxide) are supplied. It is supplied and reacted with the adsorbed material.

[0351] For example, when depositing a tungsten film using a film deposition apparatus that utilizes ALD, WF6 gas The initial tungsten film is formed by sequentially introducing S and B2H6 gas, and then WF6 gas and H Two gases are introduced sequentially to form a tungsten film. Note that SiH4 gas is used instead of B2H6 gas. Gas may be used.

[0352] For example, oxide semiconductor films, such as In-Ga-Zn-O, can be deposited using an ALD (Advanced Laser Deposition) system. When forming a film, In(CH3)3 gas and O3 gas are introduced sequentially to form an In-O layer. Then, Ga(CH3)3 gas and O3 gas are sequentially introduced to form a GaO layer, and further Subsequently, Zn(CH3)2 gas and O3 gas are introduced sequentially to form a ZnO layer. The order of these layers is not limited to this example. These gases can be used to create In-Ga-O layers and In-Zn layers. A mixed compound layer such as an O layer or a Ga-Zn-O layer may be formed. Alternatively, instead of O3 gas... H2O gas obtained by bubbling with an inert gas such as Ar may be used, but it does not contain H. It is preferable to use O3 gas, which does not contain oxygen.

[0353] A counter-target sputtering system can also be used to deposit oxide semiconductor layers. The film deposition method using the opposing target sputtering apparatus is called VDSP (vapor It can also be called a precipitate (SP).

[0354] By depositing an oxide semiconductor layer using a counter-target sputtering apparatus, Plasma damage during the deposition of oxide semiconductor layers can be reduced. Therefore, in the film... This can reduce oxygen deficiency. Furthermore, by using a counter-target sputtering apparatus... This enables film deposition at low pressure, thus reducing the impurity concentration in the deposited oxide semiconductor layer (e.g., For example, it can reduce hydrogen, noble gases (such as argon), and water.

[0355] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments. can.

[0356] (Embodiment 4) The following describes the structure of an oxide semiconductor film that can be used in one aspect of the present invention. .

[0357] In this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. This refers to the state in which something is positioned. Therefore, it also includes cases where the angle is between -5° and 5°. Also, "Perpendicular" refers to a state where two lines are positioned at an angle between 80° and 100°. Therefore, this also includes cases where the angle is between 85° and 95°.

[0358] Furthermore, in this specification, if a crystal is trigonal or rhombohedral, it will be represented as a hexagonal crystal system. .

[0359] <Oxide semiconductor structure> The structure of oxide semiconductors will be described below.

[0360] Oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, CAAC-OS (c-axis-aligned (crystalline oxide semiconductor), polycrystalline oxide Semiconductors, nc-OS (nanocrystalline oxide semiconductor) uctor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous-l Examples include oxide semiconductors and amorphous oxide semiconductors. ru.

[0361] From another perspective, oxide semiconductors include amorphous oxide semiconductors and other crystalline oxide semiconductors. It can be divided into conductors and crystalline oxide semiconductors. As for crystalline oxide semiconductors, there are single-crystal oxide semiconductors, CAAC- Examples include OS, polycrystalline oxide semiconductors, and nc-OS.

[0362] Amorphous structures are generally isotropic and lack heterogeneous structures, representing a metastable state of atomic arrangement. It is not fixed, the bonding angle is flexible, and it has short-range order but not long-range order. It is said that...

[0363] Conversely, stable oxide semiconductors can be made into completely amorphous (completely amorphous) materials. It cannot be called an oxide semiconductor (rphous). Also, it is not isotropic (for example, in a minute region) Oxide semiconductors that have a periodic structure cannot be called perfectly amorphous oxide semiconductors. On the other hand, a-like OS is not isotropic but has an unstable structure with voids (also called porous structures). It is a structure. In terms of instability, a-like OS is an amorphous oxide in terms of its physical properties. It's similar to a semiconductor.

[0364] <caac-os> First, let me explain CAAC-OS.

[0365] CAAC-OS is an oxide semiconductor having multiple c-axis oriented crystalline portions (also called pellets). It is a type of conductor.

[0366] CAAC-OS can be analyzed by X-ray diffraction (XRD). Let's explain the case of analysis. For example, InGaZnO4, which is classified as space group R-3m Structural analysis of crystalline CAAC-OS is performed using the out-of-plane method. As shown in Figure 37(A), a peak appears near a diffraction angle (2θ) of 31°. Since the 'k' is attributed to the (009) plane of the InGaZnO4 crystal, CAAC-OS The crystal has c-axis orientation, and the c-axis is the surface that forms the CAAC-OS film (also called the surface to be formed). It can be confirmed that it is facing in a direction approximately perpendicular to the top surface. Note that 2θ is 31° In addition to the nearby peak, a peak may also appear when 2θ is near 36°. The adjacent peak is due to a crystal structure classified as space group Fd-3m. Therefore, CAAC -OS preferably does not show the peak.

[0367] On the other hand, in CAAC-OS, X-rays are incident from a direction parallel to the surface being formed. Structural analysis using the ne method reveals a peak near 2θ = 56°. This peak corresponds to I It is attributed to the (110) plane of the nGaZnO4 crystal. Then, 2θ is fixed near 56°. The analysis (φ-scan) is performed while rotating the sample around the normal vector of the sample surface as the axis (φ-axis). Even when this is done, no clear peak appears, as shown in Figure 37(B). On the other hand, single crystal InGaZ When φ scanning is performed on nO4 with 2θ fixed near 56°, the result is shown in Figure 37(C). Six peaks are observed that belong to a crystal plane equivalent to the (110) plane. Therefore, X Structural analysis using RD revealed that CAAC-OS has irregular orientations in its a-axis and b-axis. This can be confirmed.

[0368] Next, we will explain CAAC-OS analyzed by electron diffraction. For example, InGaZ For CAAC-OS having nO4 crystals, a probe is applied parallel to the surface of the CAAC-OS being formed. When an electron beam with a diameter of 300 nm is incident, a diffraction pattern like the one shown in Figure 37(D) is observed (control This is also called a limited-field electron diffraction pattern. A diffraction pattern may appear. This diffraction pattern includes In The spot contains a location originating from the (009) plane of the GaZnO4 crystal. Therefore, the electron rotation Depending on the circumstances, the pellets contained in CAAC-OS may have c-axis orientation, and the c-axis may be the surface to be formed. Alternatively, it can be seen that it is oriented in a direction approximately perpendicular to the upper surface. On the other hand, for the same sample, on the sample surface Figure 37(E) shows the diffraction pattern when an electron beam with a probe diameter of 300 nm is incident vertically. As shown in Figure 37(E), a ring-shaped diffraction pattern can be observed. Therefore, the probe Electron diffraction using an electron beam with a diameter of 300 nm also revealed the presence of peridotites in CAAC-OS. It can be seen that the a-axis and b-axis of the net do not have orientation. Note that in Figure 37(E) The ring is caused by the (010) and (100) planes of the InGaZnO4 crystal, among other things. It is thought that the second ring in Figure 37(E) is caused by the (110) plane, etc. It's possible.

[0369] Furthermore, a transmission electron microscope (TEM) A composite image of the bright-field image and diffraction pattern of CAAC-OS obtained by (croscope) analysis. When observing a high-resolution TEM image (also known as a TEM image), multiple pellets can be identified. On the other hand, even in high-resolution TEM images, the boundaries between pellets, i.e., grain boundaries, are not visible. Also called "Nandaly." ) There are cases where it is not possible to clearly confirm this. Therefore, CAAC -OS can be said to be less prone to the decrease in electron mobility caused by grain boundaries.

[0370] Figure 38(A) shows a high-resolution T of the cross-section of CAAC-OS observed from a direction approximately parallel to the sample surface. The EM image is shown. For observing high-resolution TEM images, spherical aberration correction is required. The aberration correction function was used. High-resolution analysis was performed using the spherical aberration correction function. High-resolution TEM images are specifically called Cs-corrected high-resolution TEM images. For example, using an atomic resolution analytical electron microscope such as the JEM-ARM200F manufactured by JEOL Ltd. This can be observed.

[0371] From Figure 38(A), we can see that the pellet is a region in which metal atoms are arranged in layers. Yes, it is possible. It has been found that the size of a single pellet can be 1 nm or larger, or even 3 nm or larger. Therefore, pellets are called nanocrystals (nc). It is also possible to use CAAC-OS with CANC(C-Axis Aligned nan It can also be called an oxide semiconductor containing ocrystals. The pellet is CAAC -Reflects the unevenness of the surface or top surface of the OS, and the surface or top surface of the CAAC-OS It becomes parallel to the plane.

[0372] Furthermore, Figures 38(B) and 38(C) show CAAC observed from a direction approximately perpendicular to the sample surface. -Shows a Cs-corrected high-resolution TEM image of the OS plane. Figures 38(D) and 38(E) are shown. These are images obtained by image processing Figure 38(B) and Figure 38(C), respectively. The following describes the image processing. Let's explain the method. First, Figure 38(B) is converted to Fast Fourier Transform (FFT). The FFT image is obtained by performing a Fourier Transform (FFT) process. Next, the acquisition In the resulting FFT image, with the origin as the reference point, 2.8 nm -1 from 5.0nm -1 Leave the range between Next, the masked FFT image is subjected to the inverse Fast Fourier Transform (IFFT: By processing the image (Inverse Fast Fourier Transform), The processed image is obtained. The image obtained in this way is called an FFT filtered image. The filtered image is an image obtained by extracting the periodic component from the Cs-corrected high-resolution TEM image, and is a grid image. This shows the array.

[0373] In Figure 38(D), areas where the grid arrangement is disordered are indicated by dashed lines. The area enclosed by the dashed lines is It is a single pellet. The dotted line indicates the connection point between the pellets. The dashed line indicates a hexagonal shape, showing that the pellet is hexagonal. The shape of the net is not always a regular hexagon; it is often a non-regular hexagon.

[0374] In Figure 38(E), a dotted line separates one region with a aligned grid arrangement from another region with a aligned grid arrangement. The diagram shows the orientation of the lattice arrangement, indicated by dashed lines. Clear grain boundaries can be observed even near the dotted lines. It cannot be confirmed. Connecting the surrounding grid points to the grid point near the dotted line forms a distorted hexagon. This can be formed. In other words, the formation of grain boundaries is suppressed by distorting the lattice arrangement. This indicates that CAAC-OS has a non-dense atomic arrangement in the ab-plane direction. For example, the substitution of metal elements changes the bond distance between atoms, thus reducing strain. This is likely because it is acceptable.

[0375] As described above, CAAC-OS has c-axis orientation and multiple properties in the ab-plane direction. A number of pellets (nanocrystals) are linked together, forming a distorted crystalline structure. Therefore, CA AC-OS, CAA crystal(c-axis-aligned ab-pl It can also be called an oxide semiconductor having an anchored crystal. ru.

[0376] CAAC-OS is a highly crystalline oxide semiconductor. The crystallinity of oxide semiconductors depends on the presence of impurities. Because it can decrease due to the generation of defects or other factors, from the opposite perspective, CAAC-OS It can also be described as an oxide semiconductor with few impurities or defects (such as oxygen vacancies).

[0377] Impurities are elements other than the main components of oxide semiconductors, such as hydrogen, carbon, silicon, and transition metals. There are elements, for example. For instance, oxygen is more abundant than the metallic elements that make up oxide semiconductors such as silicon. Elements with strong bonding forces can alter the atomic arrangement of oxide semiconductors by removing oxygen from them. It disrupts the crystallinity and causes a decrease in its properties. Also, heavy metals such as iron and nickel, argon, and nickel... Because carbon oxides and other elements have a large atomic radius (or molecular radius), they affect the atomic arrangement of oxide semiconductors. This disrupts the crystallinity and reduces its properties.

[0378] When oxide semiconductors contain impurities or defects, their properties may change due to light, heat, etc. For example, impurities contained in oxide semiconductors can act as carrier traps, or carriers A can become a source of emissions. For example, oxygen vacancies in oxide semiconductors can trap carriers and In some cases, it may become a carrier source by capturing hydrogen.

[0379] CAAC-OS, with its low impurity and oxygen vacancies, is an oxide semiconductor with a low carrier density. Specifically, 8 x 10 11 pieces / cm 3 Less than 1 × 10 11 / cm 3 less than, More preferably 1 × 10 10 pieces / cm 3 It is less than 1 × 10 -9 pieces / cm 3 The above It can be made into an oxide semiconductor with a carrier density. Such an oxide semiconductor can be made into a high-purity intrinsic Alternatively, it is called a substantially high-purity intrinsic oxide semiconductor. CAAC-OS has a low impurity concentration. Furthermore, it has a low defect level density. In other words, it can be said to be an oxide semiconductor with stable properties.

[0380] <nc-os> Next, I will explain nc-OS.

[0381] This section describes the case of analyzing nc-OS using XRD. For example, for nc-OS When structural analysis is performed using the out-of-plane method, no peaks indicating orientation appear. In other words, nc-OS crystals do not have orientation.

[0382] Furthermore, for example, nc-OS having an InGaZnO4 crystal is thinned to a thickness of 34 nm. When an electron beam with a probe diameter of 50 nm is incident on the region parallel to the surface to be formed, Figure 39 A ring-shaped diffraction pattern (nanobeam electron diffraction pattern) as shown in (A) was observed. Furthermore, the diffraction pattern when an electron beam with a probe diameter of 1 nm is incident on the same sample (na The beam electron diffraction pattern is shown in Figure 39(B). From Figure 39(B), a ring-shaped region is visible. Multiple spots are observed within. Therefore, nc-OS has a probe diameter of 50 nm. Order is not confirmed by irradiating with an electron beam, but when an electron beam with a probe diameter of 1 nm is irradiated... Order can be confirmed by having them shoot.

[0383] Furthermore, when an electron beam with a probe diameter of 1 nm is incident on a region with a thickness of less than 10 nm, As shown in Figure 39(C), an electron diffraction pattern was observed in which the spots were arranged in a roughly regular hexagonal shape. This may occur. Therefore, in the range of thickness less than 10 nm, nc-OS is ordered. It can be seen that there is a region with high fissure, i.e., a crystal. Furthermore, the crystals are oriented in various directions. Therefore, there are also regions where a regular electron diffraction pattern is not observed.

[0384] Figure 39(D) shows the Cs-corrected elevation of the cross-section of nc-OS observed from a direction approximately parallel to the surface being formed. High-resolution TEM images are shown. nc-OS refers to areas indicated by auxiliary lines in the high-resolution TEM image. As shown, there are regions where the crystalline structure can be observed and regions where the crystalline structure cannot be clearly observed. It has a region and a crystal portion contained in nc-OS, with a size of 1 nm to 10 nm. Yes, and they are often between 1 nm and 3 nm in size. Oxide semiconductors with a wavelength greater than 0 nm and less than or equal to 100 nm are called microcrystalline oxide semiconductors (micro It is sometimes called a crystalline oxide semiconductor. nc-OS is useful, for example, when grain boundaries cannot be clearly identified in high-resolution TEM images. There is a possibility that the nanocrystals share the same origin as the pellets in CAAC-OS. Therefore, the crystalline portion of nc-OS may be referred to as a pellet in the following text.

[0385] Thus, nc-OS is suitable for minute regions (for example, regions between 1 nm and 10 nm, particularly The atomic arrangement has periodicity in the region between 1 nm and 3 nm. Furthermore, nc-OS is Furthermore, no regularity is observed in the crystal orientation between different pellets. Therefore, orientation is not observed throughout the entire film. Therefore, nc-OS can be analyzed using methods that produce a-like OS or amorphous OS. It can sometimes be indistinguishable from oxide semiconductors.

[0386] Furthermore, since there is no regularity in the crystal orientation between pellets (nanocrystals), nc-OS is used. Oxides containing RANC (Random Aligned nanocrystals) semiconductors, or containing NANC (Non-Aligned nanocrystals) It can also be called an oxide semiconductor.

[0387] nc-OS is an oxide semiconductor with higher orderliness than amorphous oxide semiconductors. Therefore, nc-OS has a lower defect level density than a-like OS and amorphous oxide semiconductors. However, nc-OS does not show any regularity in crystal orientation between different pellets. nc-OS has a higher defect level density compared to CAAC-OS.

[0388] <a-like OS> a-like OS is an oxide semiconductor having a structure between nc-OS and amorphous oxide semiconductors. It is a conductor.

[0389] Figure 40 shows a high-resolution cross-sectional TEM image of an a-like OS. Here, Figure 40(A) is This is a high-resolution cross-sectional TEM image of a-like OS at the start of electron irradiation. Figure 40(B ) is 4.3 × 10 8 e - / nm 2 electrons (e - ) High a-like OS after irradiation These are high-resolution cross-sectional TEM images. From Figures 40(A) and 40(B), a-like OS It can be seen that, from the start of electron irradiation, striped bright regions extending in the vertical direction are observed. The bright regions show a change in shape after electron irradiation. Furthermore, the bright regions are either porous or low-density. It is presumed to be in the degree range.

[0390] Because it has porosity, a-like OS has an unstable structure. Below, a-like To demonstrate that the OS has a less stable structure compared to CAAC-OS and nc-OS. This shows the structural changes caused by electron irradiation.

[0391] As samples, prepare a-like OS, nc-OS, and CAAC-OS. The sample is also an In-Ga-Zn oxide.

[0392] First, high-resolution cross-sectional TEM images are obtained for each sample. All of them have a crystalline portion.

[0393] Furthermore, the unit cell of the InGaZnO4 crystal has three In-O layers, and Ga-Zn- It is known to have a structure in which a total of nine layers, including six O layers, are stacked in layers along the c-axis. The spacing between these adjacent layers is the same as the spacing between the grid planes of the (009) plane (also called the d value). It is approximately [value], and from crystal structure analysis, its value has been determined to be 0.29 nm. Therefore, Below, areas where the spacing of the grid stripes is between 0.28 nm and 0.30 nm are represented as InGaZn. This was considered to be the crystalline portion of O4. Note that the lattice fringes correspond to the ab-plane of the InGaZnO4 crystal. ru.

[0394] Figure 41 shows an example of investigating the average size of the crystalline regions (22 to 30 locations) in each sample. The length of the lattice fringes mentioned above is used to define the size of the crystal portion. From Figure 41, a-like The crystalline portion of the OS grows larger in proportion to the cumulative amount of electrons irradiated during TEM image acquisition, etc. It can be seen that, as shown in Figure 41, the size is about 1.2 nm in the initial stages of TEM observation. The crystal region (also called the initial nucleus) is then transformed into an electron (e - The cumulative radiation dose was 4.2 × 10⁻⁶ 8 e - / nm 2 In this case, it can be seen that it has grown to a size of about 1.9 nm. On the other hand, nc -OS and CAAC-OS are defined as the cumulative electron dose from the start of electron irradiation being 4.2 × 10⁻⁶. 8 e - / nm 2 Within this range, it can be seen that there is no change in the size of the crystal portion. (Figure 41) Furthermore, regardless of the cumulative electron irradiation dose, the size of the crystal region in nc-OS and CAAC-OS is, It can be seen that they are approximately 1.3 nm and 1.8 nm, respectively. TEM observations were performed using a Hitachi transmission electron microscope H-9000NAR. Electron beam irradiation conditions The acceleration voltage is 300kV and the current density is 6.7 × 10⁻⁶. 5 e - / (nm 2 ·s), irradiation area The diameter was set to 230 nm.

[0395] Thus, in a-like OS, crystalline growth can sometimes be observed upon electron irradiation. On the other hand, nc-OS and CAAC-OS show almost no crystal growth due to electron irradiation. It cannot be seen. In other words, a-like OS is different from nc-OS and CAAC-OS. It is clear that the structure is unstable.

[0396] Furthermore, because it has porosity, a-like OS is superior to nc-OS and CAAC-OS. It has a low-density structure. Specifically, the density of a-like OS is the same as that of a single crystal of the same composition. The density will be between 78.6% and 92.3%. Also, the density of nc-OS and CAAC - The density of OS is between 92.3% and 100% of the density of a single crystal of the same composition. Oxide semiconductors with a density of less than 78% are difficult to deposit into film.

[0397] For example, in an oxide semiconductor satisfying In:Ga:Zn=1:1:1 [atomic ratio], The density of single-crystal InGaZnO4 with a faceted crystal structure is 6.357 g / cm³. 3 That's how it is. For example, in an oxide semiconductor satisfying In:Ga:Zn=1:1:1 [atomic ratio] , the density of the a-like OS is 5.0 g / cm 3 or more and less than 5.9 g / cm 3 . Also , for example, in an oxide semiconductor satisfying In:Ga:Zn = 1:1:1 [atomic ratio], the density of the nc-OS and the density of the CAAC-OS are 5.9 g / cm 3 or more and less than 6.3 g / cm 3 .

[0398] In addition, when there is no single crystal of the same composition, by combining single crystals with different compositions in any ratio, the density corresponding to the single crystal in the desired composition can be estimated. The density corresponding to the single crystal of the desired composition may be estimated using the weighted average with respect to the ratio of combining single crystals with different compositions. However, it is preferable to estimate the density by combining as few types of single crystals as possible. As described above, the oxide semiconductor has various structures and each has various characteristics. Further, the oxide semiconductor may be, for example, a laminated film having two or more of an amorphous oxide semiconductor, a-like OS, nc-OS, CAAC-OS.

[0399] The configuration shown in this embodiment can be used in appropriate combination with the configuration shown in other embodiments.

[0400]

[0401] (Embodiment 5) In this embodiment, an example of a package and a module containing an image sensor chip will be described. The image sensor chip can employ the configuration of the imaging device according to one aspect of the present invention.

[0402] ​​​​​​Figure 42(A) is a perspective view of the top view of the package containing the image sensor chip. The package consists of a package substrate 810 for fixing the image sensor chip 850, and The device includes a bar glass 820 and an adhesive 830 for bonding the two together.

[0403] Figure 42(B) is a perspective view of the bottom of the package. On the bottom of the package, It has a BGA (Ball Grid Array) configuration with 840 solder balls as bumps. Yes. Note that this applies not only to BGA, but also to LGA (Land grid array) and PGA (P You could also use something like `in Grid Array`.

[0404] Figure 42(C) shows the package with some of the cover glass 820 and adhesive 830 omitted. This is a perspective view of the package, and Figure 42(D) is a cross-sectional view of the package substrate. An electrode pad 860 is formed on 810, and the electrode pad 860 and bump 840 are connected -Electrically connected via hole 880 and land 885. Electrode pad 860 The electrodes of the image sensor chip 850 are electrically connected by the wire 870. It is.

[0405] Figure 43(A) shows a camera with an image sensor chip housed in a lens-integrated package. This is a perspective view of the top side of the camera module. The camera module is an image sensor. Package substrate 811, lens cover 821, and lens 835 for fixing the top 851 It has the following features. Also, between the package substrate 811 and the image sensor chip 851 An IC chip 890 is also provided, which has functions such as a drive circuit and a signal conversion circuit for the image device. It has a configuration as a SiP (System in Package).

[0406] Figure 43(B) is a perspective view of the lower side of the camera module. Package substrate 8 The bottom and four sides of 11 are provided with mounting lands 841 for the QFN (Quad f It has a lat no-lead package configuration. Note that this configuration is just one example. Yes, it can be a QFP (Quad flat package) or the aforementioned BGA, etc. stomach.

[0407] Figure 43(C) shows the module with the lens cover 821 and part of the lens 835 omitted. This is a perspective view of the frame, and Figure 43(D) is a cross-sectional view of the camera module. A portion of 41 is used as an electrode pad 861, and the electrode pad 861 is an image sensor chip The electrodes of the pin 851 and IC chip 890 are electrically connected by wire 871. It is.

[0408] By housing the image sensor chip in the type of package described above, implementation becomes easier. It can be incorporated into various semiconductor devices and electronic equipment.

[0409] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments. can.

[0410] (Embodiment 6) An imaging device and an electronic device including the imaging device according to one aspect of the present invention are display devices, personal devices, Digital computer, image playback device equipped with recording media (typically DVD: Digital) A display capable of playing recording media such as Versatile Discs and displaying their images. It can be used in devices that have a ray. In addition, an imaging device according to one aspect of the present invention Electronic devices that can use the said imaging device include mobile phones, mobile phones Game consoles including mobile data terminals, e-readers, video cameras, digital still cameras Cameras such as RA, goggle-type displays (head-mounted displays), navigation systems Audio systems, sound reproduction equipment (car audio, digital audio players, etc.), copying Machines, fax machines, printers, multifunction printers, automated teller machines (ATMs), self Examples include vending machines. Specific examples of these electronic devices are shown in Figure 44.

[0411] Figure 44(A) shows a portable game console, consisting of a casing 901, casing 902, display unit 903, and display unit. 904, Microphone 905, Speaker 906, Control keys 907, Stylus 908, Camera It has 909, etc. Note that the portable game console shown in Figure 44(A) has two display units 903 It has a display unit 904, but the number of display units that a portable game console has is not limited to this. It is not possible. Camera 909 can use an imaging device according to one aspect of the present invention.

[0412] Figure 44(B) shows a portable data terminal, comprising a first housing 911, a display unit 912, a camera 919, etc. It has a touch panel function on the display unit 912, which allows for information input and output. A camera 919 can be equipped with an imaging device according to one embodiment of the present invention.

[0413] Figure 44(C) shows a wristwatch-type information terminal, comprising a housing 931, a display unit 932, and a wristband 9 33. It has operating buttons 935 and a crown 936, a camera 939, etc. Display unit 932 It may be a touch panel. The camera 939 uses an imaging device according to one aspect of the present invention. It is possible.

[0414] Figure 44(D) shows a surveillance camera, which has a housing 951, a lens 952, a support part 953, etc. An imaging device according to one embodiment of the present invention can be provided at the focal point of lens 952.

[0415] Figure 44(E) shows a digital camera, consisting of a housing 961, a shutter button 962, and a microphone 9 It has a 63, a light-emitting part 967, a lens 965, etc. The light-emitting part is located at the focal point of the lens 965. An imaging device of one aspect can be provided.

[0416] Figure 44(F) shows a video camera, comprising a first housing 971, a second housing 972, a display unit 973, It has an operation key 974, a lens 975, a connecting part 976, etc. Operation key 974 and lens 975 is provided in the first housing 971, and the display unit 973 is provided in the second housing 972. And the first housing 971 and the second housing 972 are connected by a connecting part 976. The angle between the first housing 971 and the second housing 972 can be changed by the connecting part 976. The video on the display unit 973 is connected to the first housing 971 and the second housing 97 in the connection unit 976. It is also possible to configure it to switch according to the angle between 2 and 3. At the focal position of lens 975. The present invention may include an imaging device according to one embodiment of the present invention.

[0417] This embodiment can be appropriately combined with other embodiments shown herein. . [Explanation of Symbols]

[0418] 12. Imaging Operation 13. Data retention operation 14. Read operation 20 pixels 23 circuits 24 circuits 25 circuits 26 circuits 31 Comparator Circuit 32 circuits 33 circuits 34 Flip-flop circuits 35 Flip-flop circuits 36 Flip-flop circuits 41 Transistors 42 transistors 43 transistors 44 transistors 45 transistors 46 transistors 51 Inverter Circuit 52 Inverter Circuit 53 Inverter Circuit 54 Inverter Circuit 55 Inverter Circuit 56 Selector Circuit 57 Selector Circuit 58 Selector Circuit 59 Selector Circuit 61 Wiring 62 Wiring 63 Wiring 64 Wiring 65 Wiring 66 Wiring 67 Wiring 68 Wiring 69 Wiring 71 Wiring 72 Wiring 73 Wiring 74 Wiring 75 Wiring 76 Wiring 80 Insulating layer 81 Conductors 82 Insulating layer 82a Insulating layer 82b Insulating layer 83 Insulating layer 87 Wiring 87a Conductive layer 87b Conductive layer 88 Wiring 90 Wiring 91 Wiring 92 Wiring 93 Wiring 94 Wiring 95 Wiring 96 Wiring 97 Wiring 101 Transistors 102 transistors 103 Transistors 104 transistors 105 transistors 106 transistors 107 transistors 108 transistors 109 transistors 110 transistors 111 transistors 112 transistors 113 Transistors 115 circuit boards 120 Insulating layer 130 Oxide semiconductor layer 130a Oxide semiconductor layer 130b Oxide Semiconductor Layer 130c oxide semiconductor layer 140 Conductive layer 141 Conductive layer 142 Conductive layer 150 conductive layer 151 Conductive layer 152 Conductive layer 160 Insulating layer 170 Conductive layer 171 Conductive layer 172 Conductive layer 173 Conductive layer 175 Insulating layer 180 Insulating layer 190 Insulating layer 231 areas 232 areas 233 areas 331 areas 332 areas 333 areas 334 areas 335 areas 561 Photoelectric conversion layer 562 Transparent conductive layer 563 Semiconductor layer 564 Semiconductor layer 565 Semiconductor layer 566 Electrode 566a conductive layer 566b Conductive layer 567 Bulkhead 600 silicon substrate 610 transistors 620 transistors 650 active layer 660 silicon substrate 810 Package Substrate 811 Package substrate 820 Cover Glass 821 Lens Cover 830 Adhesive 835 lens 840 Bump 841 Land 850 Image Sensor Chips 851 Image Sensor Chip 860 Electrode Pads 861 Electrode Pads 870 wire 871 Wire 880 Through Hole 885 Rand 890 IC chip 901 cabinet 902 cabinet 903 Display section 904 Display section 905 Microphone 906 Speakers 907 Operation Keys 908 Stylus 909 Camera 911 cabinet 912 Display section 919 Camera 931 cabinet 932 Display section 933 Wristband 935 buttons 936 Crown 939 Camera 951 cabinet 952 Lens 953 Support part 961 cabinet 962 Shutter button 963 Mike 965 lens 967 Light-emitting part 971 cabinet 972 cabinets 973 Display section 974 Operation Keys 975 lens 976 Connection part 1100 layers 1200 layers 1400 layers 1500 diffraction grating 1600 layers 2500 Insulating layer 2510 Light blocking layer 2520 Organic resin layer 2530 Color Filters 2530a color filter 2530b color filter 2530c color filter 2540 Microlens Array 2550 Optical Conversion Layer 2560 Insulating layer

Claims

1. A plurality of pixels, each having a photoelectric conversion element and a first transistor, It has a signal processing circuit having a second transistor, The region having above the layer containing the second transistor is a region in which the layer containing the first transistor is disposed, An imaging device having a region above the first transistor in which the photoelectric conversion element is arranged, A first insulating layer having a region in contact with the side surface of the photoelectric conversion element, A second insulating layer having a region that fills the gap between the cathodes of the photoelectric conversion element of adjacent first and second pixels among the plurality of pixels, and having a region that does not overlap with the cathode, A light-shielding layer having a region that overlaps with the second insulating layer and a region that is positioned above the first insulating layer, The second insulating layer has a region in contact with the first insulating layer. Imaging device.

2. A plurality of pixels, each having a photoelectric conversion element and a first transistor, It has a signal processing circuit having a second transistor, The region having above the layer containing the second transistor is a region in which the layer containing the first transistor is disposed, An imaging device having a region above the first transistor in which the photoelectric conversion element is arranged, A first insulating layer having a region in contact with the side surface of the photoelectric conversion element, A second insulating layer having a region that fills the gap between the cathodes of the photoelectric conversion element of adjacent first and second pixels among the plurality of pixels, and having a region that does not overlap with the cathode, A light-shielding layer having a region that overlaps with the second insulating layer and a region that is positioned above the first insulating layer, The second insulating layer has a region in contact with the first insulating layer, The side surface of the photoelectric conversion element overlaps with the light-shielding layer. Imaging device.

3. In claim 1 or claim 2, The first insulating layer is a silicon oxide film. Imaging device.

4. In any one of claims 1 to 3, A conductor having a region facing the side surface of the photoelectric conversion element via the first insulating layer, Imaging device.

Images