Semiconductor structure

Abstract

1. A semiconductor structure comprising: a first dielectric layer having a first conductive metal feature embedded within the first dielectric layer; and a second dielectric layer having a second conductive metal feature embedded within the second dielectric layer, the second conductive metal feature overlying and in direct contact with the first conductive metal feature, and an interface between the second conductive metal feature and the second dielectric layer comprising a repeating scallop shape along its entire length.

Description

[Technical Field]

[0001] This invention generally relates to the field of semiconductor manufacturing, and more specifically to the alternating periodic deposition of selective metals and dielectrics. [Overview of the project]

[0002] According to one embodiment of the present invention, the semiconductor structure comprises a first dielectric layer having a first conductive metallic functional portion embedded within a first dielectric layer; and a second dielectric layer having a second conductive metallic functional portion embedded within a second dielectric layer, wherein the second conductive metallic functional portion is located above and in direct contact with the first conductive metallic functional portion, and the interface between the second conductive metallic functional portion and the second dielectric layer includes a repeating scallop shape along its entire length.

[0003] According to another embodiment, the semiconductor structure comprises a metal nanostructure embedded within a dielectric layer, and the boundary between the conductive metal functional portion and the dielectric layer has a repeating scallop shape along its entire length.

[0004] According to another embodiment, the semiconductor structure comprises a conductive nanostructure embedded within a dielectric layer, and the interface between the conductive metallic functional portion and the dielectric layer has a repeating scallop pattern along its entire length, so that the scalloped portion of the dielectric material of the dielectric layer partially overlaps with the scalloped portion of the metallic material of the conductive nanostructure. [Brief explanation of the drawing]

[0005] The following detailed description is provided for illustrative purposes only and is not intended to limit the invention to therein, and will be best understood in conjunction with the accompanying drawings.

[0006] [Figure 1] This is a cross-sectional view of a semiconductor structure according to an exemplary embodiment.

[0007] [Figure 2]A cross-sectional view of a semiconductor structure showing the state after depositing a first dielectric layer according to an exemplary embodiment.

[0008] [Figure 2A] The cross-sectional view of FIG. 2, showing cross-section A.

[0009] [Figure 3] A cross-sectional view of a semiconductor structure showing the state after depositing a first metal layer according to an exemplary embodiment.

[0010] [Figure 3A] The cross-sectional view of FIG. 3, showing cross-section A.

[0011] [Figure 4] A cross-sectional view of a semiconductor structure showing the state after periodically depositing additional dielectric layers and additional metal layers in an alternating manner according to an exemplary embodiment.

[0012] [Figure 4A] The cross-sectional view of FIG. 4, showing cross-section A.

[0013] <000​​​​​​​​​​​​​​​​​​​​​​​​​A cross-sectional view of a semiconductor structure showing the state after periodically depositing a dielectric layer and a metal layer, according to another exemplary embodiment.

[0018] [Figure 7A] The cross-sectional view of FIG. 7, showing cross-section A.

[0019] [Figure 8] A cross-sectional view of a semiconductor structure showing the state after periodically depositing a dielectric layer and a metal layer, according to another exemplary embodiment.

[0020] [Figure 8A] The cross-sectional view of FIG. 8, showing cross-section A.

[0021] [Figure 9] A cross-sectional view of a semiconductor structure showing the state after periodically depositing a dielectric layer and a metal layer, according to another exemplary embodiment.

[0022] [Figure 9A] The cross-sectional view of FIG. 9, showing cross-section A.

[0023] The elements in the figures are not necessarily to scale, unless specifically referenced and noted, and are not intended to depict specific parameters of the present invention. For clarity and ease of illustration, the scale of the elements may be shown larger than actual. For exact dimensions, refer to the detailed description. The drawings are intended to show only typical embodiments of the present invention and should not be regarded as limiting the scope of the present invention. In the drawings, like reference numerals represent like elements.

Best Mode for Carrying Out the Invention

[0024] Detailed embodiments of the claimed structure and method are disclosed herein; however, it should be understood that the disclosed embodiments are merely illustrative of the claimed structure and method, which may be embodied in various forms. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the exemplary embodiments described herein. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the embodiments presented.

[0025] References in this specification such as "one embodiment," "one example embodiment," and "one example embodiment" indicate that the embodiments described may include certain features, structures, or characteristics, but not all embodiments may necessarily include such features, structures, or characteristics. Furthermore, such phrases do not necessarily refer to the same embodiments. Moreover, if certain features, structures, or characteristics are described in relation to one embodiment, it is considered within the knowledge of those skilled in the art that such features, structures, or characteristics will be affected in relation to other embodiments, whether or not they are explicitly described.

[0026] For the purposes of the following description, the terms “upper,” “downward,” “right,” “left,” “vertical,” “horizontal,” “top,” and “bottom,” and their derivatives, refer to structures and methods disclosed as oriented in the drawings. The terms “upper,” “top,” “top,” “positioned on top,” or “positioned on top” mean that a first element, such as a first structure, is located on a second element, such as a second structure, and an intervening element, such as an interface structure, may be located between the first and second elements. The term “direct contact” means that a first element, such as a first structure, and a second element, such as a second structure, are connected at the interface of the two elements without any intermediate conductive, insulating, or semiconductor layer.

[0027] The terms substantially, substantially similar, about, or any other term indicating functionally equivalent similarity refer to cases where differences in length, height, or direction do not convey a practical difference between a clear enumeration (e.g., phrases other than the term substantially similar) and substantially similar variations. In one embodiment, substantial (and its derivatives) means a difference due to engineering or manufacturing tolerances generally accepted for similar devices, e.g., a maximum deviation of 10% in value or 10 degrees in angle.

[0028] To avoid ambiguity in the presentation of embodiments of the present invention, in the following detailed description, some processing steps or operations known in the art may be combined for presentation and illustrative purposes, and in some cases may not be described in detail. In other cases, some processing steps or operations known in the art may not be described at all. It should be understood that the following description focuses rather on the specific features or elements of various embodiments of the present invention.

[0029] To date, scaling the functional parts of integrated circuits has motivated innovation in the ever-growing semiconductor industry. Smaller functional parts enable higher device density and the manufacture of products with increased capacity. To accommodate scaling, the size and spacing of functional parts in integrated circuits have decreased over time, and this trend is expected to continue.

[0030] With the 7nm technology node in development and the 5nm node moving into development, transistor scaling is becoming increasingly complex. Furthermore, performance advantages gained in the substrate process, such as those in semiconductor devices like transistors, can easily be lost if similar improvements are not made in the wiring process. The wiring process involves creating multilayers of conductive structures, such as metal wires and vias, to form the necessary electrical connections between various microelectronic devices, such as transistors.

[0031] The metal wiring scheme for each technology node is becoming more complex, primarily due to the increasing number of transistors to be connected and the resulting need for increasingly narrower pitches. The narrower pitches and shrinking dimensions in the board manufacturing process require thinner wires in the wiring process, and thinner wires result in a higher resistive-capacitive product (RC) of the interconnection system.

[0032] Conductive structures are typically formed using lithography techniques; however, current lithography techniques have known limitations and drawbacks, particularly when the size of the functional part is less than 20 nm. Selective deposition techniques can be used to overcome some of the known shortcomings of conventional lithography techniques; however, these also have drawbacks. As an alternative to forming functional parts by lithography, dielectric materials are typically deposited selectively on dielectric materials, and metals are deposited selectively on metals to form various functional parts, such as conductive structures. Depositing materials in this manner is known to produce "mushroom-shaped" films, which, when deposited continuously, increase in size laterally. For example, each selectively deposited film is wider than the previous one.

[0033] Therefore, additional steps must be taken to control the lateral growth of functional parts formed using selective deposition. Known techniques used to control the lateral growth of selectively deposited films include some form of blocking or intermediate etching. Blocking or preventing the lateral growth of each layer allows for good control of the lateral shape and size of the resulting functional part; however, creating a blocking structure requires additional steps. In such cases, the blocking structure may involve using known masking and patterning techniques. Alternatively, intermediate etching may be used to trim or etch each layer immediately after deposition. Although the width of subsequently deposited layers increases, intermediate etching of each layer between consecutive depositions can be used to trim the width of each layer to a predetermined width, resulting in the desired shape and size of the functional part. Unfortunately, blocking and intermediate etching have their own challenges. In addition to requiring additional processing steps, both blocking and intermediate etching can experience misalignment, which can worsen with small functional part sizes and narrow pitches.

[0034] The alternating periodic deposition technique described herein enables the construction of robust nanointerconnection structures and devices with optimal electronic performance and device reliability. For example, the alternating periodic deposition technique described herein enables (a) robust and perfectly aligned via structures with controlled thickness; (b) etching-stopping diffusion / oxidation barriers; (c) increased dielectric Emax / Vmax breakdown / leakage current; and (d) nanostructures with reduced resistive capacitance. For the purposes of the present invention, a nanostructure is defined as any semiconductor structure having sublithographic dimensions. "Minimum lithographic dimension" and "sublithographic dimension" are defined only in relation to lithography tools and typically change from generation to generation of semiconductor technology, but it is understood that the minimum lithographic dimension and sublithographic dimension are defined in relation to the best performance of the lithography tools available at the time of semiconductor manufacturing. As of 2021, the minimum lithographic dimension is approximately 50 nm and is expected to shrink in the future.

[0035] According to embodiments of the present invention, metals are selectively deposited on dielectrics, and dielectrics are selectively deposited on metals. In other words, metals are deposited on metals, and dielectrics are deposited on dielectrics. For example, known CVD or ALD techniques can be used to selectively deposit metals such as Co, Ru, Mn, W, Pt, or CoWP. Similarly, known CVD or ALD techniques can be used to selectively deposit dielectrics such as SiO2, AlOx, ZnO, HfOx, SiN, or SiCOH.

[0036] Furthermore, dielectrics and metals may be selected based on the substrate material on which they are deposited. Subsequent layers may be made of the same or different substrate material on which they are deposited. Materials are carefully selected to optimize the properties of the final structure.

[0037] For example, dielectrics may be selected to optimize dielectric breakdown / leakage for nanodevice performance, such as oxidation / metal diffusion barriers (SiCN, AlOx_SiCO), Emax (C-rich SiCN, SiOx), Vmax (C-rich SiCN, bilayer), or dielectrics with storage memory / AI functionality, such as HfOx and ferroelectrics, may be used as memory cell devices with subsequent integration. For example, in some embodiments, low-k (k~3.3) C-rich SiCN may be used for the first and last layers of a multilayer dielectric stack to enhance the reliability of time-dependent dielectric breakdown (hereinafter, "TDDB") due to reduced plasma-induced damage and improved oxidation and diffusion properties. Selective metal layers may also be modified to improve the stacking properties of the metal film.

[0038] In addition, for example, to improve contact resistance, different metals such as Ti may be used below or above the Co layer, or to enhance oxidation resistance, a selective Ru or W metal may be used above the Co. In yet another example, alternating Ru / Co layers can improve both oxidation resistance and line resistance. In yet another example, the insertion of Ru or Mn nanolayers above the Co / Cu layer improves EM reliability due to the strengthened bonding between the metal interfaces and the oxygen gettering properties of Mn that form MnOx. Multilayer metals with robust in-situ metal capping at the top and bottom enhance both contact resistance and EM reliability. In yet another example, to achieve similar advantages as described above, Co and Mn may be used above and below the Cu, or Co / Ti may be used above and below the Ru metal.

[0039] The present invention generally relates to the field of semiconductor manufacturing, and more specifically to the alternating periodic deposition of thin films. More specifically, the selective deposition of dielectric materials and metals in an alternating manner can be used to independently control the lateral growth of such thin films. The use of selective deposition techniques eliminates the need for blocking or intermediate etching and improves dimensional control of the final functional part / structure. One embodiment of selective deposition of dielectric materials and metals in an alternating manner is described in detail below with reference to the accompanying drawings in Figures 1 to 9. Those skilled in the art will readily understand that the present invention extends beyond these limiting embodiments, and therefore the detailed description provided herein with respect to these figures is for illustrative purposes only.

[0040] The alternating periodic deposition technique described herein can be used to manufacture various structures with improved dimensional control, thereby enabling higher performance and enhanced reliability. For example, the alternating periodic deposition technique described herein can be used to form conductive structures such as perfectly aligned via structures, contact structures, or robust metal lines. The periodic deposition technique described herein enables precise control of thickness and lateral growth, further resulting in improved device performance. This precision further enables the manufacture of nanostructures that are better aligned with the substrate structure, thereby reducing the dielectric gap between adjacent structures. As described above, forming conductive structures using the periodic deposition technique described herein can minimize contact and line resistance, and further enable highly conductive nanostructures. Furthermore, robust, highly advanced nanometallic interconnect structures can be manufactured using low-k dielectric (fluid CVD SiCOH2.7) gap fills that do not cause plasma damage.

[0041] Advantageously, the selective deposition of thin metal and dielectric films in an alternating manner can be implemented in the wiring process and is compatible with current process flows. The wiring process can be distinguished from the substrate process in that semiconductor devices, such as transistors, can typically be manufactured in the substrate process, while the connections to and between these semiconductor devices are typically formed in the wiring process.

[0042] Referring here to Figure 1, structure 100 is shown. Structure 100 may include a dielectric layer 102 and a metallic region 104. The dielectric layer 102 and the metallic region 104 represent a single exemplary metallization layer or level in the wiring or intermediate process of the semiconductor structure. The metallization layer shown in Figure 1 may represent any interconnection level in the semiconductor structure.

[0043] The dielectric layer 102 may include any suitable dielectric material, such as silicon oxide (SiO2), silicon nitride (Si3N4), silicon dioxide (SiCOH), silicon-based low-k dielectrics, or porous dielectrics. Alternatively, the dielectric layer 102 may include ultra-low k (ULK) materials such as porous silicates, carbon-doped oxides, silicon dioxide, silicon nitride, silicon oxynitride, carbon-doped silicon oxide (SiCOH) and its porous variants, silsesquioxanes, siloxanes, or other dielectric materials having dielectric constants in the range of about 2 to about 4.

[0044] To form the dielectric layer 102, known and suitable deposition techniques such as atomic layer deposition, chemical vapor deposition, plasma-excited chemical vapor deposition, spin-on deposition, or physical vapor deposition may be used. The dielectric layer 102 may have a typical thickness in the range of about 100 nm to about 150 nm and in between, but thicknesses less than 100 nm and greater than 150 nm may be acceptable. Although only a single interconnection level is shown, it should be noted that structure 100 may have multiple interconnection levels above and / or below the shown level.

[0045] The metal region 104 is formed in the dielectric layer 102 according to known techniques. In one embodiment, the metal region 104 includes a typical conductive functional part, such as a line or wire, which is typically found in wiring processes. In a different embodiment, the metal region 104 includes a metal contact region or other metal interconnection structure.

[0046] The metallic regions 104 can have substantially similar structures and can be manufactured, for example, using typical single or dual damascene techniques in which conductive interconnecting material can be deposited in grooves formed in the dielectric layer 102. Alternatively, known subtraction techniques can also be used to form the metallic regions 104. In some embodiments, the metallic regions 104 are formed using known selective deposition techniques. Although only two metallic regions 104 are shown, it should be noted that the structure 100 can have any number of metallic regions arranged at any number of metallization levels.

[0047] The metallic region 104 can be made from any conductive material known in the art, such as copper (Cu), aluminum (Al), or tungsten (W). In one embodiment, the metallic region 104 may be copper (Cu) and may include a metallic liner (not shown), which may include one or more conformal metal layers such as tantalum nitride and tantalum (TaN / Ta), titanium, titanium nitride, cobalt, ruthenium, and manganese.

[0048] Referring to Figures 2 and 2A, the first dielectric layer 106 is selectively deposited on the upper surface of the dielectric layer 102. Figure 2A is a cross-sectional view of Figure 2, section A. The details and subsequent cross-sectional views shown in Figure 2A are provided for illustrative purposes only and are not necessarily drawn to scale.

[0049] As described herein, selective deposition refers to the selective deposition of material on surface A rather than on surface B. The ability to selectively deposit semiconductor materials enables new integration and patterning schemes while reducing the number of manufacturing operations otherwise associated with conventional semiconductor manufacturing processes, as described above. Embodiments of the present invention apply the principle of selective deposition, but the method addresses the aforementioned shortcomings.

[0050] Generally, according to known techniques, the first dielectric layer 106 is selectively deposited on the upper surface of the dielectric layer 102 without depositing on the adjacent surface of the metal region 104. Thus, the first dielectric layer 106 is generally self-aligned with the underlying dielectric layer 102; however, some lateral growth or lateral overlap is expected. In such cases, the first dielectric layer 106 extends laterally beyond the interface between the dielectric layer 102 and the metal region 104. Otherwise, a small portion of the first dielectric layer 106 is formed on top of the metal region 104, as generally shown in Figure 2A. As described above, such lateral overlap is generally undesirable, and additional measures must be taken to control the width of the layer formed using selective deposition techniques.

[0051] Furthermore, as shown in the figure, it should be noted that selectively depositing the first dielectric layer 106 generates a rounded edge or scalloped shape at the outermost edge of the first dielectric layer 106. In all cases, the exact shape and size of the scalloped shape depend on the selected selective deposition technique and the individual layer thickness. For example, layers deposited with thinner thicknesses generally have smaller scalloped shapes and less overlap. The main objective of using the techniques described herein is to optimize the fabrication of nanostructures. Therefore, thinner layers are used to precisely control the shape and position of the final structure. Generally, thinner layers produce more uniform functional areas with less irregularity. Specifically, thinner layers result in less overlap and smaller scalloped shapes, thus creating a relatively uniform interface between the dielectric and the metal. In contrast, thicker layers result in more overlap and larger scalloped shapes, thus creating a relatively non-uniform interface between the dielectric and the metal.

[0052] According to embodiments of the present invention, the first dielectric layer 106 is deposited as a very thin film. For example, in the case of nanostructures having a limiting dimension of less than 20 nm, in order to suppress lateral overlap and fully understand the advantages of the present invention, the first dielectric layer 106 has a thickness of less than 40 angstroms (4 nm), and more preferably less than 30 angstroms (3 nm) (T d It is important that the deposition is carried out in a specific manner. The amount by which the first dielectric layer 106 extends laterally beyond the interface between the dielectric layer 102 and the metal region 104 decreases as the thickness of the first dielectric layer 106 decreases. If the lateral growth is greater than 2 nm, the advantages and effectiveness of the alternating periodic deposition technique described herein are reduced. For example, lateral overlap greater than about 2 nm results in conductive nanostructures with low dielectric Emax / Vmax breakdown performance and increased resistive capacitance.

[0053] Selectively depositing a thinner first dielectric layer (106) suppresses or reduces the amount of overlap between the first dielectric layer 106 and the metal region 104. For example, a first dielectric layer 106 deposited at approximately 20-30 angstroms (approximately 2-3 nm) overlaps the metal region 104 laterally by approximately 2 nm or less. As previously described above, the alternating periodic deposition technique described herein generates a scalloped shape, which produces a small sawtooth contour along the sidewalls of any resulting metal or dielectric structure. In some embodiments, after alternating periodic deposition, some of all metal layers can be selectively removed relative to the dielectric layer, or vice versa. In such cases, wet etching or downstream non-directional plasma etching with a low etching rate can be used to smooth the sawtooth contour along the sidewalls of any resulting metal or dielectric structure.

[0054] In at least one embodiment, the selective deposition of the first dielectric layer 106 is achieved by thermal ALD or thermal CVD using a self-assembled monolayer to block the metal surface from dielectric deposition. In one embodiment, the selective deposition of the first dielectric layer 106 may be carried out with or without pretreatment of any adjacent or near metal surface.

[0055] The first dielectric layer 106 may include, but is not limited to, any dielectric material that is compatible with known selective deposition techniques, such as the exemplary materials listed above. According to one embodiment, the first dielectric layer 106 may include the same or similar dielectric material as the underlying dielectric layer 102. According to an alternative embodiment, the first dielectric layer 106 may include a dielectric material different from that of the underlying dielectric layer 102.

[0056] As explained above, different dielectric materials can be used as reinforcing layers, such as etching stop layers, to reduce plasma-induced damage, act as oxidation and / or diffusion barriers, and increase the breakdown voltage for improved device performance. The same or different materials may be specifically selected for reasons that affect manufacturing. For example, similar materials may be used to promote good adhesion of subsequently deposited layers.

[0057] Referring to Figures 3 and 3A, the first metal layer 108 is selectively deposited on the upper surface of the metal region 104. Figure 3A is a cross-sectional view of Figure 3, specifically section A.

[0058] Generally, according to known techniques, the first metal layer 108 is selectively deposited on the upper surface of the metal region 104 without depositing on the adjacent surface of the dielectric layer 102. Therefore, as shown in the figure, the first metal layer 108 is generally self-aligned with the exposed portion of the metal region 104 and stops at the side edge of the adjacent surface of the first dielectric layer 106. In fact, the previously deposited first dielectric layer 106 stops or prevents the lateral growth of the first metal layer 106; however, some lateral growth or lateral overlap is expected. In such cases, as generally shown in Figure 3A, a small portion of the first metal layer 108 extends laterally and overlaps with a small portion of the first dielectric layer 106.

[0059] The small portion of the first metal layer 108 that overlaps with the first dielectric layer 106 also has a rounded or scalloped contour, as shown in the figure. In all cases, the exact shape and size of the scalloped contour depend on the selected selective deposition technique and the individual layer thickness. For example, layers deposited at thinner thicknesses generally have smaller scalloped contours and less overlap. Similarly, for example, the first metal layer 108 deposited at about 20-30 angstroms (about 2-3 nm) overlaps the first dielectric layer 106 laterally by about 2 nm or less.

[0060] The primary objective of using the techniques described herein is to optimize the fabrication of nanostructures. Therefore, thinner layers are used to precisely control the shape and position of the final structure. Optionally, as previously described above, non-directional wet or downstream plasma etching may also be used to smooth scalloped contours.

[0061] In at least one embodiment, the selective deposition of the first metal layer 108 is achieved by thermal ALD or thermal CVD using a precursor, and suitable co-reacting materials such as hydrogen or ammonia may be used. In one embodiment, the selective deposition of the first metal layer 108 may be carried out with or without pretreatment of any adjacent or near dielectric surface.

[0062] The first metal layer 108 may include any metal that is compatible with known selective deposition techniques, such as the exemplary materials listed above, but is not limited to those described above. According to one embodiment, the first metal layer 108 may include the same or similar metal as the underlying metal region 104. Alternatively, in one embodiment, the first metal layer 108 may include a different metal from the underlying metal region 104. As previously mentioned, using a different metal layer can improve interfacial bonding with subsequent metal layers, thereby improving contact resistance, reducing line resistance, and consequently improving the electron transfer properties of the conductive structure.

[0063] Similar to the first dielectric layer 106, the first metal layer 108 is also deposited as a very thin film. For example, in order to suppress lateral overlap and fully understand the advantages of the present invention, the first metal layer 108 has a thickness of less than 40 angstroms (4 nm), and more preferably less than 30 angstroms (3 nm) (T m It is important to deposit the metal layer (108) in a thin layer. The amount by which the first metal layer 108 extends laterally and is formed on the first dielectric layer 106 decreases as the thickness of the first metal layer 108 decreases. In other words, selectively depositing thinner metal layers (108) suppresses or reduces the amount by which the first metal layer 108 overlaps with the first dielectric layer 106.

[0064] In the embodiments shown in Figures 3 and 3A, the first metal layer 108 is deposited thicker than the first dielectric layer 106 to provide some degree of control over the shape and size of the final functional part. Doing so helps in positioning the final structure and controlling the lateral growth of the laterally deposited dielectric layer formed on top of the first dielectric layer 106. More specifically, the first metal layer 108 can be up to twice the thickness of the first dielectric layer 106; however, the exact thickness can be adjusted or modified as needed to control the shape and size of the final conductive functional part.

[0065] Referring to Figures 4 and 4A, an additional dielectric layer 110 and an additional metal layer 112 are periodically deposited in an alternating manner to form a conductive functional portion 114. Figure 4A is a cross-sectional view of Figure 4, specifically section A.

[0066] Regarding the structural components of Figures 3 and 3A, the additional dielectric layer 110 and the additional metal layer 112 are selectively deposited one after the other in an alternating or periodic manner. In this example, since the first metal layer 108 was deposited immediately last, the deposition of the additional layers (110, 112) begins with the selective deposition of the additional dielectric layer. Note that the lateral growth of each layer is generally controlled by the layer deposited immediately before it.

[0067] For example, the alternating selective deposition of additional layers (110, 112) continues until the conductive functional section 114 reaches a desired size or height. The resulting height of the conductive functional section 114 is controlled by adjusting the total number of layers deposited; however, the width and shape of the conductive functional section are controlled by adjusting the thickness of the individual layers and the order in which they are deposited.

[0068] The additional dielectric layer 110 and the additional metal layer 112 are formed from the same materials as those described above for the first metal layer 106 and the first dielectric layer 108, using the same techniques and to the same thickness. Alternatively, a variety of different materials may be used to produce or control the specific properties described above. For example, the first dielectric layer 106 may be made of a different material from all of the additional dielectric layers 110, and similarly, the first metal layer 108 may be made of a different material from all of the additional metal layers 112.

[0069] In this example, the first dielectric layer 106 has a thickness (T) of the first metal layer 108. m ) is thinner than (T d ) is deposited first. Furthermore, the additional dielectric layer 110 and the additional metal layer 112 each have a thickness equal to or substantially the same as the thickness of the first metal layer 108. In other words, according to this example, the first layer to be deposited is thinner than all the layers deposited later. Therefore, the width of each conductive functional part 114 is substantially equal to or slightly smaller than the width of each metal region 104, as shown in Figure 4A.

[0070] As described above, adjusting the thickness of the first dielectric layer 106 in this embodiment ultimately determines the width of the resulting conductive functional portion 114. For example, the overlap or lateral elongation of the first dielectric layer 106 increases as the thickness of the first dielectric layer 106 increases. Similarly, the overlap or lateral elongation of the first dielectric layer 106 decreases as the thickness of the first dielectric layer 106 decreases. Therefore, depositing a very thin first dielectric layer 108 provides precise control over the width of the resulting conductive functional portion (114). In the fabrication of nanostructures, controlling the width of the resulting conductive functional portion is increasingly important to prevent electrical short circuits with adjacent structures.

[0071] In addition, as a result of the uniform or substantially equal thickness of the additional dielectric layer 110 and the additional metal layer 112, the sidewalls of the conductive functional portion 114 are substantially vertical or perpendicular.

[0072] Ultimately, the periodic deposition techniques described herein offer superior dimensional control compared to existing fabrication techniques, such as typical single or dual damascene techniques, which are prone to misalignment due to the limited lithographic resolution of nanodevices.

[0073] Figures 5 to 9 each illustrate different alternative embodiments, demonstrating the functionality and unique control of the periodic deposition techniques described above in this specification.

[0074] Referring to Figures 5 and 5A, the additional dielectric layer 110 and the additional metal layer 112 are deposited periodically in an alternating manner to form the conductive functional portion 114. Figure 5A is a cross-sectional view of Figure 5, section A. As described above, the additional dielectric layer 110 and the additional metal layer 112 are deposited sequentially and selectively in an alternating or periodic manner; however, in different orders and with different layer thicknesses.

[0075] In this example, the first metal layer 108 has a thickness (T) of the first dielectric layer 106. d ) is thinner than (T m ) is deposited first. Furthermore, the additional dielectric layer 110 and the additional metal layer 112 each have a thickness equal to or substantially similar to the thickness of the first dielectric layer 106. Thus, the width of each conductive functional part 114 is substantially equal to or slightly greater than the width of each metal region 104, as shown in Figure 5A.

[0076] As described above, adjusting the thickness of the first metal layer 108 in this embodiment ultimately determines the resulting width of the conductive functional portion 114. For example, the overlap or lateral elongation of the first metal layer 106 increases as the thickness of the first metal layer 106 increases. Similarly, the overlap or lateral elongation of the first metal layer 108 decreases as the thickness of the first metal layer 108 decreases. Therefore, depositing a very thin first metal layer 108 provides precise control over the resulting width of the conductive functional portion (114).

[0077] In addition, as with respect to Figures 4 and 4A, the sidewalls of the conductive functional portion 114 are substantially vertical or perpendicular as a result of the uniform or substantially equal thickness of the additional dielectric layer 110 and the additional metal layer 112.

[0078] Referring to Figures 6 and 6A, the additional dielectric layer 110 and the additional metal layer 112 are deposited periodically in an alternating manner to form the conductive functional portion 114. Figure 6A is a cross-sectional view of Figure 6, section A. As described above, the additional dielectric layer 110 and the additional metal layer 112 are deposited sequentially and selectively in an alternating or periodic manner; however, in different orders and with different layer thicknesses.

[0079] In this example, the first metal layer 108 has a thickness (T) equal to the thickness of all subsequent layers, including the first dielectric layer 106. m ) is deposited first. Furthermore, the additional dielectric layer 110 and the additional metal layer 112 each have a thickness equal to, or substantially similar to, both the thickness of the first metal layer 108 and the first dielectric layer 106. In other words, all layers in this embodiment are designed and deposited to equal thickness. Therefore, the width of each conductive functional part 114 in this embodiment is greater than the width of each metal region 104, as shown in Figure 6A.

[0080] As mentioned above, adjusting the thickness of the first metal layer 108 in this embodiment ultimately determines the width of the resulting conductive functional portion 114. For example, depositing a thicker first layer, in this case the first metal layer 108, results in greater overlap or lateral elongation, and therefore makes the resulting conductive functional portion 114 larger or wider than the metal region 104.

[0081] In addition, as with respect to Figures 4 and 4A, the sidewalls of the conductive functional portion 114 are substantially vertical or perpendicular as a result of the uniform or substantially equal thickness of the additional dielectric layer 110 and the additional metal layer 112.

[0082] Referring to Figures 7 and 7A, the additional dielectric layer 110 and the additional metal layer 112 are deposited periodically in an alternating manner to form the conductive functional portion 114. Figure 7A is a cross-sectional view of Figure 7, section A. As described above, the additional dielectric layer 110 and the additional metal layer 112 are deposited sequentially and selectively in an alternating or periodic manner; however, in different orders and with different layer thicknesses.

[0083] In this example, the first dielectric layer 106 has a thickness (T) equal to the thickness of all subsequent layers, including the first metal layer 108. d ) is deposited first. Furthermore, the additional dielectric layer 110 and the additional metal layer 112 each have a thickness equal to, or substantially similar to, both the thickness of the first dielectric layer 106 and the first metal layer 108. In other words, all layers in this embodiment are designed and deposited to equal thickness. Therefore, the width of each conductive functional part 114 in this embodiment is smaller than the width of each metal region 104, as shown in Figure 7A.

[0084] As mentioned above, adjusting the thickness of the first dielectric layer 106 in this embodiment ultimately determines the width of the resulting conductive functional portion 114. For example, depositing a thicker first layer, in this embodiment the first dielectric layer 106, results in greater overlap or lateral elongation, and therefore makes the resulting conductive functional portion 114 smaller or narrower than the metal region 104.

[0085] In addition, as with respect to Figures 4 and 4A, the sidewalls of the conductive functional portion 114 are substantially vertical or perpendicular as a result of the uniform or substantially equal thickness of the additional dielectric layer 110 and the additional metal layer 112.

[0086] Referring to FIGS. 8 and 8A, additional dielectric layers 110 and additional metal layers 112 are periodically deposited in an alternating manner to form conductive functional portions 114. FIG. 8A is a cross-sectional view of FIG. 8, taken along section A. As described above, the additional dielectric layers 110 and additional metal layers 112 are deposited alternately or periodically; however, they are selectively deposited one after another with different layer thicknesses in different orders.

[0087] In this example, the first dielectric layer 106 is first deposited with a thickness (T m ) greater than the thickness (T d ) of the first metal layer 108. Further, all of the additional dielectric layers 110 are deposited with a thickness equal to the thickness (T d ) of the first dielectric layer 106, and all of the additional metal layers 112 are deposited with a thickness equal to the thickness (T m ) of the first metal layer 108. In other words, all of the dielectric layers (106, 110) are thicker than all of the metal layers (108, 112). Therefore, as shown in FIG. 8A, the lateral width of each conductive functional portion 114 decreases with respect to its height. It should be noted that conductive functional portions having a similar shape can also be realized by starting the periodic deposition with the first metal layer 108. It should be noted that despite the difference in layer thickness, each layer is still deposited periodically in an alternating manner.

[0088] According to this embodiment, adjusting the thickness of the dielectric layers (106, 110) with respect to the metal layers (108, 112) ultimately determines the final shape of the resulting conductive functional portions 114. For example, in this embodiment, depositing thicker dielectric layers (106, 110) results in final conductive functional portions 114 having a trapezoidal shape. The exact shape of the final conductive functional portions 114 can be controlled by adjusting the layer thickness and the number of layers to be deposited, while the size of the final conductive functional portions 114 can be controlled by adjusting the thickness of the first layer, as previously explained above. Different from the example described above, the sidewalls of the conductive functional portions 114 shown in FIGS. 8 and 8A are not substantially vertical or perpendicular, but instead have a slight angle with respect to the plane of the layers being deposited.

[0089] Referring to Figures 9 and 9A, the additional dielectric layer 110 and the additional metal layer 112 are deposited periodically in an alternating manner to form the conductive functional portion 114. Figure 9A is a cross-sectional view of Figure 9, section A. As described above, the additional dielectric layer 110 and the additional metal layer 112 are deposited sequentially and selectively in an alternating or periodic manner; however, in different orders and with different layer thicknesses.

[0090] In this example, the first dielectric layer 106 has a thickness (T) of the first metal layer 108. m ) is thinner than (T d It is initially deposited at a thickness of (T) of the first dielectric layer 106. Furthermore, all additional dielectric layers 110 are deposited at a thickness of (T) of the first dielectric layer 106. d The additional metal layer 112 is deposited to a thickness equal to the first metal layer 108 (T m The layers are deposited with a thickness equal to ). In other words, all dielectric layers (106, 110) are thinner than all metal layers (108, 112). Therefore, as shown in Figure 9A, the width of each conductive functional part 114 increases with respect to its height. Note that conductive functional parts with a similar shape can also be realized by initiating periodic deposition on the first metal layer 108. Note that regardless of the difference in layer thickness, each layer is still deposited periodically in an alternating manner.

[0091] In this embodiment, adjusting the thickness of the metal layers (108, 112) relative to the dielectric layers (106, 110) ultimately determines the final shape of the resulting conductive functional portion 114. For example, in this embodiment, depositing thicker metal layers (108, 112) results in a final conductive functional portion 114 having a trapezoidal or inverted trapezoidal shape. The exact shape of the final conductive functional portion 114 can be controlled by adjusting the layer thickness and the number of layers deposited, while the size of the final conductive functional portion 114 can be controlled by adjusting the thickness of the first layer, as previously described above. Unlike the examples described above, the sidewalls of the conductive functional portion 114 shown in Figures 9 and 9A are not substantially vertical or perpendicular, but instead have a slight angle with respect to the plane of the deposited layers.

[0092] It is generally understood by those skilled in the art that highly specific sizes and shapes of conductive functional parts can be achieved by adjusting the order and thickness of various dielectric and metal layers deposited periodically in an alternating manner. As detailed above, embodiments of the present invention enable the manufacture of conductive functional parts (114) having highly specific shapes and sizes. Specifically, each of the above-described manufacturing techniques can be used alone or in combination to achieve the desired shape and size of the resulting conductive functional part. Accordingly, embodiments of the present invention, alone or in combination, provide precise control of the width, sidewall angle, and dielectric / metal boundary of the conductive functional part 114.

[0093] The descriptions of various embodiments of the present invention have been presented for illustrative purposes only and are not intended to be comprehensive or limitless to the embodiments disclosed. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the invention. The terms used herein have been selected to best describe the principles of the embodiments, their practical applications, or the technical improvements to the art found in the market, or to enable other persons skilled in the art to understand the embodiments disclosed herein.

Claims

1. The first dielectric layer having a first conductive metal functional portion embedded within the first dielectric layer; The second dielectric layer having a second conductive metallic functional portion embedded within the second dielectric layer Equipped with, The second dielectric layer has a uniform composition throughout, The second conductive metal functional part is located above the first conductive metal functional part and is in direct contact with it. The sidewall of the second dielectric layer has a first repeating series of convex curves, and the sidewall of the second conductive metal functional portion has a second repeating series of convex curves, The interface between the second conductive metal functional portion and the second dielectric layer is the point where the first repeating series of convex curves contact the second repeating series of convex curves. Semiconductor structure.

2. The semiconductor structure according to claim 1, wherein the second conductive metal functional portion is self-aligned with the first conductive metal functional portion.

3. The semiconductor structure according to claim 1 or 2, wherein the second conductive metal functional portion has substantially vertical side walls and a width smaller than the width of the first conductive metal functional portion embedded in the first dielectric layer.

4. The semiconductor structure according to claim 1 or 2, wherein the second conductive metal functional portion has substantially vertical side walls and a width greater than the width of the first conductive metal functional portion embedded in the first dielectric layer.

5. The semiconductor structure according to claim 1 or 2, wherein the width of the top surface of the second conductive metal functional part is smaller than the width of the bottom surface of the second conductive metal functional part.

6. The semiconductor structure according to claim 1 or 2, wherein the width of the top surface of the second conductive metal functional part is greater than the width of the bottom surface of the second conductive metal functional part.

7. A semiconductor structure comprising a metal nanostructure embedded in a dielectric layer having a uniform composition throughout, wherein the sidewalls of the metal nanostructure have a series of concave curves, the sidewalls of the dielectric layer have a series of convex curves, and the boundary between the metal nanostructure and the dielectric layer is the location where the series of concave curves contact the series of convex curves.

8. The semiconductor structure according to claim 7, wherein the metal nanostructure is self-aligned with the underlying metal region.

9. The semiconductor structure according to claim 7, wherein the metal nanostructure has a width smaller than the width of the underlying metal region.

10. The semiconductor structure according to any one of claims 7 to 9, wherein each curve in the series of concave curves complements each curve in the series of convex curves.

11. The semiconductor structure according to any one of claims 7 to 9, wherein the width of the top surface of the metal nanostructure is smaller than the width of the bottom surface of the metal nanostructure.

12. The semiconductor structure according to any one of claims 7 to 9, wherein each curve in the series of concave curves substantially coincides with each curve in the series of convex curves.

13. A semiconductor structure comprising a conductive nanostructure embedded in a dielectric layer having a uniform composition throughout, wherein the sidewall of the conductive nanostructure has a first series of convex and convex curves, the sidewall of the dielectric layer has a second series of convex and convex curves, and the interface between the conductive nanostructure and the dielectric layer is the location where the first series of convex and convex curves contact the second series of convex and convex curves.

14. The semiconductor structure according to claim 13, wherein the conductive nanostructure is self-aligned with the underlying metal region.

15. The semiconductor structure according to claim 13, wherein the conductive nanostructure has a width greater than the width of the underlying metal region.

16. The semiconductor structure according to claim 13, wherein each curve in the first series of convex and concave curves complements each curve in the second series of convex and concave curves.

17. The semiconductor structure according to claim 13, wherein each curve in the first series of convex and concave curves substantially coincides with each curve in the second series of convex and concave curves.

18. The semiconductor structure according to claim 13, wherein the width of the top surface of the conductive nanostructure is greater than the width of the bottom surface of the conductive nanostructure.

19. The semiconductor structure according to any one of claims 13 to 18, wherein the conductive nanostructure has a plurality of thin film layers made of at least two different materials.

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