Manufacturing method for semiconductor devices

Abstract

A purpose of the present invention is to suppress the occurrence of exposed parts on the surface of a semiconductor chip. This method for manufacturing a semiconductor device includes: preparing a semiconductor wafer on which are provided a plurality of chip regions, which are regions on which constituent elements of a semiconductor chip are already formed, and a wiring board assembly on which are provided, on a base material made of elastic material, a plurality of wiring board regions, which are regions in which a plurality of wires that electrically lead from one surface of the base material to the other surface are already formed; overlapping and joining the bottom surface of the semiconductor wafer and the wiring board assembly; cutting the semiconductor wafer so as to not divide the wiring board assembly; dicing the chip regions to make semiconductor chips, and extending the wiring board assembly in the horizontal direction to widen the gap between semiconductor chips; covering the semiconductor chips with a resin sealant while maintaining the widened state of the gap between semiconductor chips; cutting the resin sealant and the wiring board assembly between the semiconductor chips; and dicing the semiconductor device.

Description

Technical Field

[0004] , ,

[0001] The present technology (the technology according to the present disclosure) relates to a method for manufacturing a semiconductor device, a semiconductor device, and a wiring board for a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having a housing for housing a semiconductor chip, a semiconductor device, and a wiring board for a semiconductor device, and is an effective technology applicable thereto.

Background Art

[0002] Semiconductor chips are formed by individually separating a plurality of chip regions set on a semiconductor wafer in the manufacturing process of a semiconductor device. For example, as disclosed in Patent Document 1, a semiconductor wafer irradiated with a dicing laser is mounted on a dicing tape via an adhesive layer, and then the dicing tape is stretched from the outer periphery. Due to this tension, the chip regions are separated from each other, and a plurality of individually separated semiconductor chips are obtained. Then, the individually separated semiconductor chips are picked up from the dicing tape. Then, the individually separated semiconductor chips are incorporated into a package.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] By the way, when picking up a semiconductor chip, the number of processes increases accordingly. In addition, depending on the method of incorporating the semiconductor chip into a package, the silicon of the semiconductor chip may be exposed.

[0005] The purpose of this technology is to suppress the occurrence of exposed areas on the surface of semiconductor chips. [Means for solving the problem]

[0006] A method for manufacturing a semiconductor device according to one aspect of this technology includes preparing a semiconductor wafer having a plurality of chip regions, which are regions in which semiconductor chip components have been formed, and a wiring board assembly having a plurality of wiring board regions, which are regions in which a plurality of electrically connected wirings have been formed from one side of the base material to the other, on a base material made of stretchable material, overlapping and joining the bottom surface of the semiconductor wafer and the wiring board assembly, cutting the semiconductor wafer without dividing the wiring board assembly to separate the chip regions into individual semiconductor chips, stretching the wiring board assembly horizontally to widen the spacing between the semiconductor chips, covering the semiconductor chips with a resin encapsulant while maintaining the widened spacing between the semiconductor chips, and cutting the resin encapsulant and the wiring board assembly between the semiconductor chips to separate the semiconductor device into individual pieces.

[0007] A semiconductor device according to one aspect of this technology comprises a semiconductor chip, a wiring substrate having a base material made of a stretchable material with a stretch ratio of 200 percent or more and an elastic modulus of 100 MPa or less, having a plurality of electrically connected wirings from one side of the base material to the other side, and being bonded to the bottom surface of the semiconductor chip, and a resin encapsulant covering the semiconductor chip.

[0008] A wiring substrate for a semiconductor device according to one aspect of this technology is a substrate that is bonded to the bottom surface of a semiconductor chip, and has a base material made of a stretchable material with an expansion ratio of 200 percent or more and an elastic modulus of 100 MPa or less, and has multiple wirings that electrically connect from one side of the base material to the other side. [Brief explanation of the drawing]

[0009] [Figure 1A] This is a schematic plan view showing a semiconductor device according to the first embodiment of this technology. [Figure 1B]This is a schematic cross-sectional view showing the cross-sectional structure along the AA cutting line in Figure 1A. [Figure 2A] This diagram shows the planar structure of a semiconductor wafer. [Figure 2B] This figure shows an enlarged view of region C in Figure 2A, illustrating the configuration of the chip area. [Figure 2C] This diagram shows a magnified view of a portion of a wiring board assembly, illustrating the configuration of the wiring board region. [Figure 3A] This is a schematic process cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment of this technology. [Figure 3B] This is a schematic cross-sectional view of the process, following Figure 3A. [Figure 3C] This is a schematic cross-sectional view of the process, following Figure 3B. [Figure 3D] This is a schematic cross-sectional view of the process, following Figure 3C. [Figure 3E] This is a schematic cross-sectional view of the process, following Figure 3D. [Figure 3F] This is a schematic cross-sectional view of the process, following Figure 3E. [Figure 3G] This is a schematic cross-sectional view of the process, following Figure 3F. [Figure 4] This is a schematic cross-sectional view showing the general configuration of a semiconductor device according to Modification 1-1 of the first embodiment of this technology. [Figure 5] This is a schematic cross-sectional view showing the general configuration of a semiconductor device according to a modified example 1-2 of the first embodiment of this technology. [Figure 6] This is a schematic cross-sectional view showing the general configuration of a semiconductor device according to a second embodiment of this technology. [Figure 7] This is a schematic plan view showing the general configuration of a semiconductor chip in a semiconductor device according to the second embodiment of this technology. [Figure 8A] This is a schematic process cross-sectional view showing a method for manufacturing a semiconductor device according to a second embodiment of this technology. [Figure 8B] This is a schematic cross-sectional view of the process, following Figure 8A. [Figure 8C] This is a schematic cross-sectional view of the process, following Figure 8B. [Figure 8D] This is a schematic cross-sectional view of the process, following Figure 8C. [Figure 8E] It is a schematic process cross-sectional view following FIG. 8D. [Figure 8F] It is a schematic process cross-sectional view following FIG. 8E. [Figure 9] It is a cross-sectional view schematically showing a schematic configuration of a semiconductor device according to Modification 2-1 of the second embodiment of the present technology. [Figure 10] It is a schematic process cross-sectional view showing a manufacturing method of a semiconductor device according to Modification 2-1 of the second embodiment of the present technology.

Embodiments for Carrying Out the Invention

[0010] Hereinafter, embodiments of the present technology will be described in detail with reference to the drawings. In the description of the drawings referred to in the following explanation, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thicknesses of the respective layers, etc. are different from the actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following explanation.

[0011] Also, it is a matter of course that there are portions where the dimensional relationships and ratios are different between the drawings. Also, the effects described in this specification are merely examples and are not limited, and there may be other effects.

[0012] Also, the following embodiments exemplify devices and methods for embodying the technical idea of the present technology, and do not specify the configuration to be the following. That is, the technical idea of the present technology can be variously modified within the technical scope described in the claims.

[0013] Also, the definitions of the directions such as up and down in the following explanation are merely definitions for convenience of explanation and do not limit the technical idea of the present technology. For example, if the object is rotated 90° and observed, up and down are read as left and right, and if it is rotated 180° and observed, up and down are read in reverse, which is a matter of course.

[0014] Furthermore, in the following embodiments, in the three mutually orthogonal directions in space, the first and second directions that are mutually orthogonal within the same plane are defined as the X direction and the Y direction, respectively, and the third direction that is orthogonal to each of the first and second directions is defined as the Z direction. In the following embodiments, the thickness direction of the semiconductor device 1A, which will be described later, will be explained as the Z direction.

[0015] The explanation will be given in the following order. 1. First Embodiment 2. Second Embodiment

[0016] [First Embodiment] ≪Overall Configuration of Semiconductor Device≫ As shown in Figures 1A and 1B, the semiconductor device 1A according to the first embodiment of this technology comprises a semiconductor chip 10 and a wiring board 20 called an interposer, which is bonded to the first surface S1 of the semiconductor chip 10. The semiconductor device 1A according to the first embodiment of this technology further comprises a housing (package) 30 for housing the semiconductor chip 10. The housing 30 includes the wiring board 20 and a resin encapsulant 31 provided on the fourth surface S4 side, which is the upper surface of the wiring board 20, and for sealing the semiconductor chip 10.

[0017] <Semiconductor Chips> As shown in Figure 1A, the semiconductor chip 10 is formed with a rectangular planar shape intersecting its thickness direction (Z direction), and in this first embodiment, it is formed as a square, for example. As shown in Figure 1B, the semiconductor chip 10 mainly includes, but is not limited to, a semiconductor substrate 11, a plurality of transistors (not shown) provided on the element formation surface (main surface) of the semiconductor substrate 11, and a laminate (multilayer wiring layer) 12 formed by alternately stacking multiple layers of insulating layers and wiring layers on the element formation surface side of the semiconductor substrate 11. The semiconductor chip 10 has a first surface S1 and a second surface S2 located on opposite sides of each other. Here, the first surface S1 is sometimes called the bottom surface of the semiconductor chip 10, and the second surface S2 is sometimes called the top surface of the semiconductor chip 10. The bottom surface of the semiconductor chip 10 is the surface closer to the wiring substrate 20, and the top surface of the semiconductor chip 10 is the surface opposite to the bottom surface of the semiconductor chip 10. Also, the third surface S3 shown in Figure 1B is the side surface of the semiconductor chip 10. The third surface S3 is a surface that constitutes the outer periphery of the semiconductor chip 10, and is the surface that connects the first surface S1 and the second surface S2 in the Z direction. Also, as shown in Figure 1A, in a plan view, the wiring substrate 20 and the resin encapsulant 31 overlap with the entire semiconductor chip 10. In other words, in a plan view, the contours of the wiring substrate 20 and the resin encapsulant 31 are outside the contour of the semiconductor chip 10.

[0018] The semiconductor substrate 11 shown in Figure 1B is made of, for example, single-crystal silicon. The insulating layer of the laminate 12 is made of, for example, a silicon oxide film. The wiring layer of the laminate 12 is made of, for example, a copper (Cu), aluminum (Al) film, or an aluminum alloy film in which at least one of silicon (Si) and copper (Cu) is added to Al. Si is added mainly to improve electromigration resistance. Cu is added mainly to improve alloy spike resistance. The wiring layer of this first embodiment is made of, for example, an Al alloy film with an Al-Si-Cu composition in which Si and Cu are added to Al.

[0019] The semiconductor chip 10 contains an integrated circuit. This integrated circuit is mainly composed of transistor elements formed on the semiconductor substrate 11 and wiring formed on the wiring layer of the laminate 12.

[0020] The semiconductor chip 10 has a plurality of electrode pads 13 provided on the first surface S1 side. The electrode pads 13 are arranged, for example, along four edges in the two-dimensional plane of the semiconductor chip 10. The electrode pads 13 are formed as components of an integrated circuit and function as external terminals such as signal input / output terminals and power supply terminals. The electrode pads 13 are provided facing the first surface S1 and are superimposed and bonded with electrode pads 22a of the wiring board 20, which will be described later.

[0021] <Wiring board> As shown in Figure 1A, the wiring board 20 has a rectangular planar shape intersecting its thickness direction (Z direction), and in this first embodiment, it is formed as a square, for example. As shown in Figure 1B, the wiring board 20 has a fourth surface S4 and a fifth surface S5 located on opposite sides of each other. Here, the fourth surface S4 is sometimes referred to as the top surface of the wiring board 20, and the fifth surface S5 is sometimes referred to as the bottom surface of the wiring board 20. The top surface of the wiring board 20 is the surface closer to the semiconductor chip 10, and the bottom surface of the wiring board 20 is the surface opposite to the top surface of the wiring board 20. The top surface (fourth surface S4) of the wiring board 20 is bonded to the bottom surface (first surface S1) of the semiconductor chip 10.

[0022] The wiring board 20 has a base material 21 and a plurality of wirings 22 provided on the base material 21. The base material 21 is made of an insulating stretchable material and can be stretched by applying force. The base material 21 is made of a stretchable material with an expansion ratio of 200 percent or more and an elastic modulus of 100 MPa or less. Examples of stretchable materials include elastomers. Other examples of stretchable materials include silicone resin, urethane resin, epoxy resin, acrylic resin, and fluororubber. Furthermore, for example, the stretchable material may be a material described in Patent Document 2 or Patent Document 3.

[0023] The wiring board 20 includes a central portion 20a that overlaps with the semiconductor chip 10 in the thickness direction (overlapping in a plan view) and a peripheral portion 20b that does not overlap with the semiconductor chip 10 in the thickness direction (does not overlap in a plan view). The peripheral portion 20b is thinner than the central portion 20a. More specifically, the thickness of the peripheral portion 20b decreases as it moves away from the central portion 20a. Furthermore, the thickness of the central portion 20a is preferably, for example, 200 μm or more and 300 μm or less.

[0024] Multiple wirings 22 are provided in the central portion 20a of the wiring board 20, which is divided into a central portion 20a and a peripheral portion 20b. That is, the central portion 20a is the region where multiple wirings 22 are provided. Multiple wirings 22 are provided, but are not limited to this, such as occupying approximately 80% of the central portion 20a. The wirings 22 are electrically connected from one surface of the fourth surface S4 and the fifth surface S5 to the other surface. The wirings 22 are also electrically connected to the semiconductor chip 10 on one side of the base material 21. The wirings 22 include an electrode pad 22a provided on the fourth surface S4 side, an electrode pad 22b provided on the fifth surface S5 side, and a connection portion 22c that electrically connects the electrode pads 22a and 22b. The electrode pads 22a are positioned in a location corresponding to the electrode pads 13 of the semiconductor chip 10. The electrode pad 22a faces the fourth surface S4 and is bonded to the electrode pad 13 of the semiconductor chip 10 by overlapping it. This electrically connects the electrode pad 22a to the electrode pad 13. The electrode pad 22b is positioned at a location corresponding to a terminal on a motherboard (not shown). The configuration of 22c is not limited to the example shown in Figure 1B; other configurations are possible as long as the electrode pads 22a and 22b are electrically connected.

[0025] <Bump electrodes> Bump electrodes 61 are fixed to the electrode pad 22b and are electrically and mechanically connected. For example, solder bumps with a substantially lead-free composition that do not contain lead are used as bump electrodes 61. The bump electrodes 61 only need to be provided at positions corresponding to terminals on a motherboard (not shown), and their positions and number are not limited to those shown in Figure 1B.

[0026] <Resin encapsulant> As shown in Figure 1A, the resin encapsulant 31 has a rectangular planar shape intersecting its thickness direction (Z direction), and in this first embodiment, it is formed as a square, for example. The resin encapsulant 31 is provided with a planar shape the same size as the wiring board 20. The resin encapsulant 31 covers the semiconductor chip 10. More specifically, as shown in Figure 1B, the resin encapsulant 31 covers the second surface S2 and the third surface S3 of the semiconductor chip 10. The resin encapsulant 31 also covers the peripheral edge 20b of the wiring board 20. More specifically, the resin encapsulant 31 covers the fourth surface S4 of the peripheral edge 20b. With this configuration, the resin encapsulant 31 encapsulates the semiconductor chip 10. The resin encapsulant 31 is made of, for example, an epoxy-based thermosetting resin. As a method for forming the resin encapsulant 31, for example, a transfer molding method suitable for mass production is used.

[0027] Furthermore, the resin encapsulant 31 also extends into the wedge-shaped gap B that is slightly formed between the first surface S1 of the semiconductor chip 10 and the fourth surface S4 of the wiring substrate 20.

[0028] Manufacturing Method for Semiconductor Devices Next, the manufacturing method of semiconductor device 1A will be explained using Figures 2A to 2C and Figures 3A to 3G.

[0029] Figure 2A shows the planar configuration of a semiconductor wafer used in the manufacture of semiconductor device 1A, and Figure 2B is a magnified view of region C in Figure 2A showing the configuration of the chip region. Figure 2C is a magnified view of a part of the wiring board assembly described later, showing the configuration of the wiring board region. Figures 3A to 3G are schematic cross-sectional views illustrating the manufacturing method of semiconductor device 1A.

[0030] First, as shown in Figure 3A, a semiconductor wafer 40 and a wiring board assembly 50 are prepared. As shown in Figures 2A and 2B, the prepared semiconductor wafer 40 has multiple chip regions 41. Integrated circuits are fabricated in the chip regions 41. That is, the chip regions 41 are regions in which the components of the semiconductor chip 10 have already been formed. The chip regions 41 are demarcated by scribe lines (dicing regions) 42 and are repeatedly arranged in the X and Y directions via the scribe lines 42. That is, multiple chip regions 41 are arranged in a matrix. Then, by individually dicing these multiple chip regions 41 along the scribe lines 42, a semiconductor chip 10 with integrated circuits mounted on it is formed. In other words, Figure 2A is a diagram showing the entire semiconductor substrate in wafer form before it is diced into multiple semiconductor chips. Note that the scribe lines 42 are not physically formed.

[0031] To prepare the semiconductor wafer 40, first, an integrated circuit is formed on the chip region 41 shown in Figure 2B. The integrated circuit is constructed by forming transistor elements on the element formation surface of the semiconductor substrate 11, and then forming a laminate 12 on the element formation surface of the semiconductor substrate 11. The laminate 12 is formed by alternately stacking insulating layers and wiring layers on the element formation surface side of the semiconductor substrate 11. Electrode pads 13 are formed on the uppermost wiring layer of the laminate 12. The semiconductor substrate 11 is made of, for example, single-crystal silicon. As transistor elements, for example, p-channel conductive MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and n-channel conductive MOSFETs are used. That is, the integrated circuit has a CMOS (Complementary MOS) circuit configuration. The electrode pads 13 are formed as components of the integrated circuit and function as external terminals such as signal input / output terminals and power supply terminals. This completes the semiconductor wafer 40 shown in Figures 2A and 2B. Each of the multiple chip regions 41 of the semiconductor wafer 40 has components such as transistor elements, stacks 12, integrated circuits, and electrode pads 13 formed on it.

[0032] As shown in Figure 2C, the wiring board assembly 50 is made of a base material 21 made of stretchable material with multiple wiring board regions 51 provided on it. Within each wiring board region 51, a central portion 20a with multiple wirings 22 is fabricated. That is, each wiring board region 51 is a region with multiple wirings 22 already formed on it. Each wiring board region 51 is demarcated by regions 52 where no wirings 22 are provided, and these regions are repeatedly arranged in the X and Y directions via the regions 52. That is, multiple wiring board regions 51 are arranged in a matrix. The wiring board 20 is formed by individually separating these multiple wiring board regions 51 along the regions 52. The wiring board regions 51 are arranged in a matrix with the same pitch as the chip regions 41. This allows the chip regions 41 and the wiring board regions 51 to be superimposed when the semiconductor wafer 40 and the wiring board assembly 50 are superimposed. The boundary between the wiring board regions 51 and regions 52 is not always clearly distinguishable. The wiring board assembly 50 may be prepared, for example, using the MSAP (Modified Semi Additive Process) method. In the MSAP method, for example, vias are formed on a copper foil stretchable material with a laser, and wiring 22 is formed by photolithography. Then, the next layer of copper foil stretchable material is laminated on top of that by heating under pressure, and the same process is repeated to form a wiring pattern. Thus, the MSAP method is a process of repeatedly performing the above-described process of forming a wiring pattern. Furthermore, the Z-direction dimension (thickness) of the wiring board assembly 50 is preferably, for example, 200 μm or more and 300 μm or less.

[0033] Then, plasma is irradiated onto the first surface S1 of the semiconductor wafer 40 and the fourth surface S4 of the wiring substrate assembly 50, as shown in Figure 3A, to activate the surfaces. After that, as shown in Figure 3B, the semiconductor wafer 40 and the wiring substrate assembly 50 are stacked and bonded together. At this time, the electrode pad 13 and the electrode pad 22a are stacked and bonded together and electrically connected. Heat treatment may then be performed.

[0034] Next, as shown in Figure 3C, the semiconductor wafer 40 is cut so as not to divide the wiring board assembly 50, and the chip regions 41 are separated into individual semiconductor chips 10. More specifically, the semiconductor wafer 40 is cut along the scribe line 42 shown in Figure 2B to separate the chip regions 41 into individual semiconductor chips 10. For example, a dicing blade is used to cut the semiconductor wafer 40. When the semiconductor wafer 40 is cut with a dicing blade, a gap of approximately 100 μm is created between the semiconductor chips 10, although this is not limited to this gap. Also, when cutting the semiconductor wafer 40, grooves may be carved into the wiring board assembly 50, as shown in Figure 3C. The separated semiconductor chips 10 remain bonded to the wiring board assembly 50.

[0035] Then, as shown in Figure 3D, the wiring board assembly 50 (base material 21) is stretched horizontally (perpendicular to the Z direction) to widen the gaps between the semiconductor chips 10. The Z-direction dimension (thickness) of the wiring board assembly 50 is, for example, between 200 μm and 300 μm, so that the wiring board assembly 50 does not break when stretched horizontally. The gaps between the semiconductor chips 10 were about 100 μm before stretching, but the wiring board assembly 50 is stretched until this gap becomes, for example, about 300 μm, although this is not limited to this. This is so that after the semiconductor chips 10 are separated into individual pieces in a later process, a resin encapsulant 31 of about 100 μm remains on the side surface (third surface S3) of the semiconductor chip 10. The extent to which the wiring board assembly 50 is stretched can be determined according to the thickness of the resin encapsulant 31 to be left on the side surface of the semiconductor chip 10 and the width that will be removed during the individual piece separation process.

[0036] Furthermore, as mentioned above, the semiconductor chip 10 and the wiring board assembly 50 are joined together, and multiple wirings 22 are provided in the portion of the wiring board assembly 50 that is joined to the semiconductor chip 10. More specifically, the wirings 22 are densely packed in the portion of the wiring board assembly 50 that is joined to the semiconductor chip 10. Therefore, the portion of the wiring board assembly 50 that is stretched is mainly the portion between the wiring board regions 51 (region 52 in Figure 2C). Since there are no wirings in region 52, and grooves are carved into region 52 when the semiconductor wafer 40 is cut with a dicing blade, when force is applied to the wiring board assembly 50, that force mainly acts to stretch the base material 21 of region 52.

[0037] The Z-direction dimension of the stretched region 52 is not limited to this, but is, for example, about half of the original dimension. If the thickness of the wiring board assembly 50 before stretching was 300 μm, the thickness of the stretched region 52 is, for example, 150 μm.

[0038] Subsequently, as shown in Figure 3E, while maintaining the widened spacing between the semiconductor chips 10, a resin encapsulant 31 is formed on the fourth surface S4 side of the wiring substrate 20 to enclose the semiconductor chips 10 and the surrounding components. More specifically, while maintaining the state shown in Figure 3D, the semiconductor chips 10 and the wiring substrate assembly 50 are placed in a mold (not shown), and the heated and molten resin encapsulant 31 is poured into the mold. Then, the process is carried out until the temperature of the resin encapsulant 31 drops and it solidifies. This covers the semiconductor chips 10 with the resin encapsulant 31, as shown in Figure 3E. More specifically, both the top surface (second surface S2) and the side surface (third surface S3) of the semiconductor chips 10 are covered with the resin encapsulant 31.

[0039] Next, as shown in Figure 3F, the resin encapsulation 31 and the wiring board assembly 50 between the semiconductor chips 10 are cut. More specifically, the region 52 of the resin encapsulation 31 and the wiring board assembly 50 between the semiconductor chips 10 are cut together. This separates the semiconductor device 1A into individual pieces. Furthermore, a housing (package) 30 is formed which includes the wiring board 20 and the resin encapsulation 31 and houses the semiconductor chips 10. More specifically, a housing (package) 30 is formed which includes the wiring board 20 and the resin encapsulation 31 that covers both the top surface (second surface S2) and the side surface (third surface S3) of the semiconductor chip 10.

[0040] Subsequently, as shown in Figure 3G, bump electrodes 61 are formed on the electrode pad 22b. This almost completes the semiconductor device 1A shown in Figures 1A and 1B.

[0041] <<Main effects of the first embodiment>> Next, the main effects of this first embodiment will be described. In conventional semiconductor device manufacturing, more specifically in wafer-level CSP (Wafer-level Chip Size Package), a redistribution layer, resin encapsulation, bump electrodes, etc., are formed on one side of the wafer, and then the wafer and resin encapsulation are cut to form individual pieces. In that case, the package obtained after dicing had the other side of the wafer and the cut surface (side) with exposed silicon.

[0042] To avoid exposing silicon in this way, a technique called fan-out wafer-level packaging (FOWLP) is sometimes used. In fan-out wafer-level packaging, diced semiconductor chips are rearranged on a separate component with spacing between them, and a resin encapsulation is formed on top of that to form a pseudo-wafer. Then, the separate component is removed, and redistribution layers, bump electrodes, etc., are formed on the surface of the pseudo-wafer where the resin encapsulation has not been formed, and the wafer is separated into individual chips. In this method, since the resin encapsulation is formed on the top surface of the rearranged semiconductor chips with spacing between them and between the semiconductor chips themselves, it is possible to suppress the occurrence of exposed areas on the surface of the semiconductor chip 10. On the other hand, because the diced semiconductor chips are rearranged, the number of steps increases, and the process becomes more complex.

[0043] In contrast, in the manufacturing method of semiconductor device 1A according to the first embodiment of this technology, the bottom surface of a semiconductor wafer 40 and a wiring board assembly 50 are stacked and joined, the semiconductor wafer 40 is cut without dividing the wiring board assembly 50, the chip region 41 is separated into individual pieces to form semiconductor chips 10, the wiring board assembly 50 is stretched horizontally to widen the spacing between semiconductor chips 10, the semiconductor chips 10 are covered with a resin encapsulant 31 while maintaining the widened spacing between semiconductor chips 10, and the resin encapsulant 31 and wiring board assembly 50 between semiconductor chips 10 are cut to separate the semiconductor device 1A into individual pieces. As a result, both the top and side surfaces of the semiconductor chips 10 can be covered with the resin encapsulant 31, preventing the top and side surfaces of the semiconductor chips 10 from being exposed. This prevents chipping of the semiconductor chips 10.

[0044] Furthermore, in the manufacturing method of the semiconductor device 1A according to the first embodiment of this technology, the wiring board assembly is provided with a base material made of stretchable material, and multiple wiring board regions are provided on the base material, where multiple electrically connected wirings are already formed from one side of the base material to the other. Therefore, the wiring board assembly is not a disposable component, but is stretched to widen the spacing between semiconductor chips 10, and after other processes, is cut into individual pieces on the wiring board 20 and used as part of the semiconductor device 1A. Therefore, there is no need to rearrange the semiconductor chips 10, the number of processes can be suppressed, and the complexity of the process can be suppressed.

[0045] Furthermore, in the manufacturing method of the semiconductor device 1A according to the first embodiment of this technology, the base material 21 is made of a stretchable material with an expansion / contraction ratio of 200 percent or more, and since there are no wirings 22 in the region 52 that suppress the expansion and contraction of the base material 21, the space between the semiconductor chips 10 can be sufficiently widened. In addition, since the elastic modulus of the base material 21 is 100 MPa or less, it is possible to suppress the need for a large force to stretch the base material 21.

[0046] Furthermore, in the manufacturing method of the semiconductor device 1A according to the first embodiment of this technology, the Z-direction dimension (thickness) of the wiring substrate assembly 50 is, for example, 200 μm or more and 300 μm or less, so that even if the wiring substrate assembly 50 is stretched, breakage can be suppressed.

[0047] Furthermore, generally, the materials constituting the semiconductor device 1A and the materials constituting the motherboard have different coefficients of thermal expansion, so strain may occur between them when they return to room temperature after heat treatment. As a result, strain may occur in the bump electrodes. In contrast, in the semiconductor device 1A according to the first embodiment of this technology, the base material 21 of the wiring board 20 is made of an expandable material. Therefore, the wiring board 20 can stretch, absorbing the strain that occurs between the semiconductor device 1A and the motherboard, thereby suppressing stress on the bump electrodes 61. This suppresses the occurrence of cracks in the bump electrodes 61 and prevents a decrease in reliability.

[0048] Furthermore, in the semiconductor device 1A according to the first embodiment of this technology, the stretching of the wiring board 20 allows the semiconductor device 1A to absorb the strain generated between the semiconductor device 1A and the motherboard, thus suppressing a decrease in reliability against temperature changes after mounting on the motherboard. When the semiconductor device 1A was mounted on a motherboard and subjected to temperature cycle tests, experimental results were obtained showing improved reliability compared to conventional redistribution layers (RDL). The experimental results depend on the thickness and elasticity of the wiring board 20, but in some cases, reliability improved by more than 10 times compared to conventional redistribution layers at specific thicknesses and elasticities.

[0049] Furthermore, in the semiconductor device 1A according to the first embodiment of this technology, as shown in Figure 1B, the resin encapsulant 31 is inserted into the wedge-shaped gap B. Therefore, the semiconductor device 1A is less susceptible to physical and environmental stress.

[0050] <<Variations of the First Embodiment>> <Variation 1-1> In the first embodiment described above, the semiconductor chip 10 and the wiring substrate 20 were joined by irradiating the bonding surface with plasma, but this technology is not limited to this. As shown in Figure 4, the semiconductor chip 10 (semiconductor wafer 40) and the wiring substrate 20 (wiring substrate assembly 50) may also be joined by forming microbumps 14 on the electrode pads 13 of the semiconductor chip 10 (semiconductor wafer 40) and joining the microbumps 14 to the electrode pads 22a of the wiring substrate 20. In this way, the electrode pads 13 and 22a are electrically connected via the microbumps 14.

[0051] When a semiconductor chip 10 and a wiring board 20 are joined by microbumps 14, a sealant 62 is provided between the semiconductor chip 10 and the wiring board 20. The sealant 62 joins the first surface S1 and the fourth surface S4 of the wiring board 20. The sealant 62 may, for example, be an underfill made of epoxy resin or the like. The underfill is injected between the joined semiconductor chip 10 and the wiring board 20 and then cured. Alternatively, the sealant 62 may be an anisotropic conductive material such as an anisotropic conductive film. The anisotropic conductive material is composed of a mixture of conductive particles responsible for conductivity and an adhesive responsible for adhesion. The portion of the anisotropic conductive material located between the microbump 14 and the electrode pad 22a exhibits conductivity due to higher pressure than the surrounding area, thereby electrically connecting the microbump 14 and the electrode pad 22a.

[0052] Even with the semiconductor device 1A according to this modified example 1-1, the same effects as the semiconductor device 1A according to the first embodiment described above can be obtained.

[0053] <Variation 1-2> In the above-described modified example 1-1, microbumps 14 were formed on the semiconductor chip 10 (semiconductor wafer 40) side, but this technology is not limited to this. As shown in Figure 5, microbumps 23 may also be formed on the wiring substrate 20 (wiring substrate assembly 50) side. That is, microbumps 23 may be formed on the electrode pad 22a. The semiconductor chip 10 (semiconductor wafer 40) and the wiring substrate 20 (wiring substrate assembly 50) may then be joined by joining the microbumps 23 and the electrode pad 13 of the semiconductor chip 10. This electrically connects the electrode pad 13 and the electrode pad 22a via the microbumps 23. The encapsulant 62 is as already described.

[0054] Even with the semiconductor device 1A according to this modified example 1-2, the same effects as the semiconductor device 1A according to the first embodiment described above can be obtained.

[0055] <Variation 1-3> In the first embodiment described above, the resin encapsulant 31 was explained to be made of, for example, an epoxy-based thermosetting resin and formed using a transfer molding method, but this technology is not limited to this. For example, while maintaining the widened spacing between the semiconductor chips 10 shown in Figure 3D, a fluid resin (resin encapsulant 31) is applied to the fourth surface S4 side of the wiring substrate 20 by spin coating. The resin is then cured. The resin is cured by, for example, heat, ultraviolet light, etc. In this way, the semiconductor chips 10 may be covered with the resin encapsulant 31.

[0056] Even with the semiconductor device 1A according to this modified example 1-3, the same effects as the semiconductor device 1A according to the first embodiment described above can be obtained. Furthermore, the resin encapsulant 31 according to Modification 1-3 may also be applied to Modifications 1-1 and 1-2 described above.

[0057] <Variation 1-4> In the first embodiment described above, the semiconductor wafer 40 and the wiring substrate assembly 50 were bonded together, but this technology is not limited to this. A redistribution layer may be formed on the first surface S1 of the semiconductor wafer 40 by laminating a redistribution layer having a thickness in the Z direction that is approximately the same as that of the wiring substrate assembly 50, and having an elasticity and modulus of elasticity that are approximately the same as those of the wiring substrate assembly 50. Such a redistribution layer is formed by applying a stretchable insulating layer to the first surface S1 of the semiconductor wafer 40, exposing it, and developing it. After that, the semiconductor wafer 40 is cut or half-cut so as not to interrupt the redistribution layer. The subsequent steps are the same as those described in Embodiment 1, so their description is omitted here.

[0058] Even with the semiconductor device 1A according to this modified example 1-4, the same effects as the semiconductor device 1A according to the first embodiment described above can be obtained.

[0059] [Second Embodiment] In this second embodiment, an example of applying this technology to a semiconductor device equipped with a photodetector (semiconductor chip) such as a back-illuminated CMOS (Complementary Metal Oxide Semiconductor) image sensor will be described.

[0060] The semiconductor device 1B according to this second embodiment differs from the semiconductor device 1A according to the first embodiment described above in that it has a semiconductor chip 10B instead of semiconductor chip 10, and a housing 30B instead of housing 30. The configuration of the semiconductor device 1B otherwise is basically the same as that of the semiconductor device 1A of the first embodiment described above. The same reference numerals are used for components that have already been described, and their descriptions are omitted.

[0061] <Semiconductor Chips> As shown in Figure 6, the semiconductor device 1B according to the second embodiment includes a semiconductor chip 10B and a housing (package) 30B. First, the semiconductor chip 10B will be described. The semiconductor chip 10B is equipped with a light detection device. Examples of light detection devices include a solid-state image sensor that captures image light (incident light) from an object through an optical lens, converts the amount of light of the incident light formed on the imaging surface into an electrical signal on a pixel-by-pixel basis and outputs it as a pixel signal, and a distance measuring sensor (Time of Flight, ToF sensor) that emits light toward an object, detects the reflected light that returns after the light is reflected from the surface of the object, and calculates the distance to the object based on the time of flight from when the light is emitted until the reflected light is received. In this embodiment, the light detection device will be described as a solid-state image sensor 70 mounted on the semiconductor chip 10B shown in Figure 7, but it is not limited to this.

[0062] As shown in Figure 7, the solid-state image sensor 70 (semiconductor chip 10B) according to the second embodiment of this technology has a rectangular two-dimensional planar shape when viewed from above. The solid-state image sensor 70 comprises a rectangular pixel region 2A located in the center of a two-dimensional plane including the mutually intersecting X and Y directions, and a peripheral region 2B located outside the pixel region 2A so as to surround it.

[0063] Pixel region 2A is a light-receiving surface that receives light focused by, for example, an optical lens (optical system). Multiple pixels 3 are arranged in a matrix within pixel region 2A in a two-dimensional plane including the X and Y directions. In other words, the pixels 3 are repeatedly arranged in mutually orthogonal directions in the two-dimensional plane, specifically in the X and Y directions.

[0064] Multiple electrode pads 13B are arranged in the peripheral region 2B. The electrode pads 13B are arranged, for example, along the four edges of the semiconductor chip 10B in a two-dimensional plane. The electrode pads 13B are input / output terminals used when electrically connecting the solid-state image sensor 70 to an external device.

[0065] The solid-state image sensor 70 includes logic circuits, such as a vertical drive circuit, a column signal processing circuit, a horizontal drive circuit, an output circuit, and a control circuit. The logic circuits are composed of, for example, CMOS (Complenentary MOS) circuits.

[0066] Each of the multiple pixels 3 has a photoelectric conversion element. A readout circuit is connected to the photoelectric conversion element of each pixel 3. The photoelectric conversion elements are configured for each pixel 3 on the semiconductor substrate 11B shown in Figure 6. The photoelectric conversion element converts light into a signal charge corresponding to the amount of light received and holds it.

[0067] As shown in Figure 6, the semiconductor chip 10B has a first surface S1 and a second surface S2 that are located on opposite sides of each other in the thickness direction (Z direction). The semiconductor chip 10B comprises a semiconductor substrate 11B, a laminate (multilayer wiring layer) 12B formed by alternately stacking multiple insulating layers and wiring layers on the element formation side of the semiconductor substrate 11B, and an electrode pad 13B.

[0068] The semiconductor substrate 11B is configured with, for example, multiple MOSFETs as field-effect transistors that constitute the logic circuits and readout circuits mentioned above. A single-crystal silicon substrate can be used as the semiconductor substrate 11B. The laminate 12B has a laminated structure in which multiple layers of insulating layers and wiring layers are alternately stacked. The electrode pad 13B penetrates the semiconductor chip 10B. The electrode pad 13B is joined to and electrically connected to the electrode pad 22a.

[0069] The semiconductor chip 10B further includes a planarization film (not shown), a color filter (not shown), and a microlens 15, which are sequentially stacked on the second surface S2 side (light-receiving surface side) from the second surface S2 side. The planarization film planarizes the second surface S2 side. The microlens 15 focuses the incident light onto the semiconductor substrate 11B. The color filter separates the incident light onto the semiconductor substrate 11B into colors. The color filter and microlens 15 are provided for each pixel 3. The color filter and microlens 15 are made of, for example, a resin material.

[0070] <Storage unit> Next, the housing (package) 30B will be described. The housing 30B includes a wiring board 20, a resin encapsulant 31, and a light-transmitting substrate 32, and encapsulates the semiconductor chip 10B.

[0071] The semiconductor device 1B has a light-transmitting substrate 32 on the light-receiving surface side. More specifically, the semiconductor device 1B has a light-transmitting substrate 32 on the light-receiving surface side of the semiconductor chip 10B. The light-transmitting substrate 32 seals the light-receiving surface side (second surface S2 side) of the semiconductor chip 10B. More specifically, the light-transmitting substrate 32 seals the light-receiving surface side (second surface S2 side) of the semiconductor chip 10B with a gap between them. The light-transmitting substrate 32 is bonded to the second surface S2 side of the semiconductor chip 10B with resin 33. The light-transmitting substrate 32 is made of a material that has light-transmitting properties, and for example, a glass substrate is used, but is not limited to this. For example, an acrylic resin substrate or a sapphire substrate may be used for the light-transmitting substrate 32. Light transmitted through the light-transmitting substrate 32 is incident on a photoelectric conversion element provided on the semiconductor substrate 11B, and is photoelectrically converted into a signal charge corresponding to the amount of light by the photoelectric conversion element.

[0072] The resin encapsulant 31 is provided on the fourth surface S4 side, which is the upper surface of the wiring board 20, and mainly covers the side surface (third surface S3) of the semiconductor chip 10B. In addition, the resin encapsulant 31 covers the side surface (the surface perpendicular to the Z direction) of the light-transmitting substrate 32 and also fits into the gap between the light-transmitting substrate 32 and the semiconductor chip 10B.

[0073] Manufacturing Method for Semiconductor Devices Next, the manufacturing method of semiconductor device 1B will be explained using Figures 8A to 8F. Here, we will focus on the differences from the manufacturing method described in the first embodiment.

[0074] First, as shown in Figure 8A, a semiconductor wafer 40, a wiring board assembly 50, and a light-transmitting substrate 80 are prepared. A solid-state image sensor 70 is fabricated in the chip region 41 of the semiconductor wafer 40. The light-transmitting substrate 80 has the same size as the semiconductor wafer 40. Then, as shown in Figure 8B, the semiconductor wafer 40 and the wiring board assembly 50 are stacked and bonded together. Finally, the light-transmitting substrate 80 is bonded to the second surface S2 side of the semiconductor wafer 40 using resin 33.

[0075] Next, as shown in Figure 8C, the light-transmitting substrate 80 and the semiconductor wafer 40 are cut so as not to divide the wiring board assembly 50. As a result, the light-transmitting substrate 80 is separated into individual light-transmitting substrates 32, and the semiconductor wafer 40 is separated into individual semiconductor chips 10B. In this way, the light-transmitting substrate 32 and the semiconductor chips 10B are separated while being bonded together.

[0076] Subsequently, as shown in Figure 8D, the wiring board assembly 50 is stretched horizontally (perpendicular to the Z direction) to widen the gaps between the semiconductor chips 10B. Then, while maintaining the state shown in Figure 8D, the semiconductor chips 10B with the light-transmitting substrate 32 attached and the wiring board assembly 50 are placed in a mold (not shown), and the heated and molten resin encapsulant 31 is poured into the mold. More specifically, a film is provided on the side of the mold that is in contact with the light-transmitting substrate 32 to prevent the resin encapsulant 31 from adhering to the surface of the light-transmitting substrate 32 when filling it. Then, the temperature of the resin encapsulant 31 drops and it hardens. This forms a resin encapsulant 31 that covers the side of the light-transmitting substrate 32 and the side of the semiconductor chip 10B (third surface S3), as shown in Figure 8E. Subsequently, as shown in Figure 8F, the individual components are separated, and bump electrodes 61 are provided on the electrode pads 22b as explained using Figure 3G of the first embodiment, and the semiconductor device 1B shown in Figure 6 is almost complete.

[0077] <<Main effects of the second embodiment>> Even with the semiconductor device 1B according to this second embodiment, the same effects as those obtained with the semiconductor device 1A according to the first embodiment described above can be obtained.

[0078] Furthermore, in the semiconductor device 1B according to this second embodiment, a light-transmitting substrate 32 is provided on the light-receiving surface side. Therefore, light can be incident on the semiconductor chip 10B, and the photoelectric conversion element can perform photoelectric conversion. In addition, it is possible to prevent the top surface of the semiconductor chip 10B from being exposed. Moreover, the sides of the semiconductor chip 10B can be covered with the resin encapsulant 31, preventing the sides of the semiconductor chip 10B from being exposed. As a result, it is possible to prevent exposed areas from forming on the surface of the semiconductor chip 10B and to prevent the semiconductor chip 10B from chipping.

[0079] <<Variations of the second embodiment>> <Variation 2-1> In the second embodiment described above, the light-transmitting substrate 32 was approximately the same size as the semiconductor chip 10B in a plan view, but this technology is not limited to this. As shown in Figure 9, the light-transmitting substrate 32 may be smaller than the semiconductor chip 10B in a plan view. More specifically, it may be smaller than the semiconductor chip 10B as long as it can cover the pixel region 2A shown in Figure 7 in a plan view. In that case, the light-transmitting substrate 80 is pre-cut into individual pieces to prepare the light-transmitting substrate 32, and for example, as shown in Figure 10, the individual pieces of the light-transmitting substrate 32 are bonded to the semiconductor wafer 40 before it is cut into individual pieces using resin 33. After that, the semiconductor wafer 40 can be cut into individual pieces. The subsequent steps are the same as those in the second embodiment, so their explanation is omitted here.

[0080] Even with the semiconductor device 1B according to this modified example 2-1, the same effects as the semiconductor device 1B according to the second embodiment described above can be obtained.

[0081] [Other Embodiments] As described above, this technology has been presented in the form of the first and second embodiments, but the discussions and drawings that constitute part of this disclosure should not be understood as limiting this technology. Various alternative embodiments, examples, and operational techniques will become apparent to those skilled in the art from this disclosure.

[0082] For example, it is possible to combine the technical concepts described in the first and second embodiments. For instance, the semiconductor device 1A according to modification 1-1 of the first embodiment provided microbumps 14, and the semiconductor device 1A according to modification 1-2 of the first embodiment provided microbumps 23. Such technical concepts may also be applied to the semiconductor device 1B described in the second embodiment and its modifications. Furthermore, various combinations are possible in accordance with the respective technical concepts, such as applying the redistribution layer according to modification 1-4 of the first embodiment to the second embodiment. Furthermore, although semiconductor devices 1A and 1B were equipped with bump electrodes 61 in the above-described embodiment, they do not necessarily have to be equipped with them. Also, the state after individualization and before the formation of the bump electrodes 61, as shown in Figures 3F, 8F, etc., can also be referred to as semiconductor devices 1A and 1B.

[0083] Thus, this technology naturally includes various embodiments and other features not described herein. Therefore, the technical scope of this technology is determined solely by the inventive features described in the claims as appropriate from the above description.

[0084] Furthermore, this technology may also be configured as follows. (1) Prepare a semiconductor wafer having multiple chip regions, which are regions in which semiconductor chip components have already been formed, and a wiring substrate assembly having multiple wiring substrate regions, which are regions in which multiple electrically connected wirings have already been formed on a base material made of stretchable material, The bottom surface of the semiconductor wafer and the wiring substrate assembly are stacked and joined together. The semiconductor wafer is cut so as not to divide the wiring board assembly, and the chip region is separated into individual pieces to form a semiconductor chip. The wiring board assembly is extended horizontally to widen the gaps between the semiconductor chips, While maintaining the state in which the spacing between the semiconductor chips is widened, the semiconductor chips are covered with a resin encapsulant. A method for manufacturing a semiconductor device, comprising cutting the resin encapsulant and the wiring board assembly between the semiconductor chips to separate the semiconductor device into individual pieces. (2) The method for manufacturing a semiconductor device according to (1), wherein when covering the semiconductor chip with the resin encapsulant, at least the side surface of the semiconductor chip is covered with the resin encapsulant. (3) A method for manufacturing a semiconductor device according to (1) or (2), wherein when joining the semiconductor wafer and the wiring substrate assembly, the electrode pads provided in the chip region are electrically connected to the wiring of the wiring substrate assembly. (4) Semiconductor chips and A wiring board is bonded to the bottom surface of a semiconductor chip, having a base material made of an expandable material with an expansion ratio of 200 percent or more and an elastic modulus of 100 MPa or less, and having multiple wirings that electrically connect from one surface of the base material to the other surface, A semiconductor device comprising a resin encapsulant covering the aforementioned semiconductor chip. (5) The semiconductor device according to (4), wherein the resin encapsulant covers at least the side surface of the semiconductor chip, among the top surface and side surface. (6) The semiconductor device according to (4) or (5), wherein the electrode pads of the semiconductor chip are electrically connected to the wiring of the wiring board. (7) The light-receiving surface has a light-transmitting substrate, The semiconductor device according to any one of (4) to (6), wherein the semiconductor chip has a photoelectric conversion element. (8) The semiconductor device according to any one of (4) to (7), wherein the peripheral portion of the wiring board is thinner than the central portion. (9) A substrate that is bonded to the bottom surface of a semiconductor chip, having a base material made of a stretchable material with a stretch ratio of 200 percent or more and an elastic modulus of 100 MPa or less, and having multiple electrically connected wirings from one side of the base material to the other side. A wiring board for semiconductor devices. (10) The wiring board for semiconductor device described in (9), wherein the thickness of the central part of the wiring board is 200 μm or more and 300 μm or less. (11) The wiring is electrically connected to the semiconductor chip on one side of the base material, as described in (9) or (10), on a wiring board for a semiconductor device.

[0085] The scope of this technology is not limited to the illustrative and described exemplary embodiments, but also includes all embodiments that produce effects equivalent to those intended by this technology. Furthermore, the scope of this technology is not limited to the combination of features of the invention defined by the claims, but may be defined by any desired combination of specific features from all disclosed features. [Explanation of Symbols]

[0086] 1A, 1B Semiconductor Equipment 2A Pixel area 2B Peripheral area 3 pixels 10,10B semiconductor chip 11,11B Semiconductor substrate 12,12B laminate 13, 13B, 22a, 22b electrode pads 14,23 microbumps 15 Microlenses 20 Wiring boards 20a Central part 20b Peripheral area 21 Base material 22 Wiring 22c connection 30,30B storage unit 31 Resin sealing body 32 Light transmission substrate 33 Resin 40 Semiconductor wafers 41 Chip area 42 Scribe lines 50 Wiring board assembly 51 Wiring board area 52 areas 61 Bump electrodes 62 Sealing body 70 Solid-state image sensors 80 Light transmission substrate B Gap

Claims

1. Prepare a semiconductor wafer having multiple chip regions, which are regions in which semiconductor chip components have already been formed, and a wiring substrate assembly having multiple wiring substrate regions, which are regions in which multiple electrically connected wirings have already been formed on a base material made of stretchable material, The bottom surface of the semiconductor wafer and the wiring substrate assembly are stacked and joined together. The semiconductor wafer is cut so as not to divide the wiring board assembly, and the chip region is separated into individual pieces to form a semiconductor chip. The wiring board assembly is extended horizontally to widen the gaps between the semiconductor chips, While maintaining the state in which the spacing between the semiconductor chips is widened, the semiconductor chips are covered with a resin encapsulant. A method for manufacturing a semiconductor device, comprising cutting the resin encapsulant and the wiring board assembly between the semiconductor chips to separate the semiconductor device into individual pieces.

2. The method for manufacturing a semiconductor device according to claim 1, wherein when covering the semiconductor chip with the resin encapsulant, at least the side surface of the semiconductor chip is covered with the resin encapsulant.

3. The method for manufacturing a semiconductor device according to claim 1, wherein when joining the semiconductor wafer and the wiring substrate assembly, the electrode pads provided in the chip region are electrically connected to the wiring of the wiring substrate assembly.

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