Semiconductor equipment

Abstract

To reduce oxygen vacancies existing in an oxide semiconductor film and in the vicinity of the oxide semiconductor film and to improve electric characteristics of a transistor using the oxide semiconductor film.SOLUTION: A semiconductor device uses a gate electrode whose Gibbs free energy for oxidation reaction is higher than that of a gate insulating film. In a region where the gate electrode is in contact with the gate insulating film, oxygen moves from the gate electrode to the gate insulating film because the gate electrode has higher Gibbs free energy for oxidation reaction than that of the gate insulating film. The oxygen passes through the gate insulating film and is supplied to the oxide semiconductor film disposed in contact with the gate insulating film, thereby realizing reduction of oxygen vacancies in the oxide semiconductor film and in the vicinity of the oxide semiconductor film.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Relates to a semiconductor device and a method of manufacturing the same.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Generally speaking, electro-optical devices, semiconductor circuits, electronic devices, etc. are all semiconductor devices.

Background Art

[0003] Techniques for constructing transistors using semiconductor films formed on substrates having insulating surfaces have drawn attention. Such transistors are widely applied to semiconductor devices such as integrated circuits (ICs) and image display devices (display devices). As semiconductor films applicable to transistors, silicon -based semiconductor films are known, but in recent years, oxide-based semiconductor films have drawn attention.

[0004] [[ID=2�]]For example, transistors using amorphous oxide films containing indium, gallium, and sub- 18 / cm 3 [[ID=3 and lead with an electron carrier concentration of less than 10 are disclosed (see Patent Document 1).

[0005] Transistors using oxide semiconductor films can significantly improve the operating speed because the electron mobility in the oxide semiconductor film is higher than that in transistors using amorphous silicon films. In addition, since it is possible to improve and utilize a part of the production equipment for transistors using amorphous silicon films, there is also an advantage of suppressing capital investment. <00001 and lead with an electron carrier concentration of less than 10

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

[0007] Oxygen vacancies present in and near oxide semiconductor films can serve as donors. It generates electrons. Therefore, the structure of a transistor using an oxide semiconductor film containing oxygen vacancies The positive voltage may fluctuate in the negative direction. Note that in this specification, oxide semiconductors... The term "near the film" refers to the interface between an oxide semiconductor film and a film in contact with it.

[0008] Therefore, one aspect of the present invention relates to oxygen deficiencies present in and near oxide semiconductor films. The challenge is to reduce losses and improve the electrical characteristics of transistors using oxide semiconductor films. Let's consider it one.

[0009] Furthermore, one aspect of the present invention relates to a transistor having an oxide semiconductor film, which is highly reliable. One of the objectives is to provide semiconductor devices. [Means for solving the problem]

[0010] One aspect of the present invention is an oxide semiconductor film, a gate electrode superimposed on the oxide semiconductor film, and an oxide The gate has a gate insulating film provided between the semiconductor film and the gate electrode, and the gate The oxygen concentration near the interface with the insulating film is lower than the oxygen concentration in the middle of the gate electrode. It is a conductive device.

[0011] For example, in the case of a gate electrode with a thickness of 30 nm or more, the interface between the gate electrode and the gate insulating film. The oxygen concentration at a vertical distance of 2 nm, 3 nm, or 5 nm from the gate electrode is the gate isolation. The oxygen concentration at a perpendicular distance of 10 nm, 15 nm, or 30 nm from the interface with the edge film is greater than low.

[0012] Furthermore, the gate electrode is made of a material with a higher Gibbs free energy for oxidation than the gate insulating film. Therefore, the gate electrode is more easily reduced than the gate insulating film. Furthermore, the gate electrode has the property of being less susceptible to oxidation than the gate insulating film. In the case of a layered structure, the Gibbs free energy of the oxidation reaction of the gate electrode is greater than that of any of the layers. - is expensive.

[0013] Specifically, the gate electrode is selected from silver, copper, ruthenium, iridium, platinum, and gold. It contains one or more elements.

[0014] Furthermore, one aspect of the present invention involves an oxide semiconductor film superimposed on an oxide semiconductor film, and at least one A gate electrode comprising a layer and a second layer, and provided between the oxide semiconductor film and the gate electrode. The gate electrode has a gate insulating film and a first layer of the gate electrode, which is provided in contact with the gate insulating film. Furthermore, it is a semiconductor device in which the oxygen concentration is lower than that of the second layer of the gate electrode.

[0015] Furthermore, the first layer of the gate electrode has a Gibbs free energy for oxidation reactions that is higher than that of the gate insulating film. It is made of a high-quality material. That is, the first layer of the gate electrode is more easily reduced than the gate insulating film. It has the property of being less susceptible to oxidation than the gate insulating film. It has the following characteristics. Furthermore, if the gate insulating film has a multilayer structure, the gate electrode is greater than any of the layers. The Gibbs free energy for the oxidation reaction in the first layer is high.

[0016] Furthermore, the gate insulating film is oxygen permeable. In this specification, an oxygen permeable film and This refers to a membrane that permeates oxygen molecules, or one with a sufficiently high diffusion coefficient of oxygen atoms, and the heat treatment during the manufacturing process. This refers to a membrane that allows oxygen atoms to permeate through a specific mechanism.

[0017] Furthermore, an insulating film with low oxygen permeability is provided in contact with at least the side surface of the first layer of the gate electrode. It is preferable that this be done. In this specification, a membrane with low oxygen permeability means a membrane that does not allow oxygen molecules to pass through. The diffusion coefficient of the film and oxygen atoms is sufficiently low, and due to heat treatment during the manufacturing process, the oxygen atoms This refers to a film that does not allow oxygen to pass through. By providing an insulating film with low oxygen permeability, the first layer of the gate electrode This reduces the outward diffusion of oxygen released from the device, allowing for efficient oxygen supply to the oxide semiconductor film.

[0018] Specifically, the first and second layers of the gate electrode are made of silver, copper, ruthenium, and iridium. It consists of an oxide containing one or more elements selected from platinum and gold. Because the substance has a high Gibbs free energy for oxidation reactions, it is easily reduced itself, and the film it comes into contact with... It is easily oxidized.

[0019] Alternatively, the first layer of the gate electrode may be made from silver, copper, ruthenium, iridium, platinum, and gold. The second layer of the gate electrode is made of a metal containing one or more selected elements, and the second layer of the gate electrode is made of silver, copper, and ruthenia. It consists of an oxide containing one or more elements selected from um, iridium, platinum, and gold.

[0020] One aspect of the present invention involves forming a gate electrode containing at least an oxide, and covering the gate electrode with a gate electrode. A gate insulating film is formed, and an oxide semiconductor film is superimposed on the gate electrode via the gate insulating film. Afterward, by performing a heat treatment, the oxide semiconductor film is transferred from the gate electrode to the oxide semiconductor film via the gate insulating film. This is a method for fabricating a semiconductor device that supplies oxygen.

[0021] Alternatively, in one aspect of the present invention, an oxide semiconductor film is formed, and a gate insulating film is placed on the oxide semiconductor film. A gate insulating film is formed and superimposed with an oxide semiconductor film via a gate insulating film, and a gate containing at least an oxide is formed. After forming the gate electrode, heat treatment is performed to allow acid to escape from the gate electrode through the gate insulating film. This is a method for fabricating semiconductor devices that supply oxygen to a crystalline semiconductor film.

[0022] Alternatively, in one aspect of the present invention, an oxide semiconductor film is formed, and a gate insulating film is placed on the oxide semiconductor film. After forming a film and then forming a conductive film containing at least an oxide on the gate insulating film, heat treatment is performed. This process supplies oxygen from the conductive film to the oxide semiconductor film via the gate insulating film, and oxidizes the oxygen. A method for fabricating a semiconductor device in which a conductive film supplied to a physical semiconductor film is processed to form a gate electrode. be.

[0023] By applying one aspect of the present invention, oxygen moves from the gate electrode to the gate insulating film, The oxygen permeates the gate insulating film and is supplied to the oxide semiconductor film provided in contact with the gate insulating film. Therefore, to reduce oxygen vacancies in and near oxide semiconductor films, This is possible. This is because, in the region where the gate electrode and the gate insulating film are in contact, the gate electrode is This is because the Gibbs free energy of the oxidation reaction is higher than that of the insulating film. Therefore, oxides This can suppress variations in the electrical characteristics of transistors using semiconductor films.

[0024] Furthermore, due to the operation of the transistor, in the oxide semiconductor film and / or the oxide semiconductor film Oxygen vacancies may occur in the vicinity. In particular, acid vacancies may form at the interface between the oxide semiconductor film and the gate insulating film. When a primary defect occurs, it has a significant impact on the electrical characteristics of the transistor. In such cases, By ensuring that the electrode contains sufficient oxygen, the resulting oxygen deficiency can be reduced. Therefore, the transistor according to one aspect of the present invention does not exhibit fluctuations in electrical characteristics due to oxygen deficiency. It is difficult to fold. In other words, the semiconductor device having the transistor has high reliability. [Effects of the Invention]

[0025] Reduce oxygen vacancies present in and near oxide semiconductor films, The electrical characteristics of transistors using films can be improved.

[0026] Furthermore, improving the reliability of semiconductor devices having transistors using oxide semiconductor films is possible. can. [Brief explanation of the drawing]

[0027] [Figure 1] A top view and a cross-sectional view showing an example of a transistor according to one aspect of the present invention. [Figure 2] A cross-sectional view showing an example of a method for manufacturing a transistor according to one aspect of the present invention. [Figure 3] A cross-sectional view showing an example of a method for manufacturing a transistor according to one aspect of the present invention. [Figure 4] A top view and a cross-sectional view showing an example of a transistor according to one aspect of the present invention. [Figure 5] A cross-sectional view showing an example of a method for manufacturing a transistor according to one aspect of the present invention. [Figure 6] A cross-sectional view showing an example of a method for manufacturing a transistor according to one aspect of the present invention. [Figure 7] A top view and a cross-sectional view showing an example of a transistor according to one aspect of the present invention. [Figure 8] A cross-sectional view showing an example of a method for manufacturing a transistor according to one aspect of the present invention. [Figure 9] A cross-sectional view showing an example of a method for manufacturing a transistor according to one aspect of the present invention. [Figure 10]A cross-sectional view showing an example of a method for manufacturing a transistor according to one aspect of the present invention. [Figure 11] A cross-sectional view showing an example of a method for manufacturing a transistor according to one aspect of the present invention. [Figure 12] A top view and a cross-sectional view showing an example of a transistor according to one aspect of the present invention. [Figure 13] A circuit diagram showing an example of a liquid crystal display device according to one aspect of the present invention. [Figure 14] A circuit diagram and a diagram showing electrical characteristics illustrating an example of a semiconductor memory device according to one aspect of the present invention. [Figure 15] A circuit diagram and a diagram showing electrical characteristics illustrating an example of a semiconductor memory device according to one aspect of the present invention. [Figure 16] A block diagram showing a specific example of a CPU according to one aspect of the present invention, and a circuit diagram of a part thereof. [Figure 17] A perspective view showing an example of an electronic device having a semiconductor device according to one aspect of the present invention. [Figure 18] A diagram illustrating the diffusion of oxygen in a silicon oxide film. [Figure 19] A diagram illustrating the oxygen permeability of an aluminum oxide film. [Figure 20] A diagram illustrating the oxygen permeability of the YSZ membrane. [Figure 21] A diagram showing the Gibbs free energy of an oxidation reaction. [Modes for carrying out the invention]

[0028] Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is described below. It is not limited to the above, and its form and details can be easily changed in various ways, as can be easily seen by those skilled in the art. It is understood that the present invention is to be interpreted as being limited to the embodiments described below. No. Furthermore, when explaining the structure of the invention using drawings, the same reference numerals may refer to different things. It is used consistently across drawings. Furthermore, when referring to similar items, the hatch pattern is the same. Furthermore, sometimes no symbol is assigned.

[0029] The ordinal numbers "1st" and "2nd" are used for convenience only and do not necessarily indicate the order of processes or stacking. This does not indicate that. Furthermore, in this specification, the proper nouns used to specify the invention are not used to indicate that. This does not indicate a title.

[0030] (Embodiment 1) In this embodiment, a transistor according to one aspect of the present invention will be explained using Figures 1 to 3. I will reveal it.

[0031] Figure 1(A) is a top view of a transistor according to one embodiment of the present invention. A cross-sectional view corresponding to the dashed line AB is shown in Figure 1(B). For simplicity, Figure 1(A) is shown below. Therefore, the protective insulating film 118, gate insulating film 112, etc., are omitted from the diagram.

[0032] The transistor shown in Figure 1(B) has an underlayer insulating film 102 provided on the substrate 100, and the underlayer A first layer 104a, a second layer 104b, and a third layer 104 are provided on the insulating film 102. A gate electrode 104 having c, and a gate that covers at least the gate electrode 104. An insulating film 112 and a gate electrode 104 superimposed on the gate insulating film 112, The oxide semiconductor film 106 and a pair of electrodes 116 provided on the oxide semiconductor film 106 are It has. The first layer 104a of the gate electrode 104 is provided in contact with the gate insulating film 112. The third layer 104c of the gate electrode 104 is provided in contact with the underlying insulating film 102, The second layer 104b of the electrode 104 is provided between the first layer 104a and the third layer 104c. It can be made. Note that the transistor shown in Figure 1(B) has at least an oxide semiconductor film 106 and It is preferable to have a protective insulating film 118 that covers the pair of electrodes 116. A back gate electrode may be provided on the oxide semiconductor film 106 via the protective insulating film 118. .

[0033] In this specification, "B provided covering A" means at least the upper surface of A and This is not limited to cases where B is provided adjacent to the side, but also when something else is provided between A and B. That is also fine. However, if B has an opening for wiring or other connections, and a part of A is exposed That's fine too.

[0034] Here, the first layer 104a of the gate electrode 104 is connected to the second layer 104b of the gate electrode 104. This layer has a lower oxygen concentration than the gate. Also, the third layer 104c of the gate electrode 104 is the gate This layer has higher conductivity than the first layer 104a and the second layer 104b of the electrode 104.

[0035] The first layer 104a and the second layer 104b of the gate electrode 104 are gate insulating film 1 It consists of a substance whose Gibbs free energy for oxidation is higher than that of 12. That is, gate electrode 10 The first layer 104a and the second layer 104b of 4 are more easily reduced than the gate insulating film 112. It has the property. In other words, the first layer 104a and the second layer 10 of the gate electrode 104 4b has properties that make it less susceptible to oxidation than the gate insulating film 112.

[0036] For reference, Figure 21 shows the Gibbs free energies for the oxidation reactions of each element. The horizontal axis of Figure 21 is The graph shows temperature [°C], and the vertical axis represents Gibbs free energy (ΔG [kJ / mol]). Figure 2 The Gibbs free energy for the oxidation reaction shown in 1 was determined by the following calculation. Table 1 shows the standard enthalpy of formation ΔH and standard entropy S values ​​for each substance. By substituting this into the equations for each oxidation reaction shown in Table 2, we can obtain the standard product of each oxidation reaction. The values ​​of enthalpy ΔH and standard entropy of formation ΔS are calculated. Table 2 shows the calculated values ​​for each acid. The values ​​of the standard enthalpy of formation ΔH and standard entropy of formation ΔS in chemical reactions are shown. The standard enthalpy of formation ΔH and standard entropy S for each substance shown in Table 1 are The values ​​were primarily quoted from "Chemical Handbook Basic Edition II, 4th Revised Edition," edited by the Chemical Society of Japan, published by Maruzen Co., Ltd. It is.

[0037] [Table 1]

[0038] [Table 2]

[0039] Next, the values ​​of the standard enthalpy of formation ΔH and standard entropy of formation ΔS shown in Table 2 are as follows: Substituting this into equation (1), we obtain the give of each oxidation reaction in the temperature range of 0°C to 900°C. The value of the free energy was calculated. Note that T in equation (1) is the temperature [K].

[0040]

number

[0041] From Figure 21, for example, the first layer 104a and the second layer 104b of the gate electrode 104 are Oxides containing one or more elements selected from silver, copper, ruthenium, iridium, platinum, and gold. A layer made of the material can be used. The oxide containing the element has a Gibbs free energy for oxidation reactions. Because of its high conductivity, it is easily reduced itself and easily oxidizes the film it comes into contact with. Therefore, it is preferable to use an oxide containing ruthenium or iridium. An example of an iridium-containing oxide is RuO X (X is between 0.5 and 3), IrO X (X is between 0.5 and 3), SrRuO X Examples include (where X is between 1 and 5).

[0042] Alternatively, the first layer 104a of the gate electrode 104 may be silver, copper, ruthenium, iridium, white The layer consists of gold and a metal containing one or more elements selected from gold, and the gate electrode 104 The second layer 104b is made of one of the following materials: silver, copper, ruthenium, iridium, platinum, and gold. The layer will consist of oxides containing the above elements.

[0043] Furthermore, the first layer 104a of the gate electrode 104 is composed of iridium, platinum, and ruthenium oxide. When using materials such as gold, which have a work function of 5 eV, preferably 5.2 eV or more, the work function Compared to using materials with a function voltage of 4.7 eV or less, the transistor threshold voltage is increased. It is preferable that it can be shifted in the S direction.

[0044] Furthermore, the third layer 104c of the gate electrode 104 is made of silver, copper, ruthenium, iridium, and platinum. The layer consists of a metal containing one or more elements selected from gold. Note that gate electrode 1 The third layer 104c of 04 is more efficient in oxidation reactions compared to the second layer 104b of the gate electrode 104. If a material with a high or similar Bus free energy is used, the second layer 10 of the gate electrode 104 It is preferable because it does not easily remove oxygen from 4b.

[0045] The gate insulating film 112 is selected from one or more of insulators including aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and may be used as a single layer or a laminate.

[0046] Note that the gate insulating film 112 has oxygen permeability. A film having oxygen permeability refers to a film that permeates oxygen molecules or a film in which the diffusion coefficient of oxygen atoms is sufficiently high and oxygen atoms permeate due to heat treatment or the like in the manufacturing process. For example, a film that permeates oxygen molecules may have a low density such that oxygen molecules can permeate. Specifically, the film density may be less than 3.2 g / cm 3 -16 2 -15 > 2 / s or more, preferably -15 2

[0047] By using the gate electrode 104 and the gate insulating film 112 as described above, oxygen can be supplied from the gate electrode 104 to the oxide semiconductor film 106 through the gate insulating film 112. Therefore, oxygen deficiencies in and near the oxide semiconductor film 106 are reduced. Therefore, fluctuations in the electrical characteristics of the transistor due to oxygen deficiencies in and near the oxide semiconductor film 106 can be suppressed.

[0048] ​​​​​​​​​​​​​​​​​​​​For example, an In-M-Zn oxide film can be used as the oxide semiconductor film 106. Metal element M is an element whose bond energy with oxygen is higher than that of In and Zn. It is an element that has the function of suppressing the detachment of oxygen from the In-M-Zn oxide film. The action of metal element M suppresses the formation of oxygen vacancies in oxide semiconductor films. Therefore, This can reduce variations in the electrical characteristics of transistors caused by oxygen deficiencies.

[0049] Metallic elements M include Al, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, and Ga , Y, Zr, Nb, Mo, Sn, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, D The elements may be y, Ho, Er, Tm, Yb, Lu, Hf, Ta, or W, preferably Al. Let Ti, Ga, Y, Zr, Ce, or Hf be the elements. The metallic element M is one of the elements mentioned above. Alternatively, you may select two or more types. Also, you may use Si or Ge instead of the metal element M. No.

[0050] The oxide semiconductor film 106 is a single crystal, polycrystalline (also called polycrystal), or amorphous Which state will it take?

[0051] Preferably, the oxide semiconductor film 106 is CAAC-OS (C Axis Aligned The film is made of crystalline oxide semiconductor material.

[0052] CAAC-OS films are neither perfectly single crystals nor perfectly amorphous. This is an oxide semiconductor film having a crystalline-amorphous multiphase structure with crystalline and amorphous parts in the amorphous phase. Yes, it exists. Furthermore, the crystalline portion must be small enough to fit within a cube with sides less than 100 nm long. There are many. Also, transmission electron microscopes (TEM) In the image observed using a microscope, the amorphous region contained in the CAAC-OS film and The boundary with the crystalline portion is not clear. Also, TEM revealed grain boundaries in the CAAC-OS film. Also called inboundary. ) cannot be confirmed. Therefore, the CAAC-OS film has grain boundaries. The resulting decrease in carrier mobility is suppressed.

[0053] The crystalline portion contained in the CAAC-OS film has a c-axis that is the normal vector to the surface on which the CAAC-OS film is formed. Aligned in a direction parallel to the normal vector of the plane or surface, and triangular when viewed from a direction perpendicular to the ab plane. Having a shape or hexagonal atomic arrangement, the metal atoms are layered or when viewed from a direction perpendicular to the c-axis. Metal atoms and oxygen atoms are arranged in layers. Furthermore, between different crystalline regions, the a-axis is... The orientation of the b-axis may be different. In this specification, when simply referred to as vertical, 8 The range of 5° to 95° is also included. Furthermore, when simply describing something as parallel, -5 This will include the range of 5° to 5°.

[0054] Furthermore, the distribution of crystalline regions in the CAAC-OS film does not need to be uniform. For example, CAA When crystal growth is performed from the surface side of the oxide semiconductor film 106 during the formation process of the C-OS film. Furthermore, the proportion of crystalline material may be higher near the surface compared to the vicinity of the formed surface. By adding impurities to the CAAC-OS film, the crystalline region in the impurity-added area is formed. It can also become amorphous.

[0055] The c-axis of the crystalline portion contained in the CAAC-OS film is the normal vector to the surface on which the CAAC-OS film is formed. Because it aligns in a direction parallel to the normal vector of the surface or the material, the shape of the CAAC-OS film (formed Depending on the cross-sectional shape of the surface or face, they may face in different directions. Oh, the direction of the c-axis of the crystalline portion is the normal vector to the surface on which the CAAC-OS film was formed. The direction is parallel to the normal vector of the crystalline or surface. The crystalline portion is formed by deposition, and It is formed by performing crystallization treatments such as heat treatment after film formation.

[0056] Oxide semiconductor films have a band gap of approximately 2.8 eV to 3.2 eV, and minority carriers 10 -9 pieces / cm 3 The amount is extremely small, and the majority of carriers come from the transistor source. Therefore, transistors using oxide semiconductor films are avalanche break. No down.

[0057] Furthermore, in transistors using oxide semiconductor films, the electric field of the gate electrode is the transistor's channel To completely deplete the Nell region, for example, when the channel length is 3 μm and the channel width is 1 μm... The off-current is 10 at 85°C to 95°C. -23 It can be less than or equal to A, and at room temperature. This has an even lower off-current (specifically 10 -25 It can be set to A or less.

[0058] Furthermore, transistors using oxide semiconductor films exhibit electrical properties when irradiated with visible or ultraviolet light. The fluctuations are small. Therefore, this transistor is highly reliable.

[0059] There are no major restrictions on the substrate 100, but it should at least have enough heat resistance to withstand subsequent heat treatment. It is necessary to do so. For example, glass substrates, ceramic substrates, quartz substrates, sapphire substrates These may be used as the substrate 100. Alternatively, single crystal semiconductors such as silicon or silicon carbide may be used. Conductor substrates, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI ( It is also possible to apply a silicon-on-insulator (SIO) substrate, etc. A substrate 100 may be used in which semiconductor elements are provided on these substrates.

[0060] Also, as substrate 100, the 5th generation (1000mm x 1200mm or 1300mm x 1500mm), 6th generation (1500mm x 1800mm), 7th generation (1870mm x 2200mm), 8th generation (2200mm x 2500mm), 9th generation (2400mm x Large glass substrates such as 2800mm and 10th generation (2880mm x 3130mm) are used. If present, shrinkage of the substrate 100 due to heat treatment during the semiconductor device manufacturing process. Therefore, fine processing can be difficult. For this reason, large glass substrates as described above are used as substrates. When used as 100, it is preferable to use one with small shrinkage. For example, substrate 10 Starting from 0, heat at a temperature of 400°C, preferably 450°C, and more preferably 500°C for 1 hour. The amount of shrinkage after heat treatment is 10 ppm or less, preferably 5 ppm or less, and more preferably A large glass substrate with a concentration of 3 ppm or less can be used.

[0061] Furthermore, a flexible substrate may be used as the substrate 100. One method for creating a transistor is to fabricate a transistor on a non-flexible substrate, and then... Another method involves peeling off the zista and transferring it to a flexible substrate, substrate 100. In that case, It is preferable to provide a delamination layer between the non-flexible substrate and the transistor.

[0062] The underlying insulating film 102 is designed so that impurities originating from the substrate 100 do not affect the oxide semiconductor film 106. It is provided to prevent this. However, if the substrate 100 does not contain impurities, the underlying insulating film is provided. It is not necessary to include 102.

[0063] The underlying insulating film 102 includes aluminum oxide, aluminum nitride, magnesium oxide, Silicon oxide, silicon oxide nitride, silicon nitride, silicon nitride, germanium oxide Yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide And one or more insulating materials containing tantalum oxide can be selected and used in a single layer or in a laminated form. stomach.

[0064] Silicon oxiditride refers to a material in which the oxygen content is higher than the nitrogen content. For example, oxygen at 50 to 70 atomic percent and nitrogen at 0.5 to 15 atomic percent. The range is 25 atomic percent to 35 atomic percent of silicon and 0 atomic percent to 10 atomic percent of hydrogen. It refers to substances that are included in it. Also, silicon nitride oxide is a substance whose composition contains more nitrogen than oxygen. This indicates the amount of an element present in large quantities. For example, oxygen is present in 5 to 30 atomic percent, and nitrogen in 20 atomic percent. Ato% to 55 atomic%, silicon 25 atomic% to 35 atomic%, hydrogen 10 atoms This refers to substances containing between % and 25 atomic percent. However, the above range is defined as Rutherford. Rutherford Backscattering Spec (RBS) (Trometry) and Hydrogen Forward Scattering (HFS) This is the result of measurements using scattering spectrometry. Furthermore, the composition of the constituent elements shall not exceed a total of 100 atomic percent.

[0065] The pair of electrodes 116 are made of Al, Ti, Cr, Co, Ni, Cu, Y, Zr, Mo, Ag, and T. A single layer or laminate of a and W, containing one or more elements, nitrides, oxides, or alloys. It is sufficient if they are present. In this embodiment, the pair of electrodes 116 are on the upper surface of the oxide semiconductor film 106. This shows the structure in contact with the other, but it is not limited to this structure. For example, The structure may also be one in which a pair of electrodes 116 are in contact on the lower surface of the oxide semiconductor film 106. Furthermore, in the vicinity of the portion of the oxide semiconductor film 106 that is in contact with the pair of electrodes 116, It may also have higher conductivity compared to other parts.

[0066] The protective insulating film 118 is made of aluminum oxide, aluminum nitride, magnesium oxide, and silver oxide. Silicon oxide nitride, silicon nitride, silicon nitride, germanium oxide, oxide Yttrium, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide and One or more insulating materials containing tantalum oxide can be selected and used in a single layer or in a laminated configuration.

[0067] Furthermore, it is preferable that the protective insulating film 118 has a low dielectric constant and sufficient thickness. For example For example, a silicon oxide film with a relative permittivity of approximately 3.8 is used, with a wavelength of 200 nm to 1000 nm. It should be provided with the thickness shown below. The surface of the protective insulating film 118 is slightly fixed due to the influence of atmospheric components, etc. It has an electric charge, and as a result, the threshold voltage of the transistor may fluctuate. Therefore, the protective insulating film 118 has a ratio within a range such that the effect of the charge generated on the surface is sufficiently small. It is preferable to have a dielectric constant and thickness. For similar reasons, a resin film on the protective insulating film 118 It is acceptable to reduce the effect of the charge generated on the surface by forming it.

[0068] Note that the transistor shown in Figure 1(C) has a different gate electrode than the transistor shown in Figure 1(B). The structure has a different configuration. Specifically, the gate electrode of the transistor shown in Figure 1(C) 105 has a first layer 105a and a second layer 105b, each having a gate electrode 104 These layers are similar to the first layer 104a and the second layer 104b. That is, gate electrode 105 This configuration omits the third layer 104c from the gate electrode 104. Therefore, the gate electrode 1 05 has a higher resistance than the gate electrode 104 due to the third layer 104c, but it is easy to form. This is the result.

[0069] The method for fabricating the transistor shown in Figure 1(B) will be explained below using Figures 2 and 3. .

[0070] First, prepare the substrate 100 and deposit the underlayer insulating film 102 on the substrate 100. 02 is the sputtering method, chemical vapor deposition (CVD). Eposition method, Molecular beam epitaxy (MBE) Epitaxy method, atomic layer deposition (ALD) method (tion) method or pulsed laser deposition (PLD) The film can be deposited using the (orthography) method.

[0071] Next, conductive films 114b and 114a are deposited in this order (see Figure 2(A)). Note that conductive film 114a is a metal oxide film. Also, conductive film 114b is conductive film 114 A metal film with lower resistance than a is used. Conductive films 114b and 114a are made by sputtering. The film can be deposited using the CVD method, CVD method, MBE method, ALD method, or PLD method.

[0072] Next, conductive films 114b and 114a are processed to form the conductive film 1 which has the shape of a gate electrode. Form 24b and the conductive film 124a (see Figure 2(B)).

[0073] In this specification, when the term "processing" is used, it may refer to, for example, photolithography. This demonstrates how to shape a film into a desired form using a resist mask formed by the process.

[0074] Furthermore, the presence of halogens and hydrogen in an oxide semiconductor film can generate carriers. When ruthenium or ruthenium oxide is used as the conductive film 114a, halogens A pneumatic compound that is produced from oxygen, a noble gas (preferably argon), etc., without using either hydrogen or pneumatic compounds. It becomes possible to etch the conductive film 114a using only the rasma. By etching 4a without using halogens and hydrogen, a halogen is introduced into the oxide semiconductor film. This reduces the likelihood of ion and hydrogen contamination and suppresses fluctuations in the transistor's threshold voltage. It is possible.

[0075] Next, the gate insulating film 112 is deposited. The gate insulating film 112 is deposited by sputtering, CV The film can be deposited using the D method, MBE method, ALD method, or PLD method.

[0076] The gate insulating film 112 is preferably deposited using a sputtering method. A gas (oxygen, ozone, or nitrous oxide) is added in an amount of 5% or more, preferably 10% or more, more preferably A film-forming gas containing 20% ​​or more, more preferably 50% or more, is used. Therefore, a gas with a low concentration of impurities such as hydrogen is used. Also, the substrate temperature during film formation should be above room temperature (20°C). Below 0°C, preferably above room temperature and below 150°C, and more preferably above room temperature and below 120°C. By using the above method, the concentration of impurities such as hydrogen is low, and excess oxygen is produced. Because it is easily incorporated, a gate insulating film 112 that releases oxygen by heat treatment can be formed. can.

[0077] The gate insulating film 112 is suitable for temperatures between 150°C and 650°C, or between 200°C and 450°C. An insulating film that releases oxygen upon heat treatment at the following temperatures is used.

[0078] In transistors using oxide semiconductor films, oxygen vacancies in the oxide semiconductor film are donors and Therefore, this becomes a factor that shifts the transistor's threshold voltage in the negative direction. Oxygen vacancies at the interface between the gate insulating film and the oxide semiconductor film affect the electrical properties of the transistor. This becomes a major factor in causing fluctuations. Therefore, in oxide semiconductor films, and between oxide semiconductor films and gates Reducing oxygen vacancies at the interface with the insulating film is possible when using an oxide semiconductor film. This leads to stabilizing the electrical characteristics of the gate and improving its reliability. When oxygen is released from the insulating film, it enters the oxide semiconductor film and the gate insulation between the oxide semiconductor film and the gate. This is preferable because it can reduce oxygen deficiency at the interface with the film.

[0079] "Releasing oxygen through heat treatment" means that, in TDS analysis, the amount of oxygen converted to oxygen atoms is... The amount released is 1.0 × 10 19 atoms / cm 3 The above is 3.0 × 10 19 atoms / cm 3 The above is 1.0 × 10 20 atoms / cm 3 Above, or 3.0 × 10 20 atoms / cm 3 This means that it is as described above.

[0080] Here, we will explain the method for measuring the amount of oxygen released in terms of oxygen atoms using TDS analysis, as follows: I will explain it to them.

[0081] The total amount of gas released when a sample is subjected to TDS analysis is proportional to the integral value of the ionic intensity of the released gas. For example, by comparing it with the reference value of a standard sample, the total amount of gas released can be calculated. ru.

[0082] For example, the TDS analysis results of a silicon wafer containing hydrogen of a predetermined density, which is a standard sample, and From the TDS analysis results of the measured sample, the amount of oxygen molecules released from the measured sample (N O2 ) is the formula (2 This can be determined by the following formula. Here, the mass-to-charge ratio (M / z) obtained by TDS analysis is 32. Assume that all detected gases originate from oxygen molecules. Other gases with an M / z of 32 include... Although CH3OH exists, it is unlikely to be present and will not be considered here. Also, oxygen Oxygen molecules containing oxygen atoms with mass number 17 and oxygen atoms with mass number 18, which are isotopes of the atom. We will not consider offspring either, as their proportion in the natural world is extremely small.

[0083]

number

[0084] N H2 This value represents the density of hydrogen molecules detached from the standard sample. H2 The standard test This is the integral value of the ionic intensity when the material is analyzed by TDS. Here, the reference value of the standard sample is N H2 / S H2 Let's assume that. S O2This is the integral value of the ionic intensity when the sample is subjected to TDS analysis. Yes, α is a coefficient that affects the ionic strength in TDS analysis. See the details of equation (2) below. For further information, see Japanese Patent Publication No. 6-275697 and U.S. Patent No. 5,528,032. The amount of oxygen released above was measured using the EMD-WA1 temperature-controlled desorption analyzer manufactured by Denshi Kagaku Co., Ltd. Using 000S / W, 1 × 10⁻¹⁰ 16 atoms / cm 2 Contains hydrogen atoms Measurements were taken using a silicon wafer.

[0085] Furthermore, in TDS analysis, some oxygen is detected as oxygen atoms. Oxygen molecules and oxygen atoms The ratio of these can be calculated from the ionization rate of oxygen molecules. Note that α above represents the oxygen component. Because it includes the ionization rate of the oxygen atom, by evaluating the amount of oxygen molecule released, the amount of oxygen atom released can be determined. Even if they are present, it can still be estimated.

[0086] Note N O2 This is the amount of oxygen molecules released. The amount released when converted to oxygen atoms is the amount of oxygen molecules. This will be twice the amount released.

[0087] Next, an oxide semiconductor film 136 is deposited on the gate insulating film 112 (see Figure 2(C)). The oxide semiconductor film 136 is produced by sputtering, CVD, MBE, ALD, or PL. The film should be deposited using method D.

[0088] The oxide semiconductor film 136 is preferably deposited using the sputtering method. The amount of the gas is 5% or more, preferably 10% or more, more preferably 20% or more. A film-forming gas containing 50% or more of the above is used. The film-forming gas has a low concentration of impurities such as hydrogen. Use gas.

[0089] Next, a heat treatment is performed. The heat treatment is carried out using an inert gas (nitrogen, or helium, neon, aluminum). (Noble gases such as chlorine, krypton, and xenon) atmosphere, oxidizing gas at 10 ppm or more, preferred Or an atmosphere containing 1% or more, more preferably 10% or more, or a reduced pressure state (10 Pa or less) At a temperature of 150°C or higher (preferably 1 Pa or less, more preferably 0.1 Pa or less), The process is carried out at a temperature of 650°C or lower, preferably between 200°C and 450°C.

[0090] The heat treatment reduces a portion of the conductive film 124a, and the oxygen produced by this reduction is used to isolate the gate. The edge film 112 reaches into and near the oxide semiconductor film 136. This reduces oxygen vacancies in and near the oxide semiconductor film 136. It is possible.

[0091] In this way, a portion of the conductive film 124a is reduced, resulting in a higher oxygen content than the conductive film 124a. The first layer 104a has a reduced concentration, and the conductive film 124a has an oxygen concentration similar to that of the first layer 104a. The second layer 104b is formed. The conductive film 124b remains unchanged until the third layer is formed. This results in 104c. As a result, the first layer 104a, the second layer 104b, and the third layer 104c are A gate electrode 104 is formed (see Figure 3(A)).

[0092] Here, the substrate temperature during the deposition of the oxide semiconductor film 136 is preferably between 150°C and 450°C. The aforementioned heat treatment can be substituted by setting the temperature between 200°C and 400°C.

[0093] Furthermore, if an insulating film that releases oxygen by heat treatment is provided as the gate insulating film 112, Oxygen is supplied to the oxide semiconductor film 106 from the gate insulating film 112 by heat treatment. However However, the release of oxygen can sometimes degrade the film quality of the gate insulating film 112. In this case, oxygen is supplied from the conductive film 124a to the gate insulating film 112, This can suppress the deterioration of the film quality of the gate insulating film 112 that occurs when these substances are emitted.

[0094] Next, the oxide semiconductor film 136 is processed to form island-shaped oxide semiconductor films 106 (Figure 3( See B). ).

[0095] Next, a conductive film is formed to form a pair of electrodes 116. The film can be deposited using puttering, CVD, MBE, ALD, or PLD methods. Next, a conductive film that will become a pair of electrodes 116 is processed to form the pair of electrodes 116.

[0096] Next, a protective insulating film 118 is deposited (see Figure 3(C)). The protective insulating film 118 is spat The film can be deposited using the taring method, CVD method, MBE method, ALD method, or PLD method. Furthermore, even if a back gate electrode is formed on the oxide semiconductor film 106 via the protective insulating film 118, That's fine. For the back gate electrode, refer to the description for gate electrode 104.

[0097] The transistor shown in Figure 1(B) can be fabricated in the manner described above.

[0098] The transistor shown in Figure 1(B) is located in the oxide semiconductor film 106 and the oxide semiconductor film 106 It has low oxygen vacancies in the vicinity and excellent electrical properties. Also, for transistor operation Since the resulting fluctuations in electrical characteristics are also suppressed, the semiconductor device using the transistor This can increase reliability.

[0099] This embodiment makes it possible to provide a transistor with excellent electrical characteristics. A highly reliable semiconductor device using the transistor can be provided.

[0100] This embodiment can be used in combination with other embodiments as appropriate.

[0101] (Embodiment 2) In this embodiment, Figures 4 to 6 show a transistor with a different structure from that of Embodiment 1. I will use it to explain.

[0102] Figure 4(A) is a top view of a transistor according to one embodiment of the present invention. A cross-sectional view corresponding to the dashed line AB is shown in Figure 4(B). For simplicity, Figure 4(A) is shown below. Therefore, the gate insulating film 212, the underlayer insulating film 102, etc., are omitted from the diagram.

[0103] The transistor shown in Figure 4(B) has an underlayer insulating film 102 provided on the substrate 100, and the underlayer An oxide semiconductor film 206 provided on the insulating film 102, and provided on the oxide semiconductor film 206 A pair of electrodes 216 are provided, and an oxide semiconductor film 206 and a pair of electrodes 216 are covered by The gate insulating film 212 is superimposed with the oxide semiconductor film 206 via the gate insulating film 212. A game having a first layer 204a, a second layer 204b, and a third layer 204c provided therein It has a gate electrode 204 and a gate dielectric film. The first layer 204a of the gate electrode 204 is a gate dielectric film. The second layer 204b of the gate electrode 204 is provided in contact with 212 and is on the first layer 204a The third layer 204c of the gate electrode 204 is provided on the second layer 204b. Alternatively, a back gate electrode may be provided beneath the oxide semiconductor film 206 via the underlying insulating film 102. No.

[0104] Here, the first layer 204a of the gate electrode 204 is connected to the second layer 204b of the gate electrode 204. This layer has a lower oxygen concentration than the gate electrode 204. Also, the third layer 204c of the gate electrode 204 is the gate This layer has higher conductivity than the first layer 204a and the second layer 204b of the electrode 204.

[0105] Furthermore, the first layer 204a of the gate electrode 204 is more susceptible to oxidation reactions than the gate insulating film 212. It is made of a material with high Bus free energy. That is, the first layer 204a of the gate electrode 204 is It has properties that make it easier to reduce than the gate insulating film 212. In other words, gate electrode 204 The first layer 204a has properties that make it less susceptible to oxidation than the gate insulating film 212.

[0106] The gate electrode 204 refers to the description of gate electrode 104.

[0107] The gate insulating film 212 is oxygen permeable. Specifically, its film density is 3.2 g / cm³. 3 less than It is an insulating film. Alternatively, the film through which oxygen atoms can permeate also depends on the thickness of the gate insulating film 212. However, the diffusion coefficient of oxygen atoms between 150°C and 450°C is 3 × 10⁻⁶ -16 cm 2 / For more than a second, preferably 1 × 10⁻⁶ seconds. -15 cm 2 / second or more, more preferably 8 × 10 -15 c m 2 It is an insulating film with a duration of 1 / second or more.

[0108] The gate insulating film 212 is described in the description of the gate insulating film 112.

[0109] The substrate 100 and the underlying insulating film 102 are described in the first embodiment.

[0110] For oxide semiconductor film 206, refer to the description of oxide semiconductor film 106.

[0111] The pair of electrodes 216 are described in the description of the pair of electrodes 116. In this embodiment, The structure shows that the pair of electrodes 216 are in contact on the upper surface of the oxide semiconductor film 206, This structure is not limited to this one. For example, a pair of electrodes 216 may be an oxide semiconductor film 206 It may also be a structure that is in contact with the lower surface.

[0112] Note that the transistor shown in Figure 4(C) has a different gate electrode than the transistor shown in Figure 4(B). The structure has a different configuration. Specifically, the gate electrode of the transistor shown in Figure 4(C) 205 has a first layer 205a and a second layer 205b, each having a gate electrode 204 These layers are similar to the first layer 204a and the second layer 204b. That is, gate electrode 205 This configuration omits the third layer 204c from the gate electrode 204. Therefore, the gate electrode 2 05 has a higher resistance than the gate electrode 204 due to the third layer 204c, but it is easy to form. This is the result.

[0113] The method for fabricating the transistor shown in Figure 4(B) is shown below with reference to Figures 5 and 6.

[0114] Furthermore, the manufacturing method up to the point where the underlayer insulating film 102 is provided on the substrate 100 is described in the implementation details. Refer to the explanation shown in Form 1.

[0115] Furthermore, it is preferable that the underlying insulating film 102 has sufficient flatness. Therefore, the underlying insulating film It is preferable to perform a planarization treatment on 102. As a planarization treatment, chemical mechanical polishing (CM) is used. P: Chemical Mechanical Polishing), or Dryer The etching method may be used. Specifically, the underlying insulating film 102 is provided such that the average surface roughness (Ra) is 1 nm or less, preferably 0.3 nm or less, more preferably 0.1 nm or less. By setting Ra to be less than or equal to the above values, crystal regions are likely to be formed in the oxide semiconductor film and the unevenness at the interface between the underlying insulating film 102 and the oxide semiconductor film is reduced, so that the influence of interface scattering can be minimized. Note that Ra is the arithmetic mean roughness defined in JIS B 0601:2001 (ISO 4287:1997), which is extended to three dimensions so that it can be applied to curved surfaces, and can be expressed as "the value obtained by averaging the absolute values of the deviations from the reference plane to the specified plane", and is defined by Equation (3). Here, the specified plane is the plane to be measured for roughness, and is defined as the rectangular area represented by the four points of coordinates ((x1, y1, f(x1, y1))(x1, y2, f(x1, y2))(x2, y1, f(x2, y1))(x2,

[0116] <着

Equation

[0117] y2, f(x2, y2)). The area of the rectangle obtained by projecting the specified plane onto the xy plane is S0, and the height of the reference plane (the average height of the specified plane) is Z0. Ra can be evaluated by an atomic force microscope (AFM). y2, f(x2, y2)) is defined as the rectangular area represented by the four points of coordinates ((x1, y1, f(x1, y1))(x1, y2, f(x1, y2))(x2, y1, f(x2, y1))(x2, y2, f(x2, y2)). The area of the rectangle obtained by projecting the specified plane onto the xy plane is S0, and the height of the reference plane (the average height of the specified plane) is Z0. Ra can be evaluated using an atomic force microscope (AFM). It is possible.

[0118] Next, the oxide semiconductor film 236 is formed (see Fig. 5(A)). The oxide semiconductor film 236 may be formed by referring to the description of the oxide semiconductor film 136 and using a sputtering method, a CVD method, an MBE method, an AL D method or a PLD method.

[0119] The oxide semiconductor film 236 is preferably formed by a sputtering method. At this time, a film-forming gas containing 5% or more, preferably 10% or more, more preferably 20% or more, and even more preferably 50% or more of an oxidizing gas is used. As the film-forming gas, a gas with a low impurity concentration such as hydrogen is used.

[0120] After forming the oxide semiconductor film 236, a first heat treatment may be performed. The temperature of the first heat treatment may be 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower. The atmosphere of the first heat treatment is an inert gas atmosphere, an atmosphere containing 10 ppm or more, preferably 1% or more, and more preferably 10% or more of an oxidizing gas, or is performed under a reduced pressure state. Alternatively, the first heat treatment is performed in an inert gas atmosphere and then, in order to supplement the desorbed oxygen, a heat treatment may be performed in an atmosphere containing 10 ppm or more, preferably 1% or more, and more preferably 10% or more of an oxidizing gas. By the first heat treatment, impurities such as hydrogen and water can be removed from the oxide semiconductor film 236.

[0121] Next, the oxide semiconductor film 236 is processed to form an island-shaped oxide semiconductor film 206 (see FIG. 5( B)).

[0122] Next, a conductive film to be a pair of electrodes 216 is formed. The conductive film to be a pair of electrodes 216 may be formed by referring to the description of the conductive film to be a pair of electrodes 116 and using a sputtering method, a CVD method, an MBE method, an ALD method or a PLD method. Next, the conductive film to be a pair of electrodes 216 is processed to form a pair of electrodes 216 (see FIG. 5(C)).

[0123] ​​​Next, the gate insulating film 212 is deposited. The gate insulating film 212 is a gate insulating film 112. Refer to the instructions and use the sputtering method, CVD method, MBE method, ALD method, or PLD method. You just need to deposit a film.

[0124] Next, conductive films 214a and 214b are deposited in this order (see Figure 6(A)). Conductive films 214a and 214b are described in the same way as conductive films 114a and 114b. Refer to the following and use sputtering, CVD, MBE, ALD, or PLD methods. A film should be formed. Note that the conductive film 214a should be a metal oxide film.

[0125] Next, a second heat treatment is performed. The second heat treatment is described in the description of the heat treatment shown in Embodiment 1. You can do this by referring to [this].

[0126] The second heat treatment reduces the conductive film 214a, and the oxygen produced by this reduction is used to isolate the gate. The edge film 212 reaches into and near the oxide semiconductor film 206. This reduces oxygen vacancies in and near the oxide semiconductor film 206. It is possible.

[0127] In this way, the oxygen concentration of the conductive film 214a is reduced, A conductive film 2 having a reduced oxygen concentration, and a conductive film 2 having an oxygen concentration similar to that of conductive film 214a. 24b is formed. Also, the conductive film 214b remains unchanged and becomes the conductive film 224c. (See Figure 6(B).)

[0128] Conductive films 224a, 224b, and 224c are processed to form the first layer 20 The gate electrode 204 is formed by 4a, the second layer 204b, and the third layer 204c. Do (see Fig. 6(C)).

[0129] Note that when halogen and hydrogen are present in the oxide semiconductor film, carriers may be generated. When ruthenium or ruthenium oxide is used as the conductive film 214a, etching can be performed without using either halogen or hydrogen. Therefore, by etching the conductive film 214a without using halogen and hydrogen, the variation in the threshold voltage of the transistor can be suppressed.

[0130] The transistor shown in Fig. 4(B) may be manufactured as described above.

[0131] The transistor shown in Fig. 4(B) has few oxygen deficiencies in and near the oxide semiconductor film 206 and has excellent electrical characteristics. In addition, since the variation in electrical characteristics that occurs during the operation of the transistor is also suppressed, the reliability of the semiconductor device using the transistor can be enhanced.

[0132] According to this embodiment, a transistor with excellent electrical characteristics can be provided. In addition, a highly reliable semiconductor device using the transistor can be provided.

[0133] Note that this embodiment can be used in combination with other embodiments as appropriate.

[0134] (Embodiment 3) In this embodiment, a transistor with a structure different from that of Embodiment 1 and Embodiment 2 will be described with reference to Figs. 7 to 11.

[0135] Fig. 7(A) is a top view of a transistor according to an aspect of the present invention. A point shown in Fig. 7(A) ​​​​​​​A cross-sectional view corresponding to the dashed line AB is shown in Figure 7(B). For simplicity, Figure 7(A) is shown below. Therefore, the protective insulating film 318, the undercoat insulating film 102, etc., are omitted from the diagram.

[0136] The transistor shown in Figure 7(B) has an underlayer insulating film 102 provided on the substrate 100, and the underlayer An oxide having a first region 306a and a second region 306b provided on an insulating film 102 A monocrystalline semiconductor film 306, a gate insulating film 312 provided on the oxide semiconductor film 306, and A first layer 304a is provided superimposed on the oxide semiconductor film 306 via an insulating film 312, A gate electrode 304 having a second layer 304b and a third layer 304c, and a gate insulating film 3 A side wall insulating film 310 provided in contact with the side surfaces of 12 and the gate electrode 304, and a side wall insulating film 310, an oxide semiconductor provided covering the gate electrode 304 and the oxide semiconductor film 306, A protective insulating film 318 having an opening that exposes a part of the body membrane 306, and the opening of the protective insulating film 318 A pair of electrodes provided in contact with the second region 306b of the oxide semiconductor film 306 via a pore. It has 316 and, in addition, the first layer 304a of the gate electrode 304 is the gate insulating film 312 The second layer 304b of the gate electrode 304 is provided in contact with the first layer 304a. The third layer 304c of the gate electrode 304 is provided on the second layer 304b, and the oxide semiconductor The first region 306a of the body membrane 306 overlaps with the gate electrode 304 and the sidewall insulating film 310. It is provided in the region. Also, backgear is provided under the oxide semiconductor film 306 via the underlying insulating film 102. You may also provide an electrode.

[0137] Here, the first layer 304a of the gate electrode 304 is connected to the second layer 304b of the gate electrode 304. This layer has a lower oxygen concentration than the gate electrode 304. Also, the third layer 304c of the gate electrode 304 is the gate This layer has higher conductivity than the first layer 304a and the second layer 304b of the electrode 304.

[0138] Furthermore, the first layer 304a of the gate electrode 304 is more susceptible to oxidation reactions than the gate insulating film 312. It is made of a material with high Bus free energy. That is, the first layer 304a of the gate electrode 304 is It has properties that make it easier to reduce than the gate insulating film 312. In other words, gate electrode 304 The first layer 304a has properties that make it less susceptible to oxidation than the gate insulating film 312.

[0139] The gate electrode 304 refers to the description of the gate electrode 104.

[0140] The gate insulating film 312 is oxygen permeable. Specifically, its film density is 3.2 g / cm³. 3 less than It is an insulating film. Alternatively, the film through which oxygen atoms can permeate also depends on the thickness of the gate insulating film 312. However, the diffusion coefficient of oxygen atoms between 150°C and 450°C is 3 × 10⁻⁶ -16 cm 2 / For more than a second, preferably 1 × 10⁻⁶ seconds. -15 cm 2 / second or more, more preferably 8 × 10 -15 c m 2 It is an insulating film with a duration of 1 / second or more.

[0141] The gate insulating film 312 is described in reference to the gate insulating film 112.

[0142] In Figure 7(B), the gate insulating film 312 has the same top surface shape as the gate electrode 304. However, it is not limited to this. For example, if the gate insulating film 312 is connected to the gate electrode 304 and the side The top surface shape may be the same as that of the wall insulating film 310 combined.

[0143] By using the gate electrode 304 and gate insulating film 312 as described above, the gate electrode Oxygen is supplied from the electrode 304 to the oxide semiconductor film 306 via the gate insulating film 312. Yes, it is possible. Therefore, oxygen vacancies exist in and near the oxide semiconductor film 306. This reduces acid in and near the oxide semiconductor film 306. This can suppress variations in the electrical characteristics of transistors caused by elementary defects.

[0144] The sidewall insulating film 310 is an insulating film with low oxygen permeability. An insulating film with low oxygen permeability is an insulating film that has low oxygen permeability. An insulating film that does not allow elementary molecules to pass through, and an oxygen atom diffusion coefficient that is sufficiently low, and the heating process during manufacturing. This refers to a membrane that, due to its properties, does not allow oxygen atoms to pass through. For example, a membrane that does not allow oxygen molecules to pass through is acid-resistant. The density should be high enough that elementary molecules cannot pass through. Specifically, the membrane density should be 3.2 g / cm³. 3 The above is sufficient. Furthermore, the permeability of the film to oxygen atoms also depends on the thickness of the sidewall insulating film 310. However, the diffusion coefficient of oxygen atoms between 150°C and 450°C is 3 × 10⁻⁶ -16 cm 2 / sec Less than 1 × 10 -16 cm 2 Less than / second, more preferably 5 × 10 -17 cm 2 It is acceptable if it is less than per second.

[0145] The sidewall insulating film 310, which has low oxygen permeability, prevents oxygen emitted from the gate electrode 304 from flowing outwards. Reduces diffusion and efficiently delivers oxygen to the oxide semiconductor film 306 and its vicinity. It can be supplied.

[0146] In this embodiment, a structure in which a side wall insulating film 310 is provided is described, but It is not limited to this. For example, a structure without a side wall insulating film 310 is also acceptable.

[0147] The substrate 100 and the underlying insulating film 102 are described in the description of Embodiment 1.

[0148] Furthermore, the first region 306a of the oxide semiconductor film 306 is the channel region of the transistor. It functions in this way. Also, the second region 306b of the oxide semiconductor film 306 is the sole of the transistor. It functions as a drain region and a drain region.

[0149] For oxide semiconductor film 306, refer to the description of oxide semiconductor film 106.

[0150] The protective insulating film 318 is described in reference to the description of the protective insulating film 118.

[0151] The pair of electrodes 316 are described in reference to the description of the pair of electrodes 116.

[0152] The method for fabricating the transistor shown in Figure 7(B) is described below with reference to Figures 8 and 9.

[0153] Furthermore, as shown in Figure 8(A), an underlayer insulating film 102 is provided on the substrate 100, and the underlayer insulating film 10 The method for fabricating the oxide semiconductor film 236 on 2 and performing the first heat treatment. Refer to the descriptions provided in Embodiments 1 and 2.

[0154] Next, a gate insulating film 313 is deposited. The gate insulating film 313 is formed by referencing the gate insulating film 112. The film is deposited using the following methods: sputtering, CVD, MBE, ALD, or PLD. That's all you need to do.

[0155] Next, conductive films 314a and 314b are deposited in this order (see Figure 8(A)). Conductive films 314a and 314b refer to conductive films 114a and 114b. Then, the film is deposited using sputtering, CVD, MBE, ALD, or PLD methods. Yes.

[0156] Next, a second heat treatment is performed. The second heat treatment is the same as the heat treatment described in Embodiment 1. You can do so by referring to the instructions.

[0157] The second heat treatment reduces the conductive film 314a, and the oxygen produced by this reduction is used to isolate the gate. The edge film 313 reaches into and near the oxide semiconductor film 306. This reduces oxygen vacancies in and near the oxide semiconductor film 306. It is possible.

[0158] In this way, the conductive film 314a is reduced, and the oxygen concentration is higher than that of the conductive film 314a. A conductive film 3 having a reduced oxygen concentration, and a conductive film 3 having an oxygen concentration similar to that of conductive film 314a. 24b is formed. Also, the conductive film 314b remains unchanged and becomes the conductive film 324c. (See Figure 8(B)).

[0159] Next, conductive films 324a, 324b, and 324c are processed, and each is first By making it layer 304a, second layer 304b and third layer 304c, gate electrode 304 It forms.

[0160] Furthermore, the presence of halogens and hydrogen in an oxide semiconductor film can generate carriers. When ruthenium or ruthenium oxide is used as the conductive film 324a, halogens Etching becomes possible without using either hydrogen or conductive film 324. By etching a without using halogens and hydrogen, the threshold voltage of the transistor is reduced. This can suppress fluctuations.

[0161] Next, by processing the gate insulating film 313, the top surface shape is the same as that of the gate electrode 304. A gate insulating film 312 is formed (see Figure 8(C)). Note that the gate insulating film 313 is formed The resist mask used to form the resist electrode 304 may be used for processing, or the resist mask After removing the scum, the gate electrode 304 may be used as a mask for processing. This exposes a portion of the surface of the oxide semiconductor film 236.

[0162] Here, without processing the gate insulating film 313, the transistor fabrication process described below is performed. You can proceed.

[0163] Next, an insulating film that will become the side wall insulating film 310 is deposited. The insulating film that will become the side wall insulating film 310 is The film can be deposited using puttering, CVD, MBE, ALD, or PLD methods. Next, the insulating film that will become the side wall insulating film 310 will be subjected to a highly anisotropic etching process. This forms the gate insulating film 312 and the side wall insulating film 310 that contacts the side surface of the gate electrode 304. This can be achieved (see Figure 9(A)). Note that without processing the gate insulating film 313, When the manufacturing process of the inverter is carried out, the side wall insulating film 310 is formed along with the gate insulating film 312 Therefore, a shape is formed that overlaps with the gate electrode 304 and the side wall insulating film 310. A thin insulating film is formed. The sidewall insulating film 310 is in contact with the side surface of the gate electrode 304. It takes shape.

[0164] Next, the oxide semiconductor film 236 is processed to form island-shaped oxide semiconductor films. Next, the sidewall insulation Using the border film 310 and gate electrode 304 as masks, impurities are added to the island-shaped oxide semiconductor film. Impurities are those that reduce the resistance of oxide semiconductor films. Specifically, helium, Boron, nitrogen, fluorine, neon, aluminum, phosphorus, argon, arsenic, krypton, i One or more elements selected from tin, antimony, and xenon may be added. Oh, that method can be done using ion implantation or ion doping. Or, oxide semiconductors... Plasma treatment or heat treatment in an atmosphere containing impurities that reduce the resistance of the body membrane can be performed. Preferably, an ion implantation method is used. Furthermore, the oxide semiconductor film is made less resistive by the ion implantation method. After adding the impurities, a third heat treatment may be performed. In this embodiment, the side Although impurities are added to the island-shaped oxide semiconductor film after the formation of the wall insulating film 310, the side wall insulating film Impurities may be added to the island-shaped oxide semiconductor film before the formation of 310. At this time, Impurities may be added to the island-shaped oxide semiconductor film via the insulating film 313, and gate insulation The film 313 is processed to form a gate insulating film 312 having the same upper surface shape as the gate electrode 304. Then, impurities may be added to the island-shaped oxide semiconductor film. After that, the side wall insulating film 310 It is sufficient to form it. When impurities are added to the island-shaped oxide semiconductor film in this way, the sidewall insulation The island-shaped oxide semiconductor film regions superimposed on film 310 also become low-resistance regions.

[0165] The region where impurities are added becomes less resistive and becomes a second region 306b. The region that is not modified remains unchanged and becomes the first region 306a. In this way, the first region An oxide semiconductor film 306 having region 306a and a second region 306b is formed (Figure 9). See (B). ).

[0166] Next, a protective insulating film is placed on the sidewall insulating film 310, the oxide semiconductor film 306, and the gate electrode 304. A protective insulating film 318 is deposited. The protective insulating film 318 is deposited by sputtering, with reference to the protective insulating film 118. The film can be deposited using CVD, MBE, ALD, or PLD methods.

[0167] Next, the protective insulating film 318 is processed to expose the second region 306b of the oxide semiconductor film 306. A pair of openings are formed. The formation of these openings is carried out so that the oxide semiconductor film 306 is as ec as possible. This is done under conditions that prevent chipping, but is not limited to these conditions. Specifically, the opening is formed In doing so, a portion of the surface of the second region 306b of the oxide semiconductor film 306 is etched. It's fine to wait, and it penetrates the second region 306b and exposes the underlying insulating film 102. That's fine.

[0168] Next, a pair of electrodes 31 are placed on the protective insulating film 318 and the exposed oxide semiconductor film 306. A conductive film is formed, which is 6. The conductive film is formed by sputtering, CVD, MBE, AL The film can be deposited using the D method or the PLD method.

[0169] Next, a conductive film that will become a pair of electrodes 316 is processed to form a pair of electrodes 316 (Figure 9(C) )reference.).

[0170] The transistor shown in Figure 7(B) can be fabricated in the manner described above.

[0171] Furthermore, regarding the method of fabricating the transistor shown in Figure 7(B), which is different from Figures 8 and 9, This will be explained using Figure 10 and Figure 11.

[0172] Note that Figure 10(A) shows a cross-sectional view similar to Figure 8(A). Therefore, up to Figure 10(A) For further explanation, please refer to the explanation up to Figure 8(A).

[0173] Next, conductive films 314a and 314b are processed to have the same top surface shape as the gate electrode. Conductive films 334a and 334b ​​are formed.

[0174] Furthermore, the presence of halogens and hydrogen in an oxide semiconductor film can generate carriers. When ruthenium or ruthenium oxide is used as the conductive film 334a, halogens Etching can be performed without using either hydrogen or conductive film. By etching a without using halogens and hydrogen, the threshold voltage of the transistor is reduced. This can suppress fluctuations.

[0175] Next, by processing the gate insulating film 313, the gate has the same top surface shape as the gate electrode. An insulating film 312 is formed (see Figure 10(B)). Note that the gate insulating film 313 is a conductive film. The resist mask used for processing 314a and conductive film 314b may be used for processing. After removing the resist mask, conductive films 334a and 334b ​​are used as a mask. It may be processed in this manner. In this way, a portion of the surface of the oxide semiconductor film 236 is exposed.

[0176] Here, without processing the gate insulating film 313, the transistor fabrication process described below is performed. You can proceed.

[0177] Next, an insulating film that will become the side wall insulating film 310 is deposited. The insulating film that will become the side wall insulating film 310 is The film can be deposited using puttering, CVD, MBE, ALD, or PLD methods. Next, the insulating film that will become the side wall insulating film 310 will be subjected to a highly anisotropic etching process. Therefore, the side wall insulating film is in contact with the side surface of the gate insulating film 312, conductive film 334a and conductive film 334b. A border film 310 can be formed (see Figure 10(C)).

[0178] Next, the oxide semiconductor film 236 is processed to form island-shaped oxide semiconductor films. Next, the sidewall insulation The edge film 310, gate insulating film 312, conductive film 334a and conductive film 334b ​​are used as a mask. An impurity is added to an island-shaped oxide semiconductor film. This impurity is shown in Figures 9(A) and 9(B). You can refer to the description of impurities explained earlier.

[0179] The region where impurities are added becomes less resistive and becomes a second region 306b. The region that is not modified remains unchanged and becomes the first region 306a. In this way, the first region An oxide semiconductor film 306 having region 306a and a second region 306b is formed (Figure 1). See 1(A). ).

[0180] Next, a second heat treatment is performed.

[0181] The second heat treatment reduces the conductive film 334a, and the oxygen produced by this reduction is used to isolate the gate. The edge film 312 reaches into and near the oxide semiconductor film 306. This reduces oxygen vacancies in and near the oxide semiconductor film 306. It is possible.

[0182] In this way, the conductive film 334a is reduced, and the oxygen concentration is higher than that of the conductive film 334a. The first layer 304a has a reduced oxygen concentration, and the second layer has an oxygen concentration similar to that of the conductive film 334a. Layer 304b is formed. Also, the conductive film 334b ​​remains unchanged until the third layer 304 c. In this way, the first layer 304a, the second layer 304b and the third layer 30 A gate electrode 304 having 4c is formed (see Figure 11(B)).

[0183] Next, a protective insulating film is placed on the sidewall insulating film 310, the oxide semiconductor film 306, and the gate electrode 304. Deposition of film 318.

[0184] Next, the protective insulating film 318 is processed to expose the second region 306b of the oxide semiconductor film 306. A pair of openings are formed. The formation of these openings is carried out so that the oxide semiconductor film 306 is as ec as possible. This is done under conditions that prevent chipping, but is not limited to these conditions. Specifically, the opening is formed In doing so, a portion of the surface of the second region 306b of the oxide semiconductor film 306 is etched. It's fine to wait, and it penetrates the second region 306b and exposes the underlying insulating film 102. That's fine.

[0185] Next, a pair of electrodes 31 are placed on the protective insulating film 318 and the exposed oxide semiconductor film 306. A conductive film that will become 6 is formed. Next, a conductive film that will become a pair of electrodes 316 is processed, and the pair of electrodes Forms 316 (see Figure 11(C)).

[0186] The transistor shown in Figure 7(B) can be fabricated in the manner described above.

[0187] The transistor shown in Figure 7(B) is located in the oxide semiconductor film 306 and the oxide semiconductor film 306 It has low oxygen vacancies in the vicinity and excellent electrical properties. Also, for transistor operation Since the resulting fluctuations in electrical characteristics are also suppressed, the semiconductor device using the transistor This can increase reliability.

[0188] This embodiment makes it possible to provide a transistor with excellent electrical characteristics. A highly reliable semiconductor device using the transistor can be provided.

[0189] This embodiment can be used in combination with other embodiments as appropriate.

[0190] (Embodiment 4) In this embodiment, a transistor with a different structure from the transistors shown in Embodiments 1 to 3 is used. The concept of "Ta" will be explained using Figure 12.

[0191] Figure 12(A) is a top view of a transistor according to one embodiment of the present invention. A cross-sectional view corresponding to the dashed line AB is shown in Figure 12(B). For simplicity, Figure 12(A) is shown. In the above example, the protective insulating film 418, the underlayer insulating film 102, etc., are omitted.

[0192] The transistor shown in Figure 12(B) has an underlayer insulating film 102 provided on the substrate 100, and Acid having a first region 406a and a second region 406b provided on the insulating film 102 A oxide semiconductor film 406, a gate insulating film 412 provided on the oxide semiconductor film 406, and A first layer 404a is provided superimposed on the oxide semiconductor film 406 via an insulating film 412. , a gate electrode 404 having a second layer 404b and a third layer 404c, and gate electrode 4 An insulating film 420 provided on the third layer 404c of 04, a gate insulating film 412, and a gate electric A side wall insulating film 410 is provided in contact with the sides of the pole 404 and insulating film 420, and an oxide semiconductor A pair of electrodes provided in contact with the second region 406b of the body membrane 406 and the side wall insulating film 410. 416, a pair of electrodes 416, insulating film 420, side wall insulating film 410, gate electrode 404 and An opening that covers the oxide semiconductor film 406 and exposes a portion of the pair of electrodes 416. A protective insulating film 418 having an opening in the protective insulating film 418, and a pair of electrodes 416 through the opening in the protective insulating film 418. It has a pair of wires 466 provided in contact with each of them. Layer 404a is provided in contact with the gate insulating film 412, and the second layer 4 of the gate electrode 404 04b is provided on the first layer 404a, and the third layer 404c of the gate electrode 404 is the second The first region 406a of the oxide semiconductor film 406 is provided on layer 404b and is the gate electrode 40 It is provided in the region that overlaps with 4 and the side wall insulating film 410. Also, via the underlay insulating film 102 Alternatively, a back gate electrode may be provided beneath the oxide semiconductor film 406.

[0193] Here, the first layer 404a of the gate electrode 404 is the second layer 404b of the gate electrode 404. This layer has a lower oxygen concentration than the gate. Also, the third layer 404c of the gate electrode 404 is the gate This layer has higher conductivity than the first layer 404a and the second layer 404b of the electrode 404.

[0194] Furthermore, the first layer 404a of the gate electrode 404 is more susceptible to oxidation reactions than the gate insulating film 412. It is made of a material with high Bus free energy. That is, the first layer 404a of the gate electrode 404 is It has properties that make it easier to reduce than the gate insulating film 412. In other words, gate electrode 404 The first layer 404a has properties that make it less susceptible to oxidation than the gate insulating film 412.

[0195] The gate electrode 404 refers to the description of gate electrode 104.

[0196] The gate insulating film 412 is oxygen permeable. Specifically, its film density is 3.2 g / cm³. 3 less than It is an insulating film. Alternatively, the film through which oxygen atoms can permeate also depends on the thickness of the gate insulating film 412. However, the diffusion coefficient of oxygen atoms between 150°C and 450°C is 3 × 10⁻⁶ -16 cm 2 / For more than a second, preferably 1 × 10⁻⁶ seconds. -15 cm 2 / second or more, more preferably 8 × 10 -15 c m 2 It is an insulating film with a duration of 1 / second or more.

[0197] The gate insulating film 412 is described in reference to the gate insulating film 112.

[0198] In Figure 12(B), the gate insulating film 412 is connected to the gate electrode 404 and the sidewall insulating film 41 The top surface shape is similar to that of a zero, but it is not limited to this. For example, gate The insulating film 412 may have the same top surface shape as the gate electrode 404.

[0199] By using the gate electrode 404 and gate insulating film 412 as described above, the gate electrode Oxygen is supplied from pole 404 to oxide semiconductor film 406 via gate insulating film 412. Yes, it is possible. Therefore, oxygen vacancies exist in and near the oxide semiconductor film 406. This reduces acid in and near the oxide semiconductor film 406. This can suppress variations in the electrical characteristics of transistors caused by elementary defects.

[0200] The sidewall insulating film 410 is an insulating film with low oxygen permeability. An insulating film with low oxygen permeability is an insulating film that has low oxygen permeability. An insulating film that does not allow elementary molecules to pass through, and an oxygen atom diffusion coefficient that is sufficiently low, and the heating process during manufacturing. This refers to a membrane that, due to its properties, does not allow oxygen atoms to pass through. For example, a membrane that does not allow oxygen molecules to pass through is acid-resistant. The density should be high enough that elementary molecules cannot pass through. Specifically, the membrane density should be 3.2 g / cm³. 3 The above is sufficient. Furthermore, the permeability of the film to oxygen atoms also depends on the thickness of the sidewall insulating film 410. However, the diffusion coefficient of oxygen atoms between 150°C and 450°C is 3 × 10⁻⁶ -16 cm 2 / sec Less than 1 × 10 -16 cm 2 Less than / second, more preferably 5 × 10 -17 cm 2 It is acceptable if it is less than per second.

[0201] The sidewall insulating film 410, which has low oxygen permeability, prevents oxygen from being released from the gate electrode 404 from reaching the outside. Reduces diffusion and efficiently delivers oxygen to the oxide semiconductor film 406 and its vicinity. It can be supplied.

[0202] The insulating film 420 is designed to prevent the pair of electrodes 416 and the gate electrode 404 from coming into contact. It is provided. The insulating film 420 is described in reference to the description of the underlay insulating film 102.

[0203] The substrate 100 and the underlying insulating film 102 are described in the description of Embodiment 1.

[0204] Furthermore, the first region 406a of the oxide semiconductor film 406 is the channel region of the transistor. It functions in this way. Also, the second region 406b of the oxide semiconductor film 406 is the sole of the transistor. It functions as a drain region and a drain region.

[0205] For oxide semiconductor film 406, refer to the description of oxide semiconductor film 106.

[0206] The protective insulating film 418 is described in reference to the description of the protective insulating film 118.

[0207] The pair of electrodes 416 and the pair of wires 466 refer to the description of the pair of electrodes 116.

[0208] The transistor shown in Figure 12(B) has a pair of electrodes 416 connected to a low-resistance oxide semiconductor film 406. Because it is possible to achieve lower resistance than in the regulated region, high on-characteristics can be obtained.

[0209] The transistor shown in Figure 12(B) is located in the oxide semiconductor film 406 and the oxide semiconductor film 40 It has few oxygen vacancies near 6 and excellent electrical properties. Also, the transistor operation Because fluctuations in electrical characteristics that occur as a result are also suppressed, semiconductor devices using this transistor are also suppressed. This can increase its reliability.

[0210] This embodiment makes it possible to provide a transistor with excellent electrical characteristics. A highly reliable semiconductor device using the transistor can be provided.

[0211] This embodiment can be used in combination with other embodiments as appropriate.

[0212] (Embodiment 5) In this embodiment, the transistor shown in any of Embodiments 1 to 4 is used The fabricated liquid crystal display device will now be described. In this embodiment, the liquid crystal display device is based on the present invention. An example of applying one form of this will be explained, but it is not limited to this. For example, This invention relates to an EL (Electro-Luminescence) display device, which is a type of optical device. Applying one form of the Meiji method would be easily conceivable to anyone skilled in the art.

[0213] Figure 13 shows the circuit diagram of an active matrix driven liquid crystal display device. Source line SL_1 to source line SL_a, gate line GL_1 to gate line GL_b and It has multiple pixels 2200. Each pixel 2200 has a transistor 2230 and a capacitor It includes 2220 and liquid crystal elements 2210. Multiple such pixels 2200 come together to form a liquid crystal display. It constitutes the pixel section of the display device. Note that when simply referring to the source line or gate line, the source is used. It is sometimes written as line SL or gate line GL.

[0214] Transistor 2230 is a transistor shown in any of Embodiments 1 to 4. The transistors shown in Embodiments 1 to 4 are made of oxide with good electrical characteristics. Because it uses a semiconductor transistor, it is possible to obtain a display device with high display quality.

[0215] The gate wire GL is connected to the gate of transistor 2230, and the source wire SL is connected to transistor 2 The source of transistor 230 is connected, and the drain of transistor 2230 is connected to the capacitor 2220. One of the capacitive electrodes is connected to one of the pixel electrodes of the liquid crystal element 2210. Capacitor 2220 The other capacitive electrode and the other pixel electrode of the liquid crystal element 2210 are connected to a common electrode. The common electrode may be provided on the same layer as the gate wire GL.

[0216] Furthermore, the gate wire GL is connected to the gate drive circuit. The gate drive circuit is as follows: Embodiment 1 The device may include the transistor shown in any of embodiments to 4.

[0217] Furthermore, the source line SL is connected to the source drive circuit. The source drive circuit is in Embodiment 1 The device may include the transistor shown in any of embodiments to 4.

[0218] Furthermore, either or both of the gate drive circuit and the source drive circuit may be provided separately. Formed on a plate, and then COG (Chip On Glass), wire bonding, or T Connect each wire using methods such as AB (Tape Automated Bonding). You may continue.

[0219] Furthermore, since transistors are susceptible to damage from static electricity, it is advisable to include a protection circuit. It is preferable that the protection circuit be constructed using nonlinear elements.

[0220] When a voltage is applied to the gate line GL such that it is greater than or equal to the threshold voltage of transistor 2230, The charge supplied from the source line SL becomes the drain current of transistor 2230. The charge is stored in transistor 2220. After one row of charge is complete, transistor 2230 in that row is turned off. In this state, voltage is no longer applied from the source line SL, but it is stored in capacitor 2220. The required voltage can be maintained by the charge. Then, capacitor 222 on the next line The charging of 0 is performed. In this way, charging is performed from row 1 to row b. The drain current is, In a zista, this refers to the current that flows from the drain through the channel to the source. Current flows when the gate voltage is greater than the threshold voltage.

[0221] Note that the 2230 transistor has a low off-current. Therefore, it is suitable for images with little movement (still images). (Including...) This allows for a reduction in the display refresh frequency, enabling further reductions in power consumption. Furthermore, it becomes possible to further reduce the capacity of capacitor 2220, thus enabling charging. This can reduce the amount of power consumed.

[0222] Furthermore, the 2230 transistor exhibits small fluctuations in electrical characteristics due to its operation. Therefore, a highly reliable liquid crystal display device can be obtained.

[0223] As described above, according to one aspect of the present invention, a display quality is high, power consumption is low, and reliability is achieved. We can provide high-performance liquid crystal display devices.

[0224] This embodiment can be used in appropriate combination with other embodiments.

[0225] (Embodiment 6) In this embodiment, the transistor shown in any of Embodiments 1 to 4 is used. Next, I will explain an example of manufacturing a semiconductor memory device.

[0226] A typical example of a volatile semiconductor memory device is selecting transistors that constitute the memory element. By accumulating electric charge in a capacitor, information is stored using DRAM (Dynamic Radar). (NDOM Access Memory), using circuits such as flip-flops to store information in memory. The SRAM (Static Random Access Memory) that holds the data be.

[0227] A typical example of a non-volatile semiconductor memory device is the space between the gate and channel region of a transistor. There is a flash memory that has nodes and stores information by holding electric charge in those nodes. .

[0228] Some of the transistors included in the semiconductor memory device described above are in Embodiments 1 to 4 One of the transistors shown can be applied.

[0229] First, a semiconductor to which the transistor shown in any of Embodiments 1 to 4 is applied. Figure 14 will be used to explain the memory cells of a storage device.

[0230] The memory cell has a transistor Tr and a capacitor C, and the gate of the transistor Tr The terminal is electrically connected to the word line WL and to either the source or drain of the transistor Tr. It is electrically connected to the bit line BL, and the other of the source or drain of the transistor Tr is One end of capacitor C is electrically connected, and the other end of capacitor C is grounded, and bit line BL It is electrically connected to the sense amplifier SAmp (see Figure 14(A)).

[0231] The time change of the voltage held in capacitor C is determined by the off-current of transistor Tr, as shown in Figure 1. As shown in 4(B), it is known to gradually decrease. Initially, it increases from V0 to V1. The applied voltage decreases over time to VA, which is the limit point for reading data1. Let this period be called the retention period T_1. That is, in the case of a binary memory cell, during the retention period T_1 It needs to be refreshed.

[0232] Here, the transistor Tr is a transistor as shown in any of Embodiments 1 to 4 By applying this, the off-current is small, which allows the holding period T_1 to be extended. This allows for a reduction in the frequency of refreshes, thereby lowering power consumption. For example, if the off-current is 1 × 10 -21 A or less, preferably 1 × 10 -24 A or lower When a memory cell is constructed using a transistor made of an oxide semiconductor film, it can be used without supplying power. It will be possible to retain data for periods ranging from several days to several decades.

[0233] Furthermore, the transistor Tr is a transistor shown in any of Embodiments 1 to 4. When applied, the transistor exhibits small fluctuations in electrical characteristics due to its operation. Therefore, highly reliable semiconductor memory devices can be obtained.

[0234] As described above, according to one aspect of the present invention, a memory cell with high reliability and low power consumption is obtained. A semiconductor memory device can be obtained.

[0235] Next, as an example different from Figure 14, the trap shown in any of Embodiments 1 to 4 Figure 15 illustrates the memory cell of a semiconductor memory device that utilizes a generator.

[0236] Figure 15(A) is a circuit diagram of a memory cell and its surroundings. The memory cell is a transistor It has a transistor Tr_1, a transistor Tr_2, and a capacitor C. The gate of Tr_1 is electrically connected to the word line WL_1, and the saw of transistor Tr_1 One of the drains or the other is electrically connected to the source wire SL_1 and transistor Tr_2 The gate is either the source or drain of transistor Tr_1, and the capacitor C By being electrically connected to one end, it forms node N, and the source of transistor Tr_2 and One side of the drain is electrically connected to the drain wire DL_2, and the sole of transistor Tr_2 The other end of the drain or source wire is electrically connected to source wire SL_2, and the other end of capacitor C It is electrically connected to the capacitance line CL.

[0237] In this embodiment, the non-volatile memory is configured such that, depending on the potential of node N, transistor T This method utilizes the fact that the apparent threshold voltage of r_2 fluctuates. For example, see Figure 15. (B) is the voltage V across the capacitance line CL. CL And the drain current I flowing through transistor Tr_2 d _ This diagram explains the relationship with 2.

[0238] Here, node N can adjust its potential via transistor Tr_1. For example Let the potential of source line SL_1 be VDD. At this time, let the potential of word line WL_1 be TRA By setting the threshold voltage Vth of the transistor Tr_1 to a potential greater than or equal to the potential obtained by adding VDD, the node The potential of N can be set to HIGH. Also, the potential of the word line WL_1 can be set to the transistor By setting the threshold voltage of Tr_1 below Vth, the potential of node N can be set to LOW. can.

[0239] Therefore, V shown with N=LOW CL -I d _2 curve and V shown with N=HIGH CL -I d _2 curves can be obtained. That is, when N=LOW, V CL =0V at I d Since _2 is small, the data is 0. Also, when N=HIGH, V CL = 0V I d Since _2 is large, it becomes data 1. In this way, data can be stored. Cut.

[0240] Here, transistor Tr_1 is a transistor as shown in any of Embodiments 1 to 4. By applying a zista, the transistor's off-current can be made extremely small, The charge accumulated at node N is unintentionally transferred between the source and drain of transistor Tr_1 This prevents data leaks. Therefore, data can be retained over a long period of time. Furthermore, a memory cell included in a semiconductor memory device according to one aspect of the present invention is a transistor Because the threshold voltage of Tr_1 is adjusted, the voltage required for writing is small, flash Compared to memory and other components, it can reduce power consumption.

[0241] Furthermore, transistor Tr_1 is a transistor as shown in any of Embodiments 1 to 4 When the stylus is applied, the transistor exhibits small fluctuations in electrical characteristics caused by the transistor's operation. Therefore, highly reliable semiconductor memory devices can be obtained.

[0242] Furthermore, transistor Tr_2 is a transistor as shown in any of Embodiments 1 to 4. You may apply ZISTA.

[0243] As described above, according to one aspect of the present invention, a semiconductor memory device is made highly reliable and consumes little power. You can obtain a place.

[0244] This embodiment can be used in appropriate combination with other embodiments.

[0245] (Embodiment 7) A transistor as shown in any of Embodiments 1 to 4 or as shown in Embodiment 6 A CPU (Central Processor) uses semiconductor memory devices in at least part of its components. It is possible to configure an ng Unit.

[0246] Figure 16(A) is a block diagram showing the specific configuration of the CPU. The PU is an arithmetic logic unit (ALU) located on the circuit board 1190. Unit 1191, ALU controller 1192, instruction decoder 11 93, interrupt controller 1194, timing controller 1195, registers 1196, Register Controller 1197, Bus Interface (Bus I / F) 1 198, rewritable ROM1199, and ROM interface (ROM I / It has F)1189. The substrate 1190 is a semiconductor substrate, SOI substrate, glass substrate, etc. The ROM 1199 and ROM interface 1189 are provided on a separate chip. That is also fine. Of course, the CPU shown in Figure 16(A) is just one example of a simplified configuration. In fact, actual CPUs have a wide variety of configurations depending on their intended use.

[0247] Instructions input to the CPU via the bus interface 1198 are instructions The signal is input to decoder 1193, decoded, and then processed by ALU controller 1192, interface Raptor controller 1194, register controller 1197, timing controller It is entered into 1195.

[0248] ALU controller 1192, interrupt controller 1194, register controller R1197 and timing controller 1195 control various commands based on the decoded instructions. To perform the operation. Specifically, the ALU controller 1192 controls the operation of the ALU 1191. It generates a signal. Also, the interrupt controller 1194 controls the CPU's program. During execution, interrupt requests from external input / output devices and peripheral circuits are processed based on their priority and masking. The system makes a judgment and processes based on the state. The register controller 1197 determines the address of register 1196. It generates a value and reads or writes to register 1196 depending on the CPU state.

[0249] Furthermore, the timing controller 1195 is connected to the ALU 1191 and the ALU controller 119 2. Instruction decoder 1193, interrupt controller 1194, and It generates signals to control the timing of the operation of the register controller 1197. For example, The timing controller 1195 uses the reference clock signal CLK1 to determine the internal clock signal It is equipped with an internal clock generation unit that generates CLK2, and the clock signal CLK2 is used by the various types described above. It supplies power to the circuit.

[0250] In the CPU shown in Figure 16(A), a memory element is provided in register 1196. The memory element of sta 1196 can be a semiconductor memory device as shown in Embodiment 6. .

[0251] In the CPU shown in Figure 16(A), the register controller 1197 is ALU1191 Following the instructions, a hold operation is performed in register 1196. That is, register 1196 In the memory element it possesses, data is held using a flip-flop or a capacitor. Data is retained by flip-flops. If data is retained by flip-flops, Power voltage is supplied to the memory elements within the ZISTA 1196. Data is stored in the capacitor. If the data is held, the data is rewritten to the capacitor, register 1196 The power supply voltage to the internal memory elements can be stopped.

[0252] Regarding power shutdown, as shown in Figure 16(B) or Figure 16(C), the memory element group and the power A switching element is installed between nodes where the source potential VDD or power supply potential VSS is provided. This can be done by doing so. The following is a description of the circuits in Figures 16(B) and 16(C). To do so.

[0253] Figures 16(B) and 16(C) show switches that control the supply of power potential to the memory elements. One configuration using a transistor as shown in any of Embodiments 1 to 4 as the ring element. Here is an example.

[0254] The memory device shown in Figure 16(B) consists of a switching element 1141 and multiple memory elements 1142. It has a group of memory elements 1143. Specifically, each memory element 1142 has The semiconductor memory device shown in Embodiment 6 can be used. The memory element group 1143 has Each of the memory elements 1142 receives high-level signals via the switching element 1141. The power supply potential VDD is supplied. Furthermore, each memory element of the memory element group 1143 has Element 1142 is given the potential of signal IN and the potential of the low-level power supply potential VSS. Yes, they are.

[0255] In Figure 16(B), the switching element 1141 is as shown in Embodiments 1 to 4. The transistor shown in one of the above is used, and the signal S applied to the gate of the transistor is used. Switching is controlled by igA.

[0256] Note that in Figure 16(B), the switching element 1141 has only one transistor. This indicates a configuration, but is not limited to this; it may have multiple transistors. (Switch) In the case where the switching element 1141 has multiple transistors that function as switching elements In addition, the above-mentioned transistors may be connected in parallel or in series. That's fine, and it's also acceptable if series and parallel connections are combined.

[0257] Furthermore, Figure 16(C) shows that each of the memory elements 1142 in the memory element group 1143 has, A low-level power supply potential VSS is supplied via the switching element 1141. An example of a memory device is shown. The switching element 1141 controls the memory element group 1143. It is possible to control the supply of a low-level power supply potential VSS to each memory element 1142. Cut.

[0258] Between the memory element group and the node to which the power supply potential VDD or power supply potential VSS is provided, When a switching element is installed to temporarily stop the CPU's operation and cut off the power supply voltage, Even when data is stored, it is possible to reduce power consumption. For example, when a personal computer user inputs information into an input device such as a keyboard Even while stopped, the CPU operation can be halted, thereby reducing power consumption. It is possible.

[0259] Here, we used the CPU as an example, but DSP (Digital Signal Processor) Processor), custom LSI, FPGA (Field Programmable) It can also be applied to LSIs such as e Gate Arrays.

[0260] This embodiment can be implemented in appropriate combination with the above embodiment.

[0261] (Embodiment 8) In this embodiment, at least one of Embodiments 1 to 7 is applied to the electronic Let's explain some examples of equipment.

[0262] Figure 17(A) shows a portable information terminal. The portable information terminal shown in Figure 17(A) has a housing 93 00, button 9301, microphone 9302, display unit 9303, speaker 9 The present invention comprises 304 and a camera 9305, and functions as a portable telephone. One embodiment can be applied to the display unit 9303 and the camera 9305. Also, as shown in the figure... However, one embodiment of the present invention can be applied to the arithmetic unit, wireless circuit, or memory circuit located inside the main unit. It is also possible.

[0263] Figure 17(B) shows the display. The display shown in Figure 17(B) is housed in enclosure 931 It comprises 0 and a display unit 9311. One aspect of the present invention is applied to the display unit 9311. This is possible. By applying one embodiment of the present invention, it is possible to achieve high display quality, low power consumption, and reliable This can result in a highly reliable display.

[0264] Figure 17(C) shows a digital still camera. The components are the housing 9320, the button 9321, the microphone 9322, and the display unit 9323. The present invention comprises the following. One embodiment of the present invention can be applied to the display unit 9323. Also, Figure Although not shown, one embodiment of the present invention can also be applied to a memory circuit or an image sensor.

[0265] Figure 17(D) shows a foldable portable information terminal. The portable information terminal consists of a housing 9630, a display unit 9631a, a display unit 9631b, and a fastener 9633. , has an operating switch 9638. One embodiment of the present invention has a display unit 9631a and a display unit It can be applied to 9631b. Also, although not shown in the diagram, the arithmetic unit inside the main body, One embodiment of the present invention can also be applied to a linear circuit or a memory circuit.

[0266] Furthermore, the display unit 9631a and / or the display unit 9631b may be partially or entirely touch-sensitive. It can be turned on, and data input and other operations can be performed by touching the displayed operation keys. can.

[0267] By using a semiconductor device according to one aspect of the present invention, the performance and reliability of electronic devices can be improved. It can be improved.

[0268] This embodiment can be used in appropriate combination with other embodiments. [Examples]

[0269] In this example, secondary ion mass spectrometry (SIMS) was used. Using spectrometry, the behavior of oxygen in a silicon oxide film during heat treatment is observed. explain.

[0270] SIMS is a quadrupole secondary ion mass spectrometer manufactured by ULVAC-PHI, Inc. DEPT1010 was used.

[0271] The method for preparing the sample is shown below.

[0272] First, prepare a quartz substrate, and on the quartz substrate 18 A silicon oxide film was deposited using O2. The silicon oxide film in question was deposited by sputtering. Specifically, the silicon oxide film was deposited by sputtering. Using a target, argon is introduced at a rate of 25 sccm and oxygen ( 18 Contains 25 sccm of O2) In a controlled atmosphere, the pressure was controlled to 0.4 Pa, and the substrate heating temperature during film deposition was set to 100°C. The film was deposited with a thickness of 300 nm using a power supply of 1.5 kW (13.56 MHz).

[0273] Here, 18 O2 is an isotope of the oxygen atom with an atomic weight of 18. 18 Oxygen component consisting of O) It refers to a child.

[0274] next, 18 A silicon oxide film was deposited on a silicon oxide film using O2. The silicon film was deposited by sputtering. Specifically, a silicon oxide target was used. Using this method, in an atmosphere containing 25 sccm of argon and 25 sccm of oxygen, the pressure was set The pressure is controlled to 0.4 Pa, the substrate heating temperature during film deposition is 100°C, and the deposition power is 1.5 kW (13. The film was deposited with a thickness of 100 nm at 56 MHz. This silicon oxide film was intentionally 18 It does not contain O.

[0275] The sample prepared as described above was subjected to a nitrogen atmosphere at 150°C, 250°C, and 35°C. Heat treatment was performed at temperatures of 0°C and 550°C for 1 hour. In addition, the heat treatment was performed in particular. We also prepared samples that did not contain any material (referred to as-depo).

[0276] Figure 18 shows the results of SIMS. 18 This is the depth direction analysis result for O, as-d shown in Figure 18. The indications EPO, 150°C, 250°C, 350°C, and 550°C refer to the heat treatment conditions, respectively. This corresponds to the matter. Also, the area to the right of the dashed line shown in Figure 18 is 18 Oxidation film formation using O2 Silicon film (silicon oxide ( 18 This indicates that O2) is the notation.

[0277] As shown in FIG. 18, by performing heat treatment, 18 from the silicon oxide film formed using O2 to the silicon oxide film 18 it was found that O diffuses. Also, the higher the heat treatment temperature, 18 from the silicon oxide film formed using O2 to the silicon oxide film 18 the amount of O diffusing was found to be large.

[0278] From the above, even in the heat treatment at about 150 °C, it was found that oxygen diffuses about 40 nm in the silicon oxide film. was found.

[0279] From this example, it can be seen that oxygen diffuses in the silicon oxide film by heat treatment.

Example

[0280] In this example, TDS analysis is used to explain the oxygen permeability of the aluminum oxide film.

[0281] The evaluation of gas release was performed using a temperature programmed desorption analyzer EMD-WA1000S / W manufactured by Electronic Science Co., Ltd. was used.

[0282] The method for preparing the sample is shown below.

[0283] First, a silicon wafer was prepared, and a thermal oxide film was formed on the silicon wafer. The thermal oxide film was formed in an oxygen atmosphere containing 3% HCl at a temperature of 950 °C, and the thickness was 100 nm.

[0284] Next, a silicon oxide film was formed on the thermal oxide film.

[0285] The silicon oxide film was formed by sputtering. Specifically, using a silicon oxide target in an atmosphere containing 50 sccm of oxygen, the pressure was controlled to 0.4 Pa, and the film formation Assuming a substrate heating temperature of 100°C and a deposition power of 2kW (13.56MHz), the film thickness is 300nm. The film was deposited to this thickness. This sample will be designated as Sample A.

[0286] Next, an aluminum oxide film was deposited on the silicon oxide film.

[0287] The aluminum oxide film was deposited by sputtering. Specifically, aluminum oxide Using a target, in an atmosphere containing 25 sccm of argon and 25 sccm of oxygen... The pressure is controlled to 0.4 Pa, the substrate heating temperature during film deposition is 250°C, and the deposition power is 2.5 A film was deposited at a thickness of 10 nm using kW (13.56 MHz). The sample up to this point is referred to as Sample B. do.

[0288] Samples A and B were prepared as described above. Next, the gas desorption from each sample was evaluated. It was worth it.

[0289] Figure 19 shows the ionic strength of the gas with an M / z of 32 as determined by TDS analysis. Here, Figure 19(A ) is determined by TDS analysis of sample A, which does not have an aluminum oxide film on the silicon oxide film. This is the ionic strength of a gas with M / z 32. Also, Figure 19(B) shows an acid on a silicon oxide film. TDS analysis of sample B, which has an aluminum oxide film, showed that the ionic intensity of the gas with an M / z of 32 was... be.

[0290] As shown in Figure 19(A), TDS analysis of sample A revealed that the substrate temperature was between 200°C and 400°C. The desorption of a gas with an M / z of 32 was confirmed. The amount released, when converted to oxygen atoms, was 5.0 ×10 20 atoms / cm 3 That was the case.

[0291] On the other hand, as shown in Figure 19(B), TDS analysis of sample B revealed that the substrate temperature was 200°C or higher and 400°C. At temperatures below ℃, almost no desorption of gases with an M / z of 32 was observed.

[0292] A comparison of sample A and sample B shows that oxidation occurs on the silicon oxide film that releases oxygen upon heat treatment. By adding a 10 nm aluminum film, the outward diffusion of oxygen released from the silicon oxide film is facilitated. It was found that this can be prevented.

[0293] This example shows that aluminum oxide films have low oxygen permeability. [Examples]

[0294] In this example, TDS was used to create yttria-stabilized zirconia (also known as YSZ). This section explains the oxygen permeability of a membrane made of conium with yttrium oxide added.

[0295] Gas emission was evaluated using the EMD-WA1000S / W thermostatic desorption analyzer manufactured by Denshi Kagaku Co., Ltd. I used it.

[0296] The method for preparing the sample is shown below.

[0297] First, a silicon wafer was prepared, and a silicon oxide film was deposited on the silicon wafer.

[0298] The silicon oxide film was deposited by sputtering. Specifically, silicon oxide target Using a tweezers, in an atmosphere containing 25 sccm of argon and 25 sccm of oxygen, pressure The force is controlled to 0.4 Pa, the substrate heating temperature during film deposition is 100°C, and the film deposition power is 1.5 kW (1 The film was deposited at a thickness of 300 nm (at 3.56 MHz).

[0299] Next, a YSZ film was deposited on the silicon oxide film.

[0300] The YSZ film was deposited by sputtering. Specifically, the YSZ target (dioxide) Using yttrium oxide (molar ratio: 92:8), add 20 sc of argon. In an atmosphere containing 20 sccm of 1 / 2 cm and oxygen, the pressure was controlled to 0.4 Pa during film formation. The substrate heating temperature is room temperature, and the deposition power is 250W (13.56MHz), resulting in a thickness of 10nm. The film was deposited using [a specific method].

[0301] The sample was prepared as described above. Next, the desorption of gas from the sample was evaluated.

[0302] Figure 20 shows the ionic strength of the gas with an M / z of 32, as determined by TDS analysis.

[0303] As shown in Figure 20, TDS analysis of the sample revealed that the substrate temperature was between 200°C and 400°C and the M / z ratio was However, almost no desorption of gas 32 was observed.

[0304] Therefore, by providing a 10 nm YSZ film on the silicon oxide film, the emissions from the silicon oxide film can be released. It was found that this can prevent the outward diffusion of oxygen.

[0305] This example shows that the YSZ membrane has low oxygen permeability. [Explanation of Symbols]

[0306] 100 circuit boards 102 Underlying insulating film 104 Guard gate 104a First layer 104b Second layer 104c Third layer 105 Guard Station 105a First layer 105b Second layer 106 Oxide semiconductor film 112 Gate Insulator 114a Conductive film 114b Conductive film 116 Pair of electrodes 118 Protective insulating film 124a Conductive film 124b Conductive film 136 Oxide semiconductor film 204 Shuttle gate 204a Layer 1 204b Second layer 204c Third Layer 205 Terminal 205a First layer 205b Second layer 206 oxide semiconductor film 212 Gate Insulator 214a Conductive film 214b Conductive film 216 pairs of electrodes 224a Conductive film 224b Conductive film 224c conductive film 236 Oxide semiconductor film 304 gate 304a Layer 1 304b Second layer 304c Third Layer 306 oxide semiconductor film 306a First area 306b Second area 310 Sidewall insulating film 312 Gate Insulator 313 Gate insulating film 314a Conductive film 314b Conductive film 316 pairs of electrodes 318 Protective insulating film 324a Conductive film 324b Conductive film 324c conductive film 334a Conductive film 334b Conductive film 404 Gate 404a Layer 1 404b Second layer 404c Third Layer 406 oxide semiconductor film 406a First area 406b Second area 410 Sidewall insulating film 412 Gate Insulator 416 pairs of electrodes 418 Protective insulating film 420 Insulating film 466 Pairs of Wiring 1141 Switching element 1142 memory element 1143 Memory element group 1189 ROM Interface 1190 circuit board 1191 ALU 1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Register 1197 Register Controller 1198 Bus Interface 1199 ROM 2200 pixels 2210 Liquid crystal element 2220 Capacitor 2230 Transistors 9300 cabinet 9301 button 9302 Microphone 9303 Display section 9304 Speaker 9305 Camera 9310 enclosure 9311 Display section 9320 enclosure 9321 button 9322 Microphone 9323 Display section 9630 cabinet 9631a Display section 9631b Display section 9633 Fastener 9638 Operation switch

Claims

1. Oxide semiconductor film and The gate insulating film on the oxide semiconductor film, The gate electrode on the gate insulating film, The oxide semiconductor film has oxygen supplied from the conductive film that forms the gate electrode, via the first insulating film that forms the gate insulating film. The gate electrode comprises a first layer and a second layer on the first layer. A semiconductor device wherein the first layer has a region with a lower oxygen concentration than the second layer.

2. Oxide semiconductor film and The gate insulating film on the oxide semiconductor film, The gate electrode on the gate insulating film, It has a second insulating film provided so as to cover the side surface of the gate electrode and the side surface of the gate insulating film, The oxide semiconductor film has oxygen supplied from the conductive film that forms the gate electrode, via the first insulating film that forms the gate insulating film. The second insulating film is less permeable to oxygen than the first insulating film. The gate electrode comprises a first layer and a second layer on the first layer. A semiconductor device wherein the first layer has a region with a lower oxygen concentration than the second layer.

3. In claim 2, A semiconductor device wherein the oxygen permeability of the second insulating film is lower than that of the first insulating film.

4. In claim 2 or claim 3, A semiconductor device wherein the diffusion coefficient of oxygen in the second insulating film is lower than the diffusion coefficient of oxygen in the first insulating film.

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