Semiconductor packages

Abstract

To provide a semiconductor package improved in reliability and electric characteristics.SOLUTION: A semiconductor package 10 includes a redistribution substrate 100, and a semiconductor chip 200 on a top surface of the redistribution substrate 100. The redistribution substrate 100 includes insulating layers 101-105, and a first redistribution pattern 110, a second redistribution pattern 120 and a third redistribution pattern 130 disposed in the insulating layers. The first to third redistribution patterns are stacked in a direction from a bottom surface of the redistribution substrate 100 toward the top surface, and are electrically connected to each other. Each of the first to third redistribution patterns includes a via portion. The second redistribution pattern 120 further includes first fine wire patterns 120W' that are narrower than a wire portion of the second redistribution pattern. The via portion 110V of the first redistribution pattern 110 has the smallest width at a top surface thereof, and the via portion 130V of the third redistribution pattern 130 has the smallest width at a bottom surface thereof.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor package, and more specifically to a semiconductor package including a redistribution substrate.

Background Art

[0002] A semiconductor package is a form in which an integrated circuit chip is embodied in a suitable form for use in an electronic product. Usually, a semiconductor chip is mounted on a printed circuit board, and these are generally electrically connected using bonding wires or bumps. With the development of the electronics industry, various studies for improving the reliability of semiconductor packages are underway.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The problem to be solved by the present invention is to provide a semiconductor package with improved reliability and electrical characteristics.

Means for Solving the Problems

[0005] According to the concept of the present invention, a semiconductor package includes a redistribution substrate and a semiconductor chip disposed on the upper surface of the redistribution substrate, wherein the redistribution substrate includes an insulating layer and a first redistribution pattern, a second redistribution pattern, and a third redistribution pattern provided within the insulating layer, the first to third redistribution patterns being electrically connected to each other while being provided sequentially in a direction from the lower surface to the upper surface of the redistribution substrate, each of the first to third redistribution patterns including a wiring portion extending in a direction aligned with the upper surface of the redistribution substrate, each of the first and third redistribution patterns including a via portion extending from the wiring portion in a direction perpendicular to the upper surface of the redistribution substrate, the second redistribution pattern further including a first fine wiring pattern having a width smaller than the width of the wiring portion of the second redistribution pattern, the spacing between adjacent first fine wiring patterns being 0.5 μm to 2 μm, the via portion of the first redistribution pattern having its minimum width on its upper surface, and the via portion of the third redistribution pattern having its minimum width on its bottom surface.

[0006] According to another concept of the present invention, a semiconductor package includes a redistribution substrate, a semiconductor chip disposed on the upper surface of the redistribution substrate, the semiconductor chip including chip pads electrically connected to the redistribution substrate, and conductive terminals disposed on the lower surface of the redistribution substrate, the redistribution substrate including an insulating layer and a first redistribution pattern, a second redistribution pattern, and a third redistribution pattern sequentially provided along the direction from the lower surface to the upper surface of the redistribution substrate and electrically connected to each other, each of the first to third redistribution patterns being arranged on the upper surface of the redistribution substrate The first and third rewiring patterns include a wiring portion that extends in the direction, and each of the first and third rewiring patterns includes a via portion that extends from the wiring portion in a direction perpendicular to the upper surface of the rewiring substrate, the second rewiring pattern further includes a first fine wiring pattern having a width smaller than the width of the wiring portion of the second rewiring pattern, the width of the via portion of the first rewiring pattern gradually decreases as you move from the lower surface to the upper surface of the rewiring substrate, and the width of the via portion of the third rewiring pattern gradually increases as you move from the lower surface to the upper surface of the rewiring substrate.

[0007] According to another concept of the present invention, a semiconductor package includes a redistribution substrate and a semiconductor chip disposed on the upper surface of the redistribution substrate, wherein the semiconductor chip includes a chip pad electrically connected to the redistribution substrate, a molding film covering the semiconductor chip, bonding terminals interposed between the redistribution substrate and the chip pads, and conductive terminals disposed on the lower surface of the redistribution substrate, wherein the redistribution substrate includes an underbump pattern, an insulating layer provided on the underbump pattern, a first redistribution pattern provided on the underbump pattern and in contact with the underbump pattern, a second redistribution pattern provided on the first redistribution pattern and in contact with the first redistribution pattern, a third redistribution pattern provided on the second redistribution pattern and in contact with the second redistribution pattern, a fourth redistribution pattern provided on the third redistribution pattern and in contact with the third redistribution pattern, and the fourth redistribution pattern A bonding pad provided and in contact with the fourth redistribution pattern is provided, wherein the first to fourth redistribution patterns are provided within the insulating layer, each of the first to fourth redistribution patterns includes a wiring portion extending in a direction aligned with the upper surface of the redistribution substrate, each of the first, third, and fourth redistribution patterns includes a via portion extending from the wiring portion in a direction perpendicular to the upper surface of the redistribution substrate, the second redistribution pattern further includes a first fine wiring pattern having a width smaller than the width of the wiring portion of the second redistribution pattern, the fourth redistribution pattern further includes a second fine wiring pattern having a width smaller than the width of the wiring portion of the fourth redistribution pattern, the spacing between adjacent first fine wiring patterns is 0.5 μm to 2 μm, the via portion of the first redistribution pattern may have its minimum width at its upper surface, and the via portion of the third redistribution pattern may have its minimum width at its bottom surface. [Effects of the Invention]

[0008] According to the present invention, a second redistribution pattern including a fine wiring pattern can be formed before the underbump pattern. Therefore, the undulation phenomenon of the fine wiring pattern, which may occur due to the shrinkage of the insulating layer between the underbump patterns during the manufacturing process, can be mitigated, and a more uniform line width can be ensured. As a result, the reliability of the semiconductor package can be improved.

[0009] According to the present invention, the underbump pattern can be formed to be relatively thick. As a result, the electrical characteristics of the semiconductor package can be improved. [Brief explanation of the drawing]

[0010] [Figure 1] This is a cross-sectional view showing a semiconductor package according to an embodiment of the present invention. [Figure 2] This is a magnified view of area A in Figure 1. [Figure 3A] This is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 3B] This is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 3C] This is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 3D] This is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 3E] This is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 3F] This is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 3G] This is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 3H] This is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 4]It is a cross-sectional view showing a semiconductor package according to an embodiment of the present invention. [Figure 5] It is a cross-sectional view showing a semiconductor package according to an embodiment of the present invention. [Figure 6] It is a cross-sectional view showing a semiconductor package according to an embodiment of the present invention. [Figure 7] It is a cross-sectional view showing a semiconductor package according to an embodiment of the present invention. [Figure 8] It is a cross-sectional view showing a semiconductor package according to an embodiment of the present invention. [Figure 9] It is a drawing showing an enlarged view of the B region in FIG. 8.

Mode for Carrying Out the Invention

[0011] FIG. 1 is a cross-sectional view showing a semiconductor package according to an embodiment of the present invention. FIG. 2 shows an enlarged view of the A region in FIG. 1.

[0012] Referring to FIGS. 1 and 2, the semiconductor package 10 can include a redistribution substrate 100 and a semiconductor chip 200. The redistribution substrate 100 can include insulating layers 101, 102, 103, 104, 105, a first redistribution pattern 110, a second redistribution pattern 120, a third redistribution pattern 130, a fourth redistribution pattern 140, bonding pads 150, and an under bump pattern 160. The redistribution substrate 100 can include an upper surface 100a and a lower surface 100b facing the upper surface 100a. The insulating layers can include first to fifth insulating layers 101, 102, 103, 104, 105 sequentially laminated in a direction from the lower surface 100b to the upper surface 100a of the redistribution substrate 100. In other words, the first to fifth insulating layers 101, 102, 103, 104, 105 can be sequentially laminated in a direction perpendicular to the upper surface 100a of the redistribution substrate 100. The redistribution substrate 100 can be referred to as a wiring structure. The upper surface 100a of the redistribution substrate 100 can be the upper surface of the fifth insulating layer 105. The lower surface 100b of the redistribution substrate 100 can be the lower surface of the first insulating layer 101.

[0013] The under bump pattern 160 can be provided on the lower surface 100b of the redistribution substrate 100. The under bump pattern 160 can function as a pad for the conductive terminal 400 described later. The under bump pattern 160 can contain a metallic substance such as copper. As an example, the interval D10 between two adjacent under bump patterns 160 can be 20 μm (micrometers) to 70 μm. The under bump pattern 160 can have a relatively thick thickness T1 as illustrated in FIG. 2. As an example, the thickness T1 of the under bump pattern 160 can be 10 μm to 20 μm.

[0014] According to an embodiment of the present invention, since the second redistribution pattern 120 is formed first in the manufacturing process of the semiconductor package described later, the undulation phenomenon of the first fine wiring pattern 120W’ can be alleviated. Therefore, it is not necessary to reduce the thickness of the under bump pattern 160 in order to alleviate the undulation phenomenon. As a result, the thickness of the under bump pattern 160 can be formed thick, so that the electrical characteristics of the semiconductor package can be improved.

[0015] The under bump pattern 160 can include a via portion 160V that penetrates the first insulating layer 101 and contacts the first redistribution pattern 110 and a main body portion 160B provided under the via portion 160V. The lower surface of the main body portion 160B of the under bump pattern 160 may not be covered by the first insulating layer 101. The side wall 160c of the main body portion 160B of the under bump pattern 160 may not be covered by the first insulating layer 101. In other words, the side wall 160c of the main body portion 160B of the under bump pattern 160 can be separated from the lower surface 100b of the redistribution substrate 100. As another example, a part of the side wall 160c of the main body portion 160B of the under bump pattern 160 can contact the first insulating layer 101. The via portion 160V of the under bump pattern 160 can be a portion extending in a direction perpendicular to the upper surface 100a of the redistribution substrate 100 from the main body portion 160B.

[0016] The first insulating layer 101 can be provided on the underbump pattern 160. The first insulating layer 101 can cover the sidewalls of the via portions 160V of the underbump pattern 160. The first insulating layer 101 may be the bottom insulating layer. The underside of the via portions 160V of the underbump pattern 160 can be located at substantially the same level as the underside 100b of the redistribution substrate 100. The first insulating layer 101 may include an organic material, such as a photosensitive polymer. In this specification, the photosensitive polymer may include at least one of photosensitive polyimides, polybenzoxazoles, phenolic polymers, and benzhocyclobutene polymers. The first insulating layer 101 is a positive-type photosensitive polymer, but is not limited thereto.

[0017] A first rewiring pattern 110 can be provided on the underbump pattern 160. The first rewiring pattern 110 may include a first via portion 110V and a first wiring portion 110W. The first wiring portion 110W may be located within the first insulating layer 101. The first wiring portion 110W may be located between the underbump pattern 160 and the first via portion 110V. The first wiring portion 110W may be in contact with the upper surface of the via portion 160V of the underbump pattern 160. The upper surface of the first wiring portion 110W may be located at substantially the same level as the upper surface of the first insulating layer 101.

[0018] The first via portion 110V is provided on the first wiring portion 110W and can be connected to the first wiring portion 110W. The first via portion 110V may be a portion that extends from the first wiring portion 110W in a direction perpendicular to the upper surface 100a of the redistribution board 100. Specifically, the first via portion 110V may be a portion that extends from the first wiring portion 110W in a direction from the lower surface 100b of the redistribution board 100 toward the upper surface 100a. The first wiring portion 110W may have a greater width or a longer length than the first via portion 110V. The first via portion 110V may be provided on the upper surface of the first insulating layer 101. The first via portion 110V may be located within the second insulating layer 102.

[0019] The width of the first via portion 110V can be smaller than the width of the via portion 160V of the underbump pattern 160. The angle between the top surface and the side wall of the first via portion 110V can be a first angle θ1. The first angle θ1 can be an obtuse angle. For example, the first angle θ1 can be 95° to 135°. The angle θ6 between the top surface and the side wall of the via portion 160V of the underbump pattern 160 can be an obtuse angle. For example, the angle θ6 between the top surface and the side wall of the via portion 160V of the underbump pattern 160 can be 95° to 135°.

[0020] The maximum width of the first via portion 110V may be the first width W1. The minimum width of the first via portion 110V may be the second width W2. The first via portion 110V may have a tapered shape. The width of the first via portion 110V may gradually decrease as you move from the lower surface 100b of the redistribution board 100 toward the upper surface 100a. In other words, the width of the first via portion 110V on the upper surface is the second width W2, and the width of the first via portion 110V at its lowest point may be the first width W1. Here, the lowest point of the first via portion 110V may mean the interface between the first via portion 110V and the first wiring portion 110W. The lowest point of the first via portion 110V may be located at substantially the same level as the upper surface of the first insulating layer 101.

[0021] The first redistribution pattern 110 may include a first seed pattern 111 and a first conductive pattern 113. The first conductive pattern 113 may be placed on the upper surface of the first insulating layer 101 and within the first insulating layer 101. The first conductive pattern 113 may be in contact with the underbump pattern 160. The first conductive pattern 113 may include a metallic material such as copper. The first seed pattern 111 may be interposed between the first conductive pattern 113 and the second insulating layer 102, and between the first conductive pattern 113 and the second redistribution pattern 120. The first seed pattern 111 may not be in contact with the underbump pattern 160. The first seed pattern 111 may include a conductive material such as copper, titanium, and / or alloys thereof.

[0022] Each of the first via portion 110V and the first wiring portion 110W may include a first seed pattern 111 and a first conductive pattern 113. The first seed pattern 111 of the first via portion 110V can be directly connected to the first seed pattern 111 of the first wiring portion 110W without an interface. The first seed pattern 111 can be interposed between the top surface of the first via portion 110V and the second rewiring pattern 120, between the side wall of the first via portion 110V and the second insulating layer 102, and between the top surface of the first wiring portion 110W and the second insulating layer 102. The first seed pattern 111 does not have to extend onto the side wall and bottom surface of the first conductive pattern 113 of the first wiring portion 110W. The first conductive pattern 113 of the first via portion 110V can be directly connected to the first conductive pattern 113 of the first wiring portion 110W.

[0023] The second insulating layer 102 is positioned on the first insulating layer 101 to cover the upper surface of the first insulating layer 101 and the side walls of the first via portion 110V. The second insulating layer 102 may include, for example, a photosensitive polymer. The interface between the first insulating layer 101 and the second insulating layer 102 is not defined, but is not limited thereto.

[0024] The second rewiring pattern 120 can be positioned on the first rewiring pattern 110 and electrically connected to the first rewiring pattern 110. The second rewiring pattern 120 may include a second wiring portion 120W and a first fine wiring pattern 120W'. The second wiring portion 120W and the first fine wiring pattern 120W' may be provided within the second insulating layer 102.

[0025] The second wiring portion 120W can contact the first via portion 110V of the first rewiring pattern 110. Specifically, the bottom surface of the second wiring portion 120W can contact the top surface of the first via portion 110V. The top surface of the second wiring portion 120W can be located at substantially the same level as the top surface of the second insulating layer 102. The angle between the bottom surface and the side wall of the second wiring portion 120W can be a second angle θ2. The second angle θ2 can be smaller than the first angle θ1. As an example, the second angle θ2 can be 85° to 95°.

[0026] The first fine wiring pattern 120W' may not be in contact with the first rewiring pattern 110. The first fine wiring pattern 120W' can be positioned between adjacent second wiring portions 120W. The angle between each top surface and side wall of the first fine wiring pattern 120W', and the angle between the bottom surface and side wall, can be 85° to 95°. The width of the first fine wiring pattern 120W' can be smaller than the width of the second wiring portion 120W. For example, the width W12 of each first fine wiring pattern 120W' can be 0.5 μm to 2 μm. The spacing D11 between adjacent first fine wiring patterns 120W' can be 0.5 μm to 2 μm.

[0027] According to an embodiment of the present invention, the bending phenomenon of the first fine wiring pattern 120W' can be mitigated by first forming the second rewiring pattern 120 which includes the first fine wiring pattern 120W'. As a result, the reliability of the semiconductor package can be improved. A detailed explanation of this will be given later.

[0028] The second rewiring pattern 120 may include a second seed pattern 121 and a second conductive pattern 123. For example, each of the second wiring portion 120W and the first fine wiring pattern 120W' may include a second seed pattern 121 and a second conductive pattern 123. The second seed pattern 121 may be interposed between the second conductive pattern 123 and the third insulating layer 103. The second seed pattern 121 may be positioned on the upper surface of the second conductive pattern 123. The second conductive pattern 123 may be in contact with the first rewiring pattern 110. The second seed pattern 121 may not be in contact with the first rewiring pattern 110. The second seed pattern 121 does not have to extend onto the side walls and bottom surface of the second conductive pattern 123. The second seed pattern 121 may include the material described as an example of the first seed pattern 111. The second conductive pattern 123 may include the material described as an example of the first conductive pattern 113.

[0029] The third insulating layer 103 can be placed on the second insulating layer 102. The third insulating layer 103 can cover the upper surface of the second redistribution pattern 120. The third insulating layer 103 can be in contact with at least a portion of the second seed pattern 121. The third insulating layer 103 may include, for example, a photosensitive polymer. The third insulating layer 103 may contain the same material as the second insulating layer 102. The interface between the third insulating layer 103 and the second insulating layer 102 is not defined, but is not limited thereto. The thickness of the third insulating layer 103 can be thinner than the thickness of the second insulating layer 102.

[0030] The third rewiring pattern 130 can be positioned on the second rewiring pattern 120 and electrically connected to the second rewiring pattern 120. The third rewiring pattern 130 may include a third wiring portion 130W and a second via portion 130V.

[0031] The second via portion 130V can be provided within the third insulating layer 103. The second via portion 130V can be interposed between the second rewiring pattern 120 and the third wiring portion 130W. The angle between the bottom and side walls of the second via portion 130V may be a third angle θ3. The third angle θ3 can be substantially the same as the first angle θ1. As an example, the third angle θ3 may be 95° to 135°.

[0032] The second via portion 130V may be a portion that extends from the third wiring portion 130W in a direction perpendicular to the upper surface 100a of the rewiring board 100. Specifically, the second via portion 130V may be a portion that extends from the third wiring portion 130W in a direction toward the lower surface 100b of the rewiring board 100. The third wiring portion 130W may have a greater width or a longer length than the second via portion 130V. The bottom surface of the second via portion 130V may be in contact with the upper surface of the second wiring portion 120W.

[0033] The minimum width of the second via portion 130V may be the third width W3. The minimum width of the second via portion 130V may be the fourth width W4. The second via portion 130V may have a tapered shape. The width of the second via portion 130V may gradually increase from the lower surface 100b of the redistribution board 100 toward the upper surface 100a. In other words, the width of the bottom surface of the second via portion 130V may be the third width W3, and the width of the uppermost part of the second via portion 130V may be the fourth width W4. Here, the uppermost part of the first via portion 110V may mean the interface between the second via portion 130V and the third wiring portion 130W. The uppermost part of the second via portion 130V may be located at substantially the same level as the upper surface of the third insulating layer 103.

[0034] The third width W3 can be substantially identical to the second width W2. The fourth width W4 can be substantially identical to the first width W1. For example, the ratio of the second width W2 to the third width W3 may be 0.8 to 1.2, and the ratio of the first width W1 to the fourth width W4 may be 0.8 to 1.2.

[0035] The third wiring portion 130W can be positioned on the second via portion 130V and on the upper surface of the third insulating layer 103. The third wiring portion 130W can be provided within the fourth insulating layer 104. The third wiring portion 130W can be electrically connected to the second via portion 130V. The bottom surface of the third wiring portion 130W can be positioned at substantially the same level as the upper surface of the third insulating layer 103.

[0036] The third redistribution pattern 130 may include a third seed pattern 131 and a third conductive pattern 133. The third conductive pattern 133 may be placed on the upper surface of the third insulating layer 103 and within the third insulating layer 103. The third seed pattern 131 may be interposed between the second redistribution pattern 120 and the third conductive pattern 133 and between the third conductive pattern 133 and the third insulating layer 103. The third seed pattern 131 may be in contact with the second redistribution pattern 120. Specifically, the third seed pattern 131 may be in contact with the second seed pattern 121 of the second redistribution pattern 120.

[0037] Each of the second via portion 130V and the third wiring portion 130W may include a third seed pattern 131 and a third conductive pattern 133. The third seed pattern 131 is provided on the bottom surface of the third conductive pattern 133 of the second via portion 130V and may be interposed between the sidewall of the third conductive pattern 133 of the second via portion 130V and the third insulating layer 103, and between the bottom surface of the third conductive pattern 133 of the third wiring portion 130W and the third insulating layer 103. The third seed pattern 131 may not extend onto the sidewall and top surface of the third conductive pattern 133 of the third wiring portion 130W. The third seed pattern 131 may include the material described as an example of the first seed pattern 111. The third conductive pattern 133 may include the material described as an example of the first conductive pattern 113.

[0038] A fourth insulating layer 104 can be placed on the third insulating layer 103. The fourth insulating layer 104 can cover the top surface and side walls of the third wiring portion 130W of the third rewiring pattern 130. The fourth insulating layer 104 may include, for example, a photosensitive polymer. The fourth insulating layer 104 may contain the same material as the third insulating layer 103. The interface between the fourth insulating layer 104 and the third insulating layer 103 is not defined, but is not limited to it. The thickness of the fourth insulating layer 104 is greater than the thickness of the third insulating layer 103. A fourth rewiring pattern 140 can be placed on the third rewiring pattern 130 and electrically connected to the third rewiring pattern 130. The fourth rewiring pattern 140 may include a fourth wiring portion 140W and a third via portion 140V.

[0039] The third via portion 140V can be provided within the fourth insulating layer 104. The third via portion 140V can be interposed between the third rewiring pattern 130 and the fourth wiring portion 140W. The angle between the bottom and sidewalls of the third via portion 140V may be the fourth angle θ4. The fourth angle θ4 can be substantially the same as the first angle θ1. As an example, the fourth angle θ4 may be 95° to 135°.

[0040] The third via portion 140V may be a portion that extends from the fourth wiring portion 140W in a direction perpendicular to the upper surface 100a of the rewiring board 100. Specifically, the third via portion 140V may be a portion that extends from the fourth wiring portion 140W in a direction toward the lower surface 100b of the rewiring board 100. The fourth wiring portion 140W may have a greater width or a longer length than the third via portion 140V.

[0041] The minimum width of the third via portion 140V may be the fifth width W5. The maximum width of the third via portion 140V may be the sixth width W6. The third via portion 110V may have a tapered shape. The width of the third via portion 140V can gradually increase from the bottom surface 100b to the top surface 100a of the redistribution board 100. In other words, the width at the bottom surface of the third via portion 140V may be the fifth width W5, and the width at the top of the third via portion 140V may be the sixth width W6. Here, the top of the third via portion 140V may mean the interface between the third via portion 140V and the fourth wiring portion 140W. The top of the third via portion 140V may be located at substantially the same level as the top surface of the fourth insulating layer 104. The sixth width W6 may be substantially the same as the fourth width W4. The fifth width W5 may be substantially the same as the third width W3.

[0042] The fourth wiring portion 140W can be positioned on the third via portion 140V and on the upper surface of the fourth insulating layer 104. The fourth wiring portion 140W can be provided within the fifth insulating layer 105. The fourth wiring portion 140W can be electrically connected to the third via portion 140V. The bottom surface of the fourth wiring portion 140W can be positioned at substantially the same level as the upper surface of the fourth insulating layer 104.

[0043] The fourth redistribution pattern 140 may include a fourth seed pattern 141 and a fourth conductive pattern 143. The fourth conductive pattern 143 may be placed on the upper surface of the fourth insulating layer 104 and within the fourth insulating layer 104. The fourth seed pattern 141 may be interposed between the third redistribution pattern 130 and the fourth conductive pattern 143 and between the fourth conductive pattern 143 and the fourth insulating layer 104. The fourth seed pattern 141 may be in contact with the third redistribution pattern 130. Specifically, the fourth seed pattern 141 may be in contact with the third conductive pattern 133 of the third redistribution pattern 130.

[0044] Each of the third via section 140V and the fourth wiring section 140W may include a fourth seed pattern 141 and a fourth conductive pattern 143. The fourth seed pattern 141 is provided on the bottom surface of the fourth conductive pattern 143 of the third via section 140V and may be interposed between the sidewall of the fourth conductive pattern 143 of the third via section 140V and the fourth insulating layer 104, and between the bottom surface of the fourth conductive pattern 143 of the fourth wiring section 140W and the fourth insulating layer 104. The fourth seed pattern 141 may not extend onto the sidewall and top surface of the fourth conductive pattern 143 of the fourth wiring section 140W. The fourth seed pattern 141 may include the material described as an example of the first seed pattern 111. The fourth conductive pattern 143 may include the material described as an example of the first conductive pattern 113.

[0045] The fourth rewiring pattern 140 may further include a second fine wiring pattern 140W'. The second fine wiring pattern 140W' may be placed within the fifth insulating layer 105. The second fine wiring pattern 140W' may not be in contact with the third rewiring pattern 130. The second fine wiring pattern 140W' may be placed between adjacent fourth wiring portions 140W. The angle between the top surface and side wall of each second fine wiring pattern 140W', and the angle between the bottom surface and side wall, may be 85° to 95°. The width of the second fine wiring pattern 140W' may be smaller than the width of the fourth wiring portion 120W. As an example, the width W13 of each second fine wiring pattern 140W' may be 0.5 μm to 2 μm. The spacing between adjacent second fine wiring patterns 140W' may be 0.5 μm to 2 μm. Each of the second fine wiring patterns 140W' may include a fourth seed pattern 141 and a fourth conductive pattern 143. The fourth conductive pattern 143 can be provided on the upper surface of the fourth seed pattern 141.

[0046] The fifth insulating layer 105 is positioned on the fourth insulating layer 104 to cover the upper surface of the fourth insulating layer 104 and the upper surface and side walls of the fourth wiring portion 140W. The fifth insulating layer 105 may include, for example, a photosensitive polymer. The fifth insulating layer 105 may contain the same material as the fourth insulating layer 104. The interface between the fifth insulating layer 105 and the fourth insulating layer 104 is not defined, but is not limited thereto.

[0047] The number of laminated insulating layers 101, 102, 103, 104, and 105, and the number of rewiring patterns 110, 120, 130, and 140 are not limited to those shown in the illustration and can be varied in many ways.

[0048] A bonding pad 150 can be placed on the upper surface of the fourth redistribution pattern 140. The bonding pad 150 can be electrically connected to the fourth redistribution pattern 140. The bonding pad 150 may contain a conductive material. For example, the bonding pad 150 may contain a metal such as copper, titanium, aluminum, tungsten, and / or alloys thereof.

[0049] The bonding pad 150 may include a via portion 150V that penetrates the fifth insulating layer 105 and contacts the fourth redistribution pattern 140, and a body portion 150B provided on the via portion 150V. The side walls of the body portion 150B of the bonding pad 150 may not be covered by the fifth insulating layer 105. The bottom surface of the body portion 150B of the bonding pad 150 may be located at substantially the same level as the top surface of the fifth insulating layer 105.

[0050] The minimum width of the via portion 150V of the bonding pad 150 may be the seventh width W7. The maximum width of the via portion 150V of the bonding pad 150 may be the eighth width W8. The via portion 150V of the bonding pad 150 may have a tapered shape. The width of the via portion 150V of the bonding pad 150 can gradually increase from the lower surface 100b of the redistribution board 100 toward the upper surface 100a. In other words, the width of the via portion 150V of the bonding pad 150 at the bottom surface is the seventh width W7, and the width of the via portion 150V of the bonding pad 150 at the top surface is the eighth width W8. Here, the top surface of the via portion 150V of the bonding pad 150 may mean the interface between the via portion 150V of the bonding pad 150 and the main body portion 150B. The uppermost via portion 150V of the bonding pad 150 can be positioned at substantially the same level as the upper surface of the fifth insulating layer 105. The seventh width W7 can be substantially the same as the third width W3. The eighth width W8 can be substantially the same as the fourth width W4.

[0051] The angle between the bottom surface and the side wall of the via portion 150V of the bonding pad 150 may be a fifth angle θ5. The fifth angle θ5 can be substantially the same as the first angle θ1. For example, the fifth angle θ5 may be between 95° and 135°.

[0052] The minimum width of the via portion 160V of the underbump pattern 160 may be the 9th width W9. The maximum width of the via portion 160V of the underbump pattern 160 may be the 10th width W10. The via portion 160V of the underbump pattern 160 may have a tapered shape. The width of the via portion 160V of the underbump pattern 160 can gradually decrease as you move from the lower surface 100b of the redistribution board 100 toward the upper surface 100a. In other words, the width of the via portion 160V of the underbump pattern 160 on the upper surface is the 9th width W9, and the width of the via portion 160V of the underbump pattern 160 at its lowest point may be the 10th width W10. Here, the uppermost part of the via portion 160V of the underbump pattern 160 can mean the interface between the via portion 160V of the underbump pattern 160 and the main body portion 160B. The lowest part of via portion 160V of the underbump pattern 160 can be located at substantially the same level as the underside of the first insulating layer 101. The width of via portion 160V of the underbump pattern 160 can be greater than the width of the first via portion 110V. For example, the ninth width W9 can be greater than the second width W2, and the tenth width W10 can be greater than the first width W1.

[0053] A semiconductor chip 200 can be mounted on the upper surface 100a of the redistribution substrate 100. The semiconductor chip 200 may include a chip pad 205. The chip pad 205 may be exposed on the lower surface of the semiconductor chip 200. Although not shown, an integrated circuit may be placed inside the semiconductor chip 200.

[0054] A bonding terminal 250 is provided between the chip pad 205 and the bonding pad 150 of the semiconductor chip 200, enabling the chip pad 205 and the bonding pad 150 to be electrically connected. The bonding terminal 250 may include at least one of solder, pillars, and bumps. The bonding terminal 250 may include a conductive material such as solder. The solder material may include tin, bismuth, lead, silver, or alloys thereof. The semiconductor chip 200 can be electrically connected to the redistribution board 100 through the bonding terminal 250.

[0055] The semiconductor package 10 may further include a molding film 300. The molding film 300 can be placed on the redistribution substrate 100 to cover the semiconductor chip 200. The molding film 300 can cover the uppermost insulating layer among the insulating layers 101, 102, 103, 104, and 105. The uppermost insulating layer may be a fifth insulating layer 105. The molding film 300 can be extended into the gap between the semiconductor chip 200 and the redistribution substrate 100 to seal the bonding terminals 250. The molding film 300 may include an insulating polymer, such as an epoxy molding compound. As another example, although not shown, an underfill film may be provided in the gap region between the redistribution substrate 100 and the semiconductor chip 200.

[0056] The conductive terminal 400 can be positioned on the lower surface 100b of the redistribution board 100. The conductive terminal 400 can be positioned on the lower surface of the main body portion 160B of the underbump pattern 160 and electrically connected to the underbump pattern 160. The conductive terminal 400 can be in contact with the underbump pattern 160. Thus, the conductive terminal 400 can be electrically connected to the semiconductor chip 200 through the first to fourth redistribution patterns 110, 120, 130, 140 and the bonding terminal 250. The conductive terminal 400 may include solder, bumps, pillars, and / or combinations thereof. The conductive terminal 400 may include solder material. The conductive terminal 400 may be formed by a solder ball attachment process.

[0057] Figures 3A to 3H are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention.

[0058] Referring to Figure 3A, the first carrier substrate 900, the first release layer 910, and the etching stop layer 920 can be formed sequentially. The first seed layer 121P can be formed on the etching stop layer 920. The first seed layer 121P can conformally cover the upper surface of the etching stop layer 920. The first seed layer 121P can be formed by a vapor deposition process. The first seed layer 121P can contain a conductive material. For example, the first seed layer 121P can contain a conductive material such as copper, titanium, and / or alloys thereof.

[0059] A first resist pattern 191 can be formed on the first seed layer 121P. The first resist pattern 191 may contain a photoresist material. A first opening OP1 can be formed within the first resist pattern 191 to expose the upper surface of the first seed layer 121P. The angle between the bottom surface and the side wall of the first opening OP1 may be 85° to 95°.

[0060] The first conductive layer 123P can be formed within the first opening OP1 to cover the first seed layer 121P. The first conductive layer 123P can be formed by performing an electroplating process using the first seed layer 121P as an electrode. The first conductive layer 123P may not extend onto the upper surface of the first resist pattern 191. Therefore, a separate planarization process may not be required during the formation of the first conductive layer 123P. The first conductive layer 123P may contain a metal such as copper.

[0061] Referring to Figure 3B, the first resist pattern 191 can be removed, exposing a first portion of the first seed layer 121P. The exposed first portion of the first seed layer 121P can be removed by an etching process. In the etching process, the first conductive layer 123P may have etching selectivity with respect to the first seed layer 121P. A second portion of the first seed layer 121P is positioned on the underside of the first conductive layer 123P and is not removed by the etching process. After the etching process, the remaining second portion of the first seed layer 121P can form a second seed pattern 121, and the first conductive layer 123P can form a second conductive pattern 123. In this way, a second redistribution pattern 120 can be formed. The second redistribution pattern 120 may include the second seed pattern 121 and the second conductive pattern 123.

[0062] The second rewiring pattern 120 may include a second wiring portion 120W and a first fine wiring pattern 120W'. The width of the first fine wiring pattern 120W' may be smaller than the width of the second wiring portion 120W. The angle θ2 between the top surface and the side wall of the second rewiring pattern 120 may be between 85° and 95°.

[0063] When underbump patterns are formed first, fine wiring patterns can be formed on the insulating layer between the underbump patterns. In this case, the insulating layer between the underbump patterns may shrink during the curing process, potentially causing undulation of the fine wiring patterns. According to an embodiment of the present invention, by forming the second rewiring pattern 120, which includes the first fine wiring pattern 120W', first, the undulation of the first fine wiring pattern 120W' can be mitigated. As a result, the reliability of the semiconductor package can be improved.

[0064] Referring to Figure 3C, a second insulating layer 102 can be formed on the second rewiring pattern 120. The second insulating layer 102 can be formed by a coating process such as spin coating or slit coating. The second insulating layer 102 may include, for example, a photosensitive polymer. The second insulating layer 102 can cover the upper surface of the etching stop layer 920, the upper surface and sidewalls of the second wiring portion 120W, and the upper surface and sidewalls of the first fine wiring pattern 120W'.

[0065] The second insulating layer 102 can be patterned to form the first hole 119. The patterning of the second insulating layer 102 can be carried out by an exposure process and a development process. The first hole 119 can have a tapered shape. For example, the upper diameter of the first hole 119 can be larger than the lower diameter of the first hole 119. The first hole 119 can expose the upper surface of the second rewiring pattern 120. The angle between the bottom and side walls of the first hole 119 can be obtuse. As an example, the angle between the bottom and side walls of the first hole 119 can be 95° to 135°.

[0066] Referring to Figure 3D, a first redistribution pattern 110 can be formed on a second redistribution pattern 120. The first redistribution pattern 110 can be formed to fill a first hole 119. Forming the first redistribution pattern 110 can be carried out in the same manner as forming the second redistribution pattern 120. For example, forming the first redistribution pattern 110 may include forming a second seed layer on the upper surface of the second insulating layer 102 and along the first hole 119, forming a second resist pattern having a second opening on the second seed layer, forming a second conductive layer within the second opening, removing the second resist pattern to expose a portion of the second seed layer, and etching the exposed portion of the exposed second seed layer to form a first seed pattern 111. The etching step may cause the second conductive layer to constitute a first conductive pattern 113.

[0067] The first rewiring pattern 110 may include a first seed pattern 111 and a first conductive pattern 113. The first rewiring pattern 110 may include a first via portion 110V and a first wiring portion 110W. The first via portion 110V may be a portion formed within the first hole 119. The first wiring portion 110W may be formed on the first via portion 110V. The first wiring portion 110W may be formed on the upper surface of the second insulating layer 102. The angle θ1 between the bottom surface and the side wall of the first via portion 110V may be between 95° and 135°.

[0068] Referring to Figure 3E, a first insulating layer 101 can be formed on the first rewiring pattern 110. The first insulating layer 101 can be formed by a coating process. The first insulating layer 101 may include, for example, a photosensitive polymer. The first insulating layer 101 can cover the upper surface of the second insulating layer 102, the upper surface of the first wiring portion 110W, and the side walls.

[0069] The first insulating layer 101 can be patterned to form a second hole 118. The patterning of the first insulating layer 101 can be carried out by an exposure process and a development process. The second hole 118 can have a tapered shape. For example, the upper diameter of the second hole 118 can be larger than the lower diameter of the second hole 118. The second hole 118 can expose the upper surface of the first rewiring pattern 110. The angle between the bottom and side walls of the second hole 118 can be obtuse. As an example, the angle between the bottom and side walls of the second hole 118 can be 95° to 135°.

[0070] The underbump pattern 160 can be formed to fill the second hole 118. The underbump pattern 160 may include a via portion 160V formed within the second hole 118 and a body portion 160B formed on the via portion 160V. The angle θ6 between the bottom surface and the side wall of the via portion 160V of the underbump pattern 160 may be 95° to 135°. The top surface and side walls of the underbump pattern 160 may be exposed. The side walls of the underbump pattern 160 may not be in contact with the first insulating layer 101.

[0071] Conductive terminals 400 can be formed on the underbump pattern 160. Forming the conductive terminals 400 may include performing a solder ball attachment process.

[0072] Referring to Figure 3F, the semiconductor package can be inverted. The inverted semiconductor package can be mounted on the second carrier substrate 901. Specifically, a second release layer 911 is formed on the second carrier substrate 901, and the semiconductor package can be mounted on the second release layer 911. The upper surface of the second release layer 911 can be in contact with the lower surface of the first insulating layer 101. The main body portion 160B of the underbump pattern 160 and the conductive terminals 400 can be placed within the second release layer 911.

[0073] A third insulating layer 103 can be formed on the second rewiring pattern 120. The third insulating layer 102 can be formed by a coating process. The third insulating layer 103 may include, for example, a photosensitive polymer. The third insulating layer 103 can cover the upper surface of the second insulating layer 102 and the upper surface of the second rewiring pattern 120.

[0074] The third insulating layer 103 can be patterned to form the third hole 117. The patterning of the third insulating layer 103 can be carried out by an exposure process and a development process. The third hole 117 can have a tapered shape. For example, the upper diameter of the third hole 117 can be larger than the lower diameter of the third hole 117. The third hole 117 can expose the upper surface of the second rewiring pattern 120. The angle between the bottom and side walls of the third hole 117 can be obtuse. As an example, the angle between the bottom and side walls of the third hole 117 can be 95° to 135°.

[0075] A third redistribution pattern 130 can be formed on the second redistribution pattern 120. The third redistribution pattern 130 can be formed to fill the third hole 117. Forming the third redistribution pattern 130 can be carried out in the same manner as forming the second redistribution pattern 120. For example, forming the third redistribution pattern 130 may include forming a third seed layer on the upper surface of the third insulating layer 103 and along the third hole 117, forming a third resist pattern having a third opening on the third seed layer, forming a third conductive layer within the third opening, removing the third resist pattern to expose a portion of the third seed layer, and etching the exposed portion of the exposed third seed layer to form a third seed pattern 113. The etching step may cause the third conductive layer to constitute a third conductive pattern 133.

[0076] The third rewiring pattern 130 may include a third seed pattern 131 and a third conductive pattern 133. The third rewiring pattern 130 may include a second via portion 130V and a third wiring portion 130W. The second via portion 130V may be a portion formed within the third hole 117. The third wiring portion 130W may be formed on the second via portion 130V. The third wiring portion 130W may be formed on the upper surface of the third insulating layer 103. The angle θ3 between the bottom surface and the side wall of the second via portion 130V may be 95° to 135°.

[0077] Referring to Figure 3G, a fourth insulating layer 104 can be formed on the third rewiring pattern 130. The fourth insulating layer 104 can be formed by a coating process. The fourth insulating layer 104 may include, for example, a photosensitive polymer. The fourth insulating layer 104 can cover the upper surface of the third insulating layer 103 and the upper surface and side walls of the third wiring portion 130W.

[0078] The fourth insulating layer 104 can be patterned to form the fourth hole 116. The patterning of the fourth insulating layer 104 can be carried out by an exposure process and a development process. The fourth hole 116 can have a tapered shape. For example, the upper diameter of the fourth hole 116 can be larger than the lower diameter of the fourth hole 116. The fourth hole 116 can expose the upper surface of the third redistribution pattern 130. The angle between the bottom and side wall of the fourth hole 117 can be obtuse. As an example, the angle between the bottom and side wall of the fourth hole 117 can be 95° to 135°.

[0079] A fourth redistribution pattern 140 can be formed on the third redistribution pattern 130. The fourth redistribution pattern 140 can be formed to fill the fourth hole 116. Forming the fourth redistribution pattern 140 can be carried out in the same manner as forming the second redistribution pattern 120. For example, forming the fourth redistribution pattern 140 may include forming a fourth seed layer along the fourth insulating layer 104 and the fourth hole 116, forming a fourth resist pattern having a fourth opening on the fourth seed layer, forming a fourth conductive layer within the fourth opening, removing the fourth resist pattern to expose a portion of the fourth seed layer, and etching the exposed portion of the exposed fourth seed layer to form a fourth seed pattern 141. The etching step may cause the fourth conductive layer to constitute a fourth conductive pattern 143.

[0080] The fourth rewiring pattern 140 may include the fourth seed pattern 141 and the fourth conductive pattern 143. The fourth rewiring pattern 140 may include the third via portion 140V and the fourth wiring portion 140W. The third via portion 140V may be a portion formed within the fourth hole 116. The fourth wiring portion 140W may be formed on the third via portion 140V. The fourth wiring portion 140W may be formed on the upper surface of the fourth insulating layer 104. The angle θ4 between the bottom surface and the side wall of the third via portion 140V may be between 95° and 135°.

[0081] The fourth rewiring pattern 140 may further include a second fine wiring pattern 140W'. The width of the second fine wiring pattern 140W' can be smaller than the width of the fourth wiring portion 140W. The angle between the bottom and side walls of the second fine wiring pattern 140W' may be 85° to 95°.

[0082] Referring to Figure 3H, a fifth insulating layer 105 can be formed on the fourth rewiring pattern 140. The fifth insulating layer 105 can be formed by a coating process. The fifth insulating layer 105 may include, for example, a photosensitive polymer. The fifth insulating layer 105 can cover the upper surface of the fourth insulating layer 104 and the upper surface and side walls of the fourth wiring portion 140W.

[0083] The fifth insulating layer 105 can be patterned to form the fifth hole 115. Patterning of the fifth insulating layer 105 can be carried out by exposure and development processes. The fifth hole 115 can have a tapered shape. For example, the upper diameter of the fifth hole 115 can be larger than the lower diameter of the fifth hole 115. The fifth hole 115 can expose the upper surface of the fourth redistribution pattern 140. The angle between the bottom and sidewall of the fifth hole 115 can be obtuse. As an example, the angle between the bottom and sidewall of the fifth hole 115 can be 95° to 135°.

[0084] A bonding pad 150 can be formed on the fourth redistribution pattern 140. The bonding pad 150 can be formed to fill the fifth hole 115. The bonding pad 150 may include a via portion 150V formed within the fifth hole 115 and a body portion 150B formed on the via portion 150V. The angle θ5 between the bottom surface and the side wall of the via portion 150V of the bonding pad 150 may be 95° to 135°. The top surface and side wall of the body portion 150B of the bonding pad 150 can be exposed. By forming the bonding pad 150, the redistribution board 100 can finally be formed.

[0085] Referring again to Figure 1, the second carrier substrate 901 and the second release layer 911 can be removed. Thus, the lower surface 100b of the redistribution substrate 100 can be exposed. The semiconductor chip 200 can be placed on the redistribution substrate 100 such that the chip pads 205 of the semiconductor chip 200 face the redistribution substrate 100. Bonding terminals 250 can be formed between the bonding pad 150 and the chip pad 205.

[0086] A molding film 300 is formed on the redistribution substrate 100 to cover the semiconductor chip 200. The molding film 300 extends into the gap region between the semiconductor chip 200 and the redistribution substrate 100 to seal the bonding terminals 250. As another example, an underfill film can be formed in the gap region to seal the bonding terminals 250.

[0087] Figure 4 is a cross-sectional view showing a semiconductor package according to an embodiment of the present invention. The following information will be omitted if it is redundant with what has already been explained.

[0088] Referring to Figure 4, the underbump pattern 160 of the semiconductor package 10A can include multiple via portions 160V. For example, the underbump pattern 160 can include two via portions 160V. Adjacent via portions 160V can be separated from each other by a first insulating layer 101. The minimum width of each via portion 160V may be the ninth width W9, and the maximum width may be the tenth width W10. The width of each via portion 160V can be substantially the same as the width of the first via portion 110V. For example, referring to Figure 2, the ninth width W9 can be substantially the same as the second width W2, and the tenth width W10 can be substantially the same as the first width W1. As another example, the width of each via portion 160V can be smaller than the width of the first via portion 110V. In other words, the ninth width W9 can be smaller than the second width W2, and the tenth width W10 can be smaller than the first width W1. As another example, as explained with reference to Figures 1 and 2, the width of each via section 160V can be made larger than the width of the first via section 110V.

[0089] Figure 5 is a cross-sectional view showing a semiconductor package according to an embodiment of the present invention. The following information will be omitted if it is redundant with what has already been explained.

[0090] Referring to Figure 5, the first semiconductor chip 210A, the second semiconductor chip 220A, and the third semiconductor chip 230A can be mounted on the redistribution substrate 100 of the semiconductor package 10B. Each of the first to third semiconductor chips 210A, 220A, and 230A may be one of a logic chip, a memory chip, a buffer chip, or a system-on-a-chip (SOC).

[0091] The first semiconductor chip 210A may include a first chip pad 215A. The first chip pad 215A may be exposed on the underside of the first semiconductor chip 210A. The second semiconductor chip 220A may include a second chip pad 225A. The second chip pad 225A may be exposed on the underside of the second semiconductor chip 220A.

[0092] The bonding terminal 250 may include a first bonding terminal 251A and a second bonding terminal 252A. The first bonding terminal 251A can be interposed between the bonding pad 150 and the first tip pad 215A. The second bonding terminal 252A can be interposed between the bonding pad 150 and the second tip pad 225A.

[0093] The first semiconductor chip 210A and the second semiconductor chip 220A can be positioned at substantially the same level as each other. A third semiconductor chip 230A can be mounted on the first semiconductor chip 210A and the second semiconductor chip 220A. The first semiconductor chip 210A and the second semiconductor chip 220A can be superimposed perpendicularly on the third semiconductor chip 230A. A sixth insulating layer 106 and a seventh insulating layer 107 can be sequentially provided between the first semiconductor chip 210A and the third semiconductor chip 230A, and between the second semiconductor chip 220A and the third semiconductor chip 230A. Each of the sixth insulating layer 106 and the seventh insulating layer 107 may, as an example, include a photosensitive polymer.

[0094] A first upper connecting pad 216A and a second upper connecting pad 226A can be placed within the sixth insulating layer 106. The first upper connecting pad 216A can be placed on the first semiconductor chip 210A. The lower surface of the first upper connecting pad 216A can be in contact with the first semiconductor chip 210A. The second upper connecting pad 226A can be placed on the second semiconductor chip 220A. The lower surface of the second upper connecting pad 226A can be in contact with the second semiconductor chip 220A.

[0095] A lower connecting pad 217A can be placed within the seventh insulating layer 107. The lower connecting pad 217A can be placed on the lower surface of the third semiconductor chip 230A. The lower connecting pad 217A can be placed in positions corresponding to the first upper connecting pad 216A and the second upper connecting pad 226A. The first and second upper connecting pads 216A, 226A and the lower connecting pad 217A may contain conductive material.

[0096] The lower connecting pad 217A and the first upper connecting pad 216A can be directly bonded. The lower surface of the lower connecting pad 217A and the upper surface of the first upper connecting pad 216A can be in contact. The lower connecting pad 217A and the second upper connecting pad 226A can be directly bonded. The lower surface of the lower connecting pad 217A and the upper surface of the second upper connecting pad 216A can be in contact. As an example, the lower connecting pad 217A and the first upper connecting pad 216A, and the lower connecting pad 217A and the second upper connecting pad 226A can be hybrid bonded.

[0097] The molding film 300 is placed on the redistribution substrate 100 and can cover the sidewall of the first semiconductor chip 210A, the sidewall of the second semiconductor chip 220A, and the top surface and sidewall of the third semiconductor chip 230A. The molding film 300 can extend into the first gap region between the first semiconductor chip 210A and the redistribution substrate 100, and into the second gap region between the second semiconductor chip 220A and the redistribution substrate 100, thereby sealing the first and second bonding terminals 251A and 252A. The molding film 300 can also extend into the region between the first semiconductor chip 210A and the second semiconductor chip 220A.

[0098] Figure 6 is a cross-sectional view showing a semiconductor package according to an embodiment of the present invention. The following information will be omitted if it is redundant with what has already been described.

[0099] Referring to Figure 6, the semiconductor package 11 may include a package substrate 800, a redistribution substrate 100, conductive terminals 400, a first semiconductor chip 210, a chip stack 2000, and a molding film 300. The conductive terminals 400 and the molding film 300 may be substantially the same as those described with reference to Figure 1. The bonding terminals 250 may include a first bonding terminal 251 and a second bonding terminal 252.

[0100] The package substrate 800 may include a printed circuit board. The package substrate 800 may include an upper metal pad 810, a lower metal pad 820, and wiring 830. The wiring 830 may be provided within the package substrate 800. The upper metal pad 810 may be provided on the upper surface of the package substrate 800 and connected to the wiring 830. An external connection terminal 840 may be provided on the lower surface of the package substrate 800 and connected to the lower metal pad 820. The lower metal pad 820 may be connected to the wiring 830. External electrical signals may be transmitted through the external connection terminal 840. Solder balls may be used as the external connection terminal 840. The external connection terminal 840 may include a metallic material such as solder.

[0101] The redistribution board 100 can be placed on the package substrate 800. The redistribution board 100 can function as an interposer substrate. The conductive terminals 400 are aligned with the upper metal pads 810 of the package substrate 800 and can be connected to the upper metal pads 810. The redistribution board 100 can be electrically connected to the package substrate 800 through the conductive terminals 400. The redistribution board 100 can be substantially identical to those described in Figures 1 and 2.

[0102] A first underfill film 310 can be provided between the redistribution board 100 and the package board 800. The first underfill film 310 can seal the main body portion 160B of the underbump pattern 160 and the conductive terminals 400. The first underfill film 310 may contain an insulating polymer such as an epoxy polymer. In other examples, the first underfill film 310 may be omitted.

[0103] The first semiconductor chip 210 can be mounted on the upper surface of the redistribution substrate 100. For example, the first bonding terminal 251 can be provided between the chip pad 205 and the bonding pad 150 of the first semiconductor chip 210. The first semiconductor chip 210 can be substantially identical to the semiconductor chip 200 described with reference to Figure 1, and the arrangement, function, and material of the first bonding terminal 251 can be substantially identical to the bonding terminal 250 described with reference to Figure 1.

[0104] Multiple first bonding terminals 251 can be provided. The pitch P11 of the multiple first bonding terminals 251 can be smaller than the pitch P1 of the multiple conductive terminals 400. The pitch P11 of the multiple first bonding terminals 251 can be smaller than the pitch P2 of the external connection terminal 840.

[0105] A chip stack 2000 can be mounted on the upper surface of a redistribution board 100. The chip stack 2000 can be positioned laterally spaced from the first semiconductor chip 210. The chip stack 2000 may include a plurality of stacked second semiconductor chips 220. Each of the second semiconductor chips 220 may be identical or similar to the semiconductor chip 200 described with reference to Figure 1. However, the second semiconductor chips 220 may be of a different type from the first semiconductor chip 210. For example, the first semiconductor chip 210 may be one of a logic chip, a memory chip, a buffer chip, and a system-on-a-chip (SOC), and the second semiconductor chip 220 may be another of a logic chip, a memory chip, a buffer chip, and a system-on-a-chip (SOC). In this specification, a memory chip may include a high-bandwidth memory (HBM) chip. For example, the first semiconductor chip 210 may be a logic chip and the second semiconductor chip 220 may be a high-bandwidth memory (HBM) chip. As another example, the bottommost second semiconductor chip 220 could be a logic chip, while the remaining second semiconductor chips 220 could be high-bandwidth memory chips.

[0106] Each of the second semiconductor chips 220 may include a lower pad 225, a through-electrode 227, and an upper pad 226. The lower pad 225 and the upper pad 226 may be provided on the lower and upper surfaces, respectively, of each second semiconductor chip 220. At least one of the lower pad 225 and the upper pad 226 may be electrically connected to the integrated circuit of the second semiconductor chip 220. The through-electrode 227 is located within the second semiconductor chip 220 and can be connected to the lower pad 225 and the upper pad 226. The uppermost second semiconductor chip 220 includes the lower pad 225 but does not include the through-electrode 227 and the upper pad 226. Contrary to the illustration, the uppermost second semiconductor chip 220 may further include the through-electrode 227 and the upper pad 226. An interposer terminal 229 may be interposed between two adjacent second semiconductor chips 220 and connected to the lower pad 225 and the upper pad 226, respectively. Thus, multiple second semiconductor chips 220 can be electrically connected to one another. The interposer terminal 229 may include solder, pillars, or bumps. The interposer terminal 229 may, but is not limited to, include solder material. As another example, the interposer terminal 229 may be omitted. In this case, the opposing lower pads 225 and upper pads 226 of the adjacent second semiconductor chip 220 can be bonded directly to each other.

[0107] The second bonding terminal 252 is interposed between the bottom second semiconductor chip 220 and the redistribution board 100, and can be connected to the bottom pad 225 and the corresponding bonding pad 150. Thus, the second semiconductor chip 220 can be electrically connected to the first semiconductor chip 210 and the conductive terminal 400 through the redistribution board 100. The arrangement, function, and material of the second bonding terminal 252 can be substantially identical to that of the bonding terminal 250 described with reference to Figure 1. The pitch P12 of the multiple second bonding terminals 252 can be smaller than the pitch P1 of the conductive terminal 400 and the pitch P2 of the external connection terminal 840.

[0108] Multiple chip stacks 2000 can be provided. The chip stacks 2000 can be arranged laterally spaced apart from each other. The first semiconductor chip 210 can be placed between the chip stacks 2000. In this way, the length of the electrical path between the first semiconductor chip 210 and the chip stacks 2000 can be reduced.

[0109] A second underfill film 320 is provided in the first gap region between the redistribution substrate 100 and the first semiconductor chip 210 to seal the first bonding terminal 251. The second underfill film 320 may include an insulating polymer such as an epoxy polymer. A third underfill film 330 is provided in each of the second gap regions between the redistribution substrate 100 and the chip stack 2000 to seal the corresponding second bonding terminal 252. The third underfill film 330 may include an insulating polymer such as an epoxy polymer. Contrary to the illustration, a single underfill film may be provided between the first and second gap regions to seal the first bonding terminal 251 and the second bonding terminal 252. A fourth underfill film 340 is provided between the second semiconductor chip 220 to seal the interposer terminal 229. The fourth underfill film 340 may include an insulating polymer such as an epoxy polymer.

[0110] The molding film 300 is placed on the redistribution substrate 100 and can cover the sidewalls of the first semiconductor chip 210 and the sidewalls of the second semiconductor chip 220. The molding film 300 can expose the top surface of the first semiconductor chip 210 and the top surface of the uppermost second semiconductor chip 220. Contrary to the illustration, the molding film 300 can cover the top surface of the first semiconductor chip 210 and the top surface of the uppermost second semiconductor chip 220. In another example, the second underfill film 320 and the third underfill film 330 may be omitted, and the molding film 300 may be extended to the first gap region and the second gap region.

[0111] Although not shown in the diagram, conductive plates can be further placed on the top surface of the first semiconductor chip 210, the top surface of the chip stack 2000, and the top surface of the molding film 300. The conductive plates can be further extended onto the side walls of the molding film 300. The conductive plates can protect the first semiconductor chip 210 and the chip stack 2000 from external elements. For example, the conductive plates can prevent the inflow of impurities or absorb physical shocks. The conductive plates can contain a material with high thermal conductivity and function as a heat sink or heat slug. For example, during the operation of the semiconductor package, heat generated in the redistribution substrate 100, the first semiconductor chip 210, or the second semiconductor chip 220 can be quickly dissipated through the conductive plates. The conductive plates can be electrically conductive and function as an electromagnetic wave shielding layer. For example, the conductive plates can shield against electromagnetic interference (EMI) between the first semiconductor chip 210 and the second semiconductor chip 220. The conductive plate is grounded through the redistribution board 100, which prevents electrical damage to the first semiconductor chip 210 or the second semiconductor chip 220 due to electrostatic discharge (ESD).

[0112] Although not shown in the diagram, a third semiconductor chip can be further mounted on the redistribution substrate 100. The third semiconductor chip may be a different type of semiconductor chip from the first and second semiconductor chips 210 and 220.

[0113] Figure 7 is a cross-sectional view showing a semiconductor package according to an embodiment of the present invention. The following information will be omitted if it is redundant with what has already been explained.

[0114] Referring to Figure 7, the semiconductor package 12 may include a lower semiconductor package 20 and an upper semiconductor package 22. The lower semiconductor package 20 may include a redistribution substrate 100, conductive terminals 400, bonding terminals 250, a first semiconductor chip 210A, a second semiconductor chip 220A, a molding film 300, and a conductive structure 520. The redistribution substrate 100, conductive terminals 400, and molding film 300 may be substantially identical to those described with reference to Figure 1.

[0115] The second semiconductor chip 220A can be separated laterally from the first semiconductor chip 210A. The second semiconductor chip 220A may be a different type of semiconductor chip from the first semiconductor chip 210A. For example, the first semiconductor chip 210A may include one of the following: a logic chip, a memory chip, or a power management chip, and the second semiconductor chip 220A may include one of the following: a logic chip, a memory chip, or a power management chip. A logic chip may include an ASIC chip or an application processor (AP) chip. An ASIC chip may include an application-specific integrated circuit (ASIC). A power management chip may include a power management integrated circuit (PMIC). As an example, the first semiconductor chip 210A may be an ASIC chip, and the second semiconductor chip 220A may be a power management chip. Each of the first semiconductor chip 210A and the second semiconductor chip 220A may be similar to the semiconductor chip 200 described with reference to Figure 1. The second semiconductor chip 220A may be omitted, as shown. As another example, a third semiconductor chip can be further mounted on the upper surface of the redistribution substrate 100.

[0116] The bonding terminal 250 may include a first bonding terminal 251A and a second bonding terminal 252A. Each of the first bonding terminals 251A is similar to the first bonding terminal 251 described in Figure 6, and each of the second bonding terminals 252A may be similar to the second bonding terminal 252 described in Figure 6. The chip pad 215A of the first semiconductor chip 210A can be electrically connected to the redistribution board 100 through the first bonding terminal 251A. The chip pad 225A of the second semiconductor chip 220A can be electrically connected to the redistribution board 100 through the second bonding terminal 252A. Therefore, the second semiconductor chip 220A can be electrically connected to the first semiconductor chip 210A through the redistribution board 100.

[0117] The conductive structure 520 can be placed on the upper surface of the redistribution board 100 and connected to the corresponding bonding pad 150. The conductive structure 520 can be positioned laterally spaced from the first and second semiconductor chips 210A and 220A. The conductive structure 520 can be provided on the edge region of the redistribution board 100 in a plan view. A metal column can be provided on the redistribution board 100 to form the conductive structure 520. That is, the conductive structure 520 can be a metal column. The conductive structure 520 can be electrically connected to the redistribution board 100. For example, the conductive structure 520 can be electrically connected to the first semiconductor chip 210A, the second semiconductor chip 220A, or the conductive terminal 400 through the redistribution board 100. The conductive structure 520 may include a metal such as copper.

[0118] The molding film 300 can be placed on the upper surface of the redistribution substrate 100 to cover the first and second semiconductor chips 210A and 220A. The molding film 300 can seal the side walls of the conductive structure 520. The molding film 300 can be provided between the first and second semiconductor chips 210A and 220A, between the first semiconductor chip 210A and the conductive structure 520, and between the second semiconductor chip 220A and the conductive structure 520. The molding film 300 can expose the upper surface 520a of the conductive structure 520.

[0119] The lower semiconductor package 20 may further include an upper redistribution layer 600. The upper redistribution layer 600 may be provided on the upper surface of the molding film 300. The upper redistribution layer 600 may include an upper insulating pattern 610, an upper redistribution pattern 620, and an upper bonding pad 640. The upper insulating pattern 610 may be laminated on the molding film 300. The upper insulating pattern 610 may include a photosensitive polymer. Each of the upper redistribution patterns 620 may include via portions within the upper insulating pattern 610 and wiring portions between the upper insulating patterns 610. The upper redistribution pattern 620 may include a metal such as copper. At least one of the upper redistribution patterns 620 may be in contact with the upper surface 520a of the conductive structure 520. Thus, the upper redistribution pattern 620 can be connected to the conductive structure 520. The upper bonding pad 640 is located on the uppermost layer of the upper insulating pattern 610 and can be connected to the upper redistribution pattern 620. The upper bonding pad 640 can be electrically connected to the conductive terminal 400, the first semiconductor chip 210A, or the second semiconductor chip 220A through the upper redistribution pattern 620 and the conductive structure 520. Since the upper redistribution pattern 620 is provided, the upper bonding pad 640 does not need to be aligned perpendicularly with the conductive structure 520.

[0120] The upper semiconductor package 22 can be placed on the lower semiconductor package 20. For example, the upper semiconductor package 22 can be placed on the upper redistribution layer 600. The upper semiconductor package 22 may include an upper substrate 710, an upper semiconductor chip 720, and an upper molding film 730. The upper substrate 710 may be a printed circuit board. As another example, the upper substrate 710 may be a redistribution layer. For example, the upper substrate 710 may be manufactured as in the example of the redistribution board 100 described in Figures 3A to 3H. The first connecting pad 701 and the second connecting pad 702 can be placed on the lower and upper surfaces of the upper substrate 710, respectively. Wiring 703 can be provided within the upper substrate 710 and connected to the first connecting pad 701 and the second connecting pad 702. The illustration of wiring 703 is schematic, and the shape and arrangement of wiring 703 can be varied. The first connecting pad 701, the second connecting pad 702, and wiring 703 may include conductive materials such as metal.

[0121] The upper semiconductor chip 720 can be placed on the upper substrate 710. The upper semiconductor chip 720 may include an integrated circuit (not shown), which may include a memory circuit, a logic circuit, or a combination thereof. The upper semiconductor chip 720 may be a different type of semiconductor chip from the first and second semiconductor chips 210A and 220A. For example, the upper semiconductor chip 720 may be a memory chip. Bump terminals 715 can be interposed between the upper substrate 710 and the upper semiconductor chip 720 to connect to the second connecting pad 702 and the chip pad 725 of the upper semiconductor chip 720. The upper semiconductor chip 720 can be electrically connected to the first connecting pad 701 through the bump terminals 715 and wiring 713. Contrary to the illustration, the bump terminals 715 may be omitted, and the chip pad 725 may be directly connected to the second connecting pad 702.

[0122] An upper molding film 730 is provided on the upper substrate 710 to cover the upper semiconductor chip 720. The upper molding film 730 may contain an insulating polymer such as an epoxy polymer.

[0123] The upper semiconductor package 22 may further include a heat dissipation structure 780. The heat dissipation structure 780 may include a heat sink, a heat slug, or a heat transfer material (TIM) layer. The heat dissipation structure 780 may include, for example, a metal. The heat dissipation structure 780 may be positioned on the upper surface of the upper molding film 730. The heat dissipation structure 780 may further extend onto the side surface of the upper molding film 730 or onto the side wall of the molding film 300.

[0124] The semiconductor package 12 may further include a connecting terminal 650. The connecting terminal 650 is interposed between the upper bonding pad 640 and the first connecting pad 701 and can be connected to the upper bonding pad 640 and the first connecting pad 701. Thus, the upper semiconductor package 22 can be electrically connected to the first semiconductor chip 210A, the second semiconductor chip 220A, and the conductive terminal 400 through the connecting terminal 650. The electrical connection of the upper semiconductor package 22 can mean an electrical connection with the integrated circuit in the upper semiconductor chip 720.

[0125] As another example, the upper substrate 710 is omitted, and the connecting terminal 650 can be directly connected to the chip pad 725 of the upper semiconductor chip 720. In this case, the upper molding film 730 can be in direct contact with the upper surface of the upper redistribution layer 600. As yet another example, the upper substrate 710 and the connecting terminal 650 are omitted, and the chip pad 725 of the upper semiconductor chip 720 can be directly connected to the upper bonding pad 640.

[0126] Figure 8 is a cross-sectional view showing a semiconductor package according to an embodiment of the present invention. Figure 9 is an enlarged view of area B in Figure 8. The following content, which overlaps with what has been explained previously, will be omitted.

[0127] Referring to Figures 8 and 9, the semiconductor package 13 can include a lower semiconductor package 21 and an upper semiconductor package 22. The lower semiconductor package 21 can include a redistribution substrate 100, conductive terminals 400, bonding terminals 250, a first semiconductor chip 210A, a second semiconductor chip 220A, a molding film 300, and a connecting substrate 500. The redistribution substrate 100, conductive terminals 400, bonding terminals 250, the first semiconductor chip 210A, the second semiconductor chip 220A, and the molding film 300 can be substantially the same as those described with reference to Figure 1. The first semiconductor chip 210A and the second semiconductor chip 220A can be substantially the same as the first semiconductor chip 210A and the second semiconductor chip 220A described in Figure 7. The bonding terminals 250 can include a first bonding terminal 251A and a second bonding terminal 252A. The first bonding terminal 251A and the second bonding terminal 252A can be substantially identical to the first bonding terminal 251A and the second bonding terminal 252A described in Figure 7. The first underfill film 311 can be provided in the first gap region between the redistribution substrate 100 and the first semiconductor chip 210A. The first underfill film 311 can seal the first bonding terminal 251A. The second underfill film 321 can be provided in the second gap region between the redistribution substrate 100 and the second semiconductor chip 220A to seal the second bonding terminal 252A.

[0128] The connecting substrate 500 can be placed on the redistribution substrate 100. The connecting substrate 500 can have substrate holes 590 that penetrate its interior. For example, the connecting substrate 500 can be manufactured by forming substrate holes 590 that penetrate the upper and lower surfaces of the printed circuit board. In a plan view, the substrate holes 590 can be formed in the center portion of the redistribution substrate 100. The first and second semiconductor chips 210A and 220A can be placed within the substrate holes 590 of the connecting substrate 500. The first and second semiconductor chips 210A and 220A can be spaced apart from the inner wall of the connecting substrate 500.

[0129] The linked substrate 500 may include a base layer 510 and a conductive structure 520'. The base layer 510 may include a plurality of stacked base layers 510. The base layer 510 may include an insulating material. For example, the base layer 510 may include a carbon-based material, ceramic, or polymer. The substrate hole 590 may penetrate the base layer 510. The conductive structure 520' may be provided within the base layer 510.

[0130] The conductive structure 520' may include a first pad 521, conductive wiring 523, vias 524, and a second pad 522. The first pad 521 may be exposed on the lower surface 500b of the connecting substrate 500. The conductive wiring 523 may be interposed between the base layers 510. The vias 524 may penetrate the base layers 510 and be connected to the conductive wiring 523. The second pad 522 may be exposed on the upper surface 500a of the connecting substrate 500 and be connected to any one of the vias 524. The second pad 522 may be electrically connected to the first pad 521 through the vias 524 and the conductive wiring 523. The second pad 522 does not have to be aligned perpendicularly to the first pad 521. The number of second pads 522 may differ from the number of first pads 521. The conductive structure 520' may include metal. The conductive structure 520' may include at least one selected from, for example, copper, aluminum, tungsten, titanium, tantalum, iron, and alloys thereof.

[0131] A connecting bump 550 can be positioned between the redistribution board 100 and the connecting board 500. The connecting bump 550 can be interposed between the first pad 521 and the corresponding bonding pad 150 to connect with the first pad 521 and the corresponding bonding pad 150. The conductive structure 520' can be electrically connected to the redistribution board 100 by the connecting bump 550. The connecting bump 550 may include at least one of solder balls, bumps, and pillars. The connecting bump 550 may include a metallic material. A third underfill film 331 can be provided in the gap between the redistribution board 100 and the connecting board 500 to seal the connecting bump 550. The third underfill film 331 may include an insulating polymer.

[0132] The molding film 300 can be provided on the first semiconductor chip 210A, the second semiconductor chip 220A, and the connecting substrate 500. The molding film 300 can be interposed between the first semiconductor chip 210A and the second semiconductor chip 220A, between the first semiconductor chip 210A and the connecting substrate 500, and between the second semiconductor chip 220A and the connecting substrate 500. According to the embodiment, the molding film 300 can be formed by adhering an adhesive insulating film to the upper surface of the connecting substrate 500, the upper surfaces of the first and second semiconductor chips 210A and 220A, and to the side walls of the first and second semiconductor chips 210A and 220A. For example, Ajinomoto Build-Up Film (ABF) can be used as the adhesive insulating film. As another example, the molding film 300 may include an insulating polymer such as an epoxy polymer. As another example, the first and second underfill films 311 and 321 may be omitted, and the molding film 300 may be further extended onto the underside of the first semiconductor chip 210A and the underside of the second semiconductor chip 220A. If the third underfill film 331 is omitted, the molding film 300 may be further extended into the gap between the redistribution substrate 100 and the connecting substrate 500.

[0133] The lower semiconductor package 21 may further include an upper redistribution layer 600. The upper redistribution layer 600 may be placed on the molding film 300 and the connecting substrate 500. The upper redistribution layer 600 may include an upper insulating pattern 610, an upper redistribution pattern 620, and an upper bonding pad 640. The upper insulating pattern 610, the upper redistribution pattern 620, and the upper bonding pad 640 may be substantially identical to those described earlier as examples in Figure 7. However, at least one of the upper redistribution patterns 620 may be extended into the molding film 300 and connected to a second pad 522.

[0134] The upper semiconductor package 22 can be placed on the lower semiconductor package 21. For example, the upper semiconductor package 22 can be placed on the upper redistribution layer 600. The upper semiconductor package 22 may include an upper substrate 710, an upper semiconductor chip 720, and an upper molding film 730. The upper semiconductor package 22 and the connecting terminal 650 can be substantially identical to those described in Figure 7. For example, the connecting terminal 650 can be interposed between the lower semiconductor package 20 and the upper semiconductor package 22. The upper semiconductor package 22 may further include a heat dissipation structure 780.

[0135] While embodiments of the present invention have been described above with reference to the attached drawings, those with ordinary skill in the art to which the present invention pertains will understand that the present invention can be implemented in other specific forms without altering its technical idea or essential features. Therefore, the embodiments described above should be understood to be illustrative and not limiting in all respects. [Explanation of Symbols]

[0136] 10 Semiconductor Packages 100 Rewiring board 150 Bonding Pads 160 Underbump Pattern 200 semiconductor chips 205 Tip Pad 250 Bonding terminals 300 Molding film 400 conductive terminals

Claims

1. Rewiring board and The redistribution board includes a semiconductor chip disposed on the upper surface of the redistribution board, The aforementioned rewiring board is Insulating layer and, The insulating layer includes a first rewiring pattern, a second rewiring pattern, and a third rewiring pattern, The first to third rewiring patterns are provided sequentially in the direction from the lower surface to the upper surface of the rewiring board, and are electrically connected to each other. Each of the first to third rewiring patterns includes a wiring portion that extends in a direction aligned with the upper surface of the rewiring board, Each of the first and third rewiring patterns further includes via portions extending from the wiring portion in a direction perpendicular to the upper surface of the rewiring board, The second rewiring pattern further includes a first fine wiring pattern having a width smaller than the width of the wiring portion of the second rewiring pattern, The spacing between adjacent first fine wiring patterns is 0.5 μm to 2 μm. The via portion of the first rewiring pattern has a minimum width on its upper surface, The via portion of the third redistribution pattern has a minimum width at its bottom surface, and is a semiconductor package.

2. The width of the via portion of the first rewiring pattern gradually decreases as you move from the lower surface to the upper surface of the rewiring substrate. The semiconductor package according to claim 1, wherein the width of the via portion of the third redistribution pattern gradually increases as you move from the lower surface to the upper surface of the redistribution substrate.

3. The angle between the top surface and the side wall of the via portion of the first rewiring pattern is 95° to 135°. The semiconductor package according to claim 1 or 2, wherein the angle between the bottom surface and the side wall of the via portion of the third redistribution pattern is 95° to 135°.

4. Each of the first to third rewiring patterns includes a conductive pattern and a seed pattern between the conductive pattern and the insulating layer. The seed pattern of the first rewiring pattern is in contact with the conductive pattern of the second rewiring pattern. The semiconductor package according to any one of claims 1 to 3, wherein the seed pattern of the third redistribution pattern is in contact with the seed pattern of the second redistribution pattern.

5. The aforementioned rewiring board is A fourth redistribution pattern provided on the third redistribution pattern, The fourth rewiring pattern further includes a bonding pad provided on the fourth rewiring pattern, The fourth rewiring pattern is, A wiring portion extending in the direction aligned on the upper surface of the rewiring board, A semiconductor package according to any one of claims 1 to 4, comprising: a via portion extending from the wiring portion in a direction perpendicular to the upper surface of the rewiring substrate and in contact with the third rewiring pattern.

6. The fourth rewiring pattern further includes a second fine wiring pattern having a width smaller than the width of the wiring portion of the fourth rewiring pattern, The bonding pad mentioned above is A via portion that penetrates the insulating layer and contacts the fourth rewiring pattern, The semiconductor package according to claim 5, comprising a main body portion provided on the via portion.

7. The redistribution board further includes an underbump pattern provided beneath the first redistribution pattern, The aforementioned underbump pattern is, A via portion that penetrates the insulating layer and contacts the first rewiring pattern, A semiconductor package according to any one of claims 1 to 6, comprising a main body portion provided below the via portion.

8. The semiconductor package according to claim 7, wherein the side wall of the main body portion of the underbump pattern is separated from the redistribution substrate.

9. The semiconductor package according to any one of claims 1 to 8, wherein the ratio of the width at the bottom of the via portion of the first redistribution pattern to the width at the top of the via portion of the third redistribution pattern is 0.8 to 1.

2.

10. The semiconductor package according to any one of claims 1 to 9, wherein the width of each of the first fine wiring patterns is 0.5 μm to 2 μm.

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