Semiconductor equipment

Abstract

To suppress increase of a leakage current between a drain and a source.SOLUTION: A semiconductor device 10 comprises: a semiconductor layer 26; a gate trench 36 that is formed in a semiconductor layer 26; an insulation layer that is formed on the semiconductor layer 26; a gate electrode that is embedded through the insulation layer within the gate trench 36; a gate wiring line 22 that is electrically connected to the gate electrode; and a protection trench 46 that is formed in the semiconductor layer 26. The semiconductor layer 26 includes: an outer peripheral region 28 that includes outer edges 26X1, 26X2, 26Y1 and 26Y2 of the semiconductor layer 26 in plan view; and an inside region 30 that is surrounded by the outer peripheral region 28. The gate trench 36 is arranged in the outer peripheral region 28 and includes an outer peripheral gate trench part 38 that is surrounded by the protection trench 46 in plan view. The outer peripheral gate trench part 38 and the protection trench 46 are formed in an annular shape which is closed along the outer edges 26X1, 26X2, 26Y1 and 26Y2 of the semiconductor layer 26 in the outer peripheral region 28.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] This disclosure relates to semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device having a trench-gate type MOSFET (Metal-Oxide-Semiconductor Field-Effect-Transistor) as its basic structure. This semiconductor device includes an active region set in a region covered by a source electrode, a gate trench formed in the active region, and a polysilicon gate embedded in the gate trench. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-194881 [Overview of the project] [Problems that the invention aims to solve]

[0004] In a trench gate type MOSFET, a relatively large drain-source leakage current I occurs due to localized electric field concentration. DSS This may occur. [Means for solving the problem]

[0005] A semiconductor device according to an aspect of the present disclosure includes a semiconductor layer, a gate trench formed in the semiconductor layer, an insulating layer formed on the semiconductor layer, a gate electrode embedded in the gate trench via the insulating layer, a gate wiring formed on the insulating layer and electrically connected to the gate electrode, and a protection trench formed in the semiconductor layer. The semiconductor layer includes an outer peripheral region including an outer edge of the semiconductor layer in plan view and an inner region surrounded by the outer peripheral region. The gate trench includes an outer peripheral gate trench portion disposed in the outer peripheral region and surrounded by the protection trench in plan view. The outer peripheral gate trench portion and the protection trench are formed in an annular shape closed along the outer edge of the semiconductor layer in the outer peripheral region.

Advantages of the Invention

[0006] According to the semiconductor device of the present disclosure, an increase in the drain-source leakage current can be suppressed.

Brief Description of the Drawings

[0007] [Figure 1] FIG. 1 is a schematic plan view of an exemplary semiconductor device according to an embodiment. [Figure 2] FIG. 2 is a schematic plan view for explaining a metal layer of the semiconductor device shown in FIG. 1. [Figure 3] FIG. 3 is a schematic plan view for explaining a configuration formed in a semiconductor layer of the semiconductor device shown in FIG. 1. [Figure 4] FIG. 4 is a partially enlarged view of FIG. 3. [Figure 5] FIG. 5 is a schematic cross-sectional view of the semiconductor device along the line F5-F5 of FIG. 4. [Figure 6] FIG. 6 is a schematic cross-sectional view of the semiconductor device along the line F6-F6 of FIG. 4. [Figure 7] FIG. 7 is a partially enlarged view of FIG. 6. [Figure 8] FIG. 8 is a partially enlarged view of FIG. 6. [Figure 9] FIG. 9 is a partially enlarged view of FIG. 3. [Figure 10] Figure 10 is a schematic cross-sectional view of the semiconductor device along the line F10-F10 in Figure 9. [Figure 11] Figure 11 is a schematic plan view of the semiconductor device according to Comparative Example 1. [Figure 12] Figure 12 is a schematic plan view of the semiconductor device according to Comparative Example 2. [Figure 13] Figure 13 is a graph showing the relationship between the number of trench bends in the inner region and the drain-source leakage current (IDSS). [Figure 14] Figure 14 is a graph showing the change in drain-source leakage current (IDSS) over time during reliability testing. [Figure 15] Figure 15 is a schematic plan view of a semiconductor device according to an example of modification. [Modes for carrying out the invention]

[0008] Some embodiments of the semiconductor device of this disclosure will be described below with reference to the attached drawings. Note that, for the sake of simplicity and clarity, the components shown in the drawings are not necessarily drawn to a consistent scale. Also, for the sake of ease of understanding, hatching lines may be omitted in cross-sectional views. The attached drawings are merely illustrative of embodiments of this disclosure and should not be considered as limiting this disclosure.

[0009] The following detailed description includes apparatus, systems, and methods that embody exemplary embodiments of the Disclosure. This detailed description is for illustrative purposes only and is not intended to limit the embodiments of the Disclosure or the application and use of such embodiments.

[0010] [Planar layout of semiconductor device] Figures 1 to 3 are schematic plan views of a semiconductor device 10 according to one embodiment of the present invention. In Figures 2 and 3, some elements of the semiconductor device 10 in Figure 1 are shown transparently. More specifically, Figure 2 is a schematic plan view of the semiconductor device 10 with the passivation layer 12 removed from Figure 1. Figure 3 is a plan view of the semiconductor device 10 with the metal layer 18 (source wiring 20, gate wiring 22, outer peripheral electrodes 24) removed from Figure 2. For ease of understanding, the metal layer 18 is shown as a dashed line in Figure 3.

[0011] As used in this disclosure, the term "planar view" refers to viewing the semiconductor device 10 in the Z direction of the mutually orthogonal XYZ axes shown in Figure 1. Unless otherwise explicitly stated, "planar view" refers to viewing the semiconductor device 10 from above along the Z axis.

[0012] As shown in Figure 1, the semiconductor device 10 may be rectangular in plan view. In one example, the semiconductor device 10 may have a rectangular parallelepiped shape. The semiconductor device 10 may include a passivation layer 12. The passivation layer 12 can be made of any material that can protect the structure beneath it. In one example, the passivation layer 12 may be formed from a silicon nitride (SiN) film. The passivation layer 12 may include pad openings 14, 16.

[0013] The semiconductor device 10 may further include a metal layer 18. The passivation layer 12 at least partially covers the metal layer 18. The metal layer 18 can be formed from at least one of titanium (Ti), nickel (Ni), gold (Au), silver (Ag), copper (Cu), aluminum (Al), Cu alloy, and Al alloy. In one example, the metal layer 18 may be formed from an AlCu alloy.

[0014] The metal layer 18 may include a source wiring 20, a gate wiring 22, and an outer electrode 24. The source wiring 20, the gate wiring 22, and the outer electrode 24 are separated from each other. The gate wiring 22 is separated from the source wiring 20 and surrounds the source wiring 20. The outer electrode 24 is separated from the gate wiring 22 and surrounds the gate wiring 22. Further details of the source wiring 20, the gate wiring 22, and the outer electrode 24 will be described later with reference to Figure 2.

[0015] The pad opening 14 can at least partially expose the source wiring 20. The pad opening 16 can at least partially expose the gate wiring 22. The pad openings 14 and 16 can be provided to allow external connections to the source wiring 20 and gate wiring 22, respectively. On the other hand, the outer periphery electrode 24 may be completely covered by the passivation layer 12. The configuration of the pad openings 14 and 16 (e.g., position, shape, size, number, etc.) can be appropriately determined according to the design and usage of the semiconductor device 10, and is not limited to the illustrated example.

[0016] As shown in Figure 2, the semiconductor device 10 may include a semiconductor layer 26. The metal layer 18 is formed on the semiconductor layer 26. The semiconductor layer 26 includes a first surface 26A and a second surface 26B opposite to the first surface 26A (see Figure 5). The Z direction shown in Figure 2 corresponds to the direction perpendicular to the first surface 26A and the second surface 26B of the semiconductor layer 26.

[0017] The semiconductor layer 26 can be formed from at least one of silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). In one example, the semiconductor layer 26 may be formed from Si. The second surface 26B of the semiconductor layer 26 may include two edges 26X1, 26X2 extending along the X direction and two edges 26Y1, 26Y2 extending along the Y direction. The outer edge of the semiconductor layer 26 may include four edges 26X1, 26X2, 26Y1, 26Y2 in a plan view. In this specification, the four edges 26X1, 26X2, 26Y1, 26Y2 of the semiconductor layer 26 are collectively referred to as the outer edge 26X1, 26X2, 26Y1, 26Y2 of the semiconductor layer 26. The region defined by the outer edge 26X1, 26X2, 26Y1, 26Y2 of the semiconductor layer 26 may correspond to a single chip (die). The edges 26X1 and 26X2 extending along the X direction can have the same length as the edges 26Y1 and 26Y2 extending along the Y direction. In the example in Figure 2, the edges 26X1 and 26X2 may have a shorter length than the edges 26Y1 and 26Y2. In another example, the edges 26X1 and 26X2 may have the same length as the edges 26Y1 and 26Y2, or they may have a longer length than the edges 26Y1 and 26Y2. Thus, the outer edges 26X1, 26X2, 26Y1, and 26Y2 of the semiconductor layer 26 may be rectangular in plan view and therefore may have four corners.

[0018] The semiconductor layer 26 may include an outer region 28 and an inner region 30 enclosed by the outer region 28 in a plan view. The boundary between the outer region 28 and the inner region 30 is shown by a dashed line in Figure 2. The inner region 30 may be rectangular in shape in a plan view. The outer region 28 may include the outer edges 26X1, 26X2, 26Y1, 26Y2 of the semiconductor layer 26. The outer region 28 may be a rectangular frame surrounding the inner region 30 in a plan view. Further details of the semiconductor layer 26 will be described later with reference to Figure 5.

[0019] The source wiring 20 may include a recess 20A by having a substantially rectangular cutout in plan view. The recess 20A can be formed at the end of the source wiring 20 adjacent to any of the four sides 26X1, 26X2, 26Y1, and 26Y2 of the semiconductor layer 26. In the example in Figure 2, the recess 20A can be formed in the center in the X direction at the end of the source wiring 20 adjacent to side 26X2 of the semiconductor layer 26.

[0020] The gate wiring 22 may include a gate finger portion 32 and a gate pad portion 34. The gate finger portion 32 may be located in the outer peripheral region 28. The gate finger portion 32 may extend along at least a portion of the outer edges 26X1, 26X2, 26Y1, 26Y2 of the semiconductor layer 26 and at least partially surround the source wiring 20. The gate pad portion 34 may span both the outer peripheral region 28 and the inner region 30. The gate pad portion 34 may be integrally connected to the gate finger portion 32. The gate pad portion 34 may be located at least partially within the recess 20A of the source wiring 20. In the example of Figure 2, the gate pad portion 34 may be located to connect two portions of the gate finger portion 32 that extend along side 26X2 in a plan view.

[0021] The outer periphery electrode 24 may be a closed annular shape in plan view. The outer periphery electrode 24 may extend along the outer edges 26X1, 26X2, 26Y1, 26Y2 of the semiconductor layer 26. The outer periphery electrode 24 may be spaced apart from the four sides 26X1, 26X2, 26Y1, 26Y2 of the semiconductor layer 26.

[0022] Figure 3 schematically shows several components formed in the semiconductor layer 26. The semiconductor device 10 may further include gate trenches 36 formed in the semiconductor layer 26. The gate trenches 36 are formed in both the outer peripheral region 28 and the inner region 30 of the semiconductor layer 26. The gate trenches 36 may include an outer peripheral gate trench portion 38 located in the outer peripheral region 28, an inner gate trench portion 40 located in the inner region 30 (see Figure 4), and a connecting gate trench portion 42 that connects the outer peripheral gate trench portion 38 to the inner gate trench portion 40.

[0023] The inner region 30 of the semiconductor layer 26 may include an active region 44 that contributes to the operation of the semiconductor device 10 as a transistor. The active region 44 may overlap the source wiring 20 in a plan view. The active region 44 may have a similar shape in a plan view to the source wiring 20 including the recess 20A. The active region 44 may be slightly smaller than the source wiring 20 including the recess 20A in a plan view. The active region 44 is covered by the source wiring 20 but not by the gate pad portion 34. The inner gate trench portion 40 can be located in the active region 44.

[0024] The outer periphery gate trench portion 38 is formed in a closed annular shape along the outer edges 26X1, 26X2, 26Y1, and 26Y2 of the semiconductor layer 26 in the outer periphery region 28. That is, the outer periphery gate trench portion 38 extends along the four sides 26X1, 26X2, 26Y1, and 26Y2 of the semiconductor layer 26. In a plan view, the outer periphery gate trench portion 38 can have the same number of bends as the corners of the outer edges 26X1, 26X2, 26Y1, and 26Y2 of the semiconductor layer 26. In the illustrated example, since the outer edges 26X1, 26X2, 26Y1, and 26Y2 of the semiconductor layer 26 have four corners in a plan view, the outer periphery gate trench portion 38 has four bends in the outer periphery region 28.

[0025] The outer periphery gate trench portion 38 can be positioned to surround the inner region 30. The outer periphery gate trench portion 38 does not extend into the inner region 30. In a plan view, the outer periphery gate trench portion 38 overlaps with both the gate finger portion 32 and the gate pad portion 34.

[0026] On the other hand, the connecting gate trench portion 42 overlaps with the gate finger portion 32 in a plan view, but does not overlap with the gate pad portion 34. The outer peripheral gate trench portion 38 extends along the outer edges 26X1, 26X2, 26Y1, and 26Y2 of the semiconductor layer 26, rather than along the outer periphery of the active region 44. Therefore, the outer peripheral gate trench portion 38, located below the gate pad portion 34 and extending along the edge 26X2, is separated from the active region 44 in the Y direction by the dimensions of the gate pad portion 34. The outer peripheral gate trench portion 38, which overlaps with the gate pad portion 34 in a plan view, is not directly connected to the inner gate trench portion 40 of the active region 44 by the connecting gate trench portion 42.

[0027] The semiconductor device 10 may further include a protective trench 46 formed in the semiconductor layer 26. The protective trench 46 is formed in a closed annular shape along the outer edges 26X1, 26X2, 26Y1, 26Y2 of the semiconductor layer 26 in the peripheral region 28. That is, the protective trench 46 extends along the four sides 26X1, 26X2, 26Y1, 26Y2 of the semiconductor layer 26. In a plan view, the protective trench 46 may have the same number of bends as the corners of the outer edges 26X1, 26X2, 26Y1, 26Y2 of the semiconductor layer 26. In the illustrated example, since the outer edges 26X1, 26X2, 26Y1, 26Y2 of the semiconductor layer 26 have four corners in a plan view, the protective trench 46 has four bends in the peripheral region 28.

[0028] The protective trench 46 can be positioned to surround the outer periphery gate trench portion 38. Therefore, the protective trench 46 does not extend into the inner region 30. In a plan view, the outer periphery gate trench portion 38 is surrounded by the protective trench 46. The semiconductor device 10 may include a plurality of protective trenches 46.

[0029] [Placement of gate trenches and protective trenches around the gate finger area] Figure 4 is a magnified view of a portion of Figure 3, specifically the portion F4 enclosed by the dashed line in Figure 3. For ease of understanding, dot hatching is applied to the source wiring 20, gate wiring 22 (gate finger portion 32), and outer electrode 24 in Figure 4.

[0030] As shown in Figure 4, the inner gate trenches 40 located in the active region 44 may be formed in a grid pattern. The semiconductor device 10 may further include source contacts 48 connected to the source wiring 20, and the source contacts 48 may be arranged in a plurality of rectangular regions of the semiconductor layer 26 surrounded by the inner gate trenches 40. In another example, the inner gate trenches 40 may be formed, for example, in a stripe pattern.

[0031] The outer periphery gate trench portion 38 located in the outer periphery region 28 can have a greater width than the inner gate trench portion 40. Here, the width of the outer periphery gate trench portion 38 refers to the dimension in a direction perpendicular to the direction along the outer edge 26X1, 26X2, 26Y1, 26Y2 of the semiconductor layer 26 to which the outer periphery gate trench portion 38 extends. The width of the outer periphery gate trench portion 38 can also be said to be the width in the short-side direction of the outer periphery gate trench portion 38. For example, the outer periphery gate trench portion 38 shown in Figure 4 extends in the Y direction and has a width in the X direction. Similarly, the width of the inner gate trench portion 40 can refer to the width in the short-side direction of the inner gate trench portion 40.

[0032] The semiconductor device 10 may further include a gate contact portion 50 connected to the gate wiring 22 (gate finger portion 32), and the gate contact portion 50 may be positioned in a region that overlaps with the outer gate trench portion 38 in a plan view.

[0033] A connecting gate trench section 42, which connects the outer periphery gate trench section 38 to the inner gate trench section 40, is arranged across both the outer periphery region 28 and the inner region 30. The connecting gate trench section 42 can extend in a direction intersecting the direction in which the outer periphery gate trench section 38 extends (the Y direction in Figure 4) (the X direction in Figure 4). The connecting gate trench section 42 may include a plurality of connecting gate trenches 42A arranged in a stripe pattern.

[0034] The outer periphery gate trench section 38 is surrounded by protective trenches 46. In the example shown in Figure 4, 25 protective trenches 46 are arranged in the outer periphery region 28. The semiconductor device 10 may include one or more protective trenches 46, and the number of protective trenches 46 can be appropriately determined according to the desired performance and layout of the semiconductor device 10.

[0035] As shown in the illustrated example, if multiple protective trenches 46 are provided, some of the protective trenches 46 may overlap with the gate finger portion 32 in a plan view. Alternatively, all of the multiple protective trenches 46 may overlap with the gate finger portion 32 in a plan view.

[0036] The semiconductor device 10 may further include an outer peripheral contact portion 52 connected to the outer peripheral electrode 24. The outer peripheral contact portion 52 may be formed in a closed annular shape, and the annular outer peripheral contact portion 52 may surround the protective trench 46 in a plan view. The semiconductor device 10 may include a plurality of outer peripheral contact portions 52.

[0037] The source contact portion 48, the gate contact portion 50, and the outer peripheral contact portion 52 can be formed from any metallic material. In one example, each contact portion 48, 50, and 52 can be formed from at least one of tungsten (W), Ti, and titanium nitride (TiN).

[0038] Figure 5 is a schematic cross-sectional view of the semiconductor device 10 along the line F5-F5 in Figure 4. The semiconductor layer 26 may include a semiconductor substrate 54 including the first surface 26A of the semiconductor layer 26, and an epitaxial layer 56 formed on the semiconductor substrate 54 and including the second surface 26B of the semiconductor layer 26. In this embodiment, the semiconductor substrate 54 may be a Si substrate. The semiconductor substrate 54 can correspond to the drain region of the MISFET. The drain region (semiconductor substrate 54) contains p-type impurities. + It may be in the region of type . The impurity concentration of the semiconductor substrate 54 is 1 × 10 18 cm -3 The above 1 x 10 20 cm -3 The following may be applied: The semiconductor substrate 54 may have a thickness of 50 μm or more and 450 μm or less. The epitaxial layer 56 may be a Si layer epitaxially grown on a Si substrate. Further details of the epitaxial layer 56 will be described later with reference to Figures 7 and 8.

[0039] The semiconductor device 10 may further include a drain electrode 58 formed on the first surface 26A of the semiconductor layer 26. The drain electrode 58 is electrically connected to the drain region (semiconductor substrate 54). The drain electrode 58 can be formed from at least one of Ti, Ni, Au, Ag, Cu, Al, Cu alloy, and Al alloy.

[0040] The semiconductor device 10 may further include an insulating layer 60 formed on the semiconductor layer 26. In one example, the insulating layer 60 may be formed from a silicon oxide film (SiO2). The insulating layer 60 may additionally or alternatively include a film formed from an insulating material other than SiO2, such as SiN. The insulating layer 60 is in contact with the second surface 26B of the semiconductor layer 26. Source wiring 20, gate wiring 22, and peripheral electrodes 24 are formed on the insulating layer 60. The passivation layer 12 at least partially covers the source wiring 20, gate wiring 22, and peripheral electrodes 24 formed on the insulating layer 60. The portion of the insulating layer 60 not covered by the source wiring 20, gate wiring 22, and peripheral electrodes 24 may also be covered by the passivation layer 12.

[0041] The gate trench 36 has an opening in the second surface 26B of the semiconductor layer 26 and has depth in the Z direction. Similarly, the protective trench 46 also has an opening in the second surface 26B of the semiconductor layer 26 and has depth in the Z direction. The gate trench 36 and the protective trench 46 are shown having approximately the same depth, but in other examples they may have different depths. For example, the protective trench 46 may be formed deeper than the gate trench 36 within the semiconductor layer 26. Alternatively, the protective trench 46 may be formed shallower than the gate trench 36 within the semiconductor layer 26. In yet another example, the outer gate trench portion 38 and the inner gate trench portion 40 may have different depths. For example, the outer gate trench portion 38 may be formed deeper than the inner gate trench portion 40.

[0042] Figure 5 shows a longitudinal cross-section of one connecting gate trench 42A included in the connecting gate trench section 42. The two ends of the connecting gate trench 42A are in communication with the outer gate trench section 38 and the inner gate trench section 40, respectively. In this way, the outer gate trench section 38, the inner gate trench section 40, and the connecting gate trench section 42 are interconnected to form a gate trench 36.

[0043] A gate electrode 62, described later with reference to Figures 7 and 8, is embedded in the outer gate trench section 38, the inner gate trench section 40, and the connecting gate trench section 42 via an insulating layer 60. Since the outer gate trench section 38, the inner gate trench section 40, and the connecting gate trench section 42 are in communication with each other, the integrally constructed gate electrode 62 can be embedded across the outer gate trench section 38, the inner gate trench section 40, and the connecting gate trench section 42.

[0044] The source contact portion 48 extends through the insulating layer 60 located between the source wiring 20 and the semiconductor layer 26, connecting the source wiring 20 and the semiconductor layer 26. The outer peripheral contact portion 52 extends through the insulating layer 60 located between the outer peripheral electrode 24 and the semiconductor layer 26, connecting the outer peripheral electrode 24 and the semiconductor layer 26.

[0045] Figure 6 is a schematic cross-sectional view of the semiconductor device 10 along the line F6-F6 in Figure 4, showing the region between the two connecting gate trenches 42A. Regarding Figure 6, the same configuration as in Figure 5 will not be explained.

[0046] Figure 6 shows the portion of the outer gate trench 38 that is not in direct communication with the connecting gate trench 42A. As described above and illustrated, the outer gate trench 38 can have a greater width than the inner gate trench 40. In one example, the outer gate trench 38 can have a width of 1.2 to 2.5 times that of the inner gate trench 40.

[0047] The gate contact portion 50 extends through the insulating layer 60 and connects the gate finger portion 32 to the gate electrode 62 embedded in the outer gate trench portion 38 (see Figure 8). Therefore, the gate wiring 22 is electrically connected to the gate electrode 62.

[0048] Figure 7 is a magnified view of a portion of Figure 6, specifically the portion F7 enclosed by the dashed line in Figure 6. Figure 7 shows a cross-sectional view of the active region 44 (see Figure 3). The semiconductor device 10 can further include a gate electrode 62 embedded in the gate trench 36 via an insulating layer 60. The gate electrode 62 can be formed of, for example, conductive polysilicon. The insulating layer 60 can include a gate insulating film 64 interposed between the gate electrode 62 and the semiconductor layer 26 to cover the gate trench 36, and an interlayer insulating film 66 formed between the metal layer 18 and the semiconductor layer 26. The gate electrode 62 is separated from the semiconductor layer 26 by the gate insulating film 64.

[0049] In FIG. 7, a gate insulating film 64 interposed between the gate electrode 62 and the semiconductor layer 26 to cover the inner gate trench portion 40, and an interlayer insulating film 66 formed between the source wiring 20 and the semiconductor layer 26 are shown.

[0050] The semiconductor layer 26 (epitaxial layer 56) can include a drift region 68, a body region 70 formed on the drift region 68, and a source region 72 formed on the body region 70. The source region 72 can include the second surface 26B of the semiconductor layer 26. The semiconductor layer 26 (epitaxial layer 56) can further include a contact region 74 located under the source contact portion 48. The source wiring 20 is electrically connected to the contact region 74 via the source contact portion 48.

[0051] The drift region 68 can be a p-type region containing a lower concentration of p-type impurities than the drain region (semiconductor substrate 54). The impurity concentration of the drift region 68 can be 1×10 - cm 15 or more and 1×10 -3 cm 18 or less. The drift region 68 can have a thickness of 1 μm or more and 25 μm or less. -3 The body region 70 can be an n-type region containing n-type impurities. The source region 72 can be a p-type region containing a higher concentration of p-type impurities than the drift region 68.

[0052] - + ​​It may be a region of type 70. The impurity concentration in body region 70 is 1 × 10⁻⁶. 16 cm -3 The above 1 x 10 18 cm -3 The following is possible: The body region 70 may have a thickness of 0.5 μm or more and 1.5 μm or less.

[0053] Source region 72 contains p-type impurities at a higher concentration than drift region 68. + It may be a region of type 72. The impurity concentration in source region 72 is 1 × 10⁻⁶. 19 cm -3 The above 1 x 10 21 cm -3 The following is possible: The source region 72 may have a thickness of 0.1 μm or more and 1 μm or less.

[0054] Contact region 74 contains n-type impurities. + It may be a type region. The impurity concentration in the contact region 74 is higher than that in the body region 70, 1 × 10⁻⁶ 19 cm -3 The above 1 x 10 21 cm -3 The following is possible:

[0055] In this disclosure, p-type is also referred to as the first conductivity type, and n-type as the second conductivity type. p-type impurities may be, for example, boron (B) or aluminum (Al). n-type impurities may be, for example, phosphorus (P) or arsenic (As).

[0056] The inner gate trench portion 40 has an opening in the second surface 26B of the semiconductor layer 26 and penetrates the source region 72 and the body region 70 to reach the drift region 68. The side walls of the inner gate trench portion 40 may or may not extend in a direction perpendicular to the second surface 26B of the semiconductor layer 26 (Z direction). In the illustrated example, the inner gate trench portion 40 may have side walls that are slightly inclined with respect to the Z direction.

[0057] When a predetermined voltage is applied to the gate electrode 62, the gate insulating film 64 and adjacent n - A channel is formed within the body region 70 of the type. The semiconductor device 10 uses this channel to p + Source area 72 and p - This allows for control of the flow of holes in the Z direction between the drift region 68 of the type and the surrounding area.

[0058] Figure 8 is a magnified view of a portion of Figure 6, specifically the portion F8 enclosed by the dashed line in Figure 6. Figure 8 shows a cross-sectional view of the outer peripheral region 28 (see Figure 3), particularly the region covered by the gate finger portion 32.

[0059] As described above, the gate electrode 62 is also embedded in the outer gate trench portion 38 via an insulating layer 60. Since the outer gate trench portion 38 has a larger width than the inner gate trench portion 40, the gate electrode 62 can have a larger width in the outer gate trench portion 38 than in the inner gate trench portion 40. Similarly, the gate insulating film 64 may be formed thicker in the outer gate trench portion 38 than in the inner gate trench portion 40.

[0060] The gate contact portion 50 extends through the insulating layer 60 (interlayer insulating film 66) located between the gate electrode 62 and the gate finger portion 32, and connects the gate electrode 62, which is embedded in the outer peripheral gate trench portion 38, to the gate finger portion 32.

[0061] The protective trench 46 can be positioned at a distance from the outer perimeter gate trench section 38. If multiple protective trenches 46 are provided, the multiple protective trenches 46 can also be positioned at a distance from each other. As shown in the illustrated example, the protective trench 46 can have a width smaller than the outer perimeter gate trench section 38. In another example, the protective trench 46 may have the same width as the outer perimeter gate trench section 38, or it may have a width larger than the outer perimeter gate trench section 38.

[0062] The semiconductor device 10 may further include a protective electrode 76 embedded in a protective trench 46 via an insulating layer 60. The protective electrode 76 may, in one example, be formed from conductive polysilicon. Since the protective trench 46 is formed in a closed annular shape in plan view, the protective electrode 76 may also be formed in a closed annular shape in plan view. The insulating layer 60 may further include a protective insulating film 78 interposed between the protective electrode 76 and the semiconductor layer 26, covering the protective trench 46. The protective electrode 76 is separated from the semiconductor layer 26 by the protective insulating film 78. The protective electrode 76 embedded in the protective trench 46 may not be connected to any other metal members (e.g., gate finger portion 32) and may be electrically floating.

[0063] In regions other than the active region 44 (see Figure 3), as shown in Figure 8, the semiconductor layer 26 does not include the source region 72, but includes the drift region 68 and the body region 70. Therefore, in the region shown in Figure 8, the second surface 26B of the semiconductor layer 26 is included in the body region 70. The outer periphery gate trench 38 and the protective trench 46 have openings in the second surface 26B of the semiconductor layer 26, penetrating the body region 70 and reaching the drift region 68. The side walls of the outer periphery gate trench 38 and the protective trench 46 may or may not extend in a direction perpendicular to the second surface 26B of the semiconductor layer 26 (Z direction). In the illustrated example, the outer periphery gate trench 38 and the protective trench 46 may have side walls that are slightly inclined with respect to the Z direction.

[0064] [Placement of gate trenches and protective trenches around the gate pad area] Figure 9 is a magnified view of a portion of Figure 3, specifically the portion F9 enclosed by the dashed line in Figure 3. For ease of understanding, dot hatching is applied to the gate wiring 22 (gate pad portion 34) and the outer electrode 24 in Figure 9.

[0065] In a plan view, the inner gate trench portion 40 and the connecting gate trench portion 42 are not present in the area that overlaps with the gate pad portion 34. On the other hand, the outer gate trench portion 38 and the protective trench 46 extend approximately parallel to each other, as in the case of Figure 4.

[0066] As shown in the illustrated example, if multiple protective trenches 46 are provided, some of the protective trenches 46 may overlap with the gate pad portion 34 in a plan view. Alternatively, all of the multiple protective trenches 46 may overlap with the gate pad portion 34 in a plan view.

[0067] Figure 10 is a schematic cross-sectional view of the semiconductor device 10 along the line F10-F10 in Figure 9. Similar to the regions shown in Figures 5 and 6, the outer periphery gate trench 38 and protective trench 46 are formed in the semiconductor layer 26. The region shown in Figure 10 is relatively far from the active region 44 (see Figure 3). The region covered by the gate pad 34, including the region shown in Figure 10, does not have a connecting gate trench 42 that communicates with the inner gate trench 40 located in the active region 44 (see Figure 3).

[0068] [Effect] The operation of the semiconductor device 10 of this embodiment will be described below. In the semiconductor device 10 of this embodiment, the outer peripheral gate trench portion 38 and the protective trench 46 are formed in a closed annular shape along the outer edges 26X1, 26X2, 26Y1, and 26Y2 of the semiconductor layer 26 in the outer peripheral region 28.

[0069] Drain-source leakage current I in MOSFET DSS The drain-source leakage current (also called the drain break current) can increase due to localized electric field concentration within the semiconductor chip. According to the semiconductor device 10 of this embodiment, by providing a closed annular outer gate trench 38 and a closed annular protective trench 46 in the outer peripheral region 28, the depletion layer can be effectively extended to the outer peripheral region 28. As a result, electric field concentration in the outer peripheral region 28 can be mitigated, and the drain-source leakage current I in the semiconductor device 10 can be reduced. DSSThis can suppress the increase.

[0070] [Gate trench layout and drain-source leakage current I DSS [Relationship] The following comparisons using Comparative Examples 1 and 2 will show the drain-source leakage current I of the semiconductor device 10 of this embodiment. DSS Let's further explain the inhibitory effect.

[0071] (Comparative Example 1) Figure 11 is a schematic plan view of the semiconductor device 100 according to Comparative Example 1. In Figure 11, components similar to those in the semiconductor device 10 (see Figure 3 in particular) are denoted by the same reference numerals. Detailed explanations of components similar to those in the semiconductor device 10 are omitted.

[0072] The semiconductor device 100 includes a gate trench 102 formed in the semiconductor layer 26. The gate trench 102 is formed in both the outer peripheral region 28 and the inner region 30 of the semiconductor layer 26. The gate trench 102 includes an outer peripheral gate trench portion 104, an inner gate trench portion 106 located in the inner region 30, and a connecting gate trench portion 108 that connects the outer peripheral gate trench portion 104 to the inner gate trench portion 106.

[0073] The outer periphery gate trench portion 104 and the connecting gate trench portion 108 are arranged along the outer periphery of the active region 44, rather than along the outer edges 26X1, 26X2, 26Y1, 26Y2 of the semiconductor layer 26. The outer periphery gate trench portion 104, which overlaps with the gate pad portion 34 in a plan view, is directly connected to the inner gate trench portion 106 of the active region 44 by the connecting gate trench portion 108.

[0074] The outer periphery gate trench portion 104 is formed in a closed annular shape along the outer circumference of the active region 44. The outer periphery gate trench portion 104 extends along the outer edge of the gate pad portion 34 closer to the source wiring 20 and enters the inner region 30. As a result, the outer periphery gate trench portion 104 has six bends in the outer region 28 and two bends in the inner region 30.

[0075] The semiconductor device 100 further includes a protective trench 110 formed in the semiconductor layer 26. The protective trench 110 is formed in a closed annular shape along the outer periphery of the active region 44. The protective trench 110 extends along the outer edge of the gate pad portion 34 near the source wiring 20 and extends into the inner region 30. As a result, the protective trench 110 has six bends in the outer periphery region 28 and two bends in the inner region 30. The outer periphery gate trench portion 104 is surrounded by the protective trench 110 in a plan view.

[0076] Thus, the semiconductor device 100 differs from the semiconductor device 10 in that the outer peripheral gate trench portion 104, the connecting gate trench portion 108, and the protective trench 110 are arranged along the outer periphery of the active region 44. The outer peripheral gate trench portion 38 and protective trench 46 of the semiconductor device 10 do not have any bends within the inner region 30, whereas the outer peripheral gate trench portion 104 and protective trench 110 of the semiconductor device 100 have two bends within the inner region 30.

[0077] (Comparative Example 2) Figure 12 is a schematic plan view of the semiconductor device 200 according to Comparative Example 2. In Figure 12, components similar to those in the semiconductor device 10 (see Figure 3 in particular) are denoted by the same reference numerals. Detailed explanations of components similar to those in the semiconductor device 10 are omitted.

[0078] The semiconductor device 200 includes source wiring 202 and gate wiring 204. The source wiring 202 includes a recess 202A, which has a substantially rectangular cutout in plan view. The recess 202A is formed in a region close to the point where the edges 26X2 and 26Y2 of the semiconductor layer 26 intersect.

[0079] The gate wiring 204 includes a gate finger portion 206 and a gate pad portion 208. The gate finger portion 206 is located in the outer peripheral region 28. The gate finger portion 206 extends along a portion of the outer edge 26X1, 26X2, 26Y1, 26Y2 of the semiconductor layer 26 and partially surrounds the source wiring 202. The gate pad portion 208 is located across both the outer peripheral region 28 and the inner region 30. The gate pad portion 208 is integrally connected to the gate finger portion 206. The gate pad portion 208 is located at least partially within the recess 202A of the source wiring 202. The gate pad portion 208 is positioned to connect the portion of the gate finger portion 206 extending along edge 26X2 and the portion extending along edge 26Y2.

[0080] The semiconductor device 200 further includes a gate trench 210 formed in the semiconductor layer 26. The gate trench 210 is formed in both the outer peripheral region 28 and the inner region 30 of the semiconductor layer 26. The gate trench 210 includes an outer peripheral gate trench portion 212, an inner gate trench portion 214 located in the inner region 30, and a connecting gate trench portion 216 that connects the outer peripheral gate trench portion 212 to the inner gate trench portion 214.

[0081] The inner region 30 of the semiconductor layer 26 includes an active region 218. The active region 218 overlaps with the source wiring 202 in a plan view. The active region 218 can have a similar shape in a plan view to the source wiring 202 including the recess 202A. In a plan view, the active region 218 is slightly smaller than the source wiring 202 including the recess 202A. The active region 218 is covered by the source wiring 202 but not by the gate pad portion 208.

[0082] The inner gate trench portion 214 is located in the active region 218. The outer gate trench portion 212 and the connecting gate trench portion 216 are located along the outer periphery of the active region 218, rather than along the outer edges 26X1, 26X2, 26Y1, 26Y2 of the semiconductor layer 26. The outer gate trench portion 212, which overlaps with the gate pad portion 208 in a plan view, is directly connected to the inner gate trench portion 214 of the active region 218 by the connecting gate trench portion 216.

[0083] The outer periphery gate trench section 212 is formed in a closed annular shape along the outer periphery of the active region 218. The outer periphery gate trench section 212 extends along the outer edge of the gate pad section 208 near the source wiring 202 and enters the inner region 30. As a result, the outer periphery gate trench section 212 has five bends in the outer periphery region 28 and one bend in the inner region 30.

[0084] The semiconductor device 200 further includes a protective trench 220 formed in the semiconductor layer 26. The protective trench 220 is formed in a closed annular shape along the outer periphery of the active region 218. The protective trench 220 extends along the outer edge of the gate pad portion 208 near the source wiring 202 and extends into the inner region 30. As a result, the protective trench 220 has five bends in the outer region 28 and one bend in the inner region 30. The outer gate trench portion 212 is surrounded by the protective trench 220 in a plan view.

[0085] Thus, the semiconductor device 200 differs from the semiconductor device 10 in that the outer peripheral gate trench portion 212, the connecting gate trench portion 216, and the protective trench 220 are arranged along the outer periphery of the active region 218. Furthermore, the semiconductor device 200 differs from the semiconductor devices 10 and 100 in that the gate pad portion 208 is located close to the corner where the edges 26X2 and 26Y2 of the semiconductor layer 26 intersect.

[0086] The outer gate trench portion 38 and protective trench 46 of the semiconductor device 10 do not have a bend within the inner region 30, but the outer gate trench portion 212 and protective trench 220 of the semiconductor device 200 have one bend within the inner region 30.

[0087] (Comparison of Examples and Comparative Examples) Figure 13 shows the number of bends in the outer gate trench (or protective trench) in the inner region and the drain-source leakage current I DSS This graph shows the relationship between the two. The vertical axis of the graph represents the drain-source leakage current I. DSS The graph shows the number of bends in the outer gate trench (or protective trench) in the inner region 30, with the horizontal axis indicating the number of bends in the outer gate trench. Since the protective trench runs parallel to the outer gate trench, the number of bends in the protective trench is the same as that of the outer gate trench. Note that the drain-source leakage current I DSS This is measured by short-circuiting the gate-source while applying a predetermined voltage (in this case, the rated voltage) between the drain-source.

[0088] In the embodiment corresponding to semiconductor device 10, the number of bends is 0, and the drain-source leakage current I DSS It is relatively small. On the other hand, in Comparative Example 1, the number of bends is 2, and the drain-source leakage current I DSS It is relatively large. In Comparative Example 2, the number of bends is 1, and the drain-source leakage current I DSS It is moderate.

[0089] Thus, the drain-source leakage current I DSS This can be reduced by decreasing the number of bends in the outer gate trench and protective trench sections within the inner region. Figure 14 shows the drain-source leakage current I in reliability testing. DSS This graph shows the change over time. The vertical axis of the graph represents the drain-source leakage current I. DSSThe graph shows the drain-source leakage current I for the example corresponding to semiconductor device 10 and Comparative Example 1 corresponding to semiconductor device 100. DSS These are plotted.

[0090] Drain-source leakage current I in Comparative Example 1 DSS This increases significantly over time. On the other hand, the drain-source leakage current I of the embodiment corresponding to semiconductor device 10 DSS At the start of the test, the drain-source leakage current I of Comparative Example 1 DSS It is smaller than that and increases only slightly over time.

[0091] Thus, by adopting the layout of the semiconductor device 10 of this embodiment, the drain-source leakage current I DSS This can suppress the increase. [effect] The semiconductor device 10 of this embodiment has the following advantages.

[0092] (1) The outer peripheral gate trench portion 38 and the protective trench 46 are formed in a closed annular shape along the outer edges 26X1, 26X2, 26Y1, 26Y2 of the semiconductor layer 26 in the outer peripheral region 28.

[0093] With this configuration, the outer gate trench 38 and protective trench 46 do not have bends in the inner region 30. Furthermore, electric field concentration in the region surrounded by the outer gate trench 38 and protective trench 46 can be mitigated. As a result, the drain-source leakage current I in the semiconductor device 10 is reduced. DSS This can suppress the increase.

[0094] (2) The protective electrode 76 embedded in the protective trench 46 via the insulating layer 60 is formed in a closed annular shape when viewed from above. This configuration allows for the mitigation of electric field concentration in the region surrounded by the protective electrode 76, thereby reducing the drain-source leakage current I in the semiconductor device 10.DSS This can further suppress the increase.

[0095] (3) The connecting gate trench portion 42 overlaps with the gate finger portion 32 in a plan view, but does not overlap with the gate pad portion 34. With this configuration, the connecting gate trench portion 42 is not positioned along the active region 44, so the bend in the outer gate trench portion 38 in the inner region 30 can be made zero. Therefore, the drain-source leakage current I in the semiconductor device 10 DSS This can suppress the increase.

[0096] (4) The width of the outer gate trench section 38 is greater than the width of the inner gate trench section 40. With this configuration, the gate insulating film 64 formed in the outer gate trench portion 38 can be made thicker than the one in the inner gate trench portion 40, thereby improving the breakdown voltage of the semiconductor device 10.

[0097] (5) The outer electrode 24 is separated from the gate wiring 22 and surrounds the gate wiring 22. This configuration makes it possible to mitigate electric field concentration in the region surrounded by the outer electrode 24, thereby improving the breakdown voltage of the semiconductor device 10.

[0098] [Example of changes] The above-described embodiment can be further modified and implemented as follows. The position and dimensions of the gate pad portion 34 can be arbitrarily changed. Figure 15 is a schematic cross-sectional view of the semiconductor device 300 according to a modified example. In Figure 15, components similar to those of the semiconductor device 10 (see Figure 3 in particular) are denoted by the same reference numerals. Detailed explanations of components similar to those of the semiconductor device 10 are omitted.

[0099] The semiconductor device 300 shown in Figure 15 may include source wiring 302 and gate wiring 304. The source wiring 302 may include a recess 302A by having a substantially rectangular cutout in plan view. The recess 302A can be formed in a region close to the point where the edges 26X2 and 26Y2 of the semiconductor layer 26 intersect.

[0100] The gate wiring 304 may include a gate finger portion 306 and a gate pad portion 308. The gate finger portion 306 is located in the outer peripheral region 28. The gate finger portion 306 may extend along a portion of the outer edge 26X1, 26X2, 26Y1, 26Y2 of the semiconductor layer 26 to partially surround the source wiring 302. The gate pad portion 308 may span both the outer peripheral region 28 and the inner region 30. The gate pad portion 308 may be integrally connected to the gate finger portion 306. The gate pad portion 308 is at least partially located within the recess 302A of the source wiring 302. The gate pad portion 308 may be positioned to connect the portion of the gate finger portion 306 extending along edge 26X2 and the portion extending along edge 26Y2.

[0101] The semiconductor device 300 may further include gate trenches 310 formed in the semiconductor layer 26. The gate trenches 310 are formed in both the outer peripheral region 28 and the inner region 30 of the semiconductor layer 26. The gate trenches 310 may include an outer peripheral gate trench portion 312 located in the outer peripheral region 28, an inner gate trench portion 314 located in the inner region 30, and a connecting gate trench portion 316 that connects the outer peripheral gate trench portion 312 to the inner gate trench portion 314.

[0102] The inner region 30 of the semiconductor layer 26 includes an active region 318. The active region 318 overlaps with the source wiring 302 in a plan view. The active region 318 can have a similar shape in a plan view to the source wiring 302 including the recess 302A. The active region 318 may be slightly smaller than the source wiring 302 including the recess 302A in a plan view. The active region 318 is covered by the source wiring 302 but not by the gate pad portion 308. The inner gate trench portion 314 can be located in the active region 318.

[0103] The outer periphery gate trench portion 312 is formed in a closed annular shape along the outer edges 26X1, 26X2, 26Y1, and 26Y2 of the semiconductor layer 26 in the outer periphery region 28. That is, the outer periphery gate trench portion 312 extends along the four sides 26X1, 26X2, 26Y1, and 26Y2 of the semiconductor layer 26. In a plan view, the outer periphery gate trench portion 312 can have the same number of bends as the corners of the outer edges 26X1, 26X2, 26Y1, and 26Y2 of the semiconductor layer 26. In the illustrated example, since the outer edges 26X1, 26X2, 26Y1, and 26Y2 of the semiconductor layer 26 have four corners in a plan view, the outer periphery gate trench portion 312 has four bends in the outer periphery region 28.

[0104] The outer periphery gate trench portion 312 can be positioned to surround the inner region 30. The outer periphery gate trench portion 312 does not extend into the inner region 30. In plan view, the outer periphery gate trench portion 312 overlaps with both the gate finger portion 306 and the gate pad portion 308.

[0105] On the other hand, the connecting gate trench portion 316 overlaps with the gate finger portion 306 in a plan view, but does not overlap with the gate pad portion 308. The outer peripheral gate trench portion 312 extends along the outer edges 26X1, 26X2, 26Y1, 26Y2 of the semiconductor layer 26, rather than along the outer periphery of the active region 318. Therefore, the outer peripheral gate trench portion 312, located below the gate pad portion 308, is separated from the active region 318 in the X and Y directions by the dimensions of the gate pad portion 308. The outer peripheral gate trench portion 312, which overlaps with the gate pad portion 308 in a plan view, is not directly connected to the inner gate trench portion 314 of the active region 318 by the connecting gate trench portion 316.

[0106] The semiconductor device 300 may further include a protective trench 320 formed in the semiconductor layer 26. The protective trench 320 is formed in a closed annular shape along the outer edges 26X1, 26X2, 26Y1, 26Y2 of the semiconductor layer 26 in the peripheral region 28. That is, the protective trench 320 extends along the four sides 26X1, 26X2, 26Y1, 26Y2 of the semiconductor layer 26. In plan view, the protective trench 320 may have the same number of bends as the corners of the outer edges 26X1, 26X2, 26Y1, 26Y2 of the semiconductor layer 26. In the illustrated example, since the outer edges 26X1, 26X2, 26Y1, 26Y2 of the semiconductor layer 26 have four corners in plan view, the protective trench 320 has four bends in the peripheral region 28.

[0107] The protective trench 320 can be positioned to surround the outer periphery gate trench portion 312. Therefore, the protective trench 320 does not extend into the inner region 30. The outer periphery gate trench portion 312 is surrounded by the protective trench 320 in a plan view. The semiconductor device 300 may include a plurality of protective trenches 320.

[0108] Thus, the semiconductor device 300 differs from the semiconductor device 10 in that the gate pad portion 308 is located close to the corner where the edges 26X2 and 26Y2 of the semiconductor layer 26 intersect. On the other hand, similar to the semiconductor device 10, in the semiconductor device 300, the outer peripheral gate trench portion 312 and the protective trench 320 are formed in a closed annular shape along the outer edges 26X1, 26X2, 26Y1, and 26Y2 of the semiconductor layer 26 in the outer peripheral region 28. That is, the outer peripheral gate trench portion 312 and the protective trench 320 do not have a bend in the inner region 30. With this configuration, electric field concentration in the region surrounded by the outer peripheral gate trench portion 312 and the protective trench 320 can be mitigated. As a result, the drain-source leakage current I in the semiconductor device 300 is also reduced. DSS This can suppress the increase.

[0109] In the above embodiment, a structure in which the conductivity types of each region within the semiconductor layer 26 are reversed may be adopted. That is, a p-type region may become an n-type region, and an n-type region may become a p-type region.

[0110] One or more of the various examples described herein can be combined to the extent that they do not conflict with the technical specifications. In this specification, “at least one of A and B” should be understood to mean “A only, or B only, or both A and B.”

[0111] As used herein, the term “on” includes the meanings of “on” and “above” unless the context clearly indicates otherwise. Therefore, the expression “the first layer is formed on the second layer” is intended to mean that in one embodiment the first layer may be in contact with and directly positioned on the second layer, while in other embodiments the first layer may be positioned above the second layer without contact. In other words, the term “on” does not preclude structures in which another layer is formed between the first and second layers.

[0112] The terms used herein to indicate direction, such as “vertical,” “horizontal,” “upward,” “downward,” “up,” “down,” “forward,” “backward,” “lateral,” “left,” “right,” “front,” and “rear,” depend on the specific orientation of the apparatus described and illustrated. Various alternative orientations can be assumed in this disclosure, and therefore these terms indicating direction should not be interpreted narrowly.

[0113] For example, the Z direction as used herein does not necessarily have to be vertical, nor does it have to perfectly coincide with the vertical. Therefore, the various structures described herein (e.g., the structure shown in Figure 1) are not limited to the "up" and "down" in the Z direction described herein being the "up" and "down" in the vertical direction. For example, the X direction may be vertical, or the Y direction may be vertical.

[0114] [Note] The technical concepts that can be grasped from this disclosure are described below. Note that, not as an attempt to limit the scope but to aid understanding, the components described in the appendices are denoted by the corresponding reference numerals of the components in the embodiments. The reference numerals are provided as examples to aid understanding, and the components described in each appendice should not be limited to those indicated by the reference numerals.

[0115] (Note 1) Semiconductor layer (26), A gate trench (36) formed in the semiconductor layer (26), An insulating layer (60) formed on the semiconductor layer (26), A gate electrode (62) embedded in the gate trench (36) via the insulating layer (60), A gate wiring (22) is formed on the insulating layer (60) and electrically connected to the gate electrode (62), A protective trench (46) formed in the semiconductor layer (26) and Equipped with, The semiconductor layer (26) includes an outer peripheral region (28) that includes the outer edge (26X1, 26X2, 26Y1, 26Y2) of the semiconductor layer (26) in a plan view, and an inner region (30) surrounded by the outer peripheral region (28). The gate trench (36) includes an outer peripheral gate trench portion (38) which is located in the outer peripheral region (28) and is surrounded by the protective trench (46) in a plan view. The outer peripheral gate trench portion (38) and the protective trench (46) are formed in a closed annular shape along the outer edge (26X1, 26X2, 26Y1, 26Y2) of the semiconductor layer (26) in the outer peripheral region (28). Semiconductor equipment.

[0116] (Note 2) The semiconductor device according to Appendix 1, further comprising a protective electrode (76) embedded in the protective trench (46) via the insulating layer (60), wherein the protective electrode (76) is formed in a closed annular shape in plan view.

[0117] (Note 3) The gate trench (36) is The inner gate trench portion (40) is located in the inner region (30), A connecting gate trench section (42) that connects the outer peripheral gate trench section (38) to the inner gate trench section (40) including, Semiconductor device as described in Appendix 1 or 2.

[0118] (Note 4) The gate wiring (22) is The gate finger portion (32) is located in the outer peripheral region (28), A gate pad portion (34) is arranged across the inner region (30) and the outer peripheral region (28) Semiconductor devices as described in Appendix 3, including the semiconductor device described in Appendix 3.

[0119] (Note 5) The semiconductor device described in Appendix 4, wherein the connecting gate trench portion (42) overlaps with the gate finger portion (32) in a plan view, but does not overlap with the gate pad portion (34).

[0120] (Note 6) The semiconductor device according to Appendix 4 or 5, wherein the width of the outer peripheral gate trench portion (38) is greater than the width of the inner gate trench portion (40).

[0121] (Note 7) The semiconductor device according to any one of appendices 4 to 6, further comprising a gate contact portion (50) that extends through the insulating layer (60) and connects the gate finger portion (32) and the gate electrode (62).

[0122] (Note 8) The semiconductor layer (26) includes a drift region (68) of a first conductivity type, a body region (70) of a second conductivity type formed on the drift region (68), and a source region (72) of the first conductivity type formed on the body region (70). The semiconductor device according to any one of appendices 3 to 7, wherein the inner gate trench portion (40) penetrates the source region (72) and the body region (70) and reaches the drift region (68).

[0123] (Note 9) A source wiring (20) is formed on the insulating layer (60) and is separated from the gate wiring (22), A source contact portion (48) extends through the insulating layer (60) and connects the source wiring (20) and the semiconductor layer (26). The semiconductor device according to any one of the appendices 1 to 8, further comprising the source wiring (20) being surrounded by the gate wiring (22).

[0124] (Note 10) A semiconductor device according to any one of the appendices 1 to 9, further comprising an outer peripheral electrode (24) formed on the insulating layer (60) and separated from the gate wiring (22), wherein the outer peripheral electrode (24) surrounds the gate wiring (22).

[0125] The above description is illustrative only. Those skilled in the art will recognize that many more possible combinations and substitutions are possible beyond the components and methods (manufacturing processes) enumerated for the purpose of illustrating the technology of this disclosure. This disclosure is intended to encompass all alternatives, variations, and modifications that fall within the scope of this disclosure, including the claims. [Explanation of Symbols]

[0126] 10, 100, 200, 300… Semiconductor equipment 12… Passivation layer 14, 16… Pad opening 18...Metal layer 20,202,302… Source wiring 22,204,304…Gate wiring 24...Outer electrode 26… Semiconductor layer 26A…Side 1 26B…Second side 26X1, 26X2, 26Y1, 26Y2… outer edge 28…Outer area 30…Inner area 32,206,306… Gate finger section 34,208,308…Gate pad section 36,102,210,310…Gate trench 38,104,212,312…Outer perimeter gate trench section 40, 106, 214, 314… Inner gate trench section 42,108,216,316…Connecting gate trench section 44,218,318… Active area 46,110,220,320… Protective trench 48…Source Contact Department 50...Gate contact section 52...Outer contact area 54…Semiconductor substrate (drain region) 56…Epitaxial layer 58…Drain electrode 60...Insulating layer 62… Gate 64... Gate insulating film 66...Interlayer insulating film 68... Drift area 70...Body area 72…Source area 74… Contact area 76…Protective electrode 78…Protective insulating film

Claims

1. Semiconductor layer, A gate trench formed in the semiconductor layer, An insulating layer formed on the semiconductor layer, A gate electrode embedded in the gate trench via the insulating layer, A gate wiring formed on the insulating layer and electrically connected to the gate electrode, A protective trench formed in the semiconductor layer and Equipped with, The semiconductor layer includes an outer peripheral region that includes the outer edge of the semiconductor layer in a plan view, and an inner region surrounded by the outer peripheral region. The gate trench includes an outer periphery gate trench portion that is located in the outer periphery region and is surrounded by the protective trench in a plan view. The outer peripheral gate trench and the protective trench are formed in a closed annular shape along the outer edge of the semiconductor layer in the outer peripheral region. The gate trench is The inner gate trench portion is located in the inner region, A connecting gate trench portion that connects the outer peripheral gate trench portion to the inner gate trench portion. Includes, The aforementioned gate wiring is The gate finger portion arranged in the outer peripheral region, A gate pad portion is arranged across the inner region and the outer peripheral region. including, Semiconductor equipment.

2. A semiconductor device, Semiconductor layer, A gate trench formed in the semiconductor layer, An insulating layer formed on the semiconductor layer, A gate electrode embedded in the gate trench via the insulating layer, A gate wiring formed on the insulating layer and electrically connected to the gate electrode, A protective trench formed in the semiconductor layer and Equipped with, The semiconductor layer includes an outer peripheral region that includes the outer edge of the semiconductor layer in a plan view, and an inner region surrounded by the outer peripheral region. The gate trench includes an outer periphery gate trench portion that is located in the outer periphery region and is surrounded by the protective trench in a plan view. The outer peripheral gate trench and the protective trench are formed in a closed annular shape along the outer edge of the semiconductor layer in the outer peripheral region. The aforementioned semiconductor device is A source wiring formed on the insulating layer and separated from the gate wiring, A source contact portion extends through the insulating layer and connects the source wiring and the semiconductor layer. A semiconductor device further comprising the source wiring surrounded by the gate wiring.

3. A semiconductor device, Semiconductor layer, A gate trench formed in the semiconductor layer, An insulating layer formed on the semiconductor layer, A gate electrode embedded in the gate trench via the insulating layer, A gate wiring formed on the insulating layer and electrically connected to the gate electrode, A protective trench formed in the semiconductor layer and Equipped with, The semiconductor layer includes an outer peripheral region that includes the outer edge of the semiconductor layer in a plan view, and an inner region surrounded by the outer peripheral region. The gate trench includes an outer periphery gate trench portion that is located in the outer periphery region and is surrounded by the protective trench in a plan view. The outer peripheral gate trench and the protective trench are formed in a closed annular shape along the outer edge of the semiconductor layer in the outer peripheral region. The semiconductor device further comprises an outer electrode formed on the insulating layer and separated from the gate wiring, wherein the outer electrode surrounds the gate wiring.

4. The semiconductor device according to any one of claims 1 to 3, further comprising a protective electrode embedded in the protective trench via the insulating layer, wherein the protective electrode is formed in a closed annular shape in plan view.

5. The gate trench is The inner gate trench portion is located in the inner region, A connecting gate trench portion that connects the outer peripheral gate trench portion to the inner gate trench portion. including, The semiconductor device according to claim 2 or 3.

6. The aforementioned gate wiring is The gate finger portion arranged in the outer peripheral region, A gate pad portion is arranged across the inner region and the outer peripheral region. The semiconductor device according to claim 5, including the above.

7. The semiconductor device according to claim 1 or 6, wherein the connecting gate trench portion overlaps with the gate finger portion in a plan view, but does not overlap with the gate pad portion.

8. The semiconductor device according to any one of claims 1 or 6 to 7, wherein the width of the outer peripheral gate trench portion is greater than the width of the inner gate trench portion.

9. The semiconductor device according to any one of claims 1 or 6 to 8, further comprising a gate contact portion that extends through the insulating layer and connects the gate finger portion and the gate electrode.

10. The semiconductor layer includes a drift region of a first conductivity type, a body region of a second conductivity type formed on the drift region, and a source region of the first conductivity type formed on the body region. The semiconductor device according to any one of claims 1 or 5 to 9, wherein the inner gate trench portion penetrates the source region and the body region and reaches the drift region.

11. The semiconductor device according to claim 1 or 2, further comprising an outer peripheral electrode formed on the insulating layer and spaced apart from the gate wiring, wherein the outer peripheral electrode surrounds the gate wiring.

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