Memory controller, memory system, method, and storage medium for managing and handling datasets.

Abstract

In some aspects, the memory controller includes a data classification accelerator, a deallocation accelerator, and a mapping table accelerator. The data classification accelerator is configured to divide the deallocated logical range into a set of deallocation zones. The set of deallocation zones includes one or more first deallocation zones that are each classified into one or more alignment zones. The deallocation accelerator is operatively coupled to the data classification accelerator and configured to update a data set management (DSM) bitmap based on the one or more alignment zones. The mapping table accelerator is operatively coupled to the data classification accelerator and the deallocation accelerator. The mapping table accelerator is configured to generate a response indicating that the deallocated logical range is to be processed in response to updating the DSM bitmap.

Description

Technical Field

[0001] The present disclosure relates to a memory controller, a memory system, and an operating method thereof.

Background Art

[0002] Solid State Drives (SSDs) have become a widely adopted type of non-volatile data storage device in recent years due to numerous advantages over conventional Hard Disk Drives (HDDs), such as faster read and write speeds, durability and reliability, low power consumption, quiet operation, and smaller form factors. SSDs typically use NAND flash memory for non-volatile storage. Some SSDs, such as enterprise SSDs, may also use volatile memory (e.g., Dynamic Random Access Memory (DRAM)) to enhance performance, enabling faster access to data and more efficient handling of read and write operations.

Summary of the Invention

Means for Solving the Problems

[0003] In one aspect, a memory controller includes a data classification accelerator, a deallocation accelerator, and a mapping table accelerator. The data classification accelerator is configured to divide a deallocated logical range into a set of deallocation zones. The set of deallocation zones includes one or more first deallocation zones each classified into one or more alignment zones. The deallocation accelerator is operably coupled to the data classification accelerator and is configured to update a Data Set Management (DSM) bitmap based on the one or more alignment zones. The mapping table accelerator is operably coupled to the data classification accelerator and the deallocation accelerator. The mapping table accelerator is configured to generate a response indicating that the deallocated logical range is being processed in response to an update of the DSM bitmap.

[0004] In some implementations, the mapping table accelerator is further configured to update the logical-to-physical (L2P) mapping table based on the DSM bitmap.

[0005] In some implementations, to update the L2P mapping table based on the DSM bitmap, the mapping table accelerator is further configured to identify one or more alignment zones from the DSM bitmap and to update the L2P mapping table based on one or more alignment zones.

[0006] In some implementations, to update the L2P mapping table based on one or more alignment zones, the mapping table accelerator is further configured to identify a first list of logical addresses within one or more alignment zones and to invalidate the first list of logical addresses in the L2P mapping table.

[0007] In some implementations, the set of deallocated zones further includes one or more second deallocated zones, each classified into one or more unaligned zones. The mapping table accelerator is further configured to update the L2P mapping based on one or more unaligned zones and to generate responses that respond to both DSM bitmap updates and L2P mapping table updates based on one or more unaligned zones.

[0008] In some implementations, to update the L2P mapping table based on one or more unaligned zones, the mapping table accelerator is further configured to identify a second list of logical addresses within one or more unaligned zones and to invalidate the second list of logical addresses in the L2P mapping table.

[0009] In some implementations, the data classification accelerator is configured to divide the deallocated logical range into a set of deallocated zones based on the zoning of the logical space of a non-volatile memory device coupled to the memory controller, such that the division of the deallocated logical range matches the zoning of the logical space of the non-volatile memory device.

[0010] In some implementations, the logical space of a non-volatile memory device is divided into multiple logical zones. One or more first deallocation zones are each equal to one or more first logical zones, such that one or more first deallocation zones are each classified into one or more aligned zones, each aligned with one or more first logical zones from multiple logical zones. One or more second deallocation zones are each smaller than one or more second logical zones, such that one or more second deallocation zones are each classified into one or more unaligned zones, each not aligned with one or more second logical zones from multiple logical zones.

[0011] In some implementations, non-volatile memory devices include NAND flash memory.

[0012] In another embodiment, the memory system includes a non-volatile memory device and a memory controller operably coupled to the non-volatile memory device. The memory controller is configured to control the non-volatile memory device. The memory controller includes a data classification accelerator, a deallocation accelerator, and a mapping table accelerator. The data classification accelerator is configured to divide a deallocated logical range into a set of deallocation zones. The set of deallocation zones includes one or more first deallocation zones, each classified into one or more aligned zones. The deallocation accelerator is operably coupled to the data classification accelerator and is configured to update a DSM bitmap based on one or more aligned zones. The mapping table accelerator is operably coupled to the data classification accelerator and the deallocation accelerator. The mapping table accelerator is configured to generate a response indicating that the deallocated logical range is being processed in response to the update of the DSM bitmap.

[0013] In some implementations, the mapping table accelerator is further configured to update the L2P mapping table based on the DSM bitmap.

[0014] In some implementations, to update the L2P mapping table based on the DSM bitmap, the mapping table accelerator is further configured to identify one or more alignment zones from the DSM bitmap and to update the L2P mapping table based on one or more alignment zones.

[0015] In some implementations, to update the L2P mapping table based on one or more alignment zones, the mapping table accelerator is further configured to identify a first list of logical addresses within one or more alignment zones and to invalidate the first list of logical addresses in the L2P mapping table.

[0016] In some implementations, the set of deallocated zones further includes one or more second deallocated zones, each classified as one or more unaligned zones. The mapping table accelerator is further configured to update the L2P mapping table based on one or more unaligned zones and to generate responses based on one or more unaligned zones that respond to both DSM bitmap updates and L2P mapping table updates.

[0017] In some implementations, to update the L2P mapping table based on one or more unaligned zones, the mapping table accelerator is further configured to identify a second list of logical addresses within one or more unaligned zones and to invalidate the second list of logical addresses in the L2P mapping table.

[0018] In some implementations, the data classification accelerator is configured to divide the deallocated logical range into a set of deallocated zones based on the zoning of the logical space of the non-volatile memory device, so that the division of the deallocated logical range matches the zoning of the logical space of the non-volatile memory device.

[0019] In some implementations, the logical space of a non-volatile memory device is divided into multiple logical zones. One or more first deallocation zones are each equal to one or more first logical zones, such that one or more first deallocation zones are each classified into one or more aligned zones, each aligned with one or more first logical zones from multiple logical zones. One or more second deallocation zones are each smaller than one or more second logical zones, such that one or more second deallocation zones are each classified into one or more unaligned zones, each not aligned with one or more second logical zones from multiple logical zones.

[0020] In some implementations, non-volatile memory devices include NAND flash memory.

[0021] In yet another embodiment, a method for operating a memory controller is provided. The deallocated logical range is divided into a set of deallocated zones. The set of deallocated zones includes one or more first deallocated zones, each classified into one or more aligned zones. The DSM bitmap is updated based on one or more aligned zones. In response to the update of the DSM bitmap, a response is generated indicating that the deallocated logical range is to be processed.

[0022] In some implementations, the L2P mapping table is updated based on the DSM bitmap.

[0023] In some implementations, the step of updating the L2P mapping table based on a DSM bitmap includes the steps of identifying one or more alignment zones from the DSM bitmap and updating the L2P mapping table based on one or more alignment zones.

[0024] In some implementations, the step of updating the L2P mapping table based on one or more alignment zones includes the steps of identifying a first list of logical addresses within one or more alignment zones and invalidating the first list of logical addresses in the L2P mapping table.

[0025] In some implementations, the set of deallocated zones further includes one or more second deallocated zones, each classified as one or more unaligned zones. The method further includes the steps of updating the L2P mapping table based on one or more unaligned zones, and generating a response based on one or more unaligned zones that responds to both the DSM bitmap update and the L2P mapping table update.

[0026] In some implementations, the step of updating the L2P mapping table based on one or more non-aligned zones includes identifying a second list of logical addresses within the one or more non-aligned zones and invalidating the second list of logical addresses in the L2P mapping table.

[0027] In some implementations, the step of dividing the deallocated logical range into a set of deallocation zones includes dividing the deallocated logical range into a set of deallocation zones based on a zone division of the logical space of the non-volatile memory device coupled to the memory controller such that the division of the deallocated logical range coincides with the zone division of the logical space of the non-volatile memory device.

[0028] In some implementations, the logical space of the non-volatile memory device is divided into a plurality of logical zones. One or more first deallocation zones are each equal to their one or more first logical zones such that the one or more first deallocation zones are classified into one or more aligned zones aligned with the one or more first logical zones from the plurality of logical zones. One or more second deallocation zones are each smaller than their one or more second logical zones such that the one or more second deallocation zones are classified into one or more non-aligned zones not aligned with the one or more second logical zones from the plurality of logical zones.

[0029] In some implementations, the non-volatile memory device includes a NAND flash memory.

[0030] In yet another embodiment, a non-temporary computer-readable storage medium for storing instructions is disclosed. When the instructions are executed by the memory controller of the memory system, the memory controller causes the memory controller to execute a method. The method includes dividing a deallocated logical range into a set of deallocated zones. The set of deallocated zones includes one or more first deallocated zones, each classified into one or more aligned zones. The method also includes updating a DSM bitmap based on one or more aligned zones. In response to the update of the DSM bitmap, the method further includes generating a response indicating that the deallocated logical range is to be processed.

[0031] The accompanying drawings incorporated herein and forming part thereof illustrate aspects of the present disclosure and, together with the description, further serve to illustrate the principles of the present disclosure and enable those skilled in the art to prepare and use the present disclosure. [Brief explanation of the drawing]

[0032] [Figure 1] This is a block diagram of a system including a memory system according to some aspects of the present disclosure. [Figure 2A] This is a diagram of a memory card having a memory device according to some aspects of the present disclosure. [Figure 2B] This is a diagram of an SSD having a memory device according to some aspects of the present disclosure. [Figure 3] This is a block diagram of a memory controller according to some aspects of the present disclosure. [Figure 4] This is a schematic diagram of a NAND flash memory device including peripheral circuits according to some aspects of the present disclosure. [Figure 5] This is a schematic diagram of a DRAM device including peripheral circuits according to some aspects of the present disclosure. [Figure 6] This is a detailed schematic diagram of a memory system for DSM handling according to several aspects of the present disclosure. [Figure 7]This figure shows an L2P mapping table according to several aspects of this disclosure. [Figure 8A] This figure shows an example of updating a DSM bitmap according to several aspects of this disclosure. [Figure 8B] This figure shows another example of updating a DSM bitmap according to some aspects of this disclosure. [Figure 9] This is a flowchart of a method for operating a memory controller according to some aspects of the present disclosure. [Figure 10] This is a flowchart of another method for operating a memory controller according to some aspects of the present disclosure. [Modes for carrying out the invention]

[0033] This disclosure will be explained with reference to the attached drawings.

[0034] In general, terms can be understood at least partially from their usage in context. For example, the term “one or more” as used herein may, at least partially depending on the context, be used to describe any feature, structure, or characteristic in a singular sense, or to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as “a,” “an,” or “the” can be understood, at least partially depending on the context, to convey either a singular or plural usage. In addition, the term “based on” may be understood not necessarily to convey an exhaustive set of factors, and instead, at least partially depending on the context, may allow for the presence of additional factors that are also not necessarily explicitly described.

[0035] The Non-Volatile Memory Express (NVMe) specification defines DSM commands that can be used to mark unused host data space to improve host performance. For example, a DSM command may indicate a logical range that should be deallocated (or freed) by the host. In response to receiving a DSM command, a memory controller coupled to a non-volatile memory device may handle the deallocation of the logical range. For example, the memory controller may deallocate or free one or more logical addresses, such as logical block addresses (LBAs) included in the DSM command. In a further example, the memory controller may deallocate or free one or more logical addresses from the logical space of a non-volatile memory device coupled to the memory controller. If the logical range is small, the memory controller may deallocate the logical range quickly. The DSM response time (e.g., the time to send a response to the host indicating that the deallocation is complete) is short. However, if the logical range is large, the deallocation of the logical range by the memory controller can consume a significant amount of time. The DSM response time to the host is long, which can affect the host's read / write input / output (I / O) latency.

[0036] To address the aforementioned issues, this disclosure introduces a handling method that can reduce the DSM response time associated with the allocation of large logical ranges, thereby reducing the impact of DSM handling on host I / O latency. Specifically, a DSM command may instruct a large logical range to be deallocated. The large logical range may be divided into a set of deallocation zones, which may include at least one of (1) one or more first deallocation zones, each classified into one or more aligned zones, or (2) one or more second deallocation zones, each classified into one or more unaligned zones. One or more unaligned zones may be processed directly to update the L2P mapping table, such that a list of logical addresses in one or more unaligned zones may be marked as invalid addresses in the L2P mapping table. Alternatively, one or more aligned zones may be processed to update the DSM bitmap to record the corresponding deallocation information in the DSM bitmap. Then, before the L2P mapping table is updated for one or more aligned zones, a response indicating that the deallocated logical range has been processed may be generated and sent to the host. Subsequently, after the response is sent to the host, one or more aligned zones may be deallocated in the background based on the DSM bitmap, so that another list of logical addresses within one or more aligned zones may be marked as invalid addresses in the L2P mapping table. Therefore, since the response may be sent to the host before one or more aligned zones are actually deallocated by the memory controller, DSM handling can reduce the DSM response time to DSM commands. The impact of DSM handling on host I / O latency can be reduced.

[0037] The handling methods disclosed herein are intended to be applicable not only to handling DSM commands related to the NVMe specification, but also to handling commands related to other standards not limited herein. For example, the handling methods disclosed herein may also be applicable to handling Trim commands. The Trim command is a command that informs a solid-state drive (SSD) which LBAs are no longer needed by the host. The SSD may update its own internal records to mark an LBA as invalid (for example, by updating the corresponding entry in the logical-to-physical (L2P) mapping table to an empty address, clearing the corresponding bit in the valid page bitmap, updating the valid page count, etc.). The SSD no longer has to move LBAs that are internally marked as invalid blocks during garbage collection, which eliminates the time wasted writing invalid data back to a new flash page. In another example, the handling methods disclosed herein may also be applicable to handling UNMAP commands, which are Small Computer System Interface (SCSI) commands that a host can issue to a storage array to release LBAs that are no longer needed for allocation.

[0038] Figure 1 shows a block diagram of a system 100 including a memory system 102, according to several aspects of the present disclosure. System 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet, an in-vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage. As shown in Figure 1, system 100 may include a host 108 and a memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 may be a processor of an electronic device such as a central processing unit (CPU), or a system-on-a-chip (SoC) such as an application processor (AP). The host 108 may be configured to send data (also known as user data or host data) to or receive data from the memory system 102. The memory system 102 may be a storage product integrating the memory controller 106 and one or more memory devices 104 such as an SSD.

[0039] The memory device 104 may be any memory device disclosed in this disclosure, including non-volatile memory devices such as NAND flash memory devices. In some implementations, the memory device 104 also includes one or more volatile memory devices, such as DRAM devices or static random-access memory (SRAM) devices.

[0040] In some implementations, the memory controller 106 is operably coupled to the memory device 104 and the host 108 and configured to control the memory device 104. The memory controller 106 can manage the data stored in the memory device 104 and communicate with the host 108. In some implementations, the memory controller 106 is designed to operate in low-duty-cycle environments, such as Secure Digital (SD) cards, CompactFlash (CF) cards, Universal Serial Bus (USB) flash drives, or other media for use in electronic devices such as personal computers, digital cameras, and mobile phones. In some implementations, the memory controller 106 is designed to operate in high-duty-cycle environments with SSDs or embedded multimedia cards (eMMC) used as data storage for mobile devices such as smartphones, tablets, and laptop computers, and in enterprise storage arrays. The memory controller 106 may be configured to control the operation of the memory device 104, such as read operations, program / write operations, and / or erase operations. The memory controller 106 may also be configured to manage various functions relating to data stored or to be stored in the memory device 104, including, but not limited to, bad block management, garbage collection, L2P address translation, and wear leveling. In some implementations, the memory controller 106 may be further configured to handle error correction codes (ECC) relating to data read from and written to the memory device 104. Any other appropriate functions, such as formatting the memory device 104, may also be performed by the memory controller 106. The memory controller 106 may communicate with an external device (e.g., host 108) according to a specific communication protocol.For example, the memory controller 106 may communicate with external devices through at least one of various interface protocols, such as the Non-Volatile Memory Express (NVMe) protocol, NVMe-over-fabrics (NVMe-oF) protocol, PCI-express (PCI-E) protocol, Universal Serial Bus (USB) protocol, Multimedia Card (MMC) protocol, Peripheral Component Interconnection (PCI) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, and Firewire protocol.

[0041] The memory controller 106 and one or more memory devices 104 may be integrated into various types of storage devices, for example, in the same package such as a Universal Flash Storage (UFS) package or an eMMC package. That is, the memory system 102 can be implemented and packaged in different types of final electronic products. In one example, as shown in Figure 2A, the memory controller 106 and a single memory device 104 may be integrated into a memory card 202. The memory card 202 may include PC cards (PCMCIA, personal computer memory card international association), CF cards, SmartMedia (SM) cards, Memory Sticks, Multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may further include a memory card connector 204 that connects the memory card 202 to a host (for example, the host 108 in Figure 1). In another example, as shown in Figure 2B, the memory controller 106 and multiple memory devices 104 may be integrated into an SSD 206. The SSD206 may further include an SSD connector 208 that connects the SSD206 to a host (for example, host 108 in Figure 1). In some implementations, the storage capacity and / or operating speed of the SSD206 are greater than those of the memory card 202. In some implementations, the memory system 102 is implemented as an SSD206 that includes both non-volatile memory devices and volatile memory devices, such as memory device 104, such as an enterprise SSD.

[0042] Figure 3 shows a block diagram of a memory controller 300 according to several aspects of this disclosure. The memory controller 300 may be an example of the memory controller 106 in Figure 1. As shown in Figure 3, the memory controller 300 may include a processing unit 308, a cache 310, and a read-only memory (ROM) 311. In some implementations, the processing unit 308 is implemented by a microprocessor (e.g., a digital signal processor (DSP)) or microcontroller (also known as a microcontroller unit (MCU)) that runs firmware and / or software modules to perform the various functions described herein. The various firmware modules in the memory controller 300 described herein may be implemented as firmware code or instructions stored in the ROM 311 and executed by the processing unit 308. In some implementations, the processing unit 308 includes one or more hardware circuits, such as fixed logic units, including logic gates, multiplexers, flip-flops, state machines, field-programmable gate arrays (FPGAs), and programmable logic devices (PLDs). For example, hardware circuits may include dedicated circuits that perform a given logic function known during the manufacturing of devices such as application-specific integrated circuits (ASICs).

[0043] As shown in Figure 3, the memory controller 300 may also include various input / output (I / O) interfaces (I / F) such as a non-volatile memory interface 312, a DRAM interface 314, and a host interface 316, which are operably coupled to the non-volatile memory device 302, the DRAM 304 (for example, an example of a volatile memory device), and the host 306 (for example, an example of a host 108), respectively. The non-volatile memory interface 312, the DRAM interface 314, and the host interface 316 may be configured to transfer data, commands, clocks, or any appropriate signals between the processing unit 308 and the non-volatile memory device 302, the DRAM 304, and the host 306, respectively. The non-volatile memory interface 312, the DRAM interface 314, and the host interface 316 can implement any appropriate communication protocol that facilitates data transfer, communication, and management, such as the NVMe protocol and the PCI-E protocol, and the Double Data Rate (DDR) protocol, to name a few.

[0044] As described above, both the cache 310 and the DRAM 304 can be considered volatile memory devices that can be controlled and accessed by the memory controller 300 in a memory system. Without being inconsistent with the scope of this disclosure, the cache may be implemented as part of a volatile memory device, for example, by SRAM and / or DRAM 304. Figure 3 shows that the cache 310 is located within the memory controller 300, while the DRAM 304 is understood to be located outside the memory controller 300. In some examples, both the cache 310 and the DRAM 304 may be located either within or outside the memory controller 300.

[0045] Figure 4 shows a schematic circuit diagram of a NAND flash memory device 400 including peripheral circuitry 402 according to several embodiments of the present disclosure. The NAND flash memory device 400 may be an example of the non-volatile memory device 302 in Figure 3. The NAND flash memory device 400 may include a memory cell array 401 and peripheral circuitry 402 operably coupled to the memory cell array 401. The memory cells 406 in the memory cell array 401 are provided in the form of an array of memory strings 408, each extending vertically on a substrate (not shown). In some implementations, each memory string 408 includes a plurality of memory cells 406 operably coupled in series and stacked vertically. Each memory cell 406 can hold a continuous analog value, such as voltage or charge, which depends on the number of electrons confined in the region of the memory cell 406. Each memory cell 406 may be either a floating-gate memory cell including a floating-gate transistor, or a charge-trap memory cell including a charge-trap transistor.

[0046] In some implementations, each memory cell 406 is a single-level cell (SLC) with two possible levels (memory states) and therefore capable of storing one bit of data. For example, the first state "0" may correspond to a first range of threshold voltage, and the second state "1" may correspond to a second range of threshold voltage. In some implementations, each memory cell 406 is an xLC capable of storing multiple bits of data with more than four levels. For example, an xLC may store 2 bits per cell (also known as a multi-level cell (MLC)), 3 bits per cell (also known as a triple-level cell (TLC)), or 4 bits per cell (also known as a quad-level cell (QLC)). Each xLC has a range of possible nominal storage values ​​(i.e., 2 N It can be programmed assuming that each N-bit data corresponds to 2 NIt is set to one of the individual levels, and N is an integer greater than 1. N can represent the total number of bits per cell. For example, N=2 for MLC, N=3 for TLC, or N=4 for QLC.

[0047] As shown in Figure 4, each memory string 408 may also include a source selection gate (SSG) transistor 410 on the source side and a drain selection gate (DSG) transistor 412 on the drain side. The SSG transistor 410 and DSG transistor 412 may be configured to activate the selected memory string 408 (a column of the array) during read and program operations. In some implementations, the sources of the memory strings 408 in the same block 404 are coupled through the same source line (SL) 414, for example, a common SL. In other words, according to some implementations, all memory strings 408 in the same block 404 have an array common source (ACS). According to some implementations, the drain of each memory string 408 is coupled to a respective bit line 416 from which data can be read and written via an output bus (not shown). In some implementations, each memory string 408 is configured to be selected or deselected by applying a selection voltage or deselection voltage to the gate of each DSG transistor 412 through one or more DSG lines 413, and / or by applying a selection voltage or deselection voltage to the gate of each SSG transistor 410 through one or more SSG lines 415.

[0048] As shown in Figure 4, the memory string 408 may be organized into multiple blocks 404, each of which may have a common source line 414 coupled to, for example, ACS. In some implementations, each block 404 is the basic data unit for the erase operation, i.e., all memory cells 406 on the same block 404 are erased simultaneously. To erase the memory cells 406 in the selection block 404, the source line 414 coupled to the selection block 404, as well as the deselection block 404 on the same plane as the selection block 404, may be biased with an erase voltage (Vers), such as a high positive bias voltage (e.g., 20V or higher).

[0049] The memory cells 406 of adjacent memory strings 408 may be connected via word lines 418, which select which rows of memory cell 406 are affected by read and program operations. In some implementations, each word line 418 is connected to a physical page 420 of memory cell 406, which is the basic data unit for read and write (program) operations. The size of one physical page 420 in bits may relate to the number of memory strings 408 connected by word lines 418 in one block 404. Each word line 418 may include multiple control gates (gate electrodes) in each memory cell 406 within its respective physical page 420, and gate lines connecting the control gates.

[0050] The peripheral circuit 402 may be operably coupled to the memory cell array 401 through bit lines 416, word lines 418, source lines 414, SSG lines 415, and DSG lines 413. The peripheral circuit 402 may include any suitable analog, digital, and mixed-signal circuits to facilitate the operation of the memory cell array 401 by applying voltage and / or current signals to each selected memory cell 406 through bit lines 416, word lines 418, source lines 414, SSG lines 415, and DSG lines 413, and by sensing voltage and / or current signals from each memory cell 406. The peripheral circuit 402 may include various types of peripheral circuits formed using complementary metal-oxide-semiconductor (CMOS) technology.

[0051] Figure 5 shows a schematic circuit diagram of a DRAM device 500 including peripheral circuits 502 according to several embodiments of the present disclosure. The DRAM device 500 may be an example of the DRAM 304 in Figure 3. The DRAM device 500 may include a memory cell array 501 and peripheral circuits 502 operably coupled to the memory cell array 501. The memory cells 503 may be arranged in the memory cell array 501 having rows and columns. The DRAM device 500 requires periodic refreshing of the memory cells 503. In some implementations, each memory cell 503 includes a capacitor 507 for storing bits of data as positive or negative charge, as well as a transistor 505 that controls access to the capacitor 507. That is, according to some implementations, each memory cell 503 shown in Figure 5 is a 1-transistor 1-capacitor (1T1C) cell.

[0052] The DRAM device 500 may include word lines 504 connecting peripheral circuits 502 to the memory cell array 501 for controlling the switching of transistors 505 in memory cells 503 located in rows, and bit lines 506 connecting peripheral circuits 502 to the memory cell array 501 for sending data to and / or receiving data from memory cells 503 located in columns. That is, each word line 504 is connected to each row of memory cells 503, and each bit line 506 is connected to each column of memory cells 503. The gate of transistor 505 may be connected to a word line 504, one of the source and drain of transistor 505 may be connected to a bit line 506, the other of the source and drain of transistor 505 may be connected to one electrode of capacitor 507, and the other electrode of capacitor 507 may be connected to ground.

[0053] The peripheral circuitry 502 may be coupled to the memory cell array 501 through bit lines 506, word lines 504, and any other suitable metal wiring. The peripheral circuitry 502 may include any suitable circuitry to facilitate the operation of the memory cell array 501 by applying voltage and / or current signals to each memory cell 503 through word lines 504 and bit lines 506, and by sensing voltage and / or current signals from each memory cell 503. The peripheral circuitry 502 may include various types of peripheral circuits formed using CMOS technology.

[0054] Figure 6 shows a detailed schematic diagram of a memory system 600 for DSM handling according to several embodiments of this disclosure. The memory system 600 may be an example of the memory system 102 in Figure 1. As shown in Figure 6, the memory system 600 may include a memory controller 601, a volatile memory device 602, and a non-volatile memory device 604. The memory controller 601 may be an example of the memory controller 106 in Figure 1. The volatile memory device 602 and the non-volatile memory device 604 may be examples of the memory device 104 in Figure 1. In some implementations, the volatile memory device 602 includes a DRAM (e.g., the DRAM device 500 in Figure 5), and the non-volatile memory device 604 includes a NAND flash memory (e.g., the NAND flash memory device 400 in Figure 4). In some implementations, the memory controller 601 is further configured to cache one host / user data in the volatile memory device 602 or to flash that host / user data from the volatile memory device 602 to the non-volatile memory device 604.

[0055] To enable data retrieval and access, the non-volatile memory device 604 may be divided into multiple memory regions 605, each having a unique physical address. In some implementations, each memory region 605 contains one or more logical pages, for example, a portion of a single physical page 420 of the NAND flash memory device 400 (e.g., 1 / 2, 1 / 4, or 1 / 8). For example, the size of each memory region 605 may be 4096 bytes. It is understood that a memory region 605 may correspond to any suitable group of memory cells in the non-volatile memory device 604 other than a page, such as a page, a block (e.g., block 404 of the NAND flash memory device 400), or other portions. For example, the physical address of a memory region 605 may be called a physically allocated address (PAA), and the logical address corresponding to a PAA may be called a logical allocated address (LAA). In another example, the physical address of memory region 605 may be a physical page address (PAA) when memory region 605 corresponds to a page of non-volatile memory device 604, and the logical address corresponding to the PAA may be a logical block address (LBA).

[0056] Cache 606 may be a portion of volatile memory device 602 that temporarily stores (caches) frequently used and / or recently accessed data to speed up read and write operations of non-volatile memory device 604. Any suitable cache algorithm can be used to determine which data should be stored in cache 606, and when the data should be exchanged, including, for example, least recently used (LRU), most recently used (MRU), and first-in, first-out (FIFO). In some implementations, data from the host (host / user data) is first cached in cache 606 of volatile memory device 602 and then flushed to non-volatile memory device 604 under certain conditions based on the cache algorithm. For example, when the size of the data in cache 606 reaches a preset threshold (maximum cache size), the data in cache 606 may be flushed to non-volatile memory device 604. Cache 606 can be implemented by any suitable type of volatile memory device 602, such as DRAM 304 and / or SRAM.

[0057] In some implementations, the DSM bitmap may be stored in the cache 606, while in some other implementations, the DSM bitmap may be stored in a register (not shown) of the memory controller 601. The DSM bitmap may also be stored in a non-volatile memory device 604, and this is not limited herein.

[0058] To enable data retrieval and access, an L2P mapping table 612 may be maintained and stored in a volatile memory device 602 to map the logical address of data to the physical address 616 (e.g., PPA) of a memory region 605 in a non-volatile memory device 604. The logical address can identify host / user data and may be known to the memory controller 601. In some implementations, the logical address indicates the basic logical unit of data for each read and write operation, such as a logical block address (LBA). In some implementations, the size of each memory region 605 and the size of the data corresponding to each logical address may be the same. For example, the size of the data corresponding to each logical address may also be 4096 bytes. Since the memory controller 601 operates based on logical addresses, as opposed to physical addresses (e.g., physical address 616), the L2P mapping table 612 may be used to enable conversion between logical and physical addresses.

[0059] In some implementations, the L2P mapping table 612 may be stored in a non-volatile memory device 604. In some other implementations, the L2P mapping table 612 may be stored in any suitable type of volatile memory device 602, such as the DRAM 304 in Figure 3. For example, the same volatile memory device 602, such as the DRAM 304 in Figure 3, contains both the cache 606 and the L2P mapping table 612. In some examples, it is understood that the cache 606 and the L2P mapping table 612 may be contained in different volatile memory devices 602. For example, the cache 606 may be contained in SRAM, while the DRAM 304 may contain the L2P mapping table 612. In Figure 6, the L2P mapping table 612 is shown as being outside the cache 606, but in some examples, it is understood that the L2P mapping table 612 may also be stored in the cache 606.

[0060] In some implementations, the L2P mapping table 612 may be stored in the volatile memory device 602 using addresses within the volatile memory device 602. For example, as shown in Figure 7, the L2P mapping table 612 may contain addresses 704 (volatile memory (VM) addresses) within the volatile memory device 602, each associated with a value 706. Values ​​706 may contain physical addresses 616 (e.g., PPAs) of memory regions 605 (e.g., PPA1, PPA2, PPA3, PPA4, etc.) within the non-volatile memory device 604. As shown in Figure 7, the L2P mapping table 612 may map the logical addresses 702 (LBAs) of host / user data to the physical addresses 616 of memory regions 605 within the non-volatile memory device 604 via addresses 704. For example, for each host / user data, the corresponding address 704 for the entry in the L2P mapping table 612 within the volatile memory device 602 may be determined based on the respective LBA 702 associated with that host / user data. In one example shown in Figure 7, each LBA 702 associated with an entry (e.g., 0, 1, 2, 3, 4, 5, 6, etc.) can be multiplied by the entry size Δ and added to the address offset (OFF) to form the corresponding address 704 of the entry (e.g., address 704 = OFF + LBA × Δ), where the entry size Δ may represent the length of the value 706 stored in the entry (e.g., Δ = 4 bytes). The address offset may be determined, for example, based on where the L2P mapping table 612 is stored in the volatile memory device 602. Thus, the corresponding value 706 at the determined address 704 in the L2P mapping table 612 may be determined, which represents the physical address 616 of the memory region in the non-volatile memory device 604. Therefore, each LBA 702 of the host / user data may be mapped by the L2P mapping table 612 to multiple physical addresses (e.g., the physical address 616 of the memory region 605 in the non-volatile memory device 604).

[0061] Referring back to Figure 6, the memory controller 601 may include a number of I / O interfaces, including a volatile memory interface 620 operably coupled to a volatile memory device 602, a non-volatile memory interface 622 operably coupled to a non-volatile memory device 604, and a host interface 618 operably coupled to the cache 606 of the volatile memory device 602 and a host (not shown). Examples of these I / O interfaces may include the DRAM interface 314, the non-volatile memory interface 312, and the host interface 316 in Figure 3, which may implement any suitable communication protocol to facilitate data transfer, communication, and management, such as the NVMe protocol, PCI-E protocol, and DDR protocol, to name a few.

[0062] The host interface 618 may be configured to receive write and read requests from the host. Each write request may indicate one piece of data associated with a logical address (e.g., LBA) to be written to the memory system 600. Similarly, each read request may indicate one piece of data associated with a logical address (e.g., LBA) to be read from the memory system 600. In some implementations, in response to receiving a write or read request, the host interface 618 is also configured to fetch that data from the host to temporarily store (cach) it in the cache 606, and vice versa. For example, the host interface 618 may include a direct memory access (DMA) unit that accesses data from or to the cache 606.

[0063] In some implementations, the host interface 618 may be configured to receive DSM commands from the host and send DSM commands to the data classification accelerator 608. The DSM commands may indicate deallocated logical ranges. For example, a DSM command may indicate a logical range to be deallocated from the logical space of the non-volatile memory device 604. For example, a DSM command may indicate a logical range to be disabled from the logical space of the non-volatile memory device 604, so that the host (or memory controller 601) no longer needs to access the disabled logical addresses within the logical range. In some implementations, the host interface 618 may be configured to receive a response 617 to the DSM command from the mapping table accelerator 611 and send the response 617 to the host. The data classification accelerator 608, the mapping table accelerator 611, and the response 622 are described in more detail below.

[0064] The non-volatile memory interface 622 may be configured to allow the memory controller 601 to access data stored in the non-volatile memory device 604 based on the physical address (e.g., PPA) of the memory region 605. The volatile memory interface 620 may be configured to allow the memory controller 601 to access data stored in the volatile memory device 602, for example, by managing the L2P mapping table 612 to access data in the cache 606.

[0065] As shown in Figure 6, the memory controller 601 may further include a data classification accelerator 608, a deallocation accelerator 610, and a mapping table accelerator 611, which are operably coupled to the host interface 618, the non-volatile memory interface 622, and the volatile memory interface 620, respectively. In some implementations, the data classification accelerator 608, the deallocation accelerator 610, and the mapping table accelerator 611 are firmware modules implemented by firmware code / instructions stored in memory (e.g., ROM 311 in Figure 3 or the non-volatile memory device 302 in Figure 3) and executed by a processing unit (e.g., processing unit 308 in Figure 3). In some implementations, the data classification accelerator 608, the deallocation accelerator 610, and the mapping table accelerator 611 are implemented in software using code / instructions stored in memory (e.g., ROM 311 in Figure 3 or non-volatile memory device 302 in Figure 3) and executed by a processing unit (e.g., processing unit 308 in Figure 3). In some implementations, the data classification accelerator 608, the deallocation accelerator 610, and the mapping table accelerator 611 are hardware modules implemented by dedicated circuitry, such as ASICs, for performing the dedicated functions described herein. Hardware implementations of the data classification accelerator 608, the deallocation accelerator 610, and the mapping table accelerator 611 can reduce firmware overhead and thereby improve the performance of the memory system 600.

[0066] The data classification accelerator 608 may be configured to receive DSM commands from the host interface 618. The DSM commands may indicate a logical range to be deallocated (for example, a logical range to be allocated from the logical space of the non-volatile memory device 604). The data classification accelerator 608 may divide the logical range into a set of deallocation zones. For example, the data classification accelerator 608 may divide the logical range into a set of deallocation zones based on the zoning of the logical space of the non-volatile memory device 604, such that the division of the logical range matches the zoning of the logical space of the non-volatile memory device 604.

[0067] For example, the logical space of the non-volatile memory device 604 may be divided into multiple logical zones (for example, each logical zone having a size of 16 MiB). The logical range may then be divided into a set of deallocated zones such that each deallocated zone may be identical to a particular logical zone from the multiple logical zones (for example, the deallocated zone has the same boundary as a particular logical zone) or smaller than a particular logical zone from the multiple logical zones (for example, the deallocated zone lies within the boundary of a particular logical zone). If a deallocated zone is identical to a particular logical zone, the deallocated zone may be classified as an aligned zone, indicating that the deallocated zone is aligned with the particular logical zone. If a deallocated zone is smaller than a particular logical zone and lies within that particular logical zone, the deallocated zone may be classified as an unaligned zone, indicating that the deallocated zone is not aligned with that particular logical zone. Examples of aligned and unaligned zones are shown below with respect to Figures 8A and 8B.

[0068] In some implementations, a set of deallocated zones separated from a logical range may include one or more first deallocated zones, each classified into one or more aligned zones. For example, one or more first deallocated zones may each be equal to one or more first logical zones, such that one or more first deallocated zones may each be classified into one or more aligned zones, each being classified into one or more first logical zones from multiple logical zones. In some implementations, a set of deallocated zones may include one or more second deallocated zones, each classified into one or more unaligned zones. For example, one or more second deallocated zones may each be smaller than one or more second logical zones, such that one or more second deallocated zones may each be classified into one or more unaligned zones, each being classified into one or more second logical zones from multiple logical zones. In some other implementations, the set of deallocation zones may include a combination of (1) one or more first deallocation zones, each classified into one or more aligned zones, and (2) one or more second deallocation zones, each classified into one or more unaligned zones.

[0069] The deallocation accelerator 610 may be configured to update the DSM bitmap based on one or more aligned zones. Initially, the DSM bitmap may be generated and started for multiple logical zones of the non-volatile memory device 604. For example, each DSM bitmap may contain multiple bits for multiple logical zones, each bit corresponding to a respective logical zone and initially having a first value (e.g., "0"). Next, for each aligned zone, the deallocation accelerator 610 may update the DSM bitmap and modify the corresponding bit for the aligned zone to have a second value (e.g., "1"). The corresponding bit having a second value may indicate that the aligned zone (or equivalently, the same logical zone as the aligned zone) should be deallocated from the logical space of the non-volatile memory device 604. The deallocation accelerator 610 may then send the updated DSM bitmap to the mapping table accelerator 611. An example of a DSM bitmap is shown below with reference to Figures 8A and 8B.

[0070] As will be described in more detail below, the mapping table accelerator 611 may be configured to update the L2P mapping table 612 based on one or more unaligned zones, a DSM bitmap, or both. Without being inconsistent with some implementations of this disclosure, the set of deallocated zones to be separated from a logical range may include one or more first deallocated zones, each classified into one or more aligned zones. In this case, the deallocation accelerator 610 may update the DSM bitmap based on one or more aligned zones and send the DSM bitmap to the mapping table accelerator 611. The mapping table accelerator 611 may generate a response 617 indicating that the logical range is processed in response to the update of the DSM bitmap. For example, the mapping table accelerator 611 may generate a response 617 indicating that the logical range is deallocated from the logical range of the non-volatile memory device 604 in response to the update of the DSM bitmap. The mapping table accelerator 611 may forward the response 617 to the host interface 618, causing the host interface 618 to send the response 617 to the host.

[0071] Subsequently, the mapping table accelerator 611 may be configured to update the L2P mapping table 612 based on the DSM bitmap in order to actually deallocate one or more aligned zones (for example, to actually deallocate one or more aligned zones from the logical space of the non-volatile memory device 604). That is, the mapping table accelerator 611 may identify one or more aligned zones from the DSM bitmap and update the L2P mapping table 612 based on one or more aligned zones in order to deallocate one or more aligned zones. For example, the mapping table accelerator 611 may identify one or more bits from the DSM bitmap, each having a second value, and determine one or more aligned zones as one or more logical zones corresponding to one or more bits. The mapping table accelerator 611 may identify a first list of logical addresses in one or more logical zones and invalidate a first list of logical addresses in the L2P mapping table 612.

[0072] To invalidate the first list of logical addresses in the L2P mapping table 612, the mapping table accelerator 611 may determine a list of entries from the L2P mapping table 612 corresponding to the first list of logical addresses and modify each entry to have a predetermined value "X" (for example, X may be any suitable value, and is not limited thereto). By setting an entry in the L2P mapping table 612 as the predetermined value "X", the logical address corresponding to the entry may be marked as an invalid logical address in the L2P mapping table 612. For example, referring again to Figure 7, the value 706 of the first entry in the L2P mapping table 612 is modified from "PPA0" to the predetermined value "X", indicating that the logical address "0" associated with the first entry in the L2P mapping table 612 is marked as an invalid logical address and deallocated. Similarly, the value 706 of the second entry in the L2P mapping table 612 is changed from "PPA1" to a predetermined value "X", which indicates that the logical address "1" associated with the second entry in the L2P mapping table 612 is marked as an invalid logical address and deallocated.

[0073] Referring back to Figure 6, in some implementations, response 617 may be generated and sent to the host after the DSM bitmap update but before the L2P mapping table based on the DSM bitmap is updated (for example, before the actual deallocation of one or more aligned zones). In this case, the deallocation of one or more aligned zones can be performed in the background after response 617 is sent to the host, thus reducing the response time to the DSM command. This can reduce the response latency to the DSM command and also reduce the impact of the DSM operation on host read / write I / O latency. In some other implementations, response 617 may be generated and sent to the host after the L2P mapping table based on the DSM bitmap is updated. In this case, one or more aligned zones have already been deallocated when response 617 is sent to the host.

[0074] Without inconsistency with some implementations of this disclosure, the set of deallocated zones may include one or more second deallocated zones, each classified as one or more unmarried zones. The mapping table accelerator 611 may update the L2P mapping table 612 based on one or more unmarried zones. That is, the mapping table accelerator 611 may identify a second list of logical addresses in one or more unmarried zones and invalidate the second list of logical addresses in the L2P mapping table 612. For example, the mapping table accelerator 611 may modify the list of entries in the L2P mapping table 612 corresponding to the second list of logical addresses to have a predetermined value "X". The mapping table accelerator 611 may then generate a response 617 in response to the update of the L2P mapping table 612 based on one or more unmarried zones. In some implementations, the response 617 may be generated and sent to the host after the update of the L2P mapping table 612 based on one or more unmarried zones (for example, after one or more unmarried zones have already been deallocated).

[0075] Without being inconsistent with some implementations of this disclosure, the set of deallocated zones may include both (1) one or more first deallocated zones, each classified into one or more aligned zones, and (2) one or more second deallocated zones, each classified into one or more unaligned zones. In this case, the deallocation accelerator 610 may update the DSM bitmap based on one or more aligned zones. The mapping table accelerator 611 may update the L2P mapping table 612 based on one or more unaligned zones so that one or more unaligned zones can be deallocated from the logical space of the non-volatile memory device 604. In response to both (1) the update of the DSM bitmap by the deallocation accelerator 610 and (2) the update of the L2P mapping table 612 based on one or more unaligned zones, the mapping table accelerator 611 may generate a response 617 indicating that the zones are deallocated from the logical space of the non-volatile memory device 604. The mapping table accelerator 611 may forward the response 617 to the host interface 618, causing the host interface 618 to send the response 617 to the host. Furthermore, the mapping table accelerator 611 may update the L2P mapping table 612 based on the DSM bitmap so that one or more alignment zones can also be deallocated from the logical space of the non-volatile memory device 604.

[0076] In some implementations, response 617 may be generated and sent to the host after (1) the DSM bitmap has been updated by the deallocation accelerator 610 and (2) the L2P mapping table 612 has been updated by the mapping table accelerator 611 based on one or more unaligned zones, but before the L2P mapping table 612 is further updated based on the DSM bitmap. In this case, when response 617 is sent to the host, the deallocation of one or more aligned zones (through the update of the L2P mapping table based on the DSM bitmap) has not yet been performed. Instead, the deallocation of one or more aligned zones may be performed in the background after response 617 is sent to the host. Thus, the response time to DSM commands can be reduced. Response latency to DSM commands can be reduced, and the impact of DSM handling on read / write I / O latency can also be reduced. In some other implementations, response 617 may be generated and sent to the host after (1) the L2P mapping table has been updated based on one or more unaligned zones, and (2) the L2P mapping table 612 has been updated based on the DSM bitmap. In this case, when response 617 is sent to the host, one or more aligned zones (and one or more unaligned zones) have already been deallocated.

[0077] Referring again to Figure 6, an exemplary implementation of the disclosed DSM handling scheme is given hereby. First, the memory controller 601 (e.g., the deallocation accelerator 610 of the memory controller 601) may divide the logical space of the non-volatile memory device 604 into a plurality of logical zones. Each logical zone may have a size of 16 MiB (or any other appropriate value). The memory controller 601 (e.g., the deallocation accelerator 610 of the memory controller 601) may generate a DSM bitmap containing a plurality of bits corresponding to each of the plurality of logical zones. The memory controller 601 (e.g., the deallocation accelerator 610 of the memory controller 601) may initialize a plurality of bits in the DSM bitmap to have a first value (e.g., "0").

[0078] The data classification accelerator 608 may receive DSM commands through the host interface 618 indicating a logical range to be deallocated. The data classification accelerator 608 may divide the logical range into sets of deallocated zones and classify each deallocated zone as either an unaligned zone or an aligned zone. If the set of deallocated zones includes one or more unaligned zones, the mapping table accelerator 611 may update the L2P mapping table 612 directly based on one or more unaligned zones and deallocate one or more unaligned zones. For example, the mapping table accelerator 611 may identify logical addresses in one or more unaligned zones and mark those logical addresses as invalid logical addresses in the L2P mapping table 612. After updating the L2P mapping table 612 based on one or more unaligned zones (for example, after one or more unaligned zones have been deallocated), the mapping table accelerator 611 may generate a response 617.

[0079] If the set of deallocated zones includes one or more aligned zones, the deallocation accelerator 610 may update the DSM bitmap based on one or more aligned zones. For example, for each aligned zone, the deallocation accelerator 610 may identify the logical zone of the non-volatile memory device 604 corresponding to the aligned zone and update the bit corresponding to that logical zone in the DSM bitmap to have a second value (e.g., "1"). The mapping table accelerator 611 may generate a response 617 in response to the update of the DSM bitmap. The mapping table accelerator 611 may then further update the L2P mapping table based on the DSM bitmap to actually deallocate one or more aligned zones from the logical space of the non-volatile memory device 604. That is, the response 617 may be sent to the host after the update of the DSM bitmap but before the update of the L2P mapping table 612 based on one or more aligned zones (e.g., before the actual deallocation of one or more aligned zones from the logical space of the non-volatile memory device 604). Note that updating the L2P mapping table 612 based on one alignment zone may take about 0.5us, while updating the DSM bitmap for one alignment zone (for example, setting one bit in the DSM bitmap corresponding to the alignment zone to a second value "1") takes only about 2ns. Therefore, if response 617 is generated and sent to the host after the DSM bitmap update but before updating the L2P mapping table 612 based on one or more alignment zones, the response time to the DSM command can be reduced.

[0080] If the set of deallocated zones includes both unallocated and aligned zones, the deallocation accelerator 610 may update the DSM bitmap based on the aligned zones. The mapping table accelerator 611 may update the L2P mapping table 612 based on the unallocated zones and deallocate the unallocated zones from the logical space of the non-volatile memory device 604. The mapping table accelerator 611 may generate a response 617 in response to both (1) the update of the DSM bitmap by the deallocation accelerator 610 and (2) the update of the L2P mapping table 612 based on the unallocated zones. The mapping table accelerator 611 may forward the response 617 to the host interface 618, causing the host interface 618 to send the response 617 to the host. Furthermore, the mapping table accelerator 611 may update the L2P mapping table 612 based on the DSM bitmap so that aligned zones can be deallocated from the logical space of the non-volatile memory device 604 in the background after the response 617 has been sent. Therefore, the response time to DSM commands can be reduced because the response 617 is generated and sent to the host after (1) updating the DSM bitmap and (2) updating the L2P mapping table 612 based on unaligned zones, but before updating the L2P mapping table 612 based on aligned zones.

[0081] Figure 8A shows an example of updating a DSM bitmap according to several embodiments of the present disclosure. In some implementations, the logical space of a non-volatile memory device may be divided into multiple logical zones (e.g., logical zones 0, 1, 2, ..., M), where M is a positive integer. A DSM bitmap may be generated for multiple logical zones, with each bit corresponding to one of the respective logical zones having a first value of "0".

[0082] As shown in Figure 8A, logical range 802 will be deallocated from the logic space of the non-volatile memory device. Since logical range 802 is located within (or smaller than) the first logical zone of multiple logical zones (e.g., logical zone 0), logical range 802 does not need to be divided and is classified as an unaligned zone. The L2P mapping table can be updated directly based on the unaligned zone, so the DSM bitmap in Figure 8A does not need to be updated for the unaligned zone.

[0083] Another logical range 804 will also be deallocated from the logic space of the non-volatile memory device. Logical range 804 may be divided into four deallocated zones to match the zoning of the logic space of the non-volatile memory device. The four deallocated zones are classified into two unaligned zones 806, 808 and two aligned zones 810, 812. For example, unaligned zone 806 is in the second logical zone of a plurality of logical zones (e.g., logical zone 1). Aligned zone 810 is identical to the third logical zone of a plurality of logical zones (e.g., logical zone 2). Aligned zone 812 is identical to the fourth logical zone of a plurality of logical zones (e.g., logical zone 3). Unaligned zone 808 is in the fifth logical zone of a plurality of logical zones (e.g., logical zone 4). The DSM bitmap may be updated based on the aligned zones 810, 812. For example, bit 813, which corresponds to alignment zone 810 (equivalently logical zone 2), may be set to have a second value of "1", and bit 814, which corresponds to alignment zone 812 (equivalently logical zone 3), may be set to have a second value of "1".

[0084] Figure 8B shows another example of updating a DSM bitmap according to some aspects of the present disclosure. Similar to Figure 8A, the logical space of a non-volatile memory device may be divided into multiple logical zones (e.g., logical zones 0, 1, 2, ..., M). A DSM bitmap is generated for the multiple logical zones, with each bit corresponding to one of the logical zones having a first value of "0".

[0085] Logical range 820 will be deallocated from the logic space of the non-volatile memory device. Logical range 820 may be divided into two deallocated zones to match the zoning of the logic space of the non-volatile memory device. The two deallocated zones are classified into two unaligned zones 822 and 824. Unaligned zone 822 is in the first logical zone of a set of logical zones (e.g., logical zone 0), and unaligned zone 824 is in the second logical zone of a set of logical zones (e.g., logical zone 1). The DSM bitmap does not need to be updated for unaligned zones 822 and 824, as the L2P mapping table can be updated directly based on unaligned zones 822 and 824.

[0086] Another logical range 830 will also be deallocated from the logic space of the non-volatile memory device. Logical range 830 may be divided into two deallocated zones to match the zoning of the logic space of the non-volatile memory device. The two deallocated zones are classified into two aligned zones 832 and 834. For example, aligned zone 832 is identical to the third logical zone of the multiple logical zones (e.g., logical zone 2). Aligned zone 834 is identical to the fourth logical zone of the multiple logical zones (e.g., logical zone 3). The DSM bitmap may be updated based on the aligned zones 832 and 834. For example, bit 835 corresponding to aligned zone 832 (equivalent to logical zone 2) may be set to a second value of "1", and bit 836 corresponding to aligned zone 834 (equivalent to logical zone 3) may be set to a second value of "1".

[0087] Figure 9 shows a flowchart of method 900 for operating a memory controller according to several aspects of this disclosure. The memory controller may be any suitable memory controller disclosed herein, such as memory controller 601. The operations shown in method 900 are not exhaustive, and it should be understood that other operations may be performed before, after, or between any of the operations shown. Furthermore, some operations may be performed simultaneously or in an order different from that shown in Figure 9.

[0088] Referring to Figure 9, method 900 begins in operation 902, where the deallocated logical range (for example, the logical range to be deallocated from the logical space of a non-volatile memory device) is divided into a set of deallocated zones. Each deallocated zone contains one or more first deallocated zones, each of which is classified into one or more aligned zones. For example, a data classification accelerator 608 may divide the logical range into a set of deallocated zones, each of which may contain one or more aligned zones.

[0089] As shown in Figure 9, method 900 proceeds to operation 904, where the DSM bitmap is updated based on one or more alignment zones. For example, the deallocation accelerator 610 may update the DSM bitmap based on one or more alignment zones.

[0090] As shown in Figure 9, method 900 proceeds to operation 906, where a response indicating that the deallocated logical range is processed is generated in response to the update of the DSM bitmap. For example, the mapping table accelerator 611 may generate a response in response to the update of the DSM bitmap indicating that the deallocated logical range is deallocated from the logical space of the non-volatile memory device.

[0091] As shown in Figure 9, method 900 proceeds to operation 908, where the response is sent to the host. For example, the mapping table accelerator 611 may forward the response to the host interface 618, causing the host interface 618 to send the response to the host.

[0092] Figure 10 shows a flowchart of another method 1000 for operating a memory controller according to several aspects of this disclosure. The memory controller may be any suitable memory controller disclosed herein, such as memory controller 601. The operations shown in method 1000 are not exhaustive, and it should be understood that other operations may be performed before, after, or between any of the operations shown. Furthermore, some operations may be performed simultaneously or in an order different from that shown in Figure 10.

[0093] Referring to Figure 10, method 1000 begins with operation 1002, where a DSM command is received indicating the logical range to be deallocated.

[0094] As shown in Figure 10, method 1000 proceeds to operation 1004, where the logical range is divided into a set of deallocation zones, which include (1) one or more first deallocation zones classified into one or more aligned zones, and (2) one or more second deallocation zones classified into one or more unaligned zones.

[0095] As shown in Figure 10, method 1000 proceeds to operation 1006, in which the DSM bitmap is updated based on one or more alignment zones.

[0096] As shown in Figure 10, method 1000 proceeds to operation 1008, where the L2P mapping table is updated based on one or more unaligned zones.

[0097] As shown in Figure 10, method 1000 proceeds to operation 1010, where a response to a DSM command is generated. For example, a response may be generated in response to both an update of the L2P mapping table based on one or more unaligned zones and an update of the DSM bitmap. The response may be sent to the host.

[0098] As shown in Figure 10, method 1000 proceeds to operation 1012, where the L2P mapping table is updated based on the DSM bitmap. Operation 1012 may be performed before or after operation 1010, and this is not limited herein. In some implementations, operation 1012 may be performed in the background after the response has been sent to the host.

[0099] In various embodiments of this disclosure, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. When implemented in software, the functions may be stored as instructions on a non-temporary computer-readable medium. The computer-readable medium includes computer storage media. The storage media may be any available medium that can be accessed by a memory controller, such as the memory controller 601 in Figure 6. Such computer-readable media may include, but are not limited to, RAM, ROM, electrically erasable programmable ROM (EEPROM), compact disk read-only memory (CD-ROM), or other optical disk storage, magnetic disk storage, or other magnetic storage devices such as hard disk drives (HDDs), flash drives, SSDs, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and can be accessed by a processing system such as a mobile device or computer. In this specification, "disk" and "disc" include CDs, laserdiscs, optical discs, digital video discs (DVDs), and floppy disks, where a "disk" typically reproduces data magnetically, and a "disc" reproduces data optically using a laser. Any combination of the above should also be included within the scope of computer-readable media.

[0100] The above-mentioned descriptions of specific implementation forms can be readily modified and / or adapted to various applications. Therefore, such adaptations and modifications are intended to fall within the meaning and scope of the equivalence of the disclosed implementation forms, based on the teachings and guidance presented herein.

[0101] The scope and width of this disclosure should not be limited by any of the exemplary implementations described above, but should be defined solely by the following claims and their equivalents.

[0102] While specific configurations and scopes are discussed, it should be understood that this is for illustrative purposes only. Therefore, other configurations and arrangements may be used without departing from the scope of this disclosure. Furthermore, the subject matter described in this disclosure may also be used in various other applications. The functional and structural features described in this disclosure may be combined, adjusted, modified, and rearranged in a manner that is consistent with each other and within the scope of this disclosure. [Explanation of Symbols]

[0103] 100 Systems 102 memory systems 104 Memory Devices 106 Memory Controller 108 hosts 202 memory card 204 Memory card connector 206 SSD 208 SSD connectors 300 memory controllers 302 Non-volatile memory 304 DRAM 306 Host 308 processing units 310 Cache 311 ROM 312 Non-volatile memory interface 314 DRAM Interface 316 Host Interface 400 NAND flash memory devices 401 memory cell array 402 Peripheral Circuits 404 Block 406 memory cells 408 memory string 410 SSG Transistors 412 DSG transistors 413 DSG line 414 Source Line 415 SSG Line 416-bit line 418 Word lines 420 physical pages 500 DRAM devices 501 memory cell array 502 Peripheral Circuits 503 memory cells 504 Word Line 505 transistors 506-bit line 507 Capacitor 600 memory system 601 Memory Controller 602 Volatile memory devices 604 NV memory devices 606 cache 608 Data Classification Accelerator 610 Deallocation Accelerator 611 Mapping Table Accelerator 612 L2P Mapping Table 616 Physical Address 617 Response 618 Host Interface 620 Volatile Memory Interface 622 NV memory interface 702 Physical Address 706 values 802 Logical range 804 Logical range 806 Non-aligned zone 808 Non-aligned zone 810 Queueing Zone 812 Queueing Zone 813 bits 814 bit 820 Logical range 822 Non-aligned zone 824 Non-aligned zone 830 Logical range 832 Queueing Zone 834 Queueing Zone 835 bits 836 bits

Claims

1. A data classification accelerator configured to divide a deallocated logical range into a set of deallocated zones, wherein the set of deallocated zones comprises one or more first deallocated zones, each classified into one or more alignment zones, wherein the alignment zone is a deallocated zone that includes the start and end points of the deallocated logical range, and the start and end points of the deallocated logical range coincide with the boundaries of the deallocated zone. A deallocation accelerator operably coupled to the data classification accelerator and configured to update a dataset management (DSM) bitmap based on one or more alignment zones, The data classification accelerator and the deallocation accelerator are operably coupled, In response to the update of the DSM bitmap, a response is generated indicating that the deallocated logical range is being processed. A mapping table accelerator configured in such a way A memory controller equipped with the following features.

2. The memory controller according to claim 1, wherein the mapping table accelerator is further configured to update a logical-to-physical (L2P) mapping table based on the DSM bitmap.

3. In order to update the L2P mapping table based on the DSM bitmap, the mapping table accelerator performs the following: Identifying one or more alignment zones from the DSM bitmap, The L2P mapping table is updated based on one or more of the aforementioned alignment zones. The memory controller according to claim 2, further configured to do the following.

4. In order to update the L2P mapping table based on the one or more alignment zones, the mapping table accelerator, Identifying a first list of logical addresses within one or more of the aforementioned alignment zones, To disable the first list of logical addresses in the L2P mapping table. The memory controller according to claim 3, further configured to do the following.

5. The set of deallocation zones comprises one or more second deallocation zones, each classified into one or more unaligned zones, wherein the unaligned zone is a deallocation zone that includes the start or end point of the deallocated logical range, and the start or end point of the deallocated logical range does not coincide with the boundary of the deallocation zone, further comprising one or more second deallocation zones. The aforementioned mapping table accelerator, Updating the L2P mapping based on one or more of the aforementioned non-aligned zones, Based on the one or more unaligned zones, generate a response that responds to both the update of the DSM bitmap and the update of the L2P mapping table. The memory controller according to claim 2, further configured to do the following.

6. In order to update the L2P mapping table based on the one or more unaligned zones, the mapping table accelerator, Identifying a second list of logical addresses within the one or more unaligned zones, In the L2P mapping table, the second list of logical addresses is disabled. The memory controller according to claim 5, further configured to do the following.

7. The memory controller according to claim 5, wherein the data classification accelerator is configured to divide the deallocated logical range into the set of deallocated zones based on the zoning of the logical space of the non-volatile memory device coupled to the memory controller, such that the division of the deallocated logical range matches the zoning of the logical space of the non-volatile memory device.

8. The logical space of the non-volatile memory device is divided into a plurality of logical zones, The one or more first deallocation zones are classified into the one or more alignment zones that are aligned with one or more first logical zones from the plurality of logical zones, such that the one or more first deallocation zones are equal to one or more first logical zones from the plurality of logical zones. The memory controller according to claim 7, wherein the one or more second deallocation zones are smaller than the one or more second logical zones from the plurality of logical zones, such that each of the one or more second deallocation zones is classified as one or more unaligned zones that are not aligned with one or more second logical zones from the plurality of logical zones.

9. The memory controller according to claim 7, wherein the non-volatile memory device comprises NAND flash memory.

10. Non-volatile memory devices and The non-volatile memory device is operably coupled to the memory controller and configured to control the non-volatile memory device, wherein the memory controller A data classification accelerator configured to divide a deallocated logical range into a set of deallocated zones, wherein the set of deallocated zones comprises one or more first deallocated zones, each classified into one or more alignment zones, wherein the alignment zone is a deallocated zone that includes the start and end points of the deallocated logical range, and the start and end points of the deallocated logical range coincide with the boundaries of the deallocated zone. A deallocation accelerator operably coupled to the data classification accelerator and configured to update a dataset management (DSM) bitmap based on one or more alignment zones, The data classification accelerator and the deallocation accelerator are operably coupled, In response to the update of the DSM bitmap, a response is generated indicating that the deallocated logical range is being processed. A mapping table accelerator configured in such a way A memory system equipped with the following features.

11. The memory system according to claim 10, wherein the mapping table accelerator is further configured to update a logical-to-physical (L2P) mapping table based on the DSM bitmap.

12. In order to update the L2P mapping table based on the DSM bitmap, the mapping table accelerator performs the following: Identifying one or more alignment zones from the DSM bitmap, The L2P mapping table is updated based on one or more of the aforementioned alignment zones. The memory system according to claim 11, further configured to do the following.

13. In order to update the L2P mapping table based on the one or more alignment zones, the mapping table accelerator, Identifying a first list of logical addresses within one or more of the aforementioned alignment zones, In the L2P mapping table, the first list of logical addresses is disabled. The memory system according to claim 12, further configured to do the following.

14. The set of deallocation zones comprises one or more second deallocation zones, each classified into one or more unaligned zones, wherein the unaligned zone is a deallocation zone that includes the start or end point of the deallocated logical range, and the start or end point of the deallocated logical range does not coincide with the boundary of the deallocation zone, further comprising one or more second deallocation zones. The aforementioned mapping table accelerator, The L2P mapping table is updated based on one or more of the aforementioned unaligned zones, Based on the one or more unaligned zones, generate a response that responds to both the update of the DSM bitmap and the update of the L2P mapping table. The memory system according to claim 11, further configured to do the following.

15. In order to update the L2P mapping table based on the one or more unaligned zones, the mapping table accelerator, Identifying a second list of logical addresses within the one or more unaligned zones, In the L2P mapping table, the second list of logical addresses is disabled. The memory system according to claim 14, further configured to do the following.

16. The memory system according to claim 14, wherein the data classification accelerator is configured to divide the deallocated logical range into the set of deallocated zones based on the zoning of the logical space of the non-volatile memory device coupled to the memory controller, such that the division of the deallocated logical range matches the zoning of the logical space of the non-volatile memory device.

17. The logical space of the non-volatile memory device is divided into a plurality of logical zones, The one or more first deallocation zones are classified into the one or more alignment zones that are aligned with one or more first logical zones from the plurality of logical zones, such that the one or more first deallocation zones are equal to one or more first logical zones from the plurality of logical zones. The memory system according to claim 16, wherein the one or more second deallocation zones are smaller than the one or more second logical zones from the plurality of logical zones, such that each of the one or more second deallocation zones is classified as one or more unaligned zones that are not aligned with one or more second logical zones from the plurality of logical zones.

18. The memory system according to claim 16, wherein the non-volatile memory device comprises NAND flash memory.

19. A method for operating a memory controller, A step of dividing a deallocated logical range into a set of deallocation zones, wherein the set of deallocation zones comprises one or more first deallocation zones, each classified into one or more alignment zones, and the alignment zone is a deallocation zone that includes the start and end points of the deallocated logical range, and the start and end points of the deallocated logical range coincide with the boundaries of the deallocation zone. The steps include updating a Dataset Management (DSM) bitmap based on one or more alignment zones, The steps include generating a response indicating that the deallocated logical range is processed in response to the update of the DSM bitmap, and A method that includes [a certain feature].

20. The method according to claim 19, further comprising the step of updating a logical-to-physical (L2P) mapping table based on the DSM bitmap.

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