Junction barrier Schottky diode

The dual p-type semiconductor layer structure in the junction barrier Schottky diode addresses surge withstand capability issues by optimizing energy levels, enhancing surge withstand voltage and reducing contact resistance.

JP7836205B2Active Publication Date: 2026-03-26TDK CORP
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Patent Information

Authority / Receiving Office
JP · JP
Patent Type
Patents
Current Assignee / Owner
Filing Date
2022-03-23
Publication Date
2026-03-26

AI Technical Summary

Technical Problem

The junction barrier Schottky diode using gallium oxide faces issues with surge withstand capability due to the energy difference between the valence band upper level of the p-type semiconductor layer and the drift layer, which affects the contact resistance and hole injection efficiency.

Method used

A junction barrier Schottky diode design utilizing two p-type semiconductor layers with different energy levels, where the upper valence band level of the second p-type semiconductor layer is lower than that of the first, reducing the energy difference and enhancing the surge withstand capability.

Benefits of technology

The design increases the surge withstand voltage and reduces contact resistance, enabling efficient hole injection and improved performance under surge conditions.

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Abstract

To increase the surge resistance of a junction barrier Schottky diode in which a gallium oxide is used.SOLUTION: A junction barrier Schottky diode 1 includes: a semiconductor substrate 20 and a drift layer 30 that are formed from a gallium oxide; an anode electrode 40 that is in contact with the drift layer 30; a cathode electrode 50 that is in contact with the semiconductor substrate 20; and a p-type semiconductor layer 60 that is in contact with the anode electrode 40 and the drift layer 30. The p-type semiconductor layer 60 includes a first p-type semiconductor layer 61 that is in contact with the anode electrode 40 and a second p-type semiconductor layer 62 that is in contact with the drift layer 30. The upper-end level of the valence band of the second p-type semiconductor layer 62 is lower than the upper-end level of the valence band of the first p-type semiconductor layer 61. Surge resistance can thus be increased since the two p-type semiconductor layers 61, 62 having different energy levels are used.SELECTED DRAWING: Figure 1
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Description

[Technical Field]

[0001] The present invention relates to a junction barrier Schottky diode, and more particularly to a junction barrier Schottky diode using gallium oxide. [Background technology]

[0002] Schottky barrier diodes are rectifier elements that utilize the Schottky barrier created by the junction of a metal and a semiconductor. Compared to ordinary diodes with a PN junction, they have a lower forward voltage and a faster switching speed. For this reason, Schottky barrier diodes are sometimes used as switching elements in power devices.

[0003] When Schottky barrier diodes are used as switching elements for power devices, it is necessary to ensure sufficient reverse breakdown voltage. Therefore, instead of silicon (Si), silicon carbide (SiC), gallium nitride (GaN), and gallium oxide (Ga2O3), which have larger band gaps, are sometimes used. Among these, gallium oxide has a very large band gap of 4.8 to 4.9 eV and a large dielectric breakdown field of approximately 8 MV / cm, making Schottky barrier diodes using gallium oxide very promising as switching elements for power devices. An example of a Schottky barrier diode using gallium oxide is described in Patent Document 1.

[0004] Patent Document 1 discloses a junction barrier Schottky diode having a structure in which a p-type semiconductor material is embedded in a plurality of trenches provided in a gallium oxide layer. In this way, by providing a plurality of trenches in the gallium oxide layer and embedding a p-type semiconductor material in the plurality of trenches, when a reverse voltage is applied, the mesa region located between the trenches becomes a depletion layer, and the channel region of the drift layer is pinched off. As a result, leakage current when a reverse voltage is applied can be significantly suppressed. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2019-036593 [Overview of the project] [Problems that the invention aims to solve]

[0006] However, the junction barrier Schottky diode described in Patent Document 1 had a problem in that, if a material with a valence band upper level close to the Fermi level was selected as the material for the p-type semiconductor layer, the energy difference with the valence band upper level of the drift layer would increase, which would increase the energy required to inject holes into the drift layer and worsen the surge withstand capability. Conversely, if a material with a valence band upper level close to the valence band upper level of the drift layer was selected as the material for the p-type semiconductor layer, the energy difference with the Fermi level would increase, which would increase the contact resistance between the anode electrode and the p-type semiconductor layer, and in this case as well, the surge withstand capability would worsen.

[0007] Therefore, the present invention aims to improve the surge withstand capability of a junction barrier Schottky diode using gallium oxide. [Means for solving the problem]

[0008] The junction barrier Schottky diode according to the present invention comprises a semiconductor substrate made of gallium oxide, a drift layer made of gallium oxide provided on the semiconductor substrate, an anode electrode in contact with the drift layer, a cathode electrode in contact with the semiconductor substrate, and a p-type semiconductor layer in contact with the anode electrode and the drift layer, wherein the p-type semiconductor layer includes a first p-type semiconductor layer in contact with the anode electrode and a second p-type semiconductor layer in contact with the drift layer, and the upper valence band level of the second p-type semiconductor layer is lower than the upper valence band level of the first p-type semiconductor layer.

[0009] According to the present invention, since two p-type semiconductor layers with different energy levels are used, it is possible to reduce the difference between the Fermi level and the upper valence band level of the p-type semiconductor layer, and also reduce the difference between the upper valence band level of the p-type semiconductor layer and the upper valence band level of the drift layer.

[0010] In the present invention, the second p-type semiconductor layer and the first p-type semiconductor layer may be stacked in this order on the flat upper surface of the drift layer. According to this, it becomes possible to fabricate with a simple manufacturing process.

[0011] In the present invention, the drift layer may have a trench, and at least a part of the p-type semiconductor layer may be embedded in the trench. According to this, it becomes possible to expand the contact area between the p-type semiconductor layer and the drift layer.

[0012] In the present invention, the energy difference between the Fermi level and the upper valence band level of the first p-type semiconductor layer may be 1 eV or less, and the energy difference between the upper valence band level of the second p-type semiconductor layer and the upper valence band level of the drift layer may be 2 eV or less. According to this, it becomes possible to make an ohmic contact between the anode electrode and the first p-type semiconductor layer, and also to sufficiently reduce the energy required to inject holes into the drift layer.

[0013] In the present invention, the p-type semiconductor layer may further include a third p-type semiconductor layer located between the first p-type semiconductor layer and the second p-type semiconductor layer, and the upper valence band level of the third p-type semiconductor layer may be lower than the upper valence band level of the first p-type semiconductor layer and higher than the upper valence band level of the second p-type semiconductor layer. According to this, it becomes possible to further increase the surge withstand voltage.

Effect of the Invention

[0014] Thus, according to the present invention, it becomes possible to increase the surge withstand voltage of the junction barrier Schottky diode using gallium oxide.

Brief Description of the Drawings

[0015] [Figure 1] Figure 1(a) is a schematic plan view showing the configuration of a junction barrier Schottky diode 1 according to the first embodiment of the present invention. Figure 1(b) is a substantially cross-sectional view along line AA shown in Figure 1(a). [Figure 2] Figure 2 is the energy band diagram of the junction barrier Schottky diode 1, where (a) shows the energy band in the first current path P1 and (b) shows the energy band in the second current path P2. [Figure 3] Figure 3 is a graph showing the relationship between forward voltage VF and forward current IF. [Figure 4] Figure 4 is a schematic plan view showing the configuration of a junction barrier Schottky diode according to the first modification. [Figure 5] Figure 5 is a schematic plan view showing the configuration of a junction barrier Schottky diode according to a second modification. [Figure 6] Figure 6 is a schematic plan view showing the configuration of a junction barrier Schottky diode according to a third modification. [Figure 7] Figure 7 is a schematic plan view showing the configuration of a junction barrier Schottky diode according to the fourth modification. [Figure 8] Figure 8(a) is a schematic plan view showing the configuration of a junction barrier Schottky diode according to the fifth modification. Figure 8(b) is a roughly cross-sectional view along line AA shown in Figure 8(a). [Figure 9] Figure 9(a) is a schematic plan view showing the configuration of a junction barrier Schottky diode according to the sixth modification. Figure 9(b) is a roughly cross-sectional view along line AA shown in Figure 9(a). [Figure 10] Figure 10(a) is a schematic plan view showing the configuration of a junction barrier Schottky diode according to the seventh modification. Figure 10(b) is a roughly cross-sectional view along line AA shown in Figure 10(a). [Figure 11]Figure 11(a) is a schematic plan view showing the configuration of a junction barrier Schottky diode 2 according to a second embodiment of the present invention. Figure 11(b) is a substantially cross-sectional view along line AA shown in Figure 11(a). [Figure 12] Figure 12 is a schematic cross-sectional view showing the configuration of a junction barrier Schottky diode according to the eighth modification. [Figure 13] Figure 13 is a schematic cross-sectional view showing the configuration of a junction barrier Schottky diode 3 according to a third embodiment of the present invention. [Figure 14] Figure 14 is the energy band diagram of the junction barrier Schottky diode 3, showing the energy band in the second current path P2. [Figure 15] Figure 15 is an energy band diagram for the first example where the p-type semiconductor layer 60 has an n-layer structure. [Figure 16] Figure 16 is an energy band diagram for a second example where the p-type semiconductor layer 60 has an n-layer structure. [Modes for carrying out the invention]

[0016] Preferred embodiments of the present invention will be described in detail below with reference to the attached drawings.

[0017] <First Embodiment> Figure 1(a) is a schematic plan view showing the configuration of a junction barrier Schottky diode 1 according to the first embodiment of the present invention. Figure 1(b) is a substantially cross-sectional view along line AA shown in Figure 1(a).

[0018] As shown in Figure 1, the junction barrier Schottky diode 1 according to the first embodiment comprises a semiconductor substrate 20 and a drift layer 30, both made of gallium oxide (β-Ga2O3). Silicon (Si) or tin (Sn) is introduced as an n-type dopant in the semiconductor substrate 20 and the drift layer 30. The dopant concentration is higher in the semiconductor substrate 20 than in the drift layer 30, and as a result, the semiconductor substrate 20 is n + Layer, drift layer 30 is n - It functions as a layer. The impurity concentration of the semiconductor substrate 20 is, for example, 1 × 10⁻⁶. 18 cm -3 The impurity concentration in the drift layer 30 is, for example, 3 × 10⁻⁶. 16 cm -3 It is to that extent.

[0019] The semiconductor substrate 20 is formed by cutting a bulk crystal created using a method such as melt growth, and its thickness is approximately 250 μm. The planar size of the semiconductor substrate 20 is not particularly limited, but is generally selected according to the amount of current flowing through the device. If the maximum forward current is approximately 20 A, then a planar size of approximately 2.4 mm × 2.4 mm is sufficient.

[0020] The semiconductor substrate 20 has an upper surface 21 that is located on the upper side during mounting, and a back surface 22 that is on the opposite side of the upper surface 21 and located on the lower side during mounting. A drift layer 30 is formed on the entire surface of the upper surface 21. The drift layer 30 is a thin film of gallium oxide epitaxially grown on the upper surface 21 of the semiconductor substrate 20 using reactive sputtering, PLD method, MBE method, MOCVD method, HVPE method, etc. The thickness of the drift layer 30 is not particularly limited, but is generally selected according to the reverse withstand voltage of the device, and for example, a thickness of about 7 μm is sufficient to ensure a withstand voltage of about 600 V.

[0021] On the upper surface 31 of the drift layer 30, an anode electrode 40 that makes a Schottky contact with the drift layer 30 and a p-type semiconductor layer 60 that makes a pn junction with the drift layer 30 are formed. The anode electrode 40 is made of a metal such as platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), molybdenum (Mo), copper (Cu), etc. The anode electrode 40 may have a multilayer structure in which different metal films are laminated, for example, Pt / Au, Pt / Al, Pd / Au, Pd / Al, Pt / Ti / Au, or Pd / Ti / Au.

[0022] The p-type semiconductor layer 60 includes a first p-type semiconductor layer 61 and a second p-type semiconductor layer 62. The p-type semiconductor layer 60 is formed in a double ring shape in plan view, and the second p-type semiconductor layer 62 and the first p-type semiconductor layer 61 are laminated in this order on the flat upper surface 31 of the drift layer 30. Thereby, the first p-type semiconductor layer 61 contacts the anode electrode 40, and the second p-type semiconductor layer 62 makes a pn junction with the drift layer 30. In the example shown in FIG. 1, the side surface of the second p-type semiconductor layer 62 also contacts the anode electrode 40. As the materials of the first and second p-type semiconductor layers 61 and 62, Si, GaAs, GaN, SiC, Ge, ZnSe, CdS, InP, SiGe, AlN, BN, AlGaN, NiO, Cu2O, Ir2O3, Ag2O, etc. can be used, but at least as the material of the second p-type semiconductor layer 62, a material whose valence band top level is lower than the valence band top level of the first p-type semiconductor layer 61 needs to be selected. As an example, NiO with an impurity concentration of about 1×10 19 cm -3 can be selected as the first p-type semiconductor layer 61, and BN with an impurity concentration of about 1×10 16 cm -3 can be selected as the second p-type semiconductor layer 62.

[0023] On the back surface 22 of the semiconductor substrate 20, a cathode electrode 50 that makes an ohmic contact with the semiconductor substrate 20 is provided. The cathode electrode 50 is made of a metal such as titanium (Ti), etc. The cathode electrode 50 may have a multilayer structure in which different metal films are laminated, for example, Ti / Au or Ti / Al.

[0024] When a forward voltage is applied to the junction barrier Schottky diode 1 according to this embodiment, two current paths are formed from the anode electrode 40 to the drift layer 30. The first current path, as indicated by the symbol P1 in Figure 1(b), is a path in which current flows directly from the anode electrode 40 to the drift layer 30 without passing through the p-type semiconductor layer 60. The second current path, as indicated by the symbol P2 in Figure 1(b), is a path that passes through the p-type semiconductor layer 60.

[0025] Figure 2 is an energy band diagram of the junction barrier Schottky diode 1 according to this embodiment, where (a) shows the energy band in the first current path P1 and (b) shows the energy band in the second current path P2.

[0026] As shown in Figure 2(a), in the first current path P1, the anode electrode 40 and the drift layer 30 are in Schottky contact, and this portion functions as a Schottky barrier diode. Therefore, because the forward voltage is low and the switching speed is fast, it turns on first when a forward voltage is applied. The height of the Schottky barrier between the anode electrode 40 and the drift layer 30 is Φ b1 Here, E F This is the Fermi level, E C E is the lower end level of the conduction band. V E is the upper level of the valence band. g This refers to the energy band gap.

[0027] In contrast, as shown in Figure 2(b), in the second current path P2, a p-type semiconductor layer 60 is interposed between the anode electrode 40 and the drift layer 30. Therefore, after current flows through the first current path P1, the second current path P2 is turned on when a higher forward voltage is applied. This significantly reduces the on-resistance.

[0028] Figure 3 is a graph showing the relationship between the forward voltage VF and the forward current IF, where symbol A represents the characteristics of the junction barrier Schottky diode 1 according to this embodiment, and symbol B represents the characteristics of a general Schottky barrier diode. As shown in Figure 3, in a general Schottky barrier diode, if a sudden large current (surge current) such as 100A flows, a voltage of approximately 50V is generated, causing burnout due to a large amount of heat. In contrast, in the junction barrier Schottky diode 1 according to this embodiment, even if a surge current of 100A flows, the second current path P2 is turned on, so the generated voltage is suppressed to about 5V.

[0029] Furthermore, in this embodiment, the first p-type semiconductor layer 61 and the second p-type semiconductor layer 62 are arranged in this order between the anode electrode 40 and the drift layer 30. As shown in Figure 2(b), the Fermi level E F The energy difference between the first p-type semiconductor layer 61 and the upper valence band level is Φ b2 The energy difference between the valence band upper level of the first p-type semiconductor layer 61 and the valence band upper level of the second p-type semiconductor layer 62 is ΔE V1 The energy difference between the upper valence band level of the second p-type semiconductor layer 62 and the upper valence band level of the drift layer 30 is ΔE V2 The band gap of the first p-type semiconductor layer 61 is E g1 The band gap of the second p-type semiconductor layer 62 is E g2 The band gap of drift layer 30 is E g3 In this embodiment, since the valence band upper level of the second p-type semiconductor layer 62 is lower than that of the first p-type semiconductor layer 61, the energy difference Φ is greater compared to the case where a single semiconductor material is used as the material for the p-type semiconductor layer 60. b2 and ΔE V2 This reduces the energy required to inject holes into the drift layer 30, and also reduces the contact resistance between the anode electrode 40 and the p-type semiconductor layer 60. As a result, the surge withstand capability increases compared to when a single semiconductor material is used for the p-type semiconductor layer 60.

[0030] Here, the materials for the first and second p-type semiconductor layers 61 and 62 are, b2 The energy difference ΔE becomes less than 1 eV. V2 It is preferable to select a material whose band gap is 2 eV or less. For example, when NiO is used as the material for the first p-type semiconductor layer 61 and BN is used as the material for the second p-type semiconductor layer 62, the band gap of NiO is E g1 The band gap of BN is approximately 3.7 eV. g2 The energy difference is approximately 6.2 eV, and the energy difference Φ b2 The voltage is less than 0.5 eV. Therefore, it is possible to make ohmic contact between the anode electrode 40 and the first p-type semiconductor layer 61. Also, the energy difference is ΔE V2 The energy difference Φ is also reduced to 2 eV or less, and the energy required to inject holes into the drift layer 30 is sufficiently reduced. b2 If the energy difference is less than 1 eV, then the energy difference ΔE V2 To make the voltage 2eV or less, NiO may be used as the material for the first p-type semiconductor layer 61 and AlN as the material for the second p-type semiconductor layer 62; Cu2O may be used as the material for the first p-type semiconductor layer 61 and BN as the material for the second p-type semiconductor layer 62; Cu2O may be used as the material for the first p-type semiconductor layer 61 and AlN as the material for the second p-type semiconductor layer 62; GaN may be used as the material for the first p-type semiconductor layer 61 and BN as the material for the second p-type semiconductor layer 62; AlGaN may be used as the material for the first p-type semiconductor layer 61 and BN as the material for the second p-type semiconductor layer 62; or CuGaO2 may be used as the material for the first p-type semiconductor layer 61 and BN as the material for the second p-type semiconductor layer 62. In contrast, if a single semiconductor material is used as the material for the p-type semiconductor layer 60, and ohmic contact cannot be secured between the anode electrode 40 and the p-type semiconductor layer 60, a relatively large voltage may be generated by surge current, as shown by characteristic C in Figure 3.

[0031] Thus, in this embodiment, since the junction barrier Schottky diode 1 has a p-type semiconductor layer 60 composed of a laminate of first and second p-type semiconductor layers 61 and 62, it is possible to obtain a larger surge withstand capability compared to when a single semiconductor material is used as the material for the p-type semiconductor layer 60. Moreover, since the p-type semiconductor layer 60 is formed on the flat upper surface 31 of the drift layer 30, it can be manufactured using a simple manufacturing process.

[0032] Here, the planar shape of the p-type semiconductor layer 60 is not limited to the shape shown in Figure 1(a). It may be striped, as in the first modified example shown in Figure 4; dotted, as in the second modified example shown in Figure 5; a combination of rings and stripes, as in the third modified example shown in Figure 6; or a combination of rings and dots, as in the fourth modified example shown in Figure 7. Furthermore, as in the fifth modified example shown in Figure 8, a portion of the p-type semiconductor layer 60 may not be covered by the anode electrode 40; and as in the sixth modified example shown in Figure 9, the width of the anode electrode 40 may be greater than that of the p-type semiconductor layer 60. Moreover, as in the seventh modified example shown in Figure 10, a field insulating film 70 may be provided on the upper surface 31 of the drift layer 30, and the end of the anode electrode 40 may be placed on the field insulating film 70. By adopting such a field plate structure, it is possible to mitigate the electric field applied to the drift layer 30.

[0033] <Second Embodiment> Figure 11(a) is a schematic plan view showing the configuration of a junction barrier Schottky diode 2 according to a second embodiment of the present invention. Figure 11(b) is a substantially cross-sectional view along line AA shown in Figure 11(a).

[0034] As shown in Figure 11, the junction barrier Schottky diode 2 according to the second embodiment differs from the junction barrier Schottky diode 1 according to the first embodiment in that a trench 32 is provided in the drift layer 30 and the second p-type semiconductor layer 62 is embedded in the trench 32. The other basic configurations are the same as those of the junction barrier Schottky diode 1 according to the first embodiment, so the same reference numerals are used for the same elements and redundant explanations are omitted.

[0035] The trench 32 has a depth that does not reach the semiconductor substrate 20 from the upper surface 31 of the drift layer 30, and the second p-type semiconductor layer 62 is embedded inside it. For example, the depth of the trench 32 can be about 3 μm, and the width of the trench 32 can be about 1.5 μm. The first p-type semiconductor layer 61 is located outside the trench 32 and in contact with the second p-type semiconductor layer 62. Therefore, in this embodiment, the anode electrode 40 and the second p-type semiconductor layer 62 do not come into direct contact.

[0036] Thus, in the junction barrier Schottky diode 2 according to the second embodiment, the second p-type semiconductor layer 62 is embedded in a trench 32 provided in the drift layer 30, which increases the contact area between the second p-type semiconductor layer 62 and the drift layer 30. This makes it possible to further reduce the resistance value of the second current path P2.

[0037] Furthermore, in the example shown in Figure 11, the entire second p-type semiconductor layer 62 is embedded in the trench 32, but a part of the second p-type semiconductor layer 62 may be provided outside the trench 32, or, as shown in the modified example in Figure 12, the entire p-type semiconductor layer 60, including the first p-type semiconductor layer 61, may be embedded in the trench 32.

[0038] <Third Embodiment> Figure 13 is a schematic cross-sectional view showing the configuration of a junction barrier Schottky diode 3 according to a third embodiment of the present invention.

[0039] As shown in Figure 13, the junction barrier Schottky diode 3 according to the third embodiment differs from the junction barrier Schottky diode 1 according to the first embodiment in that the p-type semiconductor layer 60 includes a third p-type semiconductor layer 63. Since the other basic configurations are the same as those of the junction barrier Schottky diode 1 according to the first embodiment, the same reference numerals are used for the same elements, and redundant explanations are omitted.

[0040] The third p-type semiconductor layer 63 is located between the first p-type semiconductor layer 61 and the second p-type semiconductor layer 62. The material selected for the third p-type semiconductor layer 63 is one in which the valence band upper level is lower than that of the first p-type semiconductor layer 61 and higher than that of the second p-type semiconductor layer 62.

[0041] Figure 14 is an energy band diagram of the junction barrier Schottky diode 3 according to this embodiment, showing the energy band in the second current path P2.

[0042] As shown in Figure 14, in this embodiment, since the p-type semiconductor layer 60 has a three-layer structure, the Fermi level E F The energy difference Φ between the upper valence band level of the first p-type semiconductor layer 61 and the upper valence band level of the first p-type semiconductor layer 61. b2 The energy difference ΔE between the valence band upper level of the second p-type semiconductor layer 62 and the valence band upper level of the drift layer 30. V2 This can be further reduced. As a result, the energy required to inject holes into the drift layer 30 is further reduced, and the contact resistance between the anode electrode 40 and the p-type semiconductor layer 60 is further reduced, making it possible to increase the surge withstand capability.

[0043] As exemplified by the junction barrier Schottky diode 3 according to this embodiment, the surge withstand capability can be further increased by using a three-layer structure for the p-type semiconductor layer 60. Furthermore, it is also possible to use a four-layer or more p-type semiconductor layer 60. For example, if the p-type semiconductor layer has an n-layer structure, as shown in Figure 15, it is acceptable for some combinations to exist where the valence band upper level of the p-type semiconductor layer located on the anode electrode 40 side (the fourth p-layer in Figure 15) is lower than the valence band upper level of the p-type semiconductor layer located on the drift layer 30 side (the np-layer in Figure 15). Also, as shown in Figure 16, it is acceptable for the valence band upper level of the p-type semiconductor layer located closest to the drift layer 30 (the np-layer in Figure 15) to be lower than the valence band upper level of the drift layer 30.

[0044] Although preferred embodiments of the present invention have been described above, it goes without saying that the present invention is not limited to the above embodiments, and various modifications are possible without departing from the spirit of the invention, and these modifications are also included within the scope of the present invention. [Explanation of Symbols]

[0045] 1-3 Junction barrier Schottky diodes 20 Semiconductor substrates 21 Top surface of semiconductor substrate 22 Back surface of semiconductor substrate 30 drift layers 31 Top surface of semiconductor substrate 32 Trench 40 Anode electrodes 50 Cathode electrodes 60 p-type semiconductor layer 61 First p-type semiconductor layer 62 Second p-type semiconductor layer 63 Third p-type semiconductor layer 70 Field Insulating Film P1 First current path P2 Second current path

Claims

1. A semiconductor substrate made of gallium oxide, A drift layer made of gallium oxide is provided on the semiconductor substrate, The anode electrode in contact with the drift layer, A cathode electrode in contact with the semiconductor substrate, The anode electrode and the p-type semiconductor layer in contact with the drift layer are provided. The p-type semiconductor layer includes a first p-type semiconductor layer in contact with the anode electrode and a second p-type semiconductor layer in contact with the drift layer. A junction barrier Schottky diode characterized in that the valence band upper level of the second p-type semiconductor layer is lower than the valence band upper level of the first p-type semiconductor layer.

2. The junction barrier Schottky diode according to claim 1, characterized in that the second p-type semiconductor layer and the first p-type semiconductor layer are stacked in this order on the flat upper surface of the drift layer.

3. The junction barrier Schottky diode according to claim 1, characterized in that the drift layer has trenches and at least a portion of the p-type semiconductor layer is embedded in the trenches.

4. The junction barrier Schottky diode according to any one of claims 1 to 3, characterized in that the energy difference between the Fermi level and the upper valence band level of the first p-type semiconductor layer is 1 eV or less, and the energy difference between the upper valence band level of the second p-type semiconductor layer and the upper valence band level of the drift layer is 2 eV or less.

5. The p-type semiconductor layer further includes a third p-type semiconductor layer located between the first p-type semiconductor layer and the second p-type semiconductor layer. The junction barrier Schottky diode according to any one of claims 1 to 4, characterized in that the valence band upper level of the third p-type semiconductor layer is lower than the valence band upper level of the first p-type semiconductor layer and higher than the valence band upper level of the second p-type semiconductor layer.

Citation Information

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