Junction barrier Schottky diode

Abstract

To lower the on-resistance of a junction barrier Schottky diode in which a gallium oxide is used.SOLUTION: A junction barrier Schottky diode 1 includes: a semiconductor substrate 20 and a drift layer 30 that are formed from a gallium oxide; an anode electrode 40 and a p-type semiconductor layer 60 that are in contact with the drift layer 30; an n-type semiconductor layer 70 that is in contact with the anode electrode 40 and the drift layer 30; a metal layer 80 that is provided between the n-type semiconductor layer 70 and the p-type semiconductor layer 60; and a cathode electrode 50 that is in contact with the semiconductor substrate 20. The on-resistance of the junction barrier Schottky diode is thus lowered in the lead up to a forward current flowing to a p-n junction section since the n-type semiconductor layer 70 functions as a current path.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a junction barrier Schottky diode, and more particularly to a junction barrier Schottky diode using gallium oxide. [Background technology]

[0002] Schottky barrier diodes are rectifier elements that utilize the Schottky barrier created by the junction of a metal and a semiconductor. Compared to ordinary diodes with a PN junction, they have a lower forward voltage and a faster switching speed. For this reason, Schottky barrier diodes are sometimes used as switching elements in power devices.

[0003] When Schottky barrier diodes are used as switching elements for power devices, it is necessary to ensure sufficient reverse breakdown voltage. Therefore, instead of silicon (Si), silicon carbide (SiC), gallium nitride (GaN), and gallium oxide (Ga2O3), which have larger band gaps, are sometimes used. Among these, gallium oxide has a very large band gap of 4.8 to 4.9 eV and a large dielectric breakdown field of approximately 8 MV / cm, making Schottky barrier diodes using gallium oxide very promising as switching elements for power devices. An example of a Schottky barrier diode using gallium oxide is described in Patent Document 1.

[0004] Patent Document 1 discloses a junction barrier Schottky diode having a structure in which multiple trenches provided in a gallium oxide layer are filled with a p-type semiconductor material. In this way, by providing multiple trenches in a gallium oxide layer and filling the multiple trenches with a p-type semiconductor material, when a reverse voltage is applied, the mesa region located between the trenches becomes a depletion layer, causing the channel region of the drift layer to be pinched off. This makes it possible to significantly suppress leakage current when a reverse voltage is applied. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2019-036593 [Overview of the project] [Problems that the invention aims to solve]

[0006] However, the junction barrier Schottky diode described in Patent Document 1 has a problem in that, because the region that functions as a Schottky barrier diode is small, the on-resistance is high between the time the Schottky barrier diode is turned on and the time when forward current flows through the pn junction.

[0007] Therefore, the present invention aims to reduce the on-resistance of a junction barrier Schottky diode using gallium oxide. [Means for solving the problem]

[0008] The junction barrier Schottky diode according to the present invention is characterized by comprising a semiconductor substrate made of gallium oxide, a drift layer made of gallium oxide provided on the semiconductor substrate, an anode electrode and a p-type semiconductor layer in contact with the drift layer, an n-type semiconductor layer in contact with the anode electrode and the drift layer, a metal layer provided between the n-type semiconductor layer and the p-type semiconductor layer, and a cathode electrode in contact with the semiconductor substrate.

[0009] According to the present invention, since an n-type semiconductor layer is provided in contact with the anode electrode and the drift layer, the n-type semiconductor layer functions as a current path. This makes it possible to reduce the on-resistance until forward current flows through the pn junction. Moreover, since the anode electrode and the p-type semiconductor layer are not in direct contact, but rather an n-type semiconductor layer and a metal layer are provided between them, the resistance value of the current path passing through the p-type semiconductor layer is also reduced.

[0010] In the present invention, the metal layer may include a first metal layer that makes an ohmic contact with the n-type semiconductor layer and a second metal layer that makes an ohmic contact with the p-type semiconductor layer. According to this, it becomes possible to reduce the resistance between the metal layer and the n-type semiconductor layer and the p-type semiconductor layer.

[0011] In the present invention, the p-type semiconductor layer and the metal layer may be laminated in this order on the flat surface of the drift layer, and the n-type semiconductor layer may be provided so as to cover the surface of the laminate composed of the p-type semiconductor layer and the metal layer. According to this, it becomes possible to fabricate with a simple manufacturing process.

[0012] In the present invention, the drift layer may have a trench, and at least a part of the p-type semiconductor layer may be embedded in the trench. According to this, it becomes possible to expand the contact area between the p-type semiconductor layer and the drift layer. In this case, at least a part of the n-type semiconductor layer may be embedded in the trench. According to this, it becomes possible to expand the contact area between the n-type semiconductor layer and the drift layer. Further, in this case, the p-type semiconductor layer may be provided along the inner wall of the trench, and the metal layer may be provided between the inner wall of the p-type semiconductor layer and the outer wall of the n-type semiconductor layer. According to this, it becomes possible to expand the surface area of the metal layer.

Advantages of the Invention

[0013] Thus, according to the present invention, it becomes possible to reduce the on-resistance of the junction barrier Schottky diode using gallium oxide.

Brief Description of the Drawings

[0014] [Figure 1] FIG. 1(a) is a schematic plan view showing the configuration of a junction barrier Schottky diode 1 according to the first embodiment of the present invention. Further, FIG. 1(b) is a schematic cross-sectional view taken along the line A-A shown in FIG. 1(a). [Figure 2]FIG. 2 is an energy band diagram of the junction barrier Schottky diode 1, where (a) shows the energy band in the first current path P1, and (b) shows the energy band in the second current path P2. [Figure 3] FIG. 3 is a graph showing the relationship between the forward voltage VF and the forward current IF. [Figure 4] FIG. 4 is a schematic plan view showing the configuration of the junction barrier Schottky diode according to the first modification example. [Figure 5] FIG. 5 is a schematic plan view showing the configuration of the junction barrier Schottky diode according to the second modification example. [Figure 6] FIG. 12 is a schematic plan view showing the configuration of the junction barrier Schottky diode according to the third modification example. [Figure 7] FIG. 7(a) is a schematic plan view showing the configuration of the junction barrier Schottky diode according to the fourth modification example. Further, FIG. 7(b) is a schematic cross-sectional view taken along the line A-A shown in FIG. 7(a). [Figure 8] FIG. 8 is a schematic cross-sectional view showing the configuration of the junction barrier Schottky diode 2 according to the second embodiment of the present invention. [Figure 9] FIG. 9 is an energy band diagram of the junction barrier Schottky diode 2, showing the energy band of the second current path P2 in the first example. [Figure 10] FIG. 10 is an energy band diagram of the junction barrier Schottky diode 2, showing the energy band of the second current path P2 in the second example. [Figure 11] FIG. 11(a) is a schematic plan view showing the configuration of the junction barrier Schottky diode 3 according to the third embodiment of the present invention. Further, FIG. 11(b) is a schematic cross-sectional view taken along the line A-A shown in FIG. 11(a). [Figure 12] FIG. 12 is a schematic plan view showing the configuration of the junction barrier Schottky diode according to the fifth modification example. [Figure 13] Figure 13 is a schematic plan view showing the configuration of a junction barrier Schottky diode according to the sixth modification. [Figure 14] Figure 14(a) is a schematic plan view showing the configuration of a junction barrier Schottky diode according to the seventh modification. Figure 14(b) is a roughly cross-sectional view along line AA shown in Figure 14(a). [Figure 15] Figure 15 is a schematic cross-sectional view showing the configuration of a junction barrier Schottky diode according to the eighth modification. [Figure 16] Figure 16 is a schematic cross-sectional view showing the configuration of a junction barrier Schottky diode according to the ninth modification. [Figure 17] Figure 17 is a schematic cross-sectional view showing the configuration of a junction barrier Schottky diode according to the tenth modification. [Figure 18] Figure 18 is a schematic cross-sectional view showing the configuration of a junction barrier Schottky diode according to the 11th modification. [Figure 19] Figure 19(a) is a schematic plan view showing the configuration of a junction barrier Schottky diode according to the twelfth modification. Figure 19(b) is a roughly cross-sectional view along line AA shown in Figure 19(a). [Figure 20] Figure 20 is a schematic cross-sectional view showing the configuration of a junction barrier Schottky diode according to the 13th modification. [Modes for carrying out the invention]

[0015] Preferred embodiments of the present invention will be described in detail below with reference to the attached drawings.

[0016] <First Embodiment> Figure 1(a) is a schematic plan view showing the configuration of a junction barrier Schottky diode 1 according to the first embodiment of the present invention. Figure 1(b) is a substantially cross-sectional view along line AA shown in Figure 1(a).

[0017] As shown in Figure 1, the junction barrier Schottky diode 1 according to the first embodiment comprises a semiconductor substrate 20 and a drift layer 30, both made of gallium oxide (β-Ga2O3). Silicon (Si) or tin (Sn) is introduced as an n-type dopant in the semiconductor substrate 20 and the drift layer 30. The dopant concentration is higher in the semiconductor substrate 20 than in the drift layer 30, and as a result, the semiconductor substrate 20 is n + Layer, drift layer 30 is n - It functions as a layer. The impurity concentration of the semiconductor substrate 20 is, for example, 1 × 10⁻⁶. 18 cm -3 The impurity concentration in the drift layer 30 is, for example, 3 × 10⁻⁶. 16 cm -3 It is to that extent.

[0018] The semiconductor substrate 20 is formed by cutting a bulk crystal created using a method such as melt growth, and its thickness is approximately 250 μm. The planar size of the semiconductor substrate 20 is not particularly limited, but is generally selected according to the amount of current flowing through the device. If the maximum forward current is approximately 20 A, then a planar size of approximately 2.4 mm × 2.4 mm is sufficient.

[0019] The semiconductor substrate 20 has an upper surface 21 that is located on the upper side during mounting, and a back surface 22 that is on the opposite side of the upper surface 21 and located on the lower side during mounting. A drift layer 30 is formed on the entire surface of the upper surface 21. The drift layer 30 is a thin film of gallium oxide epitaxially grown on the upper surface 21 of the semiconductor substrate 20 using reactive sputtering, PLD method, MBE method, MOCVD method, HVPE method, etc. The thickness of the drift layer 30 is not particularly limited, but is generally selected according to the reverse withstand voltage of the device, and for example, a thickness of about 7 μm is sufficient to ensure a withstand voltage of about 600 V.

[0020] On the upper surface 31 of the drift layer 30, a p-type semiconductor layer 60 and a metal layer 80 are laminated in this order, an n-type semiconductor layer 70 covering the surface of the laminate composed of the p-type semiconductor layer 60 and the metal layer 80, and an anode electrode 40 covering the n-type semiconductor layer 70 and making a Schottky contact with the drift layer 30 are formed. The anode electrode 40 is made of a metal such as platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), molybdenum (Mo), copper (Cu), etc. The anode electrode 40 may have a multilayer structure in which different metal films are laminated, for example, Pt / Au, Pt / Al, Pd / Au, Pd / Al, Pt / Ti / Au or Pd / Ti / Au.

[0021] The p-type semiconductor layer 60 and the metal layer 80 are formed in a double ring shape in plan view, and the p-type semiconductor layer 60 and the metal layer 80 are laminated in this order on the flat upper surface 31 of the drift layer 30. Thereby, the p-type semiconductor layer 60 forms a pn junction with the drift layer 30. As the material of the p-type semiconductor layer 60, Si, GaAs, GaN, SiC, Ge, ZnSe, CdS, InP, SiGe, AlN, BN, AlGaN, NiO, Cu2O, Ir2O3, Ag2O, etc. can be used. As an example, as the p-type semiconductor layer 60, p-type Si with an impurity concentration of about 1×10 18 cm -3 and a thickness of about 200 nm can be selected.

[0022] The n-type semiconductor layer 70 makes a Schottky contact with the anode electrode 40 and serves to reduce the contact resistance that occurs when the anode electrode 40 and the p-type semiconductor layer 60 are in direct contact. Also, the n-type semiconductor layer 70 is in direct contact with the drift layer 30. In the example shown in FIG. 1, the n-type semiconductor layer 70 is in contact with the side surface of the p-type semiconductor layer 60 and the upper surface and side surface of the metal layer 80. As the material of the n-type semiconductor layer 70, a semiconductor material with a small band gap from which both p-type and n-type conductivity types can be obtained, for example, a material in which an n-type dopant is introduced into the same material as the p-type semiconductor layer 60 can be used. As an example, as the n-type semiconductor layer 70, n-type Ge or n-type Si with an impurity concentration of about 1×10 15 cm -3 and a thickness of about 200 nm can be selected.

[0023] The metal layer 80 is provided between the p-type semiconductor layer 60 and the n-type semiconductor layer 70, and plays a role in preventing the formation of a depletion layer caused by direct contact between the p-type semiconductor layer 60 and the n-type semiconductor layer 70. As the material for the metal layer 80, Al, Pt, Pd, etc. can be used. For example, if the n-type semiconductor layer 70 is made of n-type Si and the p-type semiconductor layer 60 is made of p-type Si, then Al with a thickness of about 100 nm can be selected as the metal layer 80.

[0024] A cathode electrode 50 is provided on the back surface 22 of the semiconductor substrate 20, which makes ohmic contact with the semiconductor substrate 20. The cathode electrode 50 is made of a metal such as titanium (Ti). The cathode electrode 50 may have a multilayer structure in which different metal films are stacked, for example, Ti / Au or Ti / Al.

[0025] When a forward voltage is applied to the junction barrier Schottky diode 1 according to this embodiment, three current paths are formed from the anode electrode 40 to the drift layer 30. The first current path, as indicated by the symbol P1 in Figure 1(b), is a path in which current flows directly from the anode electrode 40 to the drift layer 30 without passing through the p-type semiconductor layer 60 and the n-type semiconductor layer 70. The second current path, as indicated by the symbol P2 in Figure 1(b), is a path that passes through the n-type semiconductor layer 70, the metal layer 80, and the p-type semiconductor layer 60. The third current path, as indicated by the symbol P3 in Figure 1(b), is a path that passes through the n-type semiconductor layer 70 without passing through the p-type semiconductor layer 60.

[0026] Figure 2 is an energy band diagram of the junction barrier Schottky diode 1 according to this embodiment, where (a) shows the energy band in the first current path P1 and (b) shows the energy band in the second current path P2.

[0027] As shown in Figure 2(a), in the first current path P1, the anode electrode 40 and the drift layer 30 are in Schottky contact, and this portion functions as a Schottky barrier diode. Therefore, because the forward voltage is low and the switching speed is fast, it turns on first when a forward voltage is applied. The height of the Schottky barrier between the anode electrode 40 and the drift layer 30 is Φ b1 Here, E F This is the Fermi level, E C E is the lower end level of the conduction band. V E is the upper level of the valence band. g This refers to the energy band gap.

[0028] In contrast, as shown in Figure 2(b), in the second current path P2, an n-type semiconductor layer 70, a metal layer 80, and a p-type semiconductor layer 60 are interposed between the anode electrode 40 and the drift layer 30. Therefore, after current flows through the first current path P1, the second current path P2 turns on when a higher forward voltage is applied. This significantly reduces the on-resistance. Here, E S This is the vacuum level.

[0029] Figure 3 is a graph showing the relationship between the forward voltage VF and the forward current IF, where symbol A represents the characteristics of the junction barrier Schottky diode 1 according to this embodiment, and symbol B represents the characteristics of a general Schottky barrier diode. As shown in Figure 3, in a general Schottky barrier diode, if a sudden large current (surge current) such as 100A flows, a voltage of approximately 50V is generated, causing burnout due to a large amount of heat. In contrast, in the junction barrier Schottky diode 1 according to this embodiment, even if a surge current of 100A flows, the second current path P2 is turned on, so the generated voltage is suppressed to about 5V.

[0030] Furthermore, in this embodiment, an n-type semiconductor layer 70 and a metal layer 80 are arranged in this order between the anode electrode 40 and the p-type semiconductor layer 60. As shown in Figure 2(b), the energy difference of the vacuum levels between the anode electrode 40 and the n-type semiconductor layer 70 is Φb2 The energy difference between the vacuum levels of the n-type semiconductor layer 70 and the metal layer 80 is Φ b3 The energy difference between the vacuum levels of the metal layer 80 and the p-type semiconductor layer 60 is Φ b4 The energy difference between the upper valence band level of the p-type semiconductor layer 60 and the upper valence band level of the drift layer 30 is ΔE V In this embodiment, the p-type semiconductor layer 60 does not directly contact the anode electrode 40, but rather an n-type semiconductor layer 70 and a metal layer 80 are provided between them, thereby reducing the resistance between the anode electrode 40 and the p-type semiconductor layer 60. As a result, the surge withstand capability increases compared to the case where the n-type semiconductor layer 70 and the metal layer 80 are not present.

[0031] Here, if n-type Si is used as the material for the n-type semiconductor layer 70, Al is used as the material for the metal layer 80, and p-type Si is used as the material for the p-type semiconductor layer 60, the energy difference Φ b2 The energy difference is approximately 0.9 eV, Φ b3 The energy difference is approximately 0.1 eV, Φ b4 The energy difference is approximately 0.8 eV. V The voltage is approximately 4.3 eV. Therefore, the contact between the n-type semiconductor layer 70 and the metal layer 80, and the contact between the metal layer 80 and the p-type semiconductor layer 60, are ohmic contacts. In contrast, if the n-type semiconductor layer 70 and the metal layer 80 are not provided, and ohmic contact cannot be ensured between the anode electrode 40 and the p-type semiconductor layer 60, a relatively large voltage may be generated by surge current, as shown by characteristic C in Figure 3.

[0032] Furthermore, as shown in Figure 1(b), the junction barrier Schottky diode 1 according to this embodiment also has a third current path P3. The third current path P3 is a path through which current flows from the anode electrode 40 to the drift layer 30 via the n-type semiconductor layer 70. Since the anode electrode 40 and the n-type semiconductor layer 70 are in Schottky contact, it turns on almost simultaneously with the first current path P1. Because the third current path P3 does not include a p-type semiconductor layer 60, its resistance is at the same level as that of the first current path P1.

[0033] As described above, in this embodiment, the junction barrier Schottky diode 1 has an n-type semiconductor layer 70 and a metal layer 80 interposed between the anode electrode 40 and the p-type semiconductor layer 60, thereby reducing the resistance between the anode electrode 40 and the p-type semiconductor layer 60, and thus enabling a large surge withstand capability. Moreover, in this embodiment, a third current path P3 that does not pass through the p-type semiconductor layer 60 is also formed, making it possible to further reduce the on-resistance. Furthermore, since the p-type semiconductor layer 60, the metal layer 80 and the n-type semiconductor layer 70 are formed on the flat upper surface 31 of the drift layer 30, it can be manufactured using a simple manufacturing process.

[0034] Here, the planar shape of the p-type semiconductor layer 60 is not limited to the shape shown in Figure 1(a). It may be striped, as in the first modified example shown in Figure 4; it may be dotted, as in the second modified example shown in Figure 5; or it may be a combination of rings and stripes, as in the third modified example shown in Figure 6. Furthermore, as in the fourth modified example shown in Figure 7, a field insulating film 90 may be provided on the upper surface 31 of the drift layer 30, and the end of the anode electrode 40 may be placed on the field insulating film 90. By adopting such a field plate structure, it becomes possible to mitigate the electric field applied to the drift layer 30.

[0035] <Second Embodiment> Figure 8 is a schematic cross-sectional view showing the configuration of a junction barrier Schottky diode 2 according to a second embodiment of the present invention.

[0036] As shown in Figure 8, the junction barrier Schottky diode 2 according to the second embodiment differs from the junction barrier Schottky diode 1 according to the first embodiment in that the metal layer 80 consists of a first metal layer 81 and a second metal layer 82. Since the other basic configurations are the same as those of the junction barrier Schottky diode 1 according to the first embodiment, the same reference numerals are used for the same elements, and redundant explanations are omitted.

[0037] In this embodiment, Si, SiC, GaN, C, Ge, GaAs, BN, AlN, etc. can be used as the material for the n-type semiconductor layer 70. For the first metal layer 81, a material with a low work function that makes ohmic contact with the n-type semiconductor layer 70 is selected. For example, if the n-type semiconductor layer 70 is made of Si or SiC, Al can be used as the material for the first metal layer 81, and if the n-type semiconductor layer 70 is made of GaN, Ti can be used as the material for the first metal layer 81. On the other hand, for the second metal layer 82, a material with a high work function that makes ohmic contact with the p-type semiconductor layer 60 is selected. As a first example, if the n-type semiconductor layer 70 is made of n-type Si and the p-type semiconductor layer 60 is made of p-type Si, then Al with a thickness of about 100 nm can be selected as the first metal layer 81, and Pt with a thickness of about 100 nm can be selected as the second metal layer 82. As a second example, if the n-type semiconductor layer 70 is made of n-type Si and the p-type semiconductor layer 60 is made of p-type BN, then Al can be selected as the first metal layer 81 and Pd can be selected as the second metal layer 82. In both the first and second examples described above, the impurity concentration of the n-type semiconductor layer 70 is 1 × 10⁻⁶. 16 cm -3 A silicon alloy with a thickness of approximately 200 nm can be selected.

[0038] Figures 9 and 10 are energy band diagrams of the junction barrier Schottky diode 2 according to this embodiment, showing the energy bands of the second current path P2 in the first and second examples described above, respectively.

[0039] As shown in Figure 9, in the first example, the energy difference Φ b4 This is reduced to approximately 0.3 eV. Furthermore, as shown in Figure 10, in the second example, the energy difference Φ b4 This is reduced to about 0.1 eV. In the second example, the energy difference ΔE VThe on-resistance is approximately 2.8 eV. Thus, by creating a two-layer structure for the metal layer 80, selecting a material that makes ohmic contact with the n-type semiconductor layer 70 as the material for the first metal layer 81, and selecting a material that makes ohmic contact with the p-type semiconductor layer 60 as the material for the second metal layer 82, the on-resistance in the second current path P2 can be further reduced.

[0040] <Third Embodiment> Figure 11(a) is a schematic plan view showing the configuration of a junction barrier Schottky diode 3 according to a third embodiment of the present invention. Figure 11(b) is a substantially cross-sectional view along line AA shown in Figure 11(a).

[0041] As shown in Figure 11, the junction barrier Schottky diode 3 according to the third embodiment differs from the junction barrier Schottky diode 2 according to the second embodiment in that a trench 32 is provided in the drift layer 30, and the p-type semiconductor layer 60 and the metal layer 80 are embedded in the trench 32. The other basic configurations are the same as those of the junction barrier Schottky diode 2 according to the second embodiment, so the same reference numerals are used for the same elements, and redundant explanations are omitted.

[0042] The trench 32 has a depth that does not reach the semiconductor substrate 20 from the upper surface 31 of the drift layer 30, and is formed in a double ring shape in plan view. For example, the depth of the trench 32 can be about 3 μm, and the width of the trench 32 can be about 1.5 μm. A p-type semiconductor layer 60 and a metal layer 80 are embedded inside the trench 32. The n-type semiconductor layer 70 is located outside the trench 32 and is in contact with the first metal layer 81 and the drift layer 30.

[0043] Thus, in the junction barrier Schottky diode 3 according to the third embodiment, the p-type semiconductor layer 60 is embedded in the trench 32 provided in the drift layer 30, which increases the contact area between the p-type semiconductor layer 60 and the drift layer 30. This makes it possible to further reduce the resistance value of the second current path P2.

[0044] Here, the planar shape of the trench 32 is not limited to the shape shown in Figure 11(a), but may be striped as in the fifth modified example shown in Figure 12, or a combination of rings and stripes as in the sixth modified example shown in Figure 13. Furthermore, as in the seventh modified example shown in Figure 14, a field insulating film 90 may be provided on the upper surface 31 of the drift layer 30, and the end of the anode electrode 40 may be placed on the field insulating film 90. By adopting such a field plate structure, it is possible to mitigate the electric field applied to the drift layer 30.

[0045] Furthermore, as shown in the eighth modified example in Figure 15, a portion of the n-type semiconductor layer 70 may be embedded in the trench 32, or as shown in the ninth modified example in Figure 16, the entire n-type semiconductor layer 70 may be embedded in the trench 32. By embedding at least a portion of the n-type semiconductor layer 70 in the trench 32 in this way, the contact area between the n-type semiconductor layer 70 and the drift layer 30 is increased, making it possible to further reduce the resistance value of the third current path P3. In addition, as shown in the tenth modified example in Figure 17, an insulating film 91 may be provided between the metal layer 80 and the drift layer 30.

[0046] Furthermore, as shown in the 11th modified example in Figure 18, a p-type semiconductor layer 60 may be provided along the inner wall of the trench 32, and a metal layer 80 may be provided between the outer wall of the n-type semiconductor layer 70 embedded in the trench 32 and the inner wall of the p-type semiconductor layer 60. This increases the contact area between the p-type semiconductor layer 60 and the drift layer 30, and also increases the surface area of ​​the metal layer 80, making it possible to further reduce the resistance value of the second current path P2.

[0047] Furthermore, as shown in the 12th modified example in Figure 19, an outer periphery trench 33 surrounding the trench 32 may be provided in the drift layer 30, and the p-type semiconductor layer 60 in contact with the anode electrode 40 may be embedded in the outer periphery trench 33. Alternatively, as shown in the 13th modified example in Figure 20, the inner wall of the outer periphery trench 33 may be covered with an insulating film 92, and the anode electrode 40 may be embedded in the outer periphery trench 33. Providing such an outer periphery trench 33 makes it possible to mitigate the electric field concentrated at the bottom of the trench 32.

[0048] Although preferred embodiments of the present invention have been described above, it goes without saying that the present invention is not limited to the above embodiments, and various modifications are possible without departing from the spirit of the invention, and these modifications are also included within the scope of the present invention. [Explanation of Symbols]

[0049] 1-3 Junction barrier Schottky diodes 20 Semiconductor substrates 21 Top surface of semiconductor substrate 22 Back surface of semiconductor substrate 30 drift layers 31 Top surface of semiconductor substrate 32 Trench 33 Outer trench 40 Anode electrodes 50 Cathode electrodes 60 p-type semiconductor layer 70 n-type semiconductor layer 80 metal layer 81 First metal layer 82 Second metal layer 90 Field Insulator 91,92 Insulating film P1 First current path P2 Second current path P3 Third current path

Claims

1. A semiconductor substrate made of gallium oxide, A drift layer made of gallium oxide is provided on the semiconductor substrate, The anode electrode and p-type semiconductor layer in contact with the drift layer, The anode electrode and the n-type semiconductor layer in contact with the drift layer, A metal layer provided between the n-type semiconductor layer and the p-type semiconductor layer, A junction barrier Schottky diode characterized by comprising a cathode electrode in contact with the semiconductor substrate.

2. The junction barrier Schottky diode according to claim 1, characterized in that the metal layer includes a first metal layer that is in ohmic contact with the n-type semiconductor layer and a second metal layer that is in ohmic contact with the p-type semiconductor layer.

3. The p-type semiconductor layer and the metal layer are stacked in this order on the flat surface of the drift layer. The junction barrier Schottky diode according to claim 1 or 2, characterized in that the n-type semiconductor layer is provided so as to cover the surface of a laminate consisting of the p-type semiconductor layer and the metal layer.

4. The junction barrier Schottky diode according to claim 1 or 2, characterized in that the drift layer has trenches and at least a portion of the p-type semiconductor layer is embedded in the trenches.

5. The junction barrier Schottky diode according to claim 4, characterized in that at least a portion of the n-type semiconductor layer is embedded in the trench.

6. The p-type semiconductor layer is provided along the inner wall of the trench, The junction barrier Schottky diode according to claim 5, characterized in that the metal layer is provided between the inner wall of the p-type semiconductor layer and the outer wall of the n-type semiconductor layer.

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