Image sensor, image sensing system, and image sensing method

Abstract

To provide an image sensor with improved image quality.SOLUTION: An image sensor includes: a photoelectric converter that converts received light into charges and provides the charges to a first node; a transfer transistor that provides a voltage of the first node to a floating diffusion node; a reset transistor that resets a voltage of the floating diffusion node to a driving voltage based on a reset signal; a source follower transistor that provides a unit pixel output based on the voltage of the floating diffusion node; a select transistor that is connected to the source follower transistor and gated with a selection signal to output the unit pixel output to the outside; and a ferroelectric capacitor that is connected to the floating diffusion node. The ferroelectric capacitor adjusts a conversion gain of the floating diffusion node based on a conversion gain mode of the ferroelectric capacitor, the conversion gain mode being a first conversion gain mode, a second conversion gain mode, or a third conversion gain mode.SELECTED DRAWING: Figure 9

Description

Technical Field

[0001] The present invention relates to an image sensor, an image sensing system, and an image sensing method, and particularly to an image sensor, an image sensing system, and an image sensing method including a ferroelectric capacitor.

Background Art

[0002] An image sensing device is one of semiconductor devices that convert optical information into an electrical signal. Such image sensing devices include a charge-coupled device (CCD) image sensing device and a complementary metal-oxide semiconductor (CMOS) image sensing device. The CMOS type image sensor can also be abbreviated as CIS (CMOS image sensor). CIS includes a plurality of pixels two-dimensionally arranged. Each pixel includes, for example, a photodiode (PD). The photodiode serves to convert incident light into an electrical signal.

[0003] In recent years, with the development of the computer industry and the communication industry, the demand for image sensors with improved performance in various fields such as digital cameras, camcorders, smartphones, game devices, security cameras, medical microcameras, robots, and vehicles has increased, and the development of image sensors having more improved image quality has become an issue.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

[0005] The present invention has been made in view of the problems of the above-mentioned conventional image sensors, and the object of the present invention is to provide an image sensor having improved image quality. Another object of the present invention is to provide an image sensing method having improved image quality and an image sensing system having improved image quality. [Means for solving the problem]

[0006] To achieve the above objective, the image sensor according to the present invention comprises: a photoelectric conversion unit that reacts to received light and converts the received light into an electric charge and provides it to a first node; a transfer transistor that provides the voltage of the first node to a floating diffusion node (FD node); a reset transistor that resets the voltage of the floating diffusion node to a drive voltage based on a reset signal; a source follower transistor that provides a unit pixel output based on the voltage of the floating diffusion node; a selection transistor connected to the source follower transistor that is gated according to a selection signal and outputs the unit pixel output to the outside; and a ferroelectric capacitor connected to the floating diffusion node. The device comprises a first transistor connected between the ferroelectric capacitor and the plate line (PL), and a second transistor connected between the ferroelectric capacitor and the floating diffusion node. The ferroelectric capacitor is characterized in that the conversion gain of the floating diffusion node is adjusted based on the conversion gain (CG) scheme of the ferroelectric capacitor, and the conversion gain scheme is a first conversion gain scheme, a second conversion gain scheme, or a third conversion gain scheme.

[0007] To achieve the above objective, the present invention provides an image sensing system comprising: an image sensor that outputs an image signal; an image signal processor (ISP) electrically connected to the image sensor and processing the image signal provided by the image sensor, wherein the image sensor includes: a photoelectric conversion unit that reacts to received light and converts the received light into an electric charge and provides it to a first node; a transfer transistor that provides the voltage of the first node to a floating diffusion node (FD node); a reset transistor that resets the voltage of the floating diffusion node to a drive voltage based on a reset signal; and a ferroelectric capacitor connected to the floating diffusion node. The device comprises a first transistor connected between the ferroelectric capacitor and the plate line (PL), and a second transistor connected between the ferroelectric capacitor and the floating diffusion node. The ferroelectric capacitor adjusts the conversion gain of the floating diffusion node based on the conversion gain scheme of the ferroelectric capacitor, and the conversion gain scheme is characterized in that it is a first conversion gain scheme, a second conversion gain scheme, or a third conversion gain scheme.

[0008] To achieve the above objective, the present invention provides an image sensing method comprising: a ferroelectric capacitor having one end connected to a floating diffusion node and the other end connected to ground; a first transistor having one end connected to one end of the ferroelectric capacitor and the other end connected to a plate line (PL); and a second transistor having one end connected to the one end of the ferroelectric capacitor and the other end connected to the floating diffusion node; and a method for adjusting the conversion gain of the floating diffusion node based on a conversion gain scheme of the ferroelectric capacitor, which is a first conversion gain scheme, a second conversion gain scheme, or a third conversion gain scheme, by the operation of the ferroelectric capacitor, the first transistor, and the second transistor, wherein in the first conversion gain scheme, the first transistor is turned on at a first time point before the light received by the floating diffusion node is provided with converted charge, and the second transistor is turned on at a second time point after the first time point. In the second conversion gain scheme, the first transistor is turned on at a third time point, before the light received by the floating diffusion node is provided with converted charge, and is turned off at a fourth time point, after the third time point. At the fourth time point, the second transistor is turned on, and a first ferroelectric capacitor reset voltage is applied to the plate line at the third time point. At a fifth time point, between the third and fourth time points, a second ferroelectric capacitor reset voltage different from the first ferroelectric capacitor reset voltage is applied to the plate line, and in the third conversion gain scheme, the first and second transistors are turned off. [Effects of the Invention]

[0009] According to the image sensor, image sensing system, and image sensing method of the present invention, an improved image sensor, image sensing system, and image sensing method can be provided by using a ferroelectric capacitor contained inside and having different capacitance values ​​for the floating diffusion nodes according to their respective conversion gain methods. [Brief explanation of the drawing]

[0010] [Figure 1] This is a block diagram showing a schematic configuration of an image sensor according to an embodiment of the present invention. [Figure 2] This is an exemplary circuit diagram illustrating a unit pixel of an image sensor according to an embodiment of the present invention. [Figure 3] This is an exemplary circuit diagram illustrating the operation of a unit pixel in an image sensor according to an embodiment of the present invention. [Figure 4] This is an exemplary circuit diagram illustrating the operation of a unit pixel in an image sensor according to an embodiment of the present invention. [Figure 5] This is an exemplary circuit diagram illustrating the operation of a unit pixel in an image sensor according to an embodiment of the present invention. [Figure 6] This is an exemplary circuit diagram illustrating the operation of a unit pixel in an image sensor according to an embodiment of the present invention. [Figure 7] This is an exemplary circuit diagram illustrating a unit pixel of an image sensor according to another embodiment of the present invention. [Figure 8] This is a graph illustrating the operation of an image sensor according to an embodiment of the present invention. [Figure 9] This is an exemplary circuit diagram of a unit pixel included in an image sensor according to an embodiment of the present invention. [Figure 10] This is an exemplary timing diagram illustrating the operation of an image sensor according to an embodiment of the present invention. [Figure 11] This is an exemplary timing diagram illustrating the operation of an image sensor according to an embodiment of the present invention. [Figure 12] An exemplary timing diagram for explaining the operation of an image sensor according to an embodiment of the present invention. [Figure 13] An exemplary circuit diagram of a unit pixel included in an image sensor according to another embodiment of the present invention. [Figure 14] An exemplary timing diagram for explaining the operation of an image sensor according to another embodiment of the present invention. [Figure 15] An exemplary timing diagram for explaining the operation of an image sensor according to another embodiment of the present invention. [Figure 16] An exemplary timing diagram for explaining the operation of an image sensor according to another embodiment of the present invention. [Figure 17] A block diagram showing a schematic configuration of an electronic device including a multi-camera module according to an embodiment of the present invention. [Figure 18] A block diagram showing a detailed configuration of the camera module of FIG. 14.

Mode for Carrying Out the Invention

[0011] Next, specific examples of embodiments for implementing the image sensor, image sensing system, and image sensing method according to the present invention will be described with reference to the drawings.

[0012] FIG. 1 is a block diagram showing a schematic configuration of an image sensor according to an embodiment of the present invention. Referring to FIG. 1, an image sensor 100 according to an embodiment of the present invention includes a pixel array 110, a CDS (Correlated Double Sampler) 120, a column scan circuit 130, a row scan circuit 140, and a timing control circuit 150.

[0013] The pixel array 110 includes a plurality of unit pixels 112. The plurality of unit pixels 112 are arranged in a matrix form. The unit pixel 112 can be classified into 3-transistor structures, 4-transistor structures, 5-transistor structures, 6-transistor structures, etc., depending on the number of transistors included in the signal generation circuit. A row selection line is wired to each row of the pixel array 110, and a column selection line is wired to each column. For example, if the pixel array 110 contains M × N pixels (where M and N are integers greater than or equal to 2), then M row selection lines and N column selection lines are wired to the pixel array 110.

[0014] In some embodiments, when the image sensor 100 employs Bayer pattern technology, the pixels in the active pixel array 110 are arranged to receive red (R) light, green (G) light, and blue (B) light, respectively. Alternatively, pixels can be arranged to receive magenta (Mg), yellow (Y), cyan (Cy), and / or white (W) light. However, the embodiments are not limited thereto.

[0015] The CDS120 includes multiple ADCs (Analog to Digital Converters), including comparators, counters, and latches. The CDS120 is controlled by the timing control circuit 150. The CDS120 operates at each row scan cycle, i.e., each cycle during which the row scan circuit 140 selects a row selection line in the pixel array 110.

[0016] The low scan circuit 140 receives a control signal from the timing control circuit 150. The row scan circuit 140 controls row addressing and row scanning of the pixel array 110 based on the received control signal. At this time, the row scan circuit 140 applies a signal to the pixel array 110 to activate the row selection line in order to select the row selection line from among the row selection lines. The row scan circuit 140 includes a row decoder that selects row selection lines in the pixel array 110, and a row driver that supplies a signal to activate the selected row selection lines.

[0017] The column scan circuit 130 receives a control signal from the timing control circuit 150. The column scan circuit 130 controls the column addressing and column scanning of the pixel array 110 based on the received control signals. At this time, the column scan circuit 130 outputs the digital output signal from the CDS120 to a DSP (Digital Signal Processor), ISP (Image Signal Processor), or an external host. For example, the column scan circuit 130 sequentially selects multiple ADCs within the CDS120 by outputting a horizontal scanning control signal to the CDS120. In some embodiments, the column scan circuit 130 includes a column decoder that selects one of the ADCs and a column driver that directs the output of the selected unit ADC to a horizontal transmission line. On the other hand, horizontal transmission lines have a bit width for outputting digital output signals.

[0018] The timing control circuit 150 controls the CDS 120, the column scan circuit 130, and the row scan circuit 140, and provides control signals such as a clock signal and a timing control signal required for their operation. The timing control circuit 150 may include a logic control circuit, a phase lock loop (PLL) circuit, a timing control circuit, and a communication interface circuit.

[0019] Figure 2 is an exemplary circuit diagram illustrating a unit pixel of an image sensor according to an embodiment of the present invention, and Figures 3 to 6 are exemplary circuit diagrams illustrating the operation of a unit pixel of an image sensor according to an embodiment of the present invention. Figures 2 to 6 illustrate the unit pixels (112_1 to 112_3) according to the embodiments of the present invention.

[0020] Referring to Figure 2, a unit pixel (112_1) according to an embodiment of the present invention includes a photoelectric conversion unit PD, a transfer transistor TG, a reset transistor RG, a source follower transistor SF, and a selection transistor SG. According to one embodiment, one end of the photoelectric conversion unit PD is connected to the first node N1, and the other end is connected to, for example, ground.

[0021] The photoelectric conversion unit (PD) generates photocharges from light incident from an external source. In other words, the photoelectric converter (PD) receives light and converts the optical signal into an electrical signal. The photoelectric conversion unit PD provides the converted electrical signal to the first node N1. In this case, if the amount of light received from the outside is relatively large, the photoelectric converter PD generates a relatively large amount of charge. For example, see Figure 3. The photoelectric converter (PD) generates electrons (E) using light incident from an external source. The generated electrons E are supplied to the first node N1. In other words, when the photoelectric conversion unit PD receives light from an external source, the voltage level at the first node N1 decreases. For example, if the photoelectric converter PD receives a relatively large amount of light, the voltage level at the first node N1 decreases relatively significantly.

[0022] In some figures, the photoelectric conversion unit PD is represented by the symbol for a photodiode; however, this is for illustrative purposes only, and the embodiments are not limited thereto. The photoelectric conversion unit (PD) may include, in addition to photodiodes, phototransistors, photogates, pinned photodiodes (PPDs), organic photodiodes (OPDs), quantum dots (QDs), and combinations thereof.

[0023] According to one embodiment, the transfer transistor TG is connected to the first node N1 and the floating diffusion node FD. The transfer transistor TG gates the transfer line that receives the transfer signal TX. In one embodiment, a transfer signal TX is provided to a transfer line. In other words, the transfer signal TX is supplied to the gate terminal of the transfer transistor TG. In other words, the transfer signal TX controls the on / off state of the transfer transistor TG.

[0024] When the transfer transistor TG is turned on, the first node N1 and the floating diffusion node FD are electrically connected. In other words, when the transfer transistor TG is turned on, the voltage level of the first node N1 is applied to the floating diffusion node FD. In other words, when the transfer transistor TG is turned on, the voltage level of the first node N1, which has been changed by the photoelectric conversion unit PD, is transferred to the floating diffusion node FD. For example, if there is no light received from an external source, the voltage level of the floating diffusion node FD will not decrease even if the transfer transistor TG is turned on. When the amount of light received by the photoelectric converter PD is relatively small, the voltage level of the floating diffusion node FD decreases slightly when the transfer transistor TG is turned on. Conversely, if the photoelectric converter PD receives a relatively large amount of light, when the transfer transistor TG turns on, the voltage level of the floating diffusion node FD decreases relatively significantly. For example, see Figure 4. When the transfer transistor TG is turned on, electrons E from the first node N1 are supplied to the floating diffusion node FD. As electrons E are supplied to the floating diffusion node FD, the voltage level of the floating diffusion node FD decreases.

[0025] The transfer transistor TG may be implemented as an NMOS transistor, a PMOS transistor, or a CMOS transistor, but the embodiment is not limited thereto. According to one embodiment, the reset transistor RG is connected to the floating diffusion node FD and the first voltage source VDD. The reset transistor RG is gated according to the reset signal RX. In other words, the reset transistor RG is turned on / off based on the reset signal RX. In one embodiment, the voltage level of the reset signal RX includes a high level and a low level. For example, if the voltage level of the reset signal RX is high, the reset transistor RG turns on. When the voltage level of the reset signal RX is low, the reset transistor RG turns off.

[0026] In one embodiment, the voltage level of the first voltage source VDD is referred to as the reference voltage level VDD. In one embodiment, the first voltage source VDD and the reference voltage level VDD use the same reference numeral. When the reset transistor RG is turned on, the first voltage source VDD and the floating diffusion node FD are electrically connected. When the reset transistor RG is turned off, the first voltage source VDD and the floating diffusion node FD are electrically isolated. In other words, when the reset transistor RG is turned on, the voltage level of the floating diffusion node FD is increased by the voltage level of the first voltage source VDD. In other words, when the reset transistor RG is turned on, the floating diffusion node FD is reset to the same level as the reference voltage level VDD.

[0027] In one embodiment, the voltage level of the first node N1 decreases in accordance with the amount of light received by the photoelectric conversion unit PD. At this time, when the transfer transistor TG turns on, the voltage level of the floating diffusion node FD decreases. At this time, when the reset transistor RG turns on, the voltage level of the floating diffusion node FD increases again to the reference voltage level VDD. The reset transistor RG may be implemented as an NMOS transistor, a PMOS transistor, or a CMOS transistor, but the embodiment is not limited thereto.

[0028] According to one embodiment, the source follower transistor SF is connected to the second node N2 and the first voltage source VDD. The source follower transistor SF is gated to the floating diffusion node FD. In other words, the gate terminal of the source follower transistor SF receives the voltage level provided by the floating diffusion node FD. In one embodiment, a source follower transistor SF provides a specific voltage level to a second node N2 based on the voltage level of a floating diffusion node FD. In other words, the source follower transistor SF provides a unit pixel output based on the voltage of the floating diffusion node FD.

[0029] In one embodiment, the voltage level range of the floating diffusion node FD may be within the saturation region of the source follower transistor SF. In other words, the source follower transistor SF can always be in the turned-on state. Furthermore, the drain-source current of a source follower transistor SF can always be constant. In one embodiment, the source follower transistor SF operates as a common drain amplifier. In other words, the source follower transistor SF operates as a voltage buffer.

[0030] In one embodiment, the voltage level of the floating diffusion node FD is directly transmitted to the second node N2. In one embodiment, a case was described in which the reset transistor RG and the source follower transistor SF are connected to the first voltage source VDD, but the present invention is not limited thereto. For example, the reset transistor RG and the source follower transistor SF can be connected to different voltage sources. For example, see Figure 5. The electrons E provided to the floating diffusion node FD are then provided to the second node N2 via the floating diffusion node FD. At this time, the voltage level at the second node N2 decreases.

[0031] According to one embodiment, the selection transistor SG is connected to the output terminal OUT of the unit pixel (112_1) and the second node N2. The selection transistor SG is gated according to the selection signal SX. In other words, the gate terminal of the selection transistor SG receives the selection signal SX. In one embodiment, the voltage level of the selection signal SX includes high levels and low levels. For example, if the voltage level of the selection signal SX is high, the selection transistor SG turns on. When the voltage level of the selection signal SX is low, the selection transistor SG turns off. When the selection transistor SG is turned on, the second node N2 and the output terminal OUT of the unit pixel (112_1) are electrically connected.

[0032] In other words, when the selection transistor SG is turned on, the voltage level at the second node N2 is applied to the output terminal OUT of the unit pixel (112_1). In other words, when the selected transistor SG is turned on, the voltage level provided by the source follower transistor SF, based on the voltage of the floating diffusion node FD, is applied to the output terminal OUT. For example, see Figure 6. When the selection transistor SG is turned on, the electrons E supplied to the second node N2 are supplied to the output terminal OUT of the unit pixel (112_1). At this time, the voltage level at the output terminal OUT of the unit pixel (112_1) decreases.

[0033] Figure 7 is an exemplary circuit diagram illustrating a unit pixel of an image sensor according to another embodiment of the present invention. For the sake of clarity, redundant information will be omitted or briefly explained. Referring to Figure 7, the unit pixel (112_3) according to this embodiment includes first to fourth photoelectric conversion units (PD1 to PD4), first to fourth transfer transistors (TG1 to TG4), reset transistor RG, source follower transistor SF, selection transistor SG, first to fourth ferroelectric capacitors (FC1 to FC4), and first to eighth transistors (FS1 to FS8).

[0034] In one embodiment, one end of each of the first to fourth photoelectric conversion units (PD1 to PD4) is connected to the first to fourth nodes (N1 to N4), and the other end is connected to, for example, ground. The first to fourth photoelectric conversion units (PD1 to PD4) are identical or similar to the photoelectric conversion unit PD shown in Figures 2 to 6. For example, the first to fourth photoelectric conversion units (PD1 to PD4) generate electrons using light incident from an external source. The generated electrons are then supplied to the first to fourth nodes (N1 to N4). In other words, when the first to fourth photoelectric conversion units (PD1 to PD4) receive light from an external source, the voltage levels of the first to fourth nodes (N1 to N4) decrease.

[0035] In one embodiment, the first to fourth photoelectric conversion units (PD1 to PD4) receive visible light of different wavelengths. For example, although not shown in the diagram, color filters are placed on the first to fourth photoelectric conversion units (PD1 to PD4), and the first to fourth photoelectric conversion units (PD1 to PD4) receive visible light of different wavelengths from each other. For example, the first photoelectric conversion unit PD1 receives red (R) light. The second and third photoelectric conversion units (PD2 and PD3) receive green (G) light. The fourth photoelectric converter PD4 receives blue (B) light.

[0036] For example, the first photoelectric conversion unit PD1 receives magenta (M) light. The second photoelectric converter PD2 receives yellow (Y) light. The third photoelectric converter PD3 receives cyan (C) light. The fourth photoelectric converter, PD4, receives white (W) light. According to one embodiment, the first to fourth transfer transistors (TG1 to TG4) are connected to the first to fourth nodes (N1 to N4) and the floating diffusion node FD. The first to fourth transfer transistors (TG1 to TG4) are gated to different transfer lines. In other words, the gate terminals of the first to fourth transfer transistors (TG1 to TG4) each receive the first to fourth transfer signals (TX1 to TX4). In other words, a unit pixel (112_3) according to one embodiment has a structure that shares a floating diffuse node FD.

[0037] On the other hand, in one embodiment, a unit pixel (112_3) adjusts the capacitance of the floating diffusion node FD using first to fourth ferroelectric capacitors (FC1 to FC4) and first to eighth transistors (FS1 to FS8) connected to the floating diffusion node FD. The specific details will be explained later.

[0038] Figure 8 is a graph illustrating the operation of the image sensor according to an embodiment of the present invention. Referring to Figure 8, the ferroelectric capacitor included in the image sensor, which will be described later, operates on the graph shown in the figure. In other words, Figure 8 represents the hysteresis curve of a ferroelectric capacitor. In other words, ferroelectric capacitors may include materials such as HFOx, HfO2 / ZrO2, and PbTiO3, but the embodiments are not limited thereto.

[0039] On the other hand, in the hysteresis curve shown in Figure 8, the slope of the tangent line at each point represents the magnitude of the capacitance of the ferroelectric capacitor. Ferroelectric capacitors behave differently depending on the magnitude and direction of the applied voltage. For example, a ferroelectric capacitor has a first capacitance (Capacitance 1) in the case of the first conversion gain method, and a second capacitance (Capacitance 2) in the case of the second conversion gain method. In other words, the value of the first capacitance (Capacitance1) is smaller than the value of the second capacitance (Capacitance2). The specific details will be explained later.

[0040] Figure 9 is an exemplary circuit diagram of a unit pixel included in an image sensor according to an embodiment of the present invention. Content that overlaps with Figures 2 to 6 will be omitted, and the explanation will focus on the differences. Referring to Figure 9, the image sensor further includes a first transistor FS1, a second transistor FS2, a ferroelectric capacitor FC, and a plate line (PL).

[0041] One end of the first transistor FS1 is connected to one end of the ferroelectric capacitor FC. The other end of the first transistor FS1 is connected to the plate line. One end of the second transistor FS2 is connected to one end of the ferroelectric capacitor FC. The other end of the second transistor FS2 is connected to the floating diffusion node FD. One end of the ferroelectric capacitor FC is connected to one end of the first transistor FS1 and one end of the second transistor FS2. In other words, the ferroelectric capacitor FC and the first transistor FS1 are connected in parallel to each other. The other end of the ferroelectric capacitor FC is connected to ground. The plate line PL is configured to apply bias voltages that determine the operation of the first transistor FS1, the ferroelectric capacitor FC, and the second transistor FS2, but the embodiment is not limited thereto. On the other hand, Figure 9 shows the case where the first transistor FS1 and the second transistor FS2 are NMOS, but the embodiments are not limited to this.

[0042] Figure 10 is an exemplary timing diagram illustrating the operation of an image sensor according to an embodiment of the present invention. Specifically, Figure 10 is a timing diagram illustrating the operation of the first conversion gain method corresponding to the middle conversion gain of the image sensor.

[0043] Referring to Figure 10, at the first time point T1, the reset transistor RG turns on. The reset transistor RG is turned on, causing the floating diffusion node FD to be reset to the reset voltage Vo. In other words, the reset voltage Vo refers to the drive voltage VDD shown in Figure 9. In response, the voltage level of the floating diffusion node (FD) increases. At the second time point T2, the transfer transistor TG turns on. The transfer transistor TG is turned on and releases the charge from the photoelectric conversion section.

[0044] At the third time point T3, the transfer transistor TG turns off, and the first transistor FS1 turns on. In other words, as shown in Figure 9, the first transistor FS1 turns on and transmits the voltage applied to the plate line PL to the ferroelectric capacitor FC. Meanwhile, at the third time point T3, a ferroelectric capacitor reset voltage is applied to the plate line PL. The magnitude of the reset voltage of the ferroelectric capacitor is equal to the negative saturation voltage of the ferroelectric capacitor shown in Figure 8, and the magnitude of the negative saturation voltage may vary depending on the embodiment. At time point T4, the first transistor FS1 turns off, and the voltage applied to the plate line PL is interrupted. At time point T5, the second transistor FS2 turns on. When the second transistor FS2 is turned on, the floating diffusion node FD and the ferroelectric capacitor FC are electrically connected. At this point, referring to Figure 8, the ferroelectric capacitor FC has a first capacitance (Capacitance 1) value due to the negative voltage applied to the plate line on the hysteresis curve.

[0045] At point 6, T6, the reset transistor RG turns off. Also, at the sixth time point T6, the transfer transistor TG turns on. In other words, when the transfer transistor TG is turned on, the charge generated in response to the light received by the photoelectric conversion unit is supplied to the floating diffusion node FD. On the other hand, the voltage due to the charge supplied to the floating diffusion node FD has a middle conversion gain due to the ferroelectric capacitor FC having a first capacitance (Capacitance1). At time point T7, the transfer transistor TG turns off. In other words, the voltage level of the floating diffusion node FD decreases due to the charge supplied from the photoelectric conversion unit. At this time, the conversion gain of the floating diffusion node FD has a middle conversion gain as described above, and provides a corresponding voltage level to the source follower transistor SF.

[0046] Figure 11 is an exemplary timing diagram illustrating the operation of an image sensor according to an embodiment of the present invention. Specifically, Figure 11 is a timing diagram illustrating the operation using a second conversion gain method corresponding to the low conversion gain of the image sensor.

[0047] Referring to Figure 11, at the first time point T1, the reset transistor RG turns on. The reset transistor RG turns on and resets the floating diffusion node FD to the reset voltage Vo. In other words, the reset voltage Vo refers to the drive voltage VDD shown in Figure 9. In response, the voltage level of the floating diffusion node (FD) increases. At the second time point T2, the transfer transistor TG turns on. The transfer transistor TG turns on and releases the residual charge in the photoelectric conversion section.

[0048] At the third time point T3, the transfer transistor TG turns off, and the first transistor FS1 turns on. In other words, as shown in Figure 9, the first transistor FS1 turns on and transmits the voltage applied to the plate line PL to the ferroelectric capacitor FC. Meanwhile, at the third time point T3, a ferroelectric capacitor reset voltage is applied to the plate line PL. The magnitude of the reset voltage of the ferroelectric capacitor is the same as the negative saturation voltage of the ferroelectric capacitor shown in Figure 8, and the magnitude of the negative saturation voltage may vary depending on the embodiment. At time point T4, the voltage applied to the plate line PL is converted from a negative saturation voltage to a positive saturation voltage. In other words, the voltage applied to the plate line PL at the third time point T3 and the voltage applied to the plate line PL at the fourth time point T4 are voltages with the same magnitude but different signs.

[0049] At time point T5, the first transistor FS1 turns off, and the voltage applied to the plate line PL is interrupted. Also, at the fifth time point T5, the second transistor FS2 turns on. When the second transistor FS2 is turned on, the floating diffusion node FD and the ferroelectric capacitor FC are electrically connected. At this point, referring to Figure 8, the ferroelectric capacitor FC has a second capacitance (Capacitance 1) value due to the positive voltage applied to the plate line on the hysteresis curve.

[0050] At point 6, T6, the reset transistor RG turns off. At time point T6, the transfer transistor TG turns on. In other words, when the transfer transistor TG is turned on, the charge generated in response to the light received by the photoelectric conversion unit is supplied to the floating diffusion node FD. On the other hand, the voltage due to the charge supplied to the floating diffusion node FD has a low conversion gain due to the ferroelectric capacitor FC having a second capacitance (Capacitance2). At time point T7, the transfer transistor TG turns off. In other words, the voltage level of the floating diffusion node FD decreases due to the charge supplied from the photoelectric conversion unit. At this time, the conversion gain of the floating diffusion node FD has a low conversion gain, as described above, and provides a corresponding voltage level to the source follower transistor SF.

[0051] Figure 12 is an exemplary timing diagram illustrating the operation of an image sensor according to an embodiment of the present invention. Specifically, Figure 12 is a timing diagram illustrating the operation of the third conversion gain method corresponding to the high conversion gain of the image sensor.

[0052] Referring to Figure 12, at the first time point T1, the reset transistor RG turns on. The reset transistor RG turns on and resets the floating diffusion node FD to the reset voltage Vo. In other words, the reset voltage Vo refers to the drive voltage VDD shown in Figure 9. In response, the voltage level of the floating diffusion node (FD) increases. At the second time point T2, the transfer transistor TG turns on. The transfer transistor TG turns on and releases the residual charge in the photoelectric conversion section. On the other hand, unlike the first and second conversion gain methods, in the third conversion gain method, the first transistor FS1 and the second transistor FS2 remain in the turned-off state. In other words, the floating diffusion node FD remains electrically disconnected from the ferroelectric capacitor FC.

[0053] At the third time point T3, the transfer transistor TG turns off. At the fourth time point T4, the reset transistor RG turns off. Also, at the fourth time point T4, the transfer transistor TG turns on. In other words, when the transfer transistor TG is turned on, the charge generated in response to the light received by the photoelectric conversion unit is supplied to the floating diffusion node FD. On the other hand, the voltage generated by the charge supplied to the floating diffusion node (FD) has a high conversion gain. Specifically, since the floating diffusion node FD is not electrically connected to the ferroelectric capacitor FC, it has a high conversion gain due to the parasitic capacitor present inside. At time point T5, the transfer transistor TG turns off. In other words, the voltage level of the floating diffusion node FD decreases due to the charge supplied from the photoelectric conversion unit. At this time, the conversion gain of the floating diffusion node FD has a high conversion gain as described above, and provides a corresponding voltage level to the source follower transistor SF.

[0054] As described above, the image sensor according to the embodiment of the present invention has different capacitance values ​​for the floating diffusion node FD depending on the conversion gain method, using a ferroelectric capacitor contained inside. Specifically, in the case of a high-conversion system where only internal parasitic capacitance exists, it has the largest conversion gain; in the case of a middle-conversion system with a first capacitance (Capacitance1) value, it has an intermediate conversion gain; in the case of a low-conversion system with a second capacitance (Capacitance2) value greater than the first capacitance (Capacitance1) value, it has the smallest conversion gain. However, the embodiments are not limited to the three methods described above, and the number of conversion gain methods can be changed arbitrarily depending on the embodiment.

[0055] Figure 13 is an illustrative circuit diagram of a unit pixel included in an image sensor according to another embodiment of the present invention. Content that overlaps with Figures 2 to 6 will be omitted, and the explanation will focus on the differences.

[0056] Referring to Figure 13, the image sensor further includes a first transistor FS1, a second transistor FS2, a ferroelectric capacitor FC, and a plate line PL. One end of the first transistor FS1 is connected to one end of the ferroelectric capacitor FC. The other end of the first transistor FS1 is connected to the plate line. One end of the second transistor FS2 is connected to the other end of the ferroelectric capacitor FC. The other end of the second transistor FS2 is connected to the floating diffusion node FD. One end of the ferroelectric capacitor FC is connected to one end of the first transistor FS1. The other end of the ferroelectric capacitor FC is connected to one end of the second transistor FS2. In other words, the ferroelectric capacitor FC and the first transistor FS1 and the second transistor FS2 are connected in series with each other. The plate line PL is configured to apply bias voltages that determine the operation of the first transistor FS1, the ferroelectric capacitor FC, and the second transistor FS2, but the embodiment is not limited thereto. On the other hand, Figure 13 shows the case where the first transistor FS1 and the second transistor FS2 are NMOS, but as explained in Figure 9, the embodiment is not limited to this.

[0057] Figure 14 is an exemplary timing diagram illustrating the operation of an image sensor according to another embodiment of the present invention. Specifically, Figure 14 is a timing diagram illustrating the operation of the first conversion method corresponding to the middle conversion gain of the image sensor.

[0058] Referring to Figure 14, at the first time point T1, the transfer transistor TG turns on. The transfer transistor TG turns on and releases the residual charge in the photoelectric conversion section. At the second time point T2, the transfer transistor TG turns off. At the second time point T2, the reset transistor RG turns on. The reset transistor RG turns on and resets the floating diffusion node FD to the reset voltage Vo. In other words, the reset voltage Vo refers to the drive voltage VDD shown in Figure 9. In response, the voltage level of the floating diffusion node (FD) increases.

[0059] At the third time point T3, the first transistor FS1 and the second transistor FS2 are turned on. When the first transistor FS1 is turned on, the voltage applied to the plate line PL is transmitted to the ferroelectric capacitor FC. Furthermore, when the second transistor FS2 is turned on, the voltage of the floating diffusion node FD is transmitted to the ferroelectric capacitor FC. The ferroelectric capacitor FC operates based on the difference between the ferroelectric capacitor reset voltage of the plate line PL provided by the first transistor FS1 and the voltage of the floating diffusion node FD provided by the second transistor FS2.

[0060] Meanwhile, at the third time point T3, a ferroelectric capacitor reset voltage is applied to the plate line PL. The magnitude of the ferroelectric capacitor reset voltage is the negative value of the sum of the saturation voltage of the ferroelectric capacitor shown in Figure 8 and the reset voltage Vo, which is the reset voltage of the floating diffusion node FD; however, the embodiments are not limited thereto. At this time, the ferroelectric capacitor FC operates on a hysteresis curve due to the difference between the plate line PL voltage supplied by the first transistor FS1 and the reset voltage Vo of the floating diffusion node FD supplied by the second transistor FS2. Specifically, the ferroelectric capacitor FC has a first capacitance (Capacitance 1) value depending on the voltage difference shown in Figure 8.

[0061] At time point T4, the first transistor FS1 turns off, and the voltage applied to the plate line PL is interrupted. At the fourth time point T4, the reset transistor RG turns off. At point T5 (the fifth time point), the reset transistor RG turns on again. Specifically, the reset transistor RG turns on again to minimize the voltage amplitude swing of the floating diffusion node FD caused by the turn-on and turn-off operations of the first transistor FS1 and the second transistor FS2. At point 6, T6, the reset transistor RG turns off. Also, at the sixth time point T6, the transfer transistor TG turns on.

[0062] In other words, when the transfer transistor TG is turned on, the charge generated in response to the light received by the photoelectric conversion unit is supplied to the floating diffusion node FD. In other words, the voltage level of the floating diffusion node FD decreases due to the charge supplied from the photoelectric conversion unit. On the other hand, the voltage due to the charge supplied to the floating diffusion node FD has a middle conversion gain due to the ferroelectric capacitor FC having a first capacitance (Capacitance1). At time point T7, the transfer transistor TG turns off. At this time, the conversion gain of the floating diffusion node FD has a middle conversion gain as described above, and provides a corresponding voltage level to the source follower transistor SF. At point 8 (T8), the second transistor FS2 turns off.

[0063] Figure 15 is an illustrative timing diagram illustrating the operation of an image sensor according to another embodiment of the present invention. Specifically, Figure 15 is a timing diagram illustrating the operation of the second conversion method corresponding to the low conversion gain of the image sensor.

[0064] Referring to Figure 15, at the first time point T1, the transfer transistor TG turns on. The transfer transistor TG turns on and releases the residual charge in the photoelectric conversion section. At the second time point T2, the transfer transistor TG turns off. At the second time point T2, the reset transistor RG turns on. The reset transistor RG turns on, resetting the floating diffusion node FD to the reset voltage Vo. In other words, the reset voltage Vo refers to the drive voltage VDD shown in Figure 9. In response, the voltage level of the floating diffusion node (FD) increases. At the third time point T3, the reset transistor RG turns off.

[0065] At the fourth time point T4, the reset transistor RG turns on again. Furthermore, at the fourth time point T4, the first transistor FS1 and the second transistor FS2 are turned on. When the first transistor FS1 is turned on, it transmits the voltage applied to the plate line PL to the ferroelectric capacitor FC. Furthermore, when the second transistor FS2 is turned on, the voltage of the floating diffusion node FD is transmitted to the ferroelectric capacitor FC. The ferroelectric capacitor FC operates based on the difference between the ferroelectric capacitor reset voltage of the plate line PL provided by the first transistor FS1 and the voltage of the floating diffusion node FD provided by the second transistor FS2.

[0066] Meanwhile, at the fourth time point T4, a ferroelectric capacitor reset voltage (for example, the first ferroelectric capacitor reset voltage) is applied to the plate line PL. The magnitude of the ferroelectric capacitor reset voltage is the negative value of the sum of the saturation voltage of the ferroelectric capacitor shown in Figure 8 and the reset voltage Vo, which is the reset voltage of the floating diffusion node FD, but the embodiments are not limited thereto. At time point T5, the voltage applied to the plate line PL has a positive saturation voltage capacitor reset voltage (e.g., second ferroelectric capacitor reset voltage). At this time, the ferroelectric capacitor FC operates on a hysteresis curve due to the difference between the plate line PL voltage supplied by the first transistor FS1 and the reset voltage Vo of the floating diffusion node FD supplied by the second transistor FS2. Specifically, the ferroelectric capacitor FC has a second capacitance (Capacitance 2) value depending on the voltage difference shown in Figure 8.

[0067] At time point T6, the first transistor FS1 turns off, and the voltage applied to the plate line PL is interrupted. At point 7, T7, the reset transistor RG turns off. At time point T7, the transfer transistor TG turns on. In other words, when the transfer transistor TG is turned on, the light generated in the photoelectric conversion section is converted into charge, which is then supplied to the floating diffusion node FD. In other words, the voltage level of the floating diffusion node FD decreases due to the charge supplied from the photoelectric conversion unit. On the other hand, the voltage due to the charge supplied to the floating diffusion node FD has a low conversion gain due to the ferroelectric capacitor FC having a second capacitance (Capacitance2). At point 8 T8, the transfer transistor TG turns off. At this time, the conversion gain of the floating diffusion node FD has a low conversion gain, as described above, and provides a corresponding voltage level to the source follower transistor SF. At time point T9, the second transistor FS2 turns off.

[0068] Figure 16 is an exemplary timing diagram illustrating the operation of an image sensor according to another embodiment of the present invention. Specifically, Figure 16 is a timing diagram illustrating the operation of the third conversion method corresponding to the high conversion gain of the image sensor.

[0069] Referring to Figure 16, at the first time point T1, the reset transistor RG turns on. The reset transistor RG turns on, resetting the floating diffusion node FD to the reset voltage Vo. In other words, the reset voltage Vo refers to the drive voltage VDD shown in Figure 9. In response, the voltage level of the floating diffusion node (FD) increases. At the second time point T2, the transfer transistor TG turns on. The transfer transistor TG turns on and releases the residual charge in the photoelectric conversion section. On the other hand, unlike the first and second conversion methods, in the third conversion method, the first transistor FS1 and the second transistor FS2 remain in the turned-off state. In other words, the floating diffusion node FD remains electrically disconnected from the ferroelectric capacitor FC.

[0070] At the third time point T3, the transfer transistor TG turns off. At the fourth time point T4, the reset transistor RG turns off. Also, at the fourth time point T4, the transfer transistor TG turns on. In other words, when the transfer transistor TG is turned on, the charge generated in response to the light received by the photoelectric conversion unit is supplied to the floating diffusion node FD. On the other hand, the voltage generated by the charge supplied to the floating diffusion node (FD) has a high conversion gain. Specifically, since the floating diffusion node FD is not electrically connected to the ferroelectric capacitor FC, it has a high conversion gain due to the parasitic capacitor present inside.

[0071] At time point T5, the transfer transistor TG turns off. In other words, the voltage level of the floating diffusion node FD decreases due to the charge supplied from the photoelectric conversion unit. At this time, the conversion gain of the floating diffusion node FD has a high conversion gain as described above, and provides a corresponding voltage level to the source follower transistor SF.

[0072] Figure 17 is a block diagram showing a schematic configuration of an electronic device including a multi-camera module according to an embodiment of the present invention, and Figure 18 is a block diagram showing a detailed configuration of one of the camera modules in Figure 17. Hereinafter, an electronic device 1000 according to another embodiment of the present invention will be described with reference to Figures 17 and 18. For the sake of clarity, any parts that overlap with the explanations using Figures 1 to 16 will be explained briefly or omitted.

[0073] Referring to Figure 17, the electronic device 1000 includes a camera module group 1100, an application processor 1200, a PMIC 1300, and an external memory 1400. The camera module group 1100 includes multiple camera modules (1100a, 1100b, 1100c). For example, the figure shows an embodiment in which three camera modules (1100a, 1100b, and 1100c) are arranged, but the embodiment is not limited to this. In one embodiment, the camera module group 1100 can be modified to include only two camera modules. Furthermore, in one embodiment, the camera module group 1100 can be modified to include n camera modules (where n is a natural number greater than or equal to 4). Here, one or more of the three camera modules (1100a, 1100b, 1100c) include an image sensor 100, as described using Figures 1 to 16.

[0074] The detailed configuration of camera module 1100b will be described in more detail below with reference to Figure 18, but the following description can also be applied to other camera modules (1100a, 1100c) depending on the embodiment. Referring to Figure 18, the camera module 1100b includes a prism 1105, an optical path folding element (OPFE) 1110, an actuator 1130, an image sensing device 1140, and a storage unit 1150. The prism 1105 includes a reflective surface 1107 made of light-reflecting material and alters the path of light L incident from the outside.

[0075] In one embodiment, the prism 1105 changes the path of light L incident in a first direction X to a second direction Y perpendicular to the first direction X. Furthermore, the prism 1105 can rotate the reflective surface 1107 of the light-reflecting material in direction A around the central axis 1106, or rotate the central axis 1106 in direction B, thereby changing the path of light L incident in the first direction X to a second direction Y which is perpendicular. At this time, OPFE1110 can also move in a third direction Z, which is perpendicular to the first direction X and the second direction Y. In one embodiment, as shown in the figure, the maximum rotation angle of the prism 1105 in the A direction is 15 degrees or less in the positive (+) A direction and greater than 15 degrees in the negative (-) A direction, but the embodiment is not limited thereto. In one embodiment, the prism 1105 can move within 20 degrees in the positive (+) or negative (-)B direction, or between 10 and 20 degrees, or between 15 and 20 degrees, where the angle of movement can be the same angle in the positive (+) or negative (-)B direction, or within approximately 1 degree range to approximately the same angle.

[0076] In one embodiment, the prism 1105 can move the reflective surface 1106 of the light-reflecting material in a third direction (for example, the Z direction) parallel to the extension direction of the central axis 1106. OPFE1110 may include, for example, an optical lens consisting of m (where m is a natural number) groups. The m lenses can be moved in the second direction Y to change the optical zoom ratio of the camera module 1100b. For example, if the basic optical zoom magnification of camera module 1100b is "Z", then by moving the m optical lenses included in OPFE1110, the optical zoom magnification of camera module 1100b can be changed to "3Z", "5Z", or an optical zoom magnification of "5Z" or higher.

[0077] The actuator 1130 moves the OPFE 1110 or optical lens (hereinafter referred to as the optical lens) to a specific position. For example, the actuator 1130 adjusts the position of the optical lens so that the image sensor 1142 is positioned at the focal length of the optical lens for accurate sensing. The image sensing device 1140 includes an image sensor 1142, control logic 1144, and memory 1146. The image sensor 1142 senses an image of the object to be sensed using light L provided through an optical lens. The control logic 1144 controls the overall operation of the camera module 1100b. For example, the control logic 1144 controls the operation of the camera module 1100b in accordance with the control signals provided via the control signal line CSLb.

[0078] Memory 1146 stores information necessary for the operation of the camera module 1100b, such as calibration data 1147. Calibration data 1147 contains information necessary for the camera module 1100b to generate image data using light L supplied from an external source. The calibration data 1147 may include, for example, information regarding the degree of rotation, focal length, and optical axis, as described earlier. If the camera module 1100b is implemented as a multi-state camera where the focal length changes depending on the position of the optical lens, the calibration data 1147 may include the focal length values ​​for each position (or state) of the optical lens and information related to autofocusing.

[0079] The storage unit 1150 stores the image data sensed via the image sensor 1142. The storage unit 1150 is located outside the image sensing device 1140 and can be implemented in a stacked configuration with the sensor chips that make up the image sensing device 1140. In one embodiment, the storage unit 1150 is implemented as an EEPROM (Electrically Erasable Programmable Read-Only Memory), but the embodiment is not limited to this.

[0080] Referring to both Figures 17 and 18, in one embodiment, each of the multiple camera modules (1100a, 1100b, 1100c) includes an actuator 1130. Therefore, each of the multiple camera modules (1100a, 1100b, 1100c) may contain identical or different calibration data 1147 resulting from the operation of the actuator 1130 contained within it. In one embodiment, one of the multiple camera modules (1100a, 1100b, 1100c) (e.g., 1100b) may be a folded lens camera module including the prism 1105 and OPFE 1110 described above, while the remaining camera modules (e.g., 1100a, 1100c) may be vertical camera modules that do not include the prism 1105 and OPFE 1110; however, the embodiment is not limited thereto.

[0081] In one embodiment, one of the multiple camera modules (1100a, 1100b, 1100c) (for example, 1100c) may be a vertical depth camera that extracts depth information using, for example, IR (Infrared Ray). In this case, the application processor 1200 can merge the image data provided by such a depth camera with the image data provided by a different camera module (e.g., 1100a or 1100b) to generate a 3D depth image.

[0082] In one embodiment, at least two camera modules (e.g., 1100a and 1100b) of a plurality of camera modules (1100a, 1100b, 1100c) may have different fields of view (angles of view). In this case, for example, the optical lenses of at least two camera modules (e.g., 1100a and 1100b) of the multiple camera modules (1100a, 1100b, and 1100c) may be different from each other, but are not limited to this. In one embodiment, the field of view of each of the multiple camera modules (1100a, 1100b, 1100c) may be different from one another. In this case, the optical lenses included in each of the multiple camera modules (1100a, 1100b, 1100c) may be different from each other, but are not limited to this. In one embodiment, each of the multiple camera modules (1100a, 1100b, 1100c) can be arranged physically separated from one another. In other words, instead of multiple camera modules (1100a, 1100b, 1100c) dividing and using the sensing area of ​​a single image sensor 1142, an independent image sensor 1142 can be placed inside each of the multiple camera modules (1100a, 1100b, 1100c).

[0083] Referring again to Figure 17, the application processor 1200 includes an image processing unit 1210, a memory controller 1220, and internal memory 1230. The application processor 1200 can be implemented separately from the multiple camera modules (1100a, 1100b, 1100c). For example, the application processor 1200 and multiple camera modules (1100a, 1100b, 1100c) can be implemented separately on individual semiconductor chips. The image processing unit 1210 includes a plurality of sub-image processors (1212a, 1212b, 1212c), an image generator 1214, and a camera module controller 1216. The image processing device 1210 includes multiple sub-image processors (1212a, 1212b, 1212c) in a number corresponding to the number of camera modules (1100a, 1100b, 1100c).

[0084] Image data generated from each camera module (1100a, 1100b, 1100c) is provided to the corresponding sub-image processors (1212a, 1212b, 1212c) via separate image signal lines (ISLa, ISLb, ISLc). For example, image data generated from camera module 1100a is provided to sub-image processor 1212a via image signal line ISLa, image data generated from camera module 1100b is provided to sub-image processor 1212b via image signal line ISLb, and image data generated from camera module 1100c is provided to sub-image processor 1212c via image signal line ISLc. Such image data transfer is performed, for example, using a Camera Serial Interface (CSI) based on MIPI (Mobile Industry Processor Interface), but the embodiments are not limited thereto.

[0085] On the other hand, in one embodiment, a single sub-image processor can be arranged to support multiple camera modules. For example, instead of being implemented separately from each other, as shown by sub-image processors 1212a and 1212c, they can be integrated into a single sub-image processor, and the image data provided by camera modules 1100a and 1100c can be selected by a selection element (e.g., a multiplexer) and then provided to the integrated sub-image processor. The image data provided to each sub-image processor (1212a, 1212b, 1212c) is then provided to the image generator 1214. The image generator 1214 generates an output image using image data provided by each sub-image processor (1212a, 1212b, 1212c) according to the generating information or mode signal.

[0086] Specifically, the image generator 1214 merges at least a portion of the image data generated from camera modules (1100a, 1100b, 1100c) having different field-of-view angles, according to the image generation information or mode signal, to generate an output image. Furthermore, the image generator 1214 selects one of the image data generated from camera modules (1100a, 1100b, 1100c) having different field-of-view angles, according to the image generation information or mode signal, and generates an output image. In one embodiment, the image generation information may include a zoom signal (or zoom factor). In one embodiment, the mode signal may be, for example, a signal based on a mode selected by the user.

[0087] If the image generation information is a zoom signal (zoom factor), and each camera module (1100a, 1100b, 1100c) has a different field of view (field of view angle), the image generator 1214 will perform different operations depending on the type of zoom signal. For example, if the zoom signal is the first signal, the image data output from camera module 1100a and the image data output from camera module 1100c are merged, and then the merged image signal and the image data output from camera module 1100b that was not used in the merging are used to generate the output image. If the zoom signal is a second signal different from the first signal, the image generator 1214 does not perform such image data merging, but instead selects one of the image data output from each camera module (1100a, 1100b, 1100c) to generate the output image. However, the embodiments are not limited thereto, and the method for processing image data can be modified and implemented in any way as needed.

[0088] In one embodiment, the image generator 1214 receives multiple image data with different exposure times from at least one of the multiple sub-image processors (1212a, 1212b, 1212c), and performs HDR (high dynamic range) processing on the multiple image data to generate merged image data with an increased dynamic range. The camera module controller 1216 provides control signals to each camera module (1100a, 1100b, 1100c). Control signals generated by the camera module controller 1216 are provided to the corresponding camera modules (1100a, 1100b, 1100c) via separate control signal lines (CSLa, CSLb, CSLc). For example, the control signal may include information related to the conversion gain mode of the ferroelectric capacitor contained in each camera module (1100a, 1100b, 1100c).

[0089] One of the multiple camera modules (1100a, 1100b, 1100c) is designated as the master camera (e.g., 1100b) depending on the image generation information or mode signal, including the zoom signal, while the remaining camera modules (e.g., 1100a, 1100c) are designated as slave cameras. This information is included in the control signals and provided to the corresponding camera modules (1100a, 1100b, 1100c) via separate control signal lines (CSLa, CSLb, CSLc).

[0090] The camera modules operating as master and slave are changed depending on the zoom factor or operating mode signal. For example, if the field of view of camera module 1100a is wider than that of camera module 1100b, and the zoom factor indicates a lower zoom magnification, then camera module 1100b will operate as the master and camera module 1100a will operate as the slave. Conversely, when the zoom factor indicates a high zoom magnification, camera module 1100a operates as the master and camera module 1100b operates as the slave.

[0091] In one embodiment, the control signals provided from the camera module controller 1216 to each camera module (1100a, 1100b, 1100c) include a sync enable signal. For example, if camera module 1100b is the master camera and camera modules (1100a, 1100b, 1100c) are slave cameras, the camera module controller 1216 transmits a sink enable signal to camera module 1100b. Upon receiving such a sync enable signal, camera module 1100b generates a sync signal based on the provided sync enable signal and provides the generated sync signal to camera modules (1100a, 1100c) via the sync signal line SSL. Camera module 1100b and camera modules (1100a, 1100c) transmit image data to the application processor 1200 in synchronization with such a sink signal.

[0092] In one embodiment, the control signals provided from the camera module controller 1216 to a plurality of camera modules (1100a, 1100b, 1100c) include mode information corresponding to the mode signal. Based on this mode information, the multiple camera modules (1100a, 1100b, 1100c) operate in a first operating mode and a second operating mode in relation to the sensing speed. Multiple camera modules (1100a, 1100b, 1100c) generate an image signal at a first speed in a first operating mode (for example, an image signal at a first frame rate), encode it at a second speed higher than the first speed (for example, an image signal at a second frame rate higher than the first frame rate), and transmit the encoded image signal to the application processor 1200. At this time, the second velocity may be 30 times or less the first velocity.

[0093] The application processor 1200 stores the received image signal, i.e., the encoded image signal, in an internal memory 1230 or application processor 1200 or an external storage 1400. Subsequently, it reads the encoded image signal from the memory 1230 or storage 1400, decodes it, and displays the image data generated based on the decoded image signal. For example, one of the multiple subprocessors (1212a, 1212b, 1212c) of the image processing device 1210 performs decoding, and also performs image processing on the decoded image signal.

[0094] Multiple camera modules (1100a, 1100b, 1100c) generate image signals in a second operating mode at a third speed lower than the first speed (for example, generating image signals at a third frame rate lower than the first frame rate) and transmit the image signals to the application processor 1200. The image signal provided to the application processor 1200 may be an unencoded signal. The application processor 1200 either performs image processing on the received image signal or stores the image signal in the memory 1230 or storage 1400.

[0095] The PMIC1300 supplies power, such as power supply voltage, to each of the multiple camera modules (1100a, 1100b, 1100c). For example, under the control of the application processor 1200, the PMIC 1300 supplies first power to camera module 1100a via power signal line PSLa, second power to camera module 1100b via power signal line PSLb, and third power to camera module 1100c via power signal line PSLc. The PMIC1300 responds to the power control signal PCON from the application processor 1200 to generate power corresponding to each of the multiple camera modules (1100a, 1100b, 1100c) and adjusts the power levels.

[0096] The power control signal PCON may include power adjustment signals for each operating mode of multiple camera modules (1100a, 1100b, 1100c). For example, the operating mode may include a low power mode, in which case the power control signal PCON may include information about the camera module operating in low power mode and the power level to be set. The power levels supplied to each of the multiple camera modules (1100a, 1100b, 1100c) may be the same or different from each other. Furthermore, the power level can be changed dynamically.

[0097] Furthermore, the present invention is not limited to the embodiments described above. It can be modified and implemented in various ways without departing from the technical scope of the present invention. [Explanation of Symbols]

[0098] 100 Image Sensors 110 pixel array 112 unit pixels 120 CDS 130 Column Scan Circuit 140 Low-scan circuit 150 Timing control circuit

Claims

1. A photoelectric conversion unit that reacts to received light, converts the received light into an electric charge, and provides it to the first node, A transfer transistor provides the voltage of the first node to a floating diffusion node (FD node), A reset transistor that resets the voltage of the floating diffusion node to the drive voltage based on a reset signal, A source follower transistor that provides a unit pixel output based on the voltage of the floating diffusion node, A selection transistor connected to the source follower transistor, which is gated according to the selection signal and outputs the unit pixel output to the outside, A ferroelectric capacitor connected to the floating diffusion node, A first transistor, one end of which is connected to one end of the ferroelectric capacitor and the other end of which is connected to a plate line (PL), It has a second transistor, one end of which is connected to the one end of the ferroelectric capacitor and the other end of which is connected to the floating diffusion node, The other end of the ferroelectric capacitor is connected to ground. The ferroelectric capacitor adjusts the conversion gain of the floating diffusion node based on the conversion gain (CG) scheme of the ferroelectric capacitor. The image sensor is characterized in that the conversion gain method is a first conversion gain method, a second conversion gain method, or a third conversion gain method.

2. The first transistor has one end connected to one end of the ferroelectric capacitor and the other end connected to the plate line, The second transistor has one end connected to one end of the ferroelectric capacitor and the other end connected to the floating diffusion node. The image sensor according to claim 1, characterized in that the other end of the ferroelectric capacitor is connected to ground.

3. In the first conversion gain scheme, at a first time point before the voltage of the first node is supplied to the floating diffusion node, the first transistor is turned on. At a second time point following the first time point, the second transistor is turned on. The image sensor according to claim 2, characterized in that a ferroelectric capacitor reset voltage is applied to the plate line at the first time point.

4. The image sensor according to claim 3, characterized in that the magnitude of the ferroelectric capacitor reset voltage is the same as the negative saturation voltage value of the ferroelectric capacitor.

5. In the second conversion gain scheme, the first transistor is turned on at a first time point before the voltage of the first node is supplied to the floating diffusion node, and is turned off at a second time point after the first time point. At the second point in time, the second transistor is turned on. At the first time point, the first ferroelectric capacitor reset voltage is applied to the plate line. The image sensor according to claim 2, characterized in that a second ferroelectric capacitor reset voltage, different from the first ferroelectric capacitor reset voltage, is applied to the plate line at a third time between the first and second time points.

6. The magnitude of the reset voltage of the first ferroelectric capacitor at the first time point is the same as the negative saturation voltage value of the ferroelectric capacitor. The image sensor according to claim 5, characterized in that the magnitude of the reset voltage of the second ferroelectric capacitor at the third time point is the same as the positive saturation voltage value of the ferroelectric capacitor.

7. The first transistor has one end connected to one end of the ferroelectric capacitor and the other end connected to the plate line, The image sensor according to claim 1, characterized in that the second transistor has one end connected to the other end of the ferroelectric capacitor and the other end connected to the floating diffusion node.

8. An image sensor that outputs an image signal, It includes an Image Signal Processor (ISP) that is electrically connected to the image sensor and receives and processes the image signal provided by the image sensor, The image sensor includes a photoelectric conversion unit that reacts to the received light, converts the received light into an electric charge, and provides it to the first node, A transfer transistor provides the voltage of the first node to a floating diffusion node (FD node), A reset transistor that resets the voltage of the floating diffusion node to the drive voltage based on a reset signal, A ferroelectric capacitor connected to the floating diffusion node, A first transistor connected between the ferroelectric capacitor and the plate line (PL), The system includes a second transistor connected between the ferroelectric capacitor and the floating diffusion node, The ferroelectric capacitor adjusts the conversion gain of the floating diffusion node based on the conversion gain scheme of the ferroelectric capacitor. The image sensing system is characterized in that the conversion gain method is a first conversion gain method, a second conversion gain method, or a third conversion gain method.

9. A ferroelectric capacitor is provided, with one end connected to a floating diffusion node and the other end connected to ground; a first transistor is provided, with one end connected to one end of the ferroelectric capacitor and the other end connected to a plate line (PL); and a second transistor is provided, with one end connected to the one end of the ferroelectric capacitor and the other end connected to the floating diffusion node. A method for adjusting the conversion gain of the floating diffusion node based on a conversion gain scheme for the ferroelectric capacitor, which is a first conversion gain scheme, a second conversion gain scheme, or a third conversion gain scheme, by the operation of the ferroelectric capacitor, the first transistor, and the second transistor, In the first conversion gain method, At a first time point, before the light received by the floating diffusion node is provided with a converted charge, the first transistor is turned on. At a second time point following the first time point, the second transistor is turned on. At the first time point, a ferroelectric capacitor reset voltage is applied to the plate line. In the second conversion gain method described above, At a third time point, before the light received by the floating diffusion node is provided with converted charge, the first transistor is turned on, and at a fourth time point, after the third time point, it is turned off. At the fourth point in time, the second transistor is turned on. At the third time point, the first ferroelectric capacitor reset voltage is applied to the plate line. At a fifth time point between the third and fourth time points, a second ferroelectric capacitor reset voltage, different from the first ferroelectric capacitor reset voltage, is applied to the plate line. In the third conversion gain method, An image sensing method characterized in that the first transistor and the second transistor are turned off.

10. The ferroelectric capacitor is HFOx, HfO ２ / ZrO ２ , PbTiO ３ The image sensing method according to claim 9, characterized by including at least one of the following.

Images