Semiconductor devices and manufacturing methods

Abstract

In one embodiment, the semiconductor device (1) comprises a semiconductor body (2), a gate electrode (33), and a first electrode (31), the semiconductor body (2) comprising a first region (21) that is a source or emitter region, and a well region (22), the first region (21) being of a first conductivity type and the well region (22) being of a different second conductivity type, the well region (22) being separated from the gate electrode (33) by a gate insulating layer (4), the first region (21) being electrically contacted by the first electrode (31) that is a source or emitter electrode, and the first region (21) comprising at least one current limiting region (5), the at least one current limiting region (5) being made of at least one electrically insulating material.

Description

Technical Field

[0001] A semiconductor device is provided. A method of manufacturing such a semiconductor device is also provided.

Background Art

[0002] U.S. Patent Application Publication No. 2017 / 0243,970, U.S. Patent Application Publication No. 2017 / 0229,535, and U.S. Patent Application Publication No. 2015 / 0108,564 relate to semiconductor devices. Patent document JP2019046996A provides a semiconductor device, a power converter, and a method for manufacturing a semiconductor device that suppress variations in short-circuit capacitance. The semiconductor device comprises a substrate, a drift layer of a first conductivity type provided on the upper surface of the substrate, a well region of a second conductivity type provided on the upper surface of the drift layer, a source region of a first conductivity type provided on the upper surface of the well region, a channel region which is part of the well region and sandwiched between the drift layer and the source region, a gate oxide film provided on the upper surface of the drift layer, a gate electrode provided on the gate oxide film, a source electrode connected to the source region, and a drain electrode provided on the back surface of the substrate. In the source region, a thin wall portion thinner than the surrounding area is provided between the portion adjacent to the channel region and the portion to which the source electrode is connected. Patent document JP6282088B2 provides a semiconductor device that can improve short-circuit withstand capability by increasing the voltage drop from the channel region to the source electrode and maintain low contact resistance between the source electrode and the source region. The corresponding MOSFET comprises a source region including a source contact region connected to a source pad, a source extension region adjacent to the channel region, and a source resistance control region formed between the source contact region and the source extension region. The source resistance control region includes a recess formed between the source extension region and the source contact region, and a semiconductor resistance region of a first conductivity type formed on the inner wall of the recess and connected to the source contact region and the source extension region.

Summary of the Invention

Problems to be Solved by the Invention

[0003] The problem to be solved is to provide a semiconductor device in which the trade-off between conduction loss and short-circuit withstand time (SCWT) is improved.

Means for Solving the Problems

[0004] This object is , Germany achieved by the semiconductor device and method defined in the independent claims. Exemplary further developments form the subject matter of the dependent claims.

[0005] Book The semiconductor device described in the specification is made of an electrically insulating material and is located in a source region or an emitter region , multiple and includes a number of current-limiting regions. By at least one current-limiting region, the source resistance value R S increases. This increase in R S must not significantly interfere with the device performance in normal operation and must be such as to improve the short-circuit behavior.

[0006] halfThe conductor device includes a semiconductor body, a gate electrode, and a first electrode. For example, the semiconductor body is a wide-bandgap semiconductor material such as SiC, Ga2O3, or GaN. However, the semiconductor body may alternatively be silicon, abbreviated as Si. The electrodes can be made from at least one metal or from a highly doped and / or ohmic conductive semiconductor material such as poly-Si.

[0007] half The conductor body includes a first region. For example, the first region is a source region or an emitter region.

[0008] half The conductor body includes a well region. The well region is located adjacent to the first region. That is, the first region can contact the well region and thus can be in direct physical contact with the well region. The channel region is part of the well region and can have the same doping concentration. During operation, electrons flow from the source region along the gate insulating layer through the channel region in the drift region. In the operation of the semiconductor device, the channel region may be the part of the well region adjacent to the gate insulating layer.

[0009] The One region is of the first conductivity type and the well region is of a different second conductivity type. For example, the first conductivity type is the n-conductivity type and the second conductivity type is the p-conductivity type, or vice versa. Hereinafter, the first conductivity type is referred to as the n-conductivity type. Therefore, if the first conductivity type is instead the p-conductivity type, the doping relationships described below must be reversed.

[0010] cormorant The well region is adjacent to the gate electrode and is separated from the gate electrode by a gate insulating layer. The gate insulating layer may be directly between the gate electrode and the well region.

[0011] TheOne region is electrically contacted by a first electrode, which is, for example, a source electrode or an emitter electrode. Thus, the first electrode can contact the semiconductor body in at least the first region. For example, a well is electrically contacted by the first electrode or by another electrode in some other way.

[0012] The In area 1 , multiple There are several current limiting regions. . electric The flow-restricting region may correspond to a recess in at least one assigned first region. , electric The flow-restricting region is formed in at least one assigned first region. ta dent It can handle departmental matters.

[0013] therefore , electric The current-limiting region consists of at least one electrical insulating material. For example, the difference in relative conductivity between the material of the first region and at least one electrical insulating material of the current-limiting region is at least 10 such that the current-limiting region does not conduct a significant amount of current compared to the first region. 2 double, or at least 10 3 double, or at least 10 4 It is double. For example, at least one electrical insulating material is a solid material at a temperature of at least 250K to 400K.

[0014] For example, at least one electrical insulating material may be a metal oxide, semiconductor oxide, metal nitride, or semiconductor nitride. For example, at least one current limiting region may include one or more of the following materials: SiO2, Si3N4, Al2O3, Y2O3, ZrO2, HfO2, La2O3, Ta2O5, and TiO2. The same material can also be applied to a gate insulating layer, which may also be called a gate oxide.

[0015] In other words The semiconductor device comprises a semiconductor body, a gate electrode, and a first electrode. The semiconductor body comprises a first region and a well region located adjacent to the first region, wherein the first region is of a first conductivity type, and the well region is of a different second conductivity type. The well region is adjacent to the gate electrode and separated from the gate electrode by the gate insulating layer. The first region is electrically contacted by the first electrode, In the first region multiple There is a current limiting region. 、 electric The flow-limiting region consists of at least one electrical insulating material.

[0016] Accordingly, this application describes, for example, a metal-insulator-semiconductor field-effect transistor (MISFET), or a metal-oxide-semiconductor field-effect transistor (MOSFET) based on, for example, a silicon carbide (SiC) material. To improve the trade-off between conduction loss and short-circuit withstand capability, at least one recess is etched in the source region or emitter region and filled with an electrical insulating material.

[0017] SiC MOSFETs are currently available from several vendors. Offered in either planar or trench cell designs, SiC MOSFETs provide competitive static dissipation, fast dynamic performance, and sufficient reliability. Regarding fault handling capability, SiC MOSFETs still lag behind the typical industry standard of approximately 10 μs shown by their Si counterparts. This is typically related to a strong trade-off between conduction dissipation and short-circuit withstand capability (SCWT). SCWT is the resistance R of the device in the on-state state. DS,on One approach to finding the optimal trade-off between the two is to slightly increase the source resistance R. S The solution is to use it.

[0018] Therefore, in this specification, for example, a SiC MOSFET will be described in which a part of the source region is removed by etching and filled with an electrically insulating material such as SiO2. When a part of the implanted n in the source region + is removed, the total source area decreases, and as a result, the source resistance R S increases.

[0019] Therefore, in the proposed Electricity current limiting region, the total source area decreases and the carrier channel-contact path increases. Both effects increase the value of the source resistance R S . Increasing the value of R S decreases the saturation current I during short circuit (abbreviated as SC: short circuit) occurrence. The depth d and the length L of the etched region can be appropriately designed to achieve the desired effect on the SC current while ignoring the influence on the total resistance between the source and the drain in the on state, also called R SAT . DS,on

[0020] According to at least one embodiment, the semiconductor device is a power device. This means, for example, that the semiconductor device is configured for a maximum current flowing through the well region of at least 10 A or at least 50 A. Optionally, the maximum current is up to 500 A or up to 1.5 kA. Alternatively or additionally, the semiconductor device is configured for a maximum voltage of at least 0.6 kV or at least 1.2 kV between the source and the drain, or between the emitter and the collector. Optionally, the maximum voltage can be up to 6.5 kV.

[0021] According to at least one embodiment, in a top view of the semiconductor body, the gate electrode and the first electrode overlap the first region. Here, and in the following, the "top view" can refer to a field of view perpendicular to the top surface of the semiconductor body to which the first electrode is applied and where the first region is located.

[0022] According to at least one embodiment, at least one current-limiting region is separated from the gate electrode and / or first electrode in a top view of the semiconductor body. For example, at least one current-limiting region is separated from both the gate electrode and the first electrode in a top view.

[0023] According to at least one embodiment, at least one current limiting region is located within an allocated first region, for example, within a manufacturing tolerance, mirror-symmetrically. That is, in a top view of the semiconductor body, the first region, together with the at least one current limiting region, has a mirror-symmetry axis with respect to the shapes of the first region and the at least one current limiting region, for example. The mirror-symmetry axis may extend parallel to the gate electrode and / or the first electrode in a top view, and / or be located between the gate electrode and the first electrode. Otherwise, a non-mirror-symmetric arrangement of at least one current limiting region within an allocated first region is also possible in a top view.

[0024] According to at least one embodiment, in a top view of the semiconductor body, the first region extends entirely between at least one current-limiting region and the first electrode, and between at least one current-limiting region and the gate electrode. In other words, between at least one current-limiting region and each electrode, a portion of the first region lies on the top surface of the semiconductor body in a top view of the semiconductor body, for example.

[0025] Alternatively, at least one current-limiting region may be partially covered by the first electrode and / or gate electrode, or at least one current-limiting region may be in contact with the first electrode and / or gate electrode from the perspective of the semiconductor body.

[0026] According to at least one embodiment, at least one current-limiting region is located between the first electrode and the gate electrode. For example, all of at least one current-limiting region is located between the electrodes.

[0027] According to at least one embodiment, when viewed in cross-section of the semiconductor body, the first region extends around at least one current-limiting region in the direction toward the well region. This can mean that the first region is embedded in the well region, and / or at least one current-limiting region is embedded in the first region. For example, when viewed in cross-section, in this case a portion of the first region is present around at least one current-limiting region, and there is no linear connection path within the semiconductor body from at least one current-limiting region to the well region without crossing the first region.

[0028] The term "cross-section of the semiconductor body" may refer, for example, to a cross-section passing through a first region, a current-limiting region, or at least one of the current-limiting regions, and passing through the gate electrode, in a direction perpendicular to the upper surface of the semiconductor body and / or perpendicular to the main extension direction of the gate electrode.

[0029] According to at least one embodiment, the volume of the at least one current-limiting region is at least 5%, at least 10%, at least 20%, at least 40%, or at least 60% of the total volume of the first region and the at least one current-limiting region combined. Alternatively or additionally, the percentage is up to 95%, up to 85%, or up to 75%. For example, this percentage is between 40% and 85%.

[0030] For example, at least one current-limiting region increases the electrical resistance through the first region between the first electrode and the channel region by at least 1.1 times, at least 1.5 times, at least 2 times, or at least 5 times. Alternatively or additionally, the coefficient is at most 100, at most 25, at most 15, at most 10, or at most 5. For example, this coefficient is between 2 and 10. The electrical resistance through the first region may refer to the normal operating current for which the semiconductor device is designed when it is on. These coefficients refer to a comparison with a device that does not have at least one current-limiting region in the first region but is identical in structure within manufacturing tolerances.

[0031] For example, at least one current-limiting region reduces the cross-sectional area of ​​the current flow within the first region from the first electrode to the well region adjacent to the gate insulating layer, i.e., the channel region, by at least 1.1 times, or at least 1.5 times, or at least 2 times, or at least 5 times. Alternatively or additionally, the coefficient is at most 100, or at most 15, or at most 10, or at most 5, or at most 2. For example, this coefficient is between 2 and 10.

[0032] According to at least one embodiment, at least one current-limiting region is at least one recess within a first region. That is, at least one electrical insulating material is located in at least one recess within the first region. If there are two or more recesses and two or more current-limiting regions, there may be a one-to-one assignment between the recesses and the current-limiting regions and / or at least one electrical insulating material. The at least one electrical insulating material may completely fill the assigned recess. It is possible for two or more electrical insulating materials to be present per recess.

[0033] According to at least one embodiment, at least one electrical insulating material is terminated in alignment with the first region. Thus, the upper surface can be planar across the first region and at least one current-limiting region. In other words, the first region and the electrical insulating material form a planar surface and are terminated in alignment with each other.

[0034] According to at least one embodiment, the semiconductor body further comprises a drift region, which is of a first conductivity type and has a lower maximum doping concentration compared to, for example, the first region and the well region.

[0035] According to at least one embodiment, the semiconductor body further comprises a second region, which is, for example, a drain region or a collector region. In the case of a drain region, the second region is also of the first conductivity type, but, for example, the maximum doping concentration is higher than that of the drift region. In the case of a collector region, the second region is of the second conductivity type.

[0036] According to at least one embodiment, the drift region is located between the well region and the second region. This separates the first region from the second region by the well region.

[0037] According to at least one embodiment, the semiconductor device further comprises a second electrode, which is, for example, a collector electrode or a drain electrode. The second electrode may be located on the side of the second region that is far from the drift region and / or far from the first region.

[0038] According to at least one embodiment, in a top view of the semiconductor body, the gate electrode and the first electrode each extend along a straight line. If there are multiple first electrodes and / or gate electrodes, there may be multiple straight lines along which the first electrodes and / or gate electrodes extend.

[0039] According to at least one embodiment, the first region extends parallel to the gate electrode and / or the first electrode. Thus, the semiconductor device can have a stripe design that includes multiple linear stripes of the gate electrode and / or the first electrode.

[0040] According to at least one embodiment, in a top view of the semiconductor body, the gate electrode and / or first electrode each include a plurality of subsections. For example, the subsections correspond to unit cells. The unit cells can be arranged, for example, in a regular two-dimensional grid. The semiconductor body may extend continuously across all unit cells and comprises a plurality of first regions arranged accordingly. Thus, the semiconductor device can have a cell design comprising a plurality of cells, each having a first electrode, a corresponding gate electrode, and a corresponding first region having at least one current-limiting region.

[0041] According to at least one embodiment, the semiconductor device has a planar design. That is, the gate insulating layer and the gate electrode are applied to the planar portion of the upper surface of the semiconductor body. A first region and at least one current limiting region may be located on the upper surface.

[0042] According to at least one embodiment, the semiconductor device has a trench design. Thus, the gate insulating layer and the gate electrode are partially or entirely located within a trench in the semiconductor body. For example, the depth of the trench begins from the top surface of the semiconductor body and exceeds the depth of the well region. In this case as well, the first region and at least one current-limiting region may be located on the top surface.

[0044] The There are multiple current limiting regions within a single region. The Multiple current-limiting regions can exist within a single region. Each current-limiting region of a first region, or exactly one first region, is separated from each other when viewed from above the semiconductor body.

[0045] In a top view of the semiconductor body, the current limiting region or each current limiting region can be completely surrounded by the first region to which it is assigned.

[0046] According to at least one embodiment, the current limiting region is arranged along one stripe or along multiple stripes. Furthermore, optionally, the current limiting region is arranged along one column or along multiple columns in a top view, and the stripes and columns may be oriented perpendicular to each other. In the case of multiple first regions, this can be applied to each of the first regions, and each of the first regions is assigned to multiple current limiting regions.

[0047] According to at least one embodiment, in a top view of the semiconductor body, the current limiting region is shaped as at least one of a triangle, square, rectangle, hexagon, or circle. In a top view, all current limiting regions may have the same shape and / or area. Otherwise, different shapes and / or sizes of current limiting regions may be combined for each first region.

[0048] In addition, a method for manufacturing a semiconductor device is provided. By this method, a semiconductor device is manufactured as shown in connection with at least one of the embodiments described above. Thus, the characteristics of the semiconductor device are disclosed with respect to the method, and vice versa.

[0049] In at least one embodiment, the manufacturing method is for manufacturing a semiconductor device. This method is, for example, in the order described, To install the semiconductor itself, Forming a first region and a well region in the semiconductor body, To create at least one current limiting region, at least one recess is etched within the first region, and at least one recess is filled with at least one electrical insulating material. Applying a gate insulating layer to the semiconductor body, Applying a gate electrode and a first electrode to a semiconductor and Includes.

[0050] According to at least one embodiment, at least one recess is etched into the semiconductor body, and then at least a portion of the doping for the first region is applied into the semiconductor body through the at least one recess. That is, by forming the at least one recess, at least one deeper region of the semiconductor body is exposed, and then the dopant for the first region is provided to this at least one deeper region. Thus, relatively deep doping can be achieved, for example, with moderate ion energy in ion implantation, or with moderate time and / or temperature in diffusion doping.

[0051] According to at least one embodiment, at least a portion of the doping of the first region is applied between etching at least one recess and applying at least one electrical insulating material to at least one recess. Thus, forming at least one current limiting region can be divided into substeps, which are not necessarily subsequent steps.

[0052] According to at least one embodiment, the method further includes forming at least one plug region within a semiconductor body. The at least one plug region is of a second conductivity type and has a maximum doping concentration higher than the maximum doping concentration of the well region. The at least one plug region is for electrical contact with the well region, for example, by a first electrode.

[0053] According to at least one embodiment, the first region extends deeper into the semiconductor body than at least one plug region.

[0054] According to at least one embodiment, creating the first region involves two different doping steps such that the doping profile of the first region, when viewed in cross-section, is stepped. That is, the first region can extend upwards.

[0055] The semiconductor devices and methods described herein are further described below in detail by exemplary embodiments with reference to the drawings. In the individual figures, the same elements are indicated by the same reference numerals. However, the relationships between elements are not shown to scale, and individual elements may be shown in an exaggerated manner to aid understanding. [Brief explanation of the drawing]

[0056] [Figure 1] This is a schematic cross-sectional perspective view of an exemplary embodiment of a semiconductor device described herein. [Figure 2]This is a schematic cross-sectional view of an exemplary embodiment of a semiconductor device described herein. [Figure 3] This is a schematic cross-sectional view of an exemplary embodiment of a semiconductor device described herein. [Figure 4] This is a schematic cross-sectional view of an exemplary embodiment of a semiconductor device described herein. [Figure 5] This is a schematic cross-sectional perspective view of an exemplary embodiment of a semiconductor device described herein. [Figure 6] This is a schematic cross-sectional perspective view of an exemplary embodiment of a semiconductor device described herein. [Figure 7] This is a schematic cross-sectional view of an exemplary embodiment of a semiconductor device described herein. [Figure 8] This is a schematic diagram of the simulated electrical characteristics of the semiconductor device described herein, compared to a corresponding semiconductor device that does not have at least one current limiting region. [Figure 9] This is a schematic diagram of the simulated electrical characteristics of the semiconductor device described herein, compared to a corresponding semiconductor device that does not have at least one current limiting region. [Figure 10] This is a schematic diagram of the simulated electrical characteristics of the semiconductor device described herein, compared to a corresponding semiconductor device that does not have at least one current limiting region. [Figure 11] This is a schematic diagram of the simulated electrical characteristics of the semiconductor device described herein, compared to a corresponding semiconductor device that does not have at least one current limiting region. [Figure 12] This is a schematic block diagram of an exemplary embodiment of a method for manufacturing a semiconductor device as described herein. [Figure 13] This is a schematic top view of an exemplary embodiment of a semiconductor device described herein. [Figure 14] This is a schematic top view of an exemplary embodiment of a semiconductor device described herein. [Modes for carrying out the invention]

[0057] Figure 1 shows an exemplary embodiment of semiconductor device 1. Semiconductor device 1 comprises a semiconductor body 2, which is, for example, SiC. The semiconductor body 2 has a first region 21, a well region 22, and a drift region 23. There is a plug region 25 for electrical contact with the well region 22.

[0058] Furthermore, the semiconductor device 1 includes a gate electrode 33 separated from the semiconductor body 2 by a gate insulating layer 4. It also has a first electrode 31, which electrically contacts the first region 21 and the plug region 25. The gate insulating layer 4 and the first electrode 31 are located on the upper surface 20 of the semiconductor body 2. The upper surface 20 is planar. The gate electrode 33 and the first electrode 31 may each extend along a straight line perpendicular to the cross-section shown in Figure 1.

[0059] For example, the first region 21 and the drift region 23 are n-doped, and the well region 22 and the plug region 25 are p-doped. If the semiconductor device 1 is an insulated-gate bipolar transistor (IGBT) or a reverse-conducting insulated-gate bipolar transistor (RC-IGBT), the first region 21 is the emitter region and the first electrode 31 is the emitter electrode. If the semiconductor device 1 is a junction-gate field-effect transistor (JFET), a metal-insulator-semiconductor field-effect transistor (MISFET), or a metal-oxide-semiconductor field-effect transistor (MOSFET), the first region 21 is the source region and the first electrode 31 is the source electrode.

[0060] The first region 21 contains a current-limiting region 5. The current-limiting region 5 is made of an electrical insulating material, such as SiO2. The current-limiting region 5 is aligned with a straight line parallel to the gate electrode 33 and the first electrode 31. The current-limiting region 5 is located directly on the upper surface 20, similar to the first region 21.

[0061] The depth of the first region 21 within the semiconductor body 2 starts from the top surface 20 and exceeds the depth of the current limiting region 5 within the semiconductor body 2. In cross-section, the first region 21 extends around the entire perimeter of the current limiting region 5, toward the well region 22 into which the first region 21 is embedded.

[0062] At least one current limiting region 5 is optionally positioned mirror-symmetrically within the first region 21 when viewed from above and in cross-section. For example, in a top view of the top surface 20, the current limiting region 5 is positioned symmetrically within the first region 21 and between electrodes 31 and 33. Thus, a line M exists that is mirror-symmetric with respect to the current limiting region 5 and the first region 21.

[0063] Therefore, Figure 1 shows the basic concept of the proposed semiconductor device 1, in which recesses are etched inside the first region 21. The etched and filled recesses can have different shapes and depths, and can be uniform or non-uniform along the direction perpendicular to the cross-section in Figure 1 (see also Figures 2 to 7 below).

[0064] In at least one current-limiting region 5 of this proposal, the total source area or emitter area is reduced, and the channel-contact path of the carriers is increased. Both effects are due to the source resistance R S Or it results in a corresponding increase in the value of the emitter resistor. S Increasing the value of will increase the saturation current I during the short circuit. SAT The depth d and length L of the current limiting region 5, which is parallel to the top surface 20 and along the cross-section in Figure 1, are determined under nominal conditions, for example, total R DS,on During conduction, the system can be appropriately designed to achieve the desired effect on short-circuit current while maintaining its influence to a negligible level.

[0065] The semiconductor device 1 in Figure 1 is a planar design. In contrast, the semiconductor device 1 in Figure 2 is a trench design. Therefore, the gate electrode 33 and the gate insulating layer 4 are located at least partially within the trench to the semiconductor body 2. Thus, the top surface 20 is not planar, as it is penetrated by the trench, in contrast to the case of Figure 1. The gate electrode 33 starts, for example, from the top surface 20 and extends deeper into the semiconductor body 2 than the well region 22.

[0066] Furthermore, Figure 2 shows that there are multiple first regions 21, and therefore current-limiting regions 5, arranged symmetrically with respect to the gate electrode 33. Multiple units shown in Figure 2 can exist adjacent to each other, and therefore, multiple stripes of the gate electrode 33 and first electrode 31 can exist extending perpendicularly to the projection plane of Figure 2.

[0067] This symmetrical arrangement in Figure 2 (see also Figure 13) and / or the trench design in Figure 2 can, of course, be applied similarly to all other embodiments.

[0068] In Figure 2, one current limiting region 5 per first region 21 is the same design as in Figure 1, i.e., a trough design having a rectangular parallelepiped shape. According to Figure 2, the trough has sharp edges and corners. According to Figure 1, the trough has rounded edges and corners. Both designs are possible in all embodiments, depending on the manufacturing process of at least one current limiting region 5.

[0069] Furthermore, Figure 2 shows that there is a second electrode 32 and the semiconductor body 2 comprises a second region 24. For example, the second region 24 is a substrate on which the other regions 23, 22, 21, and 25 are formed by growth and / or doping, such as ion implantation. In the case of an IGBT or RC-IGBT, the second electrode 32 is a collector electrode, and the second region is a collector region of the same doping type as the well region. In the case of a MOSFET or MISFET, the second electrode 32 is a drain electrode, and the second region is a drain region of the same doping type as the first region. The same applies to all other embodiments of the semiconductor device 1. For example, in Figure 1, as in Figure 2, the second region 24 and the second electrode 32 can be directly located on the side of the drift region 23 facing outward from the top surface 20.

[0070] Furthermore, as shown in Figure 2, the plug region 25 starts from the top surface 20 and reaches deeper into the semiconductor body 2 than the first region 21. Otherwise, referring to Figure 1, the plug region 25 can have the same depth as the first region 21, or it may be shallower or deeper than the first region 21. Both possibilities can be applied to all embodiments.

[0071] Similar to Figure 1, in Figure 2, at least one current-limiting region 5 per first region 21 is separated from the first electrode 31, the gate electrode 33, and the gate insulating layer 4.

[0072] For example, the maximum doping concentration in the first region 21, the second region 24, and at least one plug region 25 is at least 1 × 10⁻⁶ 18 cm -3 , or at least 5 × 10 18 cm -3 , or at least 1 × 10 19 cm -3 , and / or up to 5 × 10 20 cm -3 , or up to 2 x 10 20 cm -3 , or up to 1 x 10 20 cm -3Furthermore, the maximum doping concentration in the well region 22, and therefore in the channel region adjacent to the gate insulating layer 4, is at least 5 × 10⁻⁶. 16 cm -3 or at least 1 × 10 17 cm -3 and / or up to 5 × 10 19 cm -3 or up to 5 x 10 18 cm -3 Depending on the voltage class of semiconductor device 1, the maximum doping concentration in the drift region 23 may be at least 1 × 10⁻⁶. 11 cm -3 , or at least 1 × 10 12 cm -3 , or at least 1 × 10 13 cm -3 , and / or up to 1 × 10 17 cm -3 , or up to 5 x 10 16 cm -3 , or up to 1 x 10 16 cm -3 This is possible. The thickness of the gate insulating layer 4 is, for example, 10 nm to 250 nm, or 80 nm to 150 nm. These parameters can be applied individually or collectively to all other embodiments.

[0073] Otherwise, the same thing can be applied to Figure 2 as to Figure 1, and vice versa. In Figures 3 and 4, as in Figure 1, there is one current-limiting region 5 per first region 21. The current-limiting regions 5 can be arranged mirror-symmetrically in the first region 25, with the axis of mirror symmetry extending perpendicularly to the top surface 20.

[0074] In contrast to what is shown in Figure 1, according to Figures 3 and 4, the current limiting region 5 extends beyond the gate insulating layer 4 and the gate electrode 33. Such an arrangement is also possible in all other embodiments. Otherwise, in contrast to what is shown in Figures 3 and 4, the current limiting region 5 may be located non-mirror-symmetrically within the first region 21 such that the current limiting region 5 terminates away from the gate insulating layer 4 and therefore does not extend beyond the gate electrode 33. This is also possible in all other embodiments.

[0075] As shown in Figure 3, the current limiting region 5 is formed as a shallow trough within the first region 21, which also forms a single trough. The depth d of the current limiting region 5 is, for example, 10% to 90% or 40% to 80% of the depth D of the first region 21. The first region 21 and the plug region 25 may have the same depth, for example, within manufacturing tolerances. For example, the depth D of the first region 21 is at least 0.1 μm and / or at most 2 μm.

[0076] As shown in Figure 4, the current limiting region 5 is formed as a deep trough within the first region 21, which is formed as two troughs, one of which is above the other, and the trough adjacent to the top surface 20 has a larger range parallel to the projection plane of Figure 4. In this case as well, the maximum depth d of the current limiting region 5 can be 10% to 90% or 40% to 80% of the total depth D of the first region 21, which is composed of the two troughs. For designs with two stacked troughs, the first region 21 can extend deeper than the plug region 25 into the semiconductor body 2. The plug region 25 can be, for example, the same depth as the trough of the first region 21 adjacent to the top surface 20, within manufacturing tolerances. For example, the depth D of the first region 21 is at least 0.2 μm and / or up to 4 μm.

[0077] For example, the trough adjacent to the top surface 20 is first formed by the corresponding doping, then a recess for the current limiting region 5 is formed, and then doping for the trough further from the top surface 20 is provided through the recess before the electrical insulating material is applied. Thus, the trough in Figure 4 has a stepped design when viewed in cross-section. Otherwise, in the configuration of Figure 4, a deep trough having a rectangular shape with rounded corners is also possible, for example, as shown in Figure 3.

[0078] Both designs having a shallow or deep first region 21, as shown in Figures 3 and 4, are possible in all other embodiments as well.

[0079] For example, the length L of the current limiting region 5 is 10% to 90%, 40% to 80%, or 50% to 70% of the width B of the first region 21. This is also possible in all other embodiments.

[0080] Otherwise, the same thing can be applied to Figures 3 and 4 as to Figures 1 and 2, and vice versa.

[0081] As shown in Figures 5 to 7, there are multiple current limiting regions 5 within the first region 21. The same parameters d, D, B, and L described above apply to the case of a single current limiting region 5 within the first region 21, where L corresponds to the total width of each individual current limiting region 5. For example, compare Figure 6. Multiple current limiting regions 5 provide more design parameters for achieving an optimized first region.

[0082] If there is only one current limiting region 5 in the direction perpendicular to the gate electrode 33 and / or the first electrode 31, then, referring to Figure 5, the total width L is the same as the width W of the individual insulating current limiting regions 5, as shown in Figure 4.

[0083] However, as shown in Figure 5, there is a stripe of subsequent current-limiting region 5 extending parallel to electrodes 31 and 33. In a top view, the current-limiting region 5 is rectangular or square in shape, optionally having rounded corners, each having a width W and a length range V. For example, V is 0.5L to 100L, or 0.5L to 10L, or 0.7L to 5L.

[0084] For example, the distance Zs between adjacent current-limiting regions 5 along a stripe is 10% to 75% or 10% to 40% of the width W and / or length range V. Individual current-limiting regions 5 within a stripe can be arranged at equidistant distances from each other, or at different distances from each other, as shown in Figure 5. These embodiments can be applied individually or collectively to all other embodiments.

[0085] In addition to those illustrated, the current limiting region 5 does not need to be square in shape when viewed from above, but may be rectangular, hexagonal, a regular or irregular polygon, or circular in shape when viewed from above. The same applies to all other embodiments.

[0086] According to Figures 5 to 7, all current limiting regions 5 within the first region 21 have the same shape. This is not mandatory; that is, different shaped current limiting regions 5 can be combined within a single first region 21.

[0087] There can be N stripes of current-limiting regions 5 between electrodes 31 and 33, where N is a natural number greater than or equal to 2. For example, N is at most 10 or at most 4. According to the example in Figure 6, N is 2. For example, 0.1B / N ≤ W ≤ 0.99B / N or 0.4B / N ≤ W ≤ 0.95B / N or 0.7B / N ≤ W ≤ 0.90B / N. Alternatively or additionally, for example, the distance Zt between adjacent current-limiting regions 5 in the transverse direction perpendicular to the stripe is 10% to 75% or 10% to 40% of the length range V. Alternatively or additionally, for example, 0.1B / N ≤ V ≤ 100B / N or 0.4B / N ≤ V ≤ 10B / N or 0.7B / N ≤ V ≤ 5B / N can be applied. The current-limiting regions 5 can be arranged equidistant from electrodes 31 and 33, parallel and perpendicular to them.

[0088] As shown in Figure 6, all N stripes have the same number of current-limiting regions 5, and as a result, in each case, K current-limiting regions 5 exist adjacent to each other in a direction parallel to the stripes. As a result, a regular array of N × K current-limiting regions 5 is formed, and all current-limiting regions 5 have the same shape.

[0089] However, this is not mandatory. That is, current limiting regions 5 of different shapes and sizes can be combined, and each stripe can have a different number of current limiting regions 5 (K) and / or a different number of current limiting regions 5 (N) in a direction parallel to the width L. For example, there may be current limiting regions 5 of different widths W, and as an example, there may be rows parallel to the direction along the width L that have a single wide current limiting region 5, alternating with rows that have multiple narrower current limiting regions 5.

[0090] Figure 7 shows that N is 3. Optionally, the stripe furthest from the first electrode 31 extends beyond the gate insulating layer 4. However, apart from what is shown in Figure 7, all stripes can be separated from the gate electrode 33, for example, in a top view of the top surface 20.

[0091] Each stripe in Figure 7 can consist of multiple current limiting regions 5, as in Figures 5 and 6, or there may be only a single current limiting region 5 per stripe, as in Figures 1 to 4. The same applies to all other embodiments.

[0092] The current limiting region 5 in Figures 5 to 7 is shallower in design compared, for example, to Figure 3 above. It is also possible for all or part of the current limiting region 5 in the first region 21 to be deeper, as shown in relation to Figure 4.

[0093] Otherwise, the same thing can be applied to Figures 5 to 7 as to Figures 1 to 4, and vice versa.

[0094] Figures 8 to 11 show the gate-source voltage V GS Simulated isothermal power J at 15V and 300K temperature D V DS The drain-source voltage V of semiconductor device 1, E1 in Figure 1 is compared to the corresponding reference MOSFET design 9 without a current limiting region. DS =600V and V GS、スイング The electrical thermal short-circuit waveform at -5V / +15V is shown. See Figures 8 and 9. Figures 10 and 11 show corresponding data for two semiconductor devices 1, E2, and E3 having a deep current-limiting region 5 as shown in Figure 4. For device E1 corresponding to Figure 1, the quotient d / D between the depth d of the current-limiting region 5 and the depth D of the first region 21 is 0.65. Devices E2 and E3 corresponding to Figure 4 have quotients d / D of 1.40 and 2.00, respectively, where D refers to the depth of the first region 21 in Figure 1. The quotient L / B between the length L of the current-limiting region 5 and the width B of the first region 21 is 0.5.

[0095] Maximum saturation current I during short circuit SAT、ピーク The achieved reduction is due to the resistance R in the ON state. DS,on Note that this is greater than the increase in . The energy the device receives during a short circuit is I SATBecause it is directly related to the maximum value, the semiconductor device 1 described herein improves short-circuit withstand capability without significantly affecting conduction loss.

[0096] Figure 12 shows a method for manufacturing a semiconductor device 1. In method step S1, a semiconductor body 2 is provided. For example, the semiconductor body 2 provides a drift region 23. Then, in method step S2, a first region 21 and a well region 22 are formed in the semiconductor body 2 and the plug region 25.

[0097] Next, in step S3, at least one recess is etched into the first region 21, and at least one recess is filled with at least one electrical insulating material to create at least one current limiting region 5 per first region 21.

[0098] Next, in step S4, after applying the gate insulating layer 4, step S5 is performed to apply the gate electrode 33 and the first electrode 31 to the semiconductor body 2, and also to the second electrode 32 if necessary.

[0099] The method steps do not necessarily have to be performed in the order described. Furthermore, the method steps may be mixed; for example, some of electrodes 31, 32, and 33 may be applied before etching, and some of electrodes 31, 32, and 33 may be applied after etching.

[0100] Figure 13 shows an example of semiconductor device 1 in a top view. It can be seen that the stripes of the gate electrode 33 are symmetrically positioned, for example, between two stripes of half of the first electrode 31, and therefore between two stripes of the first region 21 having the current limiting region 5. The structure in Figure 13 corresponds to unit cells that can be multiplied so that multiple unit cells can be arranged adjacent to each other.

[0101] This stripe design can also be applied to embodiments in Figures 1 and 3-7. Figure 2 already shows this type of symmetrical design.

[0102] Otherwise, the same thing can be applied to Figure 13 as to Figures 1 to 12, and vice versa.

[0103] Furthermore, referring to Figure 14, the semiconductor device 1 can also be designed as a cell in a top view, such that rectangular or square unit cells can be produced. For example, at the center of a unit cell is a first electrode 31 framed by a gate electrode 33. Such unit cells can be arranged two-dimensionally so that the semiconductor device 1 can have a large number of such unit cells.

[0104] Otherwise, the same thing can be applied to Figure 14 as to Figure 13, and vice versa.

[0105] Unless otherwise specified, the components shown in the diagram are, illustratively, directly on top of each other in the specified order. Components that are not in contact in the diagram are, illustratively, spaced apart from each other. If lines are drawn parallel to each other, the corresponding surfaces may also be oriented parallel to each other. Similarly, unless otherwise specified, the relative positions of the depicted components are accurately reproduced in the drawing. [Explanation of Symbols]

[0107] List of reference symbols 1. Semiconductor devices 2. Semiconductor body 20 Top surface of the semiconductor main unit 21. First region (source region or emitter region) 22-well area 23. Drift Region 24. Second region (drain region or collector region) 25 Plug Area 31. First electrode (source electrode or emitter electrode) 32. Second electrode (drain electrode or collector electrode) 33 Potatoes 4 Gate Insulation Layer 5 Current limiting region 9. Comparative Examples of Semiconductor Devices B. Width of the first region d Depth of the current limiting region D Depth of the first region E1 First example of a semiconductor device E2 First example of a semiconductor device E3 First example of a semiconductor device L is the length of the current limiting region. M is the line of mirror symmetry. S. Method Steps T is a unit of time in microseconds. J D Current density in the drain region (A / cm²) 2 ) V DS Voltage (V) between the drain electrode and the source electrode V Current limiting region length range W has an isolation current limiting region. Distance between current limiting regions along the Zs stripe Zt Distance between current limiting regions in the transverse direction

Claims

1. A semiconductor device (1) comprising a semiconductor body (2), a terminal electrode (33), and a first electrode (31), The semiconductor body (2) comprises a first region (21) which is a source region or an emitter region, and a well region (22) located adjacent to the first region (21), wherein the first region (21) is a first conductivity type, and the well region (22) is a different second conductivity type. The well region (22) is adjacent to the gate electrode (33) and is separated from the gate electrode (33) by the gate insulating layer (4). The first region (21) is electrically contacted by the first electrode (31), which is a source electrode or an emitter electrode. There are multiple current limiting regions (5) within a single first region (21), The current limiting region (5) consists of at least one electrical insulating material, The current limiting regions (5) are separated from each other when viewed from above the semiconductor body (2), Multiple current limiting regions (5) are assigned to a single first region (21), A semiconductor device (1) characterized in that, in a top view of the semiconductor body (2), a plurality of current limiting regions (5) are completely surrounded by the allocated first region (21).

2. The semiconductor device (1) according to claim 1, wherein, in a top view of the semiconductor body (2), the gate electrode (33) and the first electrode (31) overlap with the first region (21), and the current limiting region (5) is separated from the gate electrode (33) and the first electrode (31).

3. The semiconductor device (1) according to claim 1 or 2, wherein, in a top view of the semiconductor body (2), the first region (21) extends completely between the current limiting region (5) and the first electrode (31), and between the current limiting region (5) and the gate electrode (33), and the current limiting region (5) is located between the first electrode (31) and the gate electrode (33).

4. The semiconductor device (1) according to claim 1 or 2, as viewed in a cross-section of the semiconductor body (2) passing through the first region (21) and the gate electrode (33), the first region (21) extends around the current limiting region (5) in a direction toward the well region (22), such that the first region (21) is embedded in the well region (22) and the current limiting region (5) is embedded in the first region (21).

5. The semiconductor device (1) according to claim 1 or 2, wherein the volume of the current limiting region (5) is at least 10% and at most 95% of the total volume of the current limiting region (5) when combined with the first region (21).

6. The current limiting region (5) is a metal oxide or a semiconductor oxide. The current limiting region (5) is a recess within the first region (21), and the at least one electrical insulating material fills the recess. The at least one electrical insulating material terminates in alignment with the first region (21), The semiconductor device (1) according to claim 1 or 2.

7. The semiconductor body (2) further comprises the drift region (23) of the first conductivity type, and also comprises a second region (24) which is a drain region or a collector region. The drift region is located between the well region (22) and the second region (24). The semiconductor device (1) further comprises a second electrode (32) which is a collector electrode or a drain electrode, and the second electrode (32) is located on the side of the second region (24) that is far from the drift region (23). The semiconductor body (2) is SiC. The semiconductor device (1) according to claim 1 or 2.

8. In a top view of the semiconductor body (2), the gate electrode (33) and the first electrode (31) each extend along a straight line, and the first region (21) extends parallel to the gate electrode (33) and the first electrode (31), or In a top view of the semiconductor body (2), the gate electrode (33) and the first electrode (31) each comprise a plurality of subsections arranged along at least one alignment line, and the first region (21) extends between adjacent subsections of the gate electrode (33) and the first electrode (31). The semiconductor device (1) according to claim 1 or 2.

9. The semiconductor device (1) according to claim 1 or 2, wherein the gate insulating layer (4) and the gate electrode (33) are planar in design so as to be applied to the planar portion of the upper surface (20) of the semiconductor body (2), and the first region (21) is located on the upper surface (20).

10. The trench design is such that the gate insulating layer (4) and the gate electrode (33) are at least partially located within the trench of the semiconductor body (2), wherein the depth of the trench begins from the upper surface (20) of the semiconductor body (2), exceeds the depth of the well region (22), and the first region (21) is located on the upper surface (20), as described in claim 1 or 2.

11. The semiconductor device (1) according to claim 1 or 2, wherein the current limiting region (5) is arranged along one stripe or along multiple stripes.

12. The semiconductor device (1) according to claim 1 or 2, wherein, in a top view of the semiconductor body (2), the current limiting region (5) is formed as at least one of a triangle, square, rectangle, hexagon, or circle.

13. A method for manufacturing a semiconductor device (1) according to claim 1 or 2, wherein the method is The semiconductor body (2) is provided, The first region (21) and the well region (22) are formed in the semiconductor body (2), To create the current limiting region (5), recesses are etched within the first region (21), and the recesses are filled with the at least one electrical insulating material. Applying the gate insulating layer (4) to the semiconductor body (2), The semiconductor body (2) is to be fitted with the gate electrode (33) and the first electrode (31). Methods that include...

14. The method according to claim 13, wherein the recess is etched into the semiconductor body (2), then at least a portion of the doping of the first region (21) is applied into the semiconductor body (2) through the recess, and then the at least one electrical insulating material is filled into the recess.

15. The invention further includes forming at least one plug region (25) within the semiconductor body (2), wherein the at least one plug region (25) is of a second conductivity type and has a maximum doping concentration higher than the maximum doping concentration of the well region (22), and the at least one plug region (25) is for electrically contacting the well region (22). The first region (21) extends deeper into the semiconductor body (2) than the at least one plug region (25). The method according to claim 13.

16. The method according to claim 13, comprising two different doping steps to create the first region (21) such that the doping profile of the first region (21) is stepped when viewed in cross-section.

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